- Fix reference of uninitialized error value in bhndb_generic_resume() if
the dynamic window count is 0.
- Fix incorrect bhnd_pmu(4) UPTME_MASK and PLL0_PC2_WILD_INT_MASK
constants.
- Variable definitions referenced by our generated SPROM layouts will never
be NULL, but add explicit asserts to make that clear.
- Add missing variable initialization in bhnd_nvram_sprom_ident().
- Fix leak of driver array in bhnd_erom_probe_driver_classes().
- Fix zero-length memset() in bhndb_pci_eio_init().
- Fix an off-by-one error and potential invalid OOBSEL bit shift operation
in bcma_dinfo_init_intrs().
- Remove dead code in siba_suspend_hw().
- Fix duplicate call to bhnd_pmu_enable_regulator() in both the enable and
disable code paths of bhnd_compat_cc_pmu_set_ldoparef().
Reported by: Coverity
CIDs: 1355194, 1362020, 1362022, 1373114, 1366563, 1373115,
1381569, 1381579, 1383555, 1383566, 1383571
Sponsored by: The FreeBSD Foundation
This commit is part of D6920 review. One of macro had wrong prefix:
BMCA => BCMA
Reviewed by: landonf, adrian (mentor)
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D6920
- Added bhnd(4) bus APIs for per-core ioctl/iost register access.
- Updated reset/suspend bhnd(4) APIs for compatibility with ioctl/iost
changes.
- Implemented core reset/suspend support for both bcma(4) and siba(4).
- Implemented explicit release of all outstanding PMU requests at the bus
level when putting a core into reset.
Approved by: adrian (mentor, implicit)
Differential Revision: https://reviews.freebsd.org/D8009
This adds bhnd(4) bus-level support for querying backplane interrupt vector
routing, and delegating machine/bridge-specific interrupt handling to the
concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly
to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively
disabling the bus-level interrupt assignment. This allows mips/broadcom
to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC
support is implemented.
Reviewed by: mizhka
Approved by: adrian (mentor, implicit)
- Added bhnd_pmu driver implementations for PMU and PWRCTL chipsets,
derived from Broadcom's ISC-licensed HND code.
- Added bhnd bus-level support for routing per-core clock and resource
power requests to the PMU device.
- Lift ChipCommon support out into the bhnd module, dropping
bhnd_chipc.
Reviewed by: mizhka
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D7492
SoCs and various chips (including, famously, their wifi chips.)
This is "just" (all 20,000 lines of it) code to enumerate the various
versions of busses inside these devices, including the PCI bridge and
the direct SIBA bridge found in MIPS chips.
It also includes shared code for some bus operations (suspend, resume, etc);
EEPROM/SROM/etc parsing and other things that are shared between chips.
Eventually this'll replace the code that bwi/bwn uses for the internal
bus, as well as some apparently upcoming mips74k broadcom SoC support
which uses bwn!
Thanks to Landon Fuller <landonf@landonf.org> for all this work!
Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
