Log:
- merge in latest xenbus from dfr's xenhvm
- fix race condition in xs_read_reply by converting tsleep to mtx_sleep
Log:
unmask evtchn in bind_{virq, ipi}_to_irq
Log:
- remove code for handling case of not being able to sleep
- eliminate tsleep - make sleeps atomic
Note, that the patch provided with this card for the Linux states that
the card uses DEFAULT_RCLK * 2, while in fact it is '* 10'. So probably
we should also use the subdevice/subvendord here. For now just ignore
that fact.
PR: kern/129665
Submitted by: bsam
Obtained from: united efforst with bsam
Now the NDISulator supports NDIS USB drivers that it've tested with
devices as follows:
- Anygate XM-142 (Conexant)
- Netgear WG111v2 (Realtek)
- U-Khan UW-2054u (Marvell)
- Shuttle XPC Accessory PN20 (Realtek)
- ipTIME G054U2 (Ralink)
- UNiCORN WL-54G (ZyDAS)
- ZyXEL G-200v2 (ZyDAS)
All of them succeeded to attach and worked though there are still some
problems that it's expected to be solved.
To use NDIS USB support, you should rebuild and install ndiscvt(8) and
if you encounter a problem to attach please set `hw.ndisusb.halt' to
0 then retry.
I expect no changes of the NDIS code for PCI, PCMCIA devices.
Obtained from: //depot/projects/ndisusb/...
Disable some unneeded pathes in overcomplicated input mixer to help parser
to handle the rest better. This gives mic input boost control in some
configurations and just more predictable operation in others.
Note that you need at least xf86-video-intel 2.4.3 for this to work.
The G4X doesn't put the GATT into the same area of stolen memory
as all the other chips and older versions of the driver didn't
handle that properly.
Tested by: ganbold
Approved by: kib
MFC after: 2 weeks
Note that there is no working backend (or at least
that is mentioned in the PR ticket) but the device
is now supported on our end.
PR: 117205
Submitted by: Artem Naluzhnyy <tut at nhamon dot com dot ua>
MFC after: 1 week
o add EHCI_SCFLG_BIGEMMIO flag to force big-endian byte-select to be
set in USBMODE
o split reset work into new public routine ehci_reset so bus shim drivers
can force big-endian byte-select before ehci_init
event from mii(4) may not be delivered if valid link was already
established. To address the issue, check current link state after
driving MII_TICK. This should fix a regression introduced in
r185753 on fast ethernet controllers.
Reported by: csjp, Bruce Cran < bruce <> cran DOT org DOT uk >
Tested by: csjp, Bruce Cran (initial version)
o add support to byte swap EHCI descriptor contents; the IXP435
has dual-EHCI controllers integral but descriptor contents are
in big-endian format; this support is configured with the
USB_EHCI_BIG_ENDIAN_DESC option and enabled with EHCI_SCFLG_BIGEDESC
o clean up EHCI USBMODE register setup during init; add #defines for
bit values
o split debug support out into a new file and enable use through ddb
o while here remove a bunch of lingering netbsd-isms
Reviewed by: imp
of OFW access semantics, in order to allow future support for real-mode
OF access and flattened device frees. OF client interface modules are
implemented using KOBJ, in a similar way to the PPC PMAP modules.
Because we need Open Firmware to be available before mutexes can be used on
sparc64, changes are also included to allow KOBJ to be used very early in
the boot process by only using the mutex once we know it has been initialized.
Reviewed by: marius, grehan
Intel 855 chips present the same pci id for both heads. This prevents
us from attaching to the dummy second head. All other chips that I
am aware of either only present a single pci id, or different ids
for each head so that we only match on the correct head.
Approved by: kib@
MFC after: 2 weeks
storage class. This check was lost. It is not important for the most cases,
but as it was reported on current@, it does important for sis driver and
surely inportant for AHCI driver. So restore it there.
Submitted by: Toshikazu ICHINOSEKI, Andrey V. Elsukov
Discussed on: current@
ati pci gart to use bus_dma to handle the allocations. This fixes
a garbled screen issue on at least some radeons (X1400 tested). It is
also likely that this is the correct fix for PR# 119324, though that
is not confirmed yet.
Reviewed by: jhb@ (mentor, prior version)
Approved by: kib@
MFC after: 2 weeks
payload length in TSO case. Leaving unused TBD also seem to cause
SCB timeouts under certain conditions when TSO/non-TSO traffics
are active at the same time.
had been the only flag with random usage patterns.
Switch inc_flags to be used as a real bit field by using
INC_ISIPV6 with bitops to check for the 'isipv6' condition.
While here fix a place or two where in case of v4 inc_flags
were not properly initialized before.[1]
Found by: rwatson during review [1]
Discussed with: rwatson
Reviewed by: rwatson
MFC after: 4 weeks
command whenever Tx completion interrupt is raised. The Tx poll
bit is cleared when all packets waiting to be transferred have been
processed. This means the second Tx poll command can be silently
ignored as the Tx poll bit could be still active while processing
of previous Tx poll command is in progress.
To address the issue re(4) used to invoke the Tx poll command in Tx
completion handler whenever it detects there are pending packets in
TxQ. However that still does not seem to completely eliminate
watchdog timeouts seen on RealTek PCIe controllers. To fix the
issue kick Tx poll command only after Tx completion interrupt is
raised as this would indicate Tx is now idle state such that it can
accept new Tx poll command again. While here apply this workaround
for PCIe based controllers as other controllers does not seem to
have this limitation.
Tested by: Victor Balada Diaz < victor <> bsdes DOT net >
out of sleep mode prior to accessing to PHY. This should fix device
attach failure seen on these controllers. Also enable the sleep
mode when device is put into sleep state.
PR: kern/123123, kern/123053
result in panic:
mdconfig -af blah.img -o force
mount /dev/md0 /mnt
mdconfig -du 0
Reviewed by: scottl
Approved by: rwatson (mentor)
Sponsored by: FreeBSD Foundation
configuration registers (which are not going to change) on every interrupt
looks expensive, especially when interrupt is shared. Profiling shows me 3%
of time spent by atapci0 on pure network load due to IRQ sharing with em0.
- Initialize variables before use.
- Remove a KASSERT() that could falsely trigger if there are other sources
of NMIs in the system.
Efficiency tweak:
- When checking PMCs that overflowed, ignore PMCs that were not configured for
sampling.
a real packet error but simply indicate that an unexpected unicast or multicast
error was received by the NIC, which was not counted in the past as well.
Reported by: many (on -stable@)
Reviewed by: davidch
MFC after: 3 days
controllers. Reading this register, for which there are indications
that it doesn't really exist, returns 0 on at least some 12160
and doing so on Sun Fire V880 causes a data access error exception.
Reported and tested by: Beat Gaetzi
Approved by: mjacob
Obtained from: OpenBSD (modulo setting isp_lvdmode)
the code for parsing interrupt maps) to PowerPC and reflect their new MI
status by moving them to the shared dev/ofw directory.
This commit also modifies the OFW PCI enumeration procedure on PowerPC to
allow the bus to find non-firmware-enumerated devices that Apple likes to add,
and adds some useful Open Firmware properties (compat and name) to the pnpinfo
string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the
change to PCI enumeration on PowerPC, X has started working again on PPC
machines with Grackle hostbridges.
Reviewed by: marius
Obtained from: sparc64
1. separating L2 tables (ARP, NDP) from the L3 routing tables
2. removing as much locking dependencies among these layers as
possible to allow for some parallelism in the search operations
3. simplify the logic in the routing code,
The most notable end result is the obsolescent of the route
cloning (RTF_CLONING) concept, which translated into code reduction
in both IPv4 ARP and IPv6 NDP related modules, and size reduction in
struct rtentry{}. The change in design obsoletes the semantics of
RTF_CLONING, RTF_WASCLONE and RTF_LLINFO routing flags. The userland
applications such as "arp" and "ndp" have been modified to reflect
those changes. The output from "netstat -r" shows only the routing
entries.
Quite a few developers have contributed to this project in the
past: Glebius Smirnoff, Luigi Rizzo, Alessandro Cerri, and
Andre Oppermann. And most recently:
- Kip Macy revised the locking code completely, thus completing
the last piece of the puzzle, Kip has also been conducting
active functional testing
- Sam Leffler has helped me improving/refactoring the code, and
provided valuable reviews
- Julian Elischer setup the perforce tree for me and has helped
me maintaining that branch before the svn conversion
time it is marked for user space callchain capture in the NMI
handler and the time the callchain capture callback runs.
- Improve code and control flow clarity by invoking hwpmc(4)'s user
space callchain capture callback directly from low-level code.
Reviewed by: jhb (kern/subr_trap.c)
Testing (various patch revisions): gnn,
Fabien Thomas <fabien dot thomas at netasq dot com>,
Artem Belevich <artemb at gmail dot com>
if (batt_sleep_ms)
AcpiOsSleep(1);
where the rest are all:
if (batt_sleep_ms)
AcpiOsSleep(batt_sleep_ms);
I can't recall why that one was different, so change it
to match the rest.
Pointed out by: Christoph Mallon
MFC after: 2 weeks
On some laptops with smart batteries, enabling battery monitoring
software causes keystrokes from atkbd to be lost. This has also been
reported on Linux, and is apparently due to the keyboard and I2C line
for the battery being routed through the same chip. Whether that's
accurate or not, adding extra sleeps to the status checking code
causes the problem to go away.
I've been running this for nearly six months now on my laptop,
it works like a charm.
Reviewed by: Nate Lawson (in a previous revision)
MFC after: 2 weeks
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
o Try to be smarter about reading the ExCA CSC register. Now, we only
do it for 16-bit cards. Add some experimental code to treat it like
a power interrupt, but I'm not 100% sure that I like it. It may be
removed upon further testing. It seemed to help in one test case, but
the evidence may be inconclusive. This may be beneficial for cleaning up
exca_reset and exca_wait_ready.
o Check for CSTS events on the socket event register. We ask for it when
we're powering up a card, but I don't think we're otherwise using
it. Just ACK the interrupt for now. In theory, we can use it
instead of the busy wait we do in cbb_cardbus_reset. More research
is necessary to see if we can optimize things there when we're
waiting for the DEVVENDOR register to become valid.
o Rework the comments a bit. Minor tidying up. Etc.
causes data corruption in combination with certain bridges.
Information about this problem was kindly provided by davidch. [1]
- As BGE_FLAG_PCIX is meant to indicate that the controller is in
PCI-X mode, revert to the pre __FreeBSD_version 602101 method of
reading the bus mode register rather than checking the mere
existence of a PCI-X capability, which is also there when the
NIC f.e. is put into a 32-bit slot causing it not to be in PCI-X
mode. Setting BGE_FLAG_PCIX inappropriately could cause the NIC
to be tuned incorrectly.
PR: 128833 [1]
Reviewed by: jhb
MFC after: 3 days
When VLAN tagged frame is received the hardware sets 'LONG' bit of
Rx status word. It is always set when the size of received frame
exceeded 1518 bytes, including CRC. This VLAN tagged frame clears
'OK' bit of Rx status word such that driver should not rely on 'OK'
bit of Rx status word to pass the VLAN tagged frame to upper stack.
To fix the bug, don't use SIS_CMDSTS_PKT_OK for Rx error check and
introduce SIS_RXSTAT_ERROR macro that checks Rx errors. If we are
configured to accept VLAN tagged frames and the received frame size
is less than or equal to maximum allowed length of VLAN tagged
frame, clear 'LONG' bit of Rx status word before checking Rx
errors.
Reported by: Vladimir Ermako < samflanker <> gmail DOT com >
Tested by: Vladimir Ermako < samflanker <> gmail DOT com >
Waiting for 1ms for each GMII register access looks overkill and it
may also decrease overall performance of driver because re(4)
invokes mii_tick for every hz.
Tested by: rpaulo
established a valid link or not. In miibus_statchg handler add a
check for established link is valid one for the controller(e.g.
1000baseT is not a valid link for fastethernet controllers.)
o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers.
o Added additional check to know whether we've really encountered
watchdog timeouts or missed Tx completion interrupts. This change
may help to track down the cause of watchdog timeouts.
o In interrupt handler, removed a check for link state change
interrupt. Not all controllers have the bit and re(4) did not
rely on the event for a long time. In addition, re(4) didn't
request the interrupt in RL_IMR register.
Tested by: rpaulo
drivers, there should be a 1us delay after every write when
bit-banging the MII. Also insert barriers in order to ensure
the intended ordering. These changes hopefully will solve the
bus wedging occasionally experienced with DM9102A since r182461.
- Deobfuscate dc_mii_readreg() a bit.
multiple algorithms and potentially collect multiple samples.
Instead of a single calibration interval we now have short and long
intervals; the long interval roughly corresponds to the previous
single interval. The short interval is used to speedup collection
of samples and happens much quicker. We make calls using the short
interval until we're told the calibration work is complete at which
point we fallback to the long interval. In addition there is a
much longer reset interval used to flush all calibration state and
cause everthing to start anew.
With these changes you can also disable calibration entirely by
setting the long interval to zero.
at. I don't think this will make a huge difference, but I have
received a report of a interrupt storm on one 16-bit card that this
might fix (chances are it won't, since I think that we may need to
check both the CBB registers for the 16-bit card as well as the PCIC
registers for power state change).
Submitted by: jhb@
the power interrupt and init code waiting for the interrupt are
running on different CPUs. I haven't seen this make any real
difference, but I've also had some reports of odd behavior I can't
otherwise explain. It is an infrequent operation, and certainly
wouldn't hurt.
my right mouse button and keyboard LEDs from working due to mangled
configuration packets. Fixed several other races and associated problems in the
main ADB stack that were exposed while fixing this.
Now it is possible to suspend/resume with inserted and active card.
To reinitialize card on resume and to detect card change while suspended,
implement bus rescan routines. It can also be used by controllers without
card presence detection signals or with multiple cards per slot support.
While there, cleanup msleep() usage. We have no any rights to exit without
"request done" signal from driver as it could lead to modify after free.
interrupt code to be more robust. I've been running these changes for
over a year... With these changes, I don't see the ath card going
into reset like the code in the tree.
packet loss, of between 10-30%. The fix is to put the PHY into
and take it out of local loopback mode when resetting the interface.
Obtained from: Chelsio Inc.
MFC after: 3 days
o Chip full mask revision 2 or later controllers have to
set correct Tx MAC and Tx offload clock depending on negotiated
link speed.
o JMC260 chip full mask revision 2 has a silicon bug that can't
handle 64bit DMA addressing. Add workaround to the bug by
limiting DMA address space to be within 32bit.
o Valid FIFO space of receive control and status register was
changed on chip full mask revision 2 or later controllers. For
these controllers, use default 16QW as it's supposed to be the
safest value for maximum PCIe compatibility. JMicron confirmed
performance will not be reduced even if the FIFO space is set
to 16QW.
o When interface is put into suspend/shutdown state, remove Tx MAC
and Tx offload clock to save more power. We don't need Tx clock
at all in this state.
o Added new register definition for chip full mask revision 2 or
later controllers.
Thanks to JMicron for their continuous support of FreeBSD.
change. As a side effect, this makes the excessive interrupts to
disappear which has been observed as a regression in recent stable/7.
Reported by: many (on -stable@)
Reviewed by: davidch
directly include only the header files needed. This reduces the
unneeded spamming of various headers into lots of files.
For now, this leaves us with very few modules including vnet.h
and thus needing to depend on opt_route.h.
Reviewed by: brooks, gnn, des, zec, imp
Sponsored by: The FreeBSD Foundation
when it sees only received packets. In some cases where a device only
recieves data it mistakenly thinks that its transmitting side is broken
and resets the device.
Obtained from: Chelsio Inc.
MFC after: 3 days
hardware for PMCs that have been configured for sampling.
- Bug fix: acknowledge PMC hardware overflows irrespective of the
the (software) PMC's state.
- break complex conditionals in to multiple lines to avoid wrapping
- remove copious unused debug statements
- be more aggressive about cleaning in the calling thread
- eliminate usage of ENOSPC
- increase number of iterations that cxgbsp can do
- eliminate "initerr" usage to simplify ENOBUFS handling
- when coalescing pass all packets to BPF
- always set overrun if hardware queue is full
offload for VLAN frames are also supported. The VLAN hardware
assistance is available only on 82550/82551 based controllers.
While I'm here change the confusing name of bit1 in byte 22 of
configuration block to vlan_drop_en. The bit controls whether
hardware strips VLAN tagged frame or not. Special thanks to wpaul
who sent valuable VLAN related information to me.
Tested on: i386, sparc64
events. Just reading PMDR register was not enough to have fxp(4)
immuninize against received magic packets during system boot.
Tested by: Alexey Shuvaev < shuvaev <> physik DOT uni-wuerzburg DOT de >
module; the ath module now brings in the hal support. Kernel
config files are almost backwards compatible; supplying
device ath_hal
gives you the same chip support that the binary hal did but you
must also include
options AH_SUPPORT_AR5416
to enable the extended format descriptors used by 11n parts.
It is now possible to control the chip support included in a
build by specifying exactly which chips are to be supported
in the config file; consult ath_hal(4) for information.
o eliminate private state indexed by 802.11 rate codes; use the hal's
rate tables directly to get the same info
o calculate a mask of operational rates to optimize lookups and checks
(instead of using for loops and similar)
o optimize size bin operations
o ignore rates marked as "do not use" in the hal phy tables
o fix bug that caused upshifting to break in 11g once the rate dropped
below 11Mb/s
o add more intelligent multi-rate tx schedules
o add support for 1/2 and 1/4 width channels
o add dev.ath.X.sample_stats sysctl to dump runtime statistics to the console
(needs to go up to a user app)
o export more tuning knobs via sysctls (still a couple of magic constants)
necessary workarounds, add code to detect these hangs and distinguish
them from other events; note this code is only invoked for anomalous
conditions and (at the moment) is a noop because the hang detection
code is in a new hal that's coming shortly
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
model 0x1C (Atom).
In these CPUs, the actual numbers, kinds and widths of PMCs present
need to queried at run time. Support for specific "architectural"
events also needs to be queried at run time.
Model 0xE CPUs support programmable PMCs, subsequent CPUs
additionally support "fixed-function" counters.
- Use event names that are close to vendor documentation, taking in
account that:
- events with identical semantics on two or more CPUs in this family
can have differing names in vendor documentation,
- identical vendor event names may map to differing events across
CPUs,
- each type of CPU supports a different subset of measurable
events.
Fixed-function and programmable counters both use the same vendor
names for events. The use of a class name prefix ("iaf-" or
"iap-" respectively) permits these to be distinguished.
- In libpmc, refactor pmc_name_of_event() into a public interface
and an internal helper function, for use by log handling code.
- Minor code tweaks: staticize a global, freshen a few comments.
Tested by: gnn
controllers. ICH based controllers are treated as 82559. 82557,
earlier revision of 82558 and 82559ER have no WOL capability.
o WOL support requires help of a firmware so add check whether
hardware is capable of handling magic frames by reading EEPROM.
o Enable accepting WOL frames only when hardware is about to
suspend or shutdown. Previously fxp(4) used to allow receipt of
magic frame under normal operation mode which could cause
hardware hang if magic frame is received by hardware. Datasheet
clearly states driver should not allow WOL frames under normal
operation mode.
o Disable WOL frame reception in device attach so have fxp(4)
immunize against system hang which can be triggered by magic
packets when the hardware is not in fully initialized state.
o Don't reset all hardware configuration data in fxp_stop()
otherwise important configuration data is lost and this would
reset WOL configuration to default state which in turn cause
hardware hang on receipt of magic frames. To fix the issue,
preserve hardware configuration data by issuing a selective
reset.
o Explicitly disable interrupts after issuing selective reset as
reset may unmask interrupts.
Tested by: Alexey Shuvaev < shuvaev <> physik DOT uni-wuerzburg DOT de >
will sometimes fail to initialize problem due to a lock
contention with management hardware. However, in order to
deliver that fix it was necessary to take a shared code
update as a whole, and this required scattered changes in
the core code to be compatible.
The em driver now has VLAN HW support added as the igb
driver had previously.
MFC after: ASAP - in time for 7.1 RELEASE
-This version has header split, and as a result a number of
aspects of the code have been improved/simplified.
- Interrupt handling refined for performance
- Many small bugs fixed along the way
MFC after: ASAP - in time for 7.1
- Bugfix: Don't excede static number of ports allowed when iterating
over endpoints within an interface.
- u3g_speeds contains speeds in baud, not bytes per second, so divide
the buffer size by 10.
o Configure controller to use dynamic TBD as TSO requires that
operation mode.
o Add a dummy TBD to tx_cb_u as TSO can access one more TBD in TSO
operation.
o Increase a DMA segment size to 4096 to hold a full IP segment
with link layer header.
o Unlike other TSO capable controllers, 82550/82551 does not
modify the first IP packet in TSO operation so driver should
create an IP packet with proper header. Subsequent IP packets
are generated from the header information in the first IP packet
header. Likewise pseudo checksum also should be computed by
driver for the first packet.
o TSO requires one more TBD to hold total TCP payload. To make
code simple for TSO/non-TSO case, increase the index of the
first available TBD array.
o Remove KASSERT that checks the size of a DMA segment should be
less than or equal to MCLBYTES as it's no longer valid in TSO.
o Tx threshold and number of TBDs field is used to store MSS in
TSO. So don't set the Tx threshold in TSO case.
82559 or later controllers added simple checksum calculation logic
in RU. For backward compatibility the computed checksum is appended
at the end of the data posted to Rx buffer. This type of simple
checksum calculation support had been used on several vendors such
as Sun HME/GEM, SysKonnect GENESIS and Marvell Yukon controllers.
Because this type of checksum offload support requires parsing of
received frame and pseudo checksum calculation with software
routine it still consumes more CPU cycles than that of full-fledged
checksum offload controller. But it's still better than software
checksum calculation.
Rx buffer and loads DMA map. Also add a function
fxp_discard_rfabuf that handles reusing Rx buffer/DMA map. With
this change fxp_add_rfabuf just handles appending a new RFA to
existing chain.
o Initialize mbuf length in fxp_new_rfabuf.
o Don't reset rnr and have fxp(4) handle received frames even if
it couldn't allocate new Rx buffer. This will make fxp(4) reload
updated RFA under rnr case. The rnr would still be reset to 0 if
polling is active and fxp(4) processed number of allowed Rx
events.
o Update if_iqdrops if fxp(4) couldn't allocate Rx buffer.
Previously fxp(4) used to try to reuse Rx buffer when new buffer
allocation is failed. But fxp(4) didn't take into account loaded
DMA map such that the same DMA map was loaded again without
unloading the map. There is no reason to unload the loaded map and
reload the same map again, just reusing the map is enough. I
believe the spare DMA map in softc was introduced to implement this
behaviour. Also fxp(4) used to stop Rx processing if once Rx buffer
allocation or DMA map load fails which in turn resulted in losing
incoming frames under heavy network load. With this change fxp(4)
should survive from resource shortage condition.
Fix some issues about re-scanning of the devices.
src/lib/libusb20/libusb20_ugen20.c
Fix issue about libusb20 having to release the
USB transfers before doing a SET_CONFIG, else
the kernel will kill the file handle.
src/sys/dev/usb2/core/usb2_device.
src/sys/dev/usb2/core/usb2_generic.c
src/sys/dev/usb2/core/usb2_generic.h
Add support for U3G devices.
Improve and cleanup FIFO free handling.
Improve device re-enumeration.
src/sys/dev/usb2/core/usb2_msctest.c
src/sys/dev/usb2/core/usb2_msctest.h
Fix some problems in the USB Mass Storage Test.
Add Huawei vendor specific quirks.
src/sys/dev/usb2/core/usb2_request.c
Improve device re-enumeration.
src/sys/dev/usb2/ethernet/if_aue2.c
src/sys/dev/usb2/include/usb2_devid.h
src/sys/dev/usb2/include/usb2_devtable.h
src/sys/dev/usb2/quirk/usb2_quirk.c
Integrate changes from the old USB driver.
src/sys/dev/usb2/include/usb2_standard.h
Add definition of USB3.0 structures from USB.org.
src/sys/dev/usb2/serial/u3g2.c
src/sys/dev/usb2/serial/ugensa2.c
src/sys/modules/usb2/Makefile
src/sys/modules/usb2/serial_3g/Makefile
Import U3G driver.
Submitted by: Hans Petter Selasky (usb4bsd)
many bugs fixes, many more performance improvements.
Submitted by: Danny Braniss
M sbin/iscontrol/iscsi.conf.5
M sbin/iscontrol/iscontrol.8
M sbin/iscontrol/iscontrol.h
M sbin/iscontrol/config.c
M sbin/iscontrol/fsm.c
M sbin/iscontrol/login.c
M sbin/iscontrol/pdu.c
M sbin/iscontrol/misc.c
M sbin/iscontrol/auth_subr.c
M sbin/iscontrol/iscontrol.c
M sys/dev/iscsi/initiator/isc_cam.c
M sys/dev/iscsi/initiator/iscsi.h
M sys/dev/iscsi/initiator/isc_soc.c
M sys/dev/iscsi/initiator/iscsi_subr.c
M sys/dev/iscsi/initiator/iscsivar.h
M sys/dev/iscsi/initiator/isc_subr.c
M sys/dev/iscsi/initiator/iscsi.c
M sys/dev/iscsi/initiator/isc_sm.c
IFF_DRV_OACTIVE to note resource shortage to upper stack.
- Don't count number of mbuf chains. Default 32 DMA segments for a
frame is enough for most cases. If bus_dmamap_mbuf_sg fails use
m_collapse(9) to collapse the mbuf chain instead of relying on
expensive m_defrag(9).
- Move bpf handling to fxp_start_body() which is supposed to be
more appropriate place.
- Always arm watchdog timer whenever a new Tx request is made.
Previously fxp(4) used to arm watchdog timer only when
FXP_CXINT_THRESH-th Tx request is made. Because fxp(4) does not
rely on Tx interrupt to reclaim transmitted mbufs it's better to
arm watchdog timer to detect potential lockups.
- Add more aggresive Tx buffer reclaiming in fxp_start_body to make
room for new Tx requests. Since fxp(4) does not request Tx
completion interrupt for every frames it's necessary to clean
TXCBs in advance to saturate link.
- Make fxp(4) try to start more packets transmitting regardless of
interrupt type in fxp_intr_body.
patch the RX/TX performance becomes about 17~18 Mbps comparing with
the previous whose values were RX 7~8Mbps and TX 13~14Mbps.
- improve AL2230 RF handling in zd1211b
- support AL2230S RF that PV2000 is renamed to AL2230S
- use register ZYD_CR244, ZYD_CR243, ZYD_CR242 when the driver writes
values on RF. This routine is more faster than the original one
- use private TX lock to avoid LOR at zyd_raw_xmit()
- increase TX slots from 1 to 5
- needs to set the channel at IEEE80211_S_AUTH not IEEE80211_S_RUN
- detailed error handling. In previous the next command was sent to the
device even if there was errors
- setting ZYD_MAC_RX_THRESHOLD value should be different between 1211
and 1211b
- only try to stop the device at zyd_init_locked() if the device is
UPed
- do not use MTX_RECURSE
- do not try to grap Giant lock when the channel is changing
- move the device initialization routines from zyd_attach to zyd_init to
give a device full-reset chance to the driver.
- code cleanup at zyd_raw_xmit()
- simplify zyd_attach() routines
- resort functions and clean up variables
- DPRINTF style change.
- style(9)
Reviewed by: sam
check to fxp_txeof(). While I'm here unarm watchdog timer only if
there are no pending queued Tx requests.
Previously the watchdog timer was unarmed whenever Tx interrupt is
raised. This could be resulted in hiding root cause of watchdog
timeouts.
checksum offload configuration. Now checksum offload can be
controlled by ifconfig(8).
While I'm here add an additional check for interface capabilities
before applying user's request.
nodes capabilities. Add "Analog"/"Digital" marks to the pcm device names.
I hope it will help new users easier accept concept of several PCM devices
and understand exact purposes of that devices.
