Commit graph

12 commits

Author SHA1 Message Date
Marius Strobl
8595e76a9f uart(4): Honor hardware state of NS8250-class for tsw_busy
In 9750d9e5, I brought the equivalent of the TS_BUSY flag back in a
mostly hardware-agnostic way in order to fix tty_drain() and, thus,
TIOCDRAIN for UARTs with TX FIFOs. This proved to be sufficient for
fixing the regression reported. So in light of the release cycle of
FreeBSD 10.3, I decided that this change was be good enough for the
time being and opted to go with the smallest possible yet generic
(for all UARTs driven by uart(4)) solution addressing the problem at
hand.

However, at least for the NS8250-class the above isn't a complete
fix as these UARTs only trigger an interrupt when the TX FIFO became
empty. At this point, there still can be an outstanding character
left in the transmit shift register as indicated via the LSR. Thus,
this change adds the 3rd (besides the tty(4) and generic uart(4) bits)
part I had in my tree ever since, adding a uart_txbusy method to be
queried in addition for tsw_busy and hooking it up as appropriate
for the NS8250-class.

As it turns out, the exact equivalent of this 3rd part later on was
implemented for uftdi(4) in 9ad221a5.

While at it, explain the rational behind the deliberately missing
locking in uart_tty_busy() (also applying to the generic sc_txbusy
testing already present).

(cherry picked from commit 353e4c5a06)
2024-01-18 21:14:46 +01:00
Warner Losh
685dc743dc sys: Remove $FreeBSD$: one-line .c pattern
Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
2023-08-16 11:54:36 -06:00
John Baldwin
c90ea83112 Remove unused uart_devclass. 2022-05-06 15:46:57 -07:00
Michal Meloun
b9cbd68d1c ARM: Enhance common Nvidia Tegra drivers by support for Tegra210 SoC.
MFC after:	4 weeks
2020-12-26 19:13:10 +01:00
Mateusz Guzik
654548838b arm: clean up empty lines in .c and .h files 2020-09-01 21:17:24 +00:00
Michal Meloun
3e13ea16a6 Fix grabbing of tegra uart.
An attempt to write to FCR register may corrupt transmit FIFO,
so we should wait for the FIFO to be empty before we can modify it.

MFC after:	1 week
2020-06-11 12:53:22 +00:00
Matt Macy
381388b9c4 add snps IP uart support / genaralize UART
This is an amalgam of a patch by Doug Ambrisko to
generalize uart_acpi_find_device, imp moving the
ACPI table to uart_dev_ns8250.c and advice by jhb
to work around a bug in the EPYC 3151 BIOS
(the BIOS incorrectly marks the serial ports as
disabled)

Reviewed by: imp
MFC after: 8 weeks
Differential Revision: https://reviews.freebsd.org/D16432
2018-08-19 21:10:21 +00:00
Ruslan Bukin
c214a270f5 Allow setting access-width for UART registers.
This is required for FDT's standard "reg-io-width" property
(similar to "reg-shift" property) found in many DTS files.

This fixes operation on Altera Arria 10 SOC Development Kit,
where standard ns8250 uart allows 4-byte access only.

Reviewed by:	kan, marcel
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D9785
2017-02-27 20:08:42 +00:00
Andrew Turner
df7675353e Stop including fdt_common.h from the arm code when it's unneeded.
Sponsored by:	ABT Systems Ltd
2016-11-14 11:41:22 +00:00
Michal Meloun
dac935533b EXTRES: Add OF node as argument to all <foo>_get_by_ofw_<bar>() functions.
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.

MFC after: 3 weeks
2016-07-10 18:28:15 +00:00
Michal Meloun
58872fc01a TEGRA: Fixes for UART driver:
- add mising 'or' in tegra_uart_attach()
   Pointed by: kan
 - fix indentation of tegra_softc
 - remove forgoten debug printf
2016-03-26 10:09:28 +00:00
Michal Meloun
ef2ee5d07a Import basic support for Nvidia Jetson TK1 board and tegra124 SoC.
The following pheripherals are supported: UART, MMC, AHCI, EHCI, PCIe, I2C,
PMIC, GPIO, CPU temperature and clock.

Note: The PCIe driver is pure mash at this moment. It will be reworked
immediately when both D5237 and D2579 enter the current tree.
2016-03-16 13:01:48 +00:00