upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-04-23 23:28:37 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

ixl(4): Fix queue MSI and legacy IRQ rearming

Browse source 
When MSI or legacy interrupt is used driver controls wheter
queues can trigger an interrupt with the Interrupt Linked List.
While processing traffic first index of the list is set to EOL
value to stop queues from triggering interrupts. This index was
not reset to the correct value when driver attempted to re-enable
interrupts from queues, what prevented driver from processing any
traffic. Fix that by setting correct first index in the
ixl_if_enable_intr function.

While at that fix the comments style and make ixl_if_enable_intr
and ixl_if_disable_intr more consistent.

Signed-off-by: Krzysztof Galazka <krzysztof.galazka@intel.com>

PR:		288077
Suggested by:	Mike Belanger <mibelanger@qnx.com>
Approved by:	kbowling (mentor), erj (mentor)
Tested by:	gowtham.kumar.ks_intel.com,
Sponsored by:	Intel Corporation
Differential Revision:	https://reviews.freebsd.org/D51331

(cherry picked from commit 6f41c1fc39d9fa9db989a7b4f325c3ab85b8fb45)
This commit is contained in:
Krzysztof Galazka 2025-08-19 14:50:33 +02:00 committed by Franco Fichtner
parent 1c7ba3ae76
commit ffe852bafb
1 changed files with 17 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
sys/dev/ixl/if_ixl.c
View file

@ -1151,13 +1151,20 @@ ixl_if_enable_intr(if_ctx_t ctx)
struct ixl_pf *pf = iflib_get_softc(ctx);
struct ixl_vsi *vsi = &pf->vsi;
struct i40e_hw *hw = vsi->hw;
struct ixl_rx_queue *que = vsi->rx_queues;
struct ixl_rx_queue *rx_que = vsi->rx_queues;
ixl_enable_intr0(hw);
/* Enable queue interrupts */
for (int i = 0; i < vsi->num_rx_queues; i++, que++)
/* TODO: Queue index parameter is probably wrong */
ixl_enable_queue(hw, que->rxr.me);
if (vsi->shared->isc_intr == IFLIB_INTR_MSIX) {
for (int i = 0; i < vsi->num_rx_queues; i++, rx_que++)
ixl_enable_queue(hw, rx_que->rxr.me);
} else {
/*
* Set PFINT_LNKLST0 FIRSTQ_INDX to 0x0 to enable
* triggering interrupts by queues.
*/
wr32(hw, I40E_PFINT_LNKLST0, 0x0);
}
}
/*
@ -1175,11 +1182,13 @@ ixl_if_disable_intr(if_ctx_t ctx)
if (vsi->shared->isc_intr == IFLIB_INTR_MSIX) {
for (int i = 0; i < vsi->num_rx_queues; i++, rx_que++)
ixl_disable_queue(hw, rx_que->msix - 1);
ixl_disable_queue(hw, rx_que->rxr.me);
} else {
// Set PFINT_LNKLST0 FIRSTQ_INDX to 0x7FF
// stops queues from triggering interrupts
wr32(hw, I40E_PFINT_LNKLST0, 0x7FF);
/*
* Set PFINT_LNKLST0 FIRSTQ_INDX to End of List (0x7FF)
* to stop queues from triggering interrupts.
*/
wr32(hw, I40E_PFINT_LNKLST0, IXL_QUEUE_EOL);
}
}