From ff7824ff5299ce6aa6e7356f1417004ccf5ce0b9 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Wed, 16 Oct 2013 02:46:00 +0000 Subject: [PATCH] Add in a write barrier after each if_arge write. Without correct barriers, this code just plain doesn't work on the mips74k cores (specifically the AR9344.) In particular, the MDIO register accesses need this barriering or MII bus access results in out-of-order garbage. Tested: * AR9344 (mips74k) * AR9331 (mips24k) --- sys/mips/atheros/if_argevar.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/sys/mips/atheros/if_argevar.h b/sys/mips/atheros/if_argevar.h index 9add6740ec1..0e934e7c603 100644 --- a/sys/mips/atheros/if_argevar.h +++ b/sys/mips/atheros/if_argevar.h @@ -55,10 +55,17 @@ /* * register space access macros */ +#define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_READ) +#define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_WRITE) +#define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_READ | \ + BUS_SPACE_BARRIER_WRITE) #define ARGE_WRITE(sc, reg, val) do { \ bus_write_4(sc->arge_res, (reg), (val)); \ + ARGE_BARRIER_WRITE((sc)); \ } while (0) - #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg)) #define ARGE_SET_BITS(sc, reg, bits) \ @@ -71,6 +78,9 @@ ARGE_WRITE((_sc), (_reg), (_val)) #define ARGE_MDIO_READ(_sc, _reg) \ ARGE_READ((_sc), (_reg)) +#define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc) +#define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc) +#define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_READ_RW(_sc) #define ARGE_DESC_EMPTY (1 << 31) #define ARGE_DESC_MORE (1 << 24)