From fa60dcbea4cb54e3d794d55098227925738f4fe0 Mon Sep 17 00:00:00 2001 From: Jake Burkholder Date: Tue, 1 Jan 2002 21:14:58 +0000 Subject: [PATCH] Enable virtual caching for kernel pages. When we enabled virtual caching for certain user pages, stores to kernel pages would not update the affected cache lines, which would sometimes cause the wrong data to be returned for loads from kernel pages. This was especially fatal when the addresses affected held the kernel stack pointer, and a random value was loaded into it. Fix a harmless off by one error in a dcache_inval_phys call. --- sys/sparc64/sparc64/pmap.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/sparc64/sparc64/pmap.c b/sys/sparc64/sparc64/pmap.c index 723bd46da5d..a71b05ec082 100644 --- a/sys/sparc64/sparc64/pmap.c +++ b/sys/sparc64/sparc64/pmap.c @@ -276,7 +276,7 @@ pmap_bootstrap(vm_offset_t ekva) va = (vm_offset_t)tsb_kernel + i * PAGE_SIZE_4M; tte.tte_tag = TT_CTX(TLB_CTX_KERNEL) | TT_VA(va); tte.tte_data = TD_V | TD_4M | TD_VA_LOW(va) | TD_PA(pa) | - TD_L | TD_CP | TD_P | TD_W; + TD_L | TD_CP | TD_CV | TD_P | TD_W; tlb_store_slot(TLB_DTLB, va, TLB_CTX_KERNEL, tte, TLB_SLOT_TSB_KERNEL_MIN + i); } @@ -523,7 +523,7 @@ pmap_cache_enter(vm_page_t m, vm_offset_t va) } } pa = VM_PAGE_TO_PHYS(m); - dcache_inval_phys(pa, pa + PAGE_SIZE); + dcache_inval_phys(pa, pa + PAGE_SIZE - 1); return (0); } @@ -550,7 +550,7 @@ pmap_kenter(vm_offset_t va, vm_offset_t pa) tte.tte_tag = TT_CTX(TLB_CTX_KERNEL) | TT_VA(va); tte.tte_data = TD_V | TD_8K | TD_VA_LOW(va) | TD_PA(pa) | - TD_REF | TD_SW | TD_CP | TD_P | TD_W; + TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W; tp = tsb_kvtotte(va); CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx", va, pa, tp, tp->tte_data);