From f8fb3cc00e8be0c0d61bfec33ce513fa9f9f02b3 Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Tue, 18 Aug 2009 20:25:02 +0000 Subject: [PATCH] MFC r196366: Backout r193289. r193289 restored page select bits to previous value instead of blindly resetting it to 0. However, it seems page select bits of some 88E1116 PHY is initialized to invalid one such that restoring page select bits after programming broke MII register access. The correct solution would be reset page select bits to 0 in PHY attach stage but it would require more testing. Since we're in BETA stage such a change would be dangerous so just back it out. This change should fix nfe(4) breakage on NVIDIA MCP55. Reported by: Ryan Rogers < webmaster <> doghouserepair dot com > Sam Fourman Jr. < sfourman <> gmail dot com > Tested by: Ryan Rogers < webmaster <> doghouserepair dot com > Sam Fourman Jr. < sfourman <> gmail dot com > Approved by: re (kib) --- sys/dev/mii/e1000phy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/sys/dev/mii/e1000phy.c b/sys/dev/mii/e1000phy.c index f0d159bbaca..4f2fa66f6e8 100644 --- a/sys/dev/mii/e1000phy.c +++ b/sys/dev/mii/e1000phy.c @@ -240,13 +240,11 @@ e1000phy_reset(struct mii_softc *sc) if (esc->mii_model == MII_MODEL_MARVELL_E1116 || esc->mii_model == MII_MODEL_MARVELL_E1149) { - page = PHY_READ(sc, E1000_EADR); - /* Select page 2, MAC specific control register. */ PHY_WRITE(sc, E1000_EADR, 2); reg = PHY_READ(sc, E1000_SCR); reg |= E1000_SCR_RGMII_POWER_UP; PHY_WRITE(sc, E1000_SCR, reg); - PHY_WRITE(sc, E1000_EADR, page); + PHY_WRITE(sc, E1000_EADR, 0); } }