upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-05-28 04:12:45 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Implement the lock with a cmpxchg instruction instead of a xchg.

Browse source 
Both are atomic, but the cmpxchg has memory ordering hints. We
give this acquire semantics.

NOTE: The unlock in libc_r is implemented by a "normal" assign
statement. This is not correct on ia64 due to the memory ordering
characteristics of the architecture. We need release semantics
for an unlock.
This commit is contained in:
Marcel Moolenaar 2002-11-16 17:05:06 +00:00
parent ecc935018a
commit f8739dd5f9
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
lib/libc_r/arch/ia64/_atomic_lock.S
View file

@ -38,11 +38,12 @@
* is not currently locked.
*
* long _atomic_lock(long *);
* eax will contain the return value (zero if lock obtained).
*/
ENTRY(_atomic_lock, 1)
mov ar.ccv = r0
add r14 = 1, r0
nop 0
;;
xchg8 r8 = [r32], r14
cmpxchg8.acq r8 = [r32], r14, ar.ccv
br.ret.sptk rp
END(_atomic_lock)