From f704d346770e52195dde4e85d37624859c58d890 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 17 Sep 2003 02:58:17 +0000 Subject: [PATCH] Fix a typo in r1.8: The GTLB enable/flush bit is 1<<7, not 1<<8. PR: kern/56297 Submitted by: Dan Angelescu --- sys/dev/agp/agp_intel.c | 2 +- sys/pci/agp_intel.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/dev/agp/agp_intel.c b/sys/dev/agp/agp_intel.c index 84fd071ee87..047ed570ab9 100644 --- a/sys/dev/agp/agp_intel.c +++ b/sys/dev/agp/agp_intel.c @@ -373,7 +373,7 @@ agp_intel_flush_tlb(device_t dev) u_int32_t val; val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); - pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); + pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); } diff --git a/sys/pci/agp_intel.c b/sys/pci/agp_intel.c index 84fd071ee87..047ed570ab9 100644 --- a/sys/pci/agp_intel.c +++ b/sys/pci/agp_intel.c @@ -373,7 +373,7 @@ agp_intel_flush_tlb(device_t dev) u_int32_t val; val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); - pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); + pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); }