mirror of
https://github.com/opnsense/src.git
synced 2026-06-09 08:43:19 -04:00
apuled: import APU 1-3 LED kernel module
Taken from: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=189772 PR: https://github.com/opnsense/core/issues/2114
This commit is contained in:
Franco Fichtner
parent
1283790d68
commit
f3a6d39cc4
3 changed files with 691 additions and 0 deletions
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@ -38,6 +38,7 @@ SUBDIR= \
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${_amdsmn} \
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${_amdtemp} \
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${_aout} \
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${_apuled} \
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${_arcmsr} \
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${_allwinner} \
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${_armv8crypto} \
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@ -715,6 +716,7 @@ _agp= agp
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.if ${MACHINE_CPUARCH} == "i386" || !empty(COMPAT_FREEBSD32_ENABLED)
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_aout= aout
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.endif
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_apuled= apuled
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_bios= bios
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.if ${MK_SOURCELESS_UCODE} != "no"
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_bxe= bxe
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4
sys/modules/apuled/Makefile
Normal file
4
sys/modules/apuled/Makefile
Normal file
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@ -0,0 +1,4 @@
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KMOD= apuled
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SRCS= apuled.c device_if.h bus_if.h isa_if.h pci_if.h
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.include <bsd.kmod.mk>
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685
sys/modules/apuled/apuled.c
Normal file
685
sys/modules/apuled/apuled.c
Normal file
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@ -0,0 +1,685 @@
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/*-
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* Copyright (c) 2014-2017 Larry Baird
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* All rights reserved.
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*
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* Feedback provided by Ermal Luci.
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*
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* Used information from daduke's linux driver (https://daduke.org/linux/apu2)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/priv.h>
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#include <sys/types.h>
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#include <sys/uio.h>
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#include <sys/proc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <x86/bus.h>
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#include <isa/isavar.h>
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#include <dev/led/led.h>
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static struct mtx gpio_lock;
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MTX_SYSINIT(gpio_lock, &gpio_lock, "gpio lock", MTX_SPIN);
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/*
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* Basic idea is to create two MMIO memory resources. One for LEDs and
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* one for button on front of APU. Then create a device for each LED and
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* the button. On an apu3 also create a device for switch for switching SIMs.
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*/
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/* See dev/amdsbwd/amdsbwd.c for magic numbers for southbridges */
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/* SB7xx RRG 2.3.3.1.1. */
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#define AMDSB_PMIO_INDEX 0xcd6
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#define AMDSB_PMIO_DATA (PMIO_INDEX + 1)
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#define AMDSB_PMIO_WIDTH 2
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#define AMDSB_SMBUS_DEVID 0x43851002
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#define AMDFCH_SMBUS_DEVID 0x780b1022
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/* SB8xx RRG 2.3.7. */
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#define AMDSB8_MMIO_BASE_ADDR_FIND 0x24
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/* Here are some magic numbers from APU1 BIOS. */
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#define SB_GPIO_OFFSET 0x100
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#define GPIO_187 187 // APU1 MODESW
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#define GPIO_188 188 // APU1 Unknown ??
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#define GPIO_189 189 // APU1 LED1#
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#define GPIO_190 190 // APU1 LED2#
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#define GPIO_191 191 // APU1 LED3#
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#define SB_GPIO_ON 0x08
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#define SB_GPIO_OFF 0xC8
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/* Here are some magic numbers for APU2. */
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#define AMDFCH41_MMIO_ADDR 0xfed80000u
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#define FCH_GPIO_OFFSET 0x1500
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#define FCH_GPIO_BASE (AMDFCH41_MMIO_ADDR + FCH_GPIO_OFFSET)
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#define FCH_GPIO_SIZE 0x300
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#define FCH_GPIO_BIT_WRITE 22
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#define FCH_GPIO_BIT_READ 16
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#define FCH_GPIO_BIT_DIR 23
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#define GPIO_68 68 // APU2/3 LED1#
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#define GPIO_69 69 // APU2/3 LED2#
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#define GPIO_70 70 // APU2/3 LED3#
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#define GPIO_89 89 // APU2/3 MODESW
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#define GPIO_90 90 // APU3 SIM switcher
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struct apu_cdev {
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struct resource *res;
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bus_size_t offset;
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struct cdev *cdev;
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uint32_t devid;
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};
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struct apu_rid {
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int rid;
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int rid_type;
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struct resource *res;
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};
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struct apu_softc {
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int sc_model;
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uint32_t sc_devid;
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struct apu_rid sc_rid[2];
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# define IDX_RID_LED 0
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# define IDX_RID_MODESW 1
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struct apu_cdev sc_led[3];
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struct apu_cdev sc_sw[2];
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# define IDX_SW_MODE 0
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# define IDX_SW_SIM 1
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};
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/*
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* Mode switch methods.
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*/
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static int sw_open(struct cdev *dev, int flags, int fmt, struct thread *td);
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static int sw_close(struct cdev *dev, int flags, int fmt, struct thread *td);
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static int sw_read(struct cdev *dev, struct uio *uio, int ioflag);
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static int sw_write(struct cdev *dev, struct uio *uio, int ioflag);
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static void
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apu_led_callback(void *ptr, int onoff);
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static struct cdevsw modesw_cdev = {
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.d_version = D_VERSION,
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.d_open = sw_open,
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.d_read = sw_read,
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.d_close = sw_close,
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.d_name = "modesw",
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};
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static struct cdevsw simsw_cdev = {
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.d_version = D_VERSION,
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.d_open = sw_open,
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.d_read = sw_read,
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.d_write = sw_write,
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.d_close = sw_close,
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.d_name = "simsw",
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};
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static int
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hw_is_apu( void )
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{
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int apu = 0;
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char *maker;
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char *product;
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maker = kern_getenv("smbios.system.maker");
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if (maker != NULL) {
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if (strcasecmp("PC Engines", maker) == 0) {
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product = kern_getenv("smbios.system.product");
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if (product != NULL) {
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if (strcasecmp("APU", product) == 0)
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apu = 1;
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else if (strcasecmp("apu2", product) == 0)
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apu = 2;
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else if (strcasecmp("apu3", product) == 0)
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apu = 3;
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else if (strcasecmp("apu4", product) == 0)
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apu = 4;
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freeenv(product);
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}
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}
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freeenv(maker);
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}
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return (apu);
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}
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static void
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sb_gpio_write( struct resource *res, bus_size_t offset, int active )
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{
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u_int8_t value;
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value = bus_read_1(res, offset);
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if (active)
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value = SB_GPIO_ON;
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else
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value = SB_GPIO_OFF;
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bus_write_1(res, offset, value);
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}
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static char
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sb_gpio_read( struct resource *res, bus_size_t offset )
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{
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uint8_t value;
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char ch;
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/* Is mode switch pressed? */
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value = bus_read_1(res, offset);
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if (value == 0x28 )
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ch = '1';
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else
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ch = '0';
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return (ch);
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}
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/*
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* gpio methods.
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*/
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static void
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fch_gpio_dir_set( struct resource *res, bus_size_t offset, int out )
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{
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u_int32_t value;
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u_int32_t dir_bit = 1 << FCH_GPIO_BIT_DIR;
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value = bus_read_4(res, offset);
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if (out)
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value |= dir_bit;
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else
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value &= ~dir_bit;
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bus_write_4(res, offset, value);
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}
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static char
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fch_gpio_read( struct resource *res, bus_size_t offset )
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{
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uint32_t value;
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char ch;
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u_int32_t read_bit = 1 << FCH_GPIO_BIT_READ;
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/* Is mode switch pressed? */
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value = bus_read_4(res, offset);
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if (!(value & read_bit))
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ch = '1';
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else
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ch = '0';
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return (ch);
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}
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static void
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fch_gpio_write( struct resource *res, bus_size_t offset, int active )
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{
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u_int32_t value;
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u_int32_t write_bit = 1 << FCH_GPIO_BIT_WRITE;
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value = bus_read_4(res, offset);
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if (active)
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value &= ~write_bit;
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else
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value |= write_bit;
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bus_write_4(res, offset, value);
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}
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/* Check to see if this is an APU board we support? */
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static void
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apuled_identify(driver_t *driver, device_t parent)
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{
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device_t child;
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device_t smb;
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uint32_t devid;
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if (resource_disabled("apuled", 0))
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return;
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if (device_find_child(parent, "apuled", -1) != NULL)
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return;
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/* Do was have expected south bridge chipset? */
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smb = pci_find_bsf(0, 20, 0);
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if (smb == NULL)
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return;
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devid = pci_get_devid(smb);
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switch (hw_is_apu()) {
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case 1:
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if (devid != AMDSB_SMBUS_DEVID)
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return;
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break;
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case 2:
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case 3:
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case 4:
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if (devid != AMDFCH_SMBUS_DEVID)
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return;
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break;
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default:
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return;
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}
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/* Everything looks good, enable probe */
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child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "apuled", -1);
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if (child == NULL)
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device_printf(parent, "apuled: bus add child failed\n");
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}
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static int
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apu_probe_sb(device_t dev, struct apu_softc *sc)
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{
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struct resource *res;
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int rc;
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uint32_t gpio_mmio_base;
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int rid;
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int i;
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/* Find the ACPImmioAddr base address */
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rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
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AMDSB_PMIO_WIDTH);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for MMIO failed\n");
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return (ENXIO);
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}
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rid = 0;
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res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0ul, ~0ul,
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AMDSB_PMIO_WIDTH, RF_ACTIVE | RF_SHAREABLE);
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if (res == NULL) {
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device_printf(dev, "bus_alloc_resource for MMIO failed.\n");
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return (ENXIO);
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}
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/* Find base address of memory mapped WDT registers. */
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/* This will probable be 0xfed80000 */
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for (gpio_mmio_base = 0, i = 0; i < 4; i++) {
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gpio_mmio_base <<= 8;
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bus_write_1(res, 0, AMDSB8_MMIO_BASE_ADDR_FIND + 3 - i);
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gpio_mmio_base |= bus_read_1(res, 1);
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}
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gpio_mmio_base &= ~0x07u;
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if (bootverbose)
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device_printf(dev, "MMIO base adddress 0x%x\n", gpio_mmio_base);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
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bus_delete_resource(dev, SYS_RES_IOPORT, rid);
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/* Set memory resource for LEDs. */
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 0,
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gpio_mmio_base + SB_GPIO_OFFSET + GPIO_189,
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(GPIO_191 - GPIO_189) + 1);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for LEDs failed\n");
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return (ENXIO);
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}
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/* Set memory resource for switches. */
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 1,
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gpio_mmio_base + SB_GPIO_OFFSET + GPIO_187, 1);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for switches failed\n");
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return (ENXIO);
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}
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return (0);
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}
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static int
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apu_probe_fch(device_t dev, struct apu_softc *sc)
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{
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int rc;
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u_long count;
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/* Set memory resource for LEDs. */
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 0,
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FCH_GPIO_BASE + (GPIO_68 * sizeof(uint32_t)),
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((GPIO_70 - GPIO_68) + 1) * sizeof(uint32_t) );
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for LEDs failed\n");
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return (ENXIO);
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}
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/* Set memory resource for switches. */
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if (sc->sc_model == 3)
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count = sizeof(uint32_t) * 2;
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else
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count = sizeof(uint32_t);
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 1,
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FCH_GPIO_BASE + (GPIO_89 * sizeof(uint32_t)), count );
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for switches failed\n");
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return (ENXIO);
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}
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return (0);
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}
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/*
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* APU LED device methods.
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*/
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static int
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apuled_probe(device_t dev)
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{
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int error;
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char buf[100];
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struct apu_softc *sc = device_get_softc(dev);
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device_t smb;
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/* Make sure we do not claim some ISA PNP device. */
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if (isa_get_logicalid(dev) != 0)
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return (ENXIO);
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sc->sc_model = hw_is_apu();
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if (sc->sc_model == 0)
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return (ENXIO);
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smb = pci_find_bsf(0, 20, 0);
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if (smb == NULL)
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return (ENXIO);
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sc->sc_devid = pci_get_devid(smb);
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snprintf(buf, sizeof(buf), "APU%d", sc->sc_model);
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device_set_desc_copy(dev, buf );
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switch( sc->sc_devid ) {
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case AMDSB_SMBUS_DEVID:
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error = apu_probe_sb(dev, sc);
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if (error)
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return error;
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break;
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case AMDFCH_SMBUS_DEVID:
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error = apu_probe_fch(dev, sc);
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if (error)
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return error;
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break;
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default: /* Should never reach here. */
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device_printf(dev, "Unexpected APU south bridge\n" );
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return (ENXIO);
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break;
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}
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return (0);
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}
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static int
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apuled_attach(device_t dev)
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{
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struct apu_softc *sc = device_get_softc(dev);
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int i;
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int j;
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for (i = 0; i < sizeof(sc->sc_rid)/sizeof(sc->sc_rid[0]); i++) {
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sc->sc_rid[i].res = NULL;
|
||||
sc->sc_rid[i].rid_type = SYS_RES_MEMORY;
|
||||
sc->sc_rid[i].rid = i;
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_rid)/sizeof(sc->sc_rid[0]); i++) {
|
||||
sc->sc_rid[i].res = bus_alloc_resource_any( dev,
|
||||
sc->sc_rid[i].rid_type, &sc->sc_rid[i].rid,
|
||||
RF_ACTIVE | RF_SHAREABLE);
|
||||
if (sc->sc_rid[i].res == NULL) {
|
||||
device_printf( dev, "Unable to allocate memory region %d\n", i );
|
||||
for (j = 0; j < i; j++) {
|
||||
bus_release_resource(dev, sc->sc_rid[j].rid_type,
|
||||
sc->sc_rid[j].rid, sc->sc_rid[j].res);
|
||||
sc->sc_rid[j].res = NULL;
|
||||
bus_delete_resource(dev, sc->sc_rid[i].rid_type,
|
||||
sc->sc_rid[i].rid );
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
}
|
||||
|
||||
if (sc->sc_devid == AMDFCH_SMBUS_DEVID)
|
||||
fch_gpio_dir_set( sc->sc_rid[IDX_RID_MODESW].res, 0, FALSE );
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_sw)/sizeof(sc->sc_sw[0]); i++)
|
||||
sc->sc_sw[i].cdev = NULL;
|
||||
|
||||
sc->sc_sw[IDX_SW_MODE].cdev = make_dev(&modesw_cdev, 0, UID_ROOT,
|
||||
GID_WHEEL, 0440, "modesw");
|
||||
if (sc->sc_sw[IDX_SW_MODE].cdev == NULL) {
|
||||
device_printf( dev, "Unable to make modesw\n" );
|
||||
} else {
|
||||
sc->sc_sw[IDX_SW_MODE].cdev->si_drv1 = &sc->sc_sw[IDX_SW_MODE];
|
||||
sc->sc_sw[IDX_SW_MODE].res = sc->sc_rid[IDX_RID_MODESW].res;
|
||||
sc->sc_sw[IDX_SW_MODE].offset = 0;
|
||||
sc->sc_sw[IDX_SW_MODE].devid = sc->sc_devid;
|
||||
}
|
||||
|
||||
if (sc->sc_model == 3) {
|
||||
sc->sc_sw[IDX_SW_SIM].cdev = make_dev(&simsw_cdev, 0, UID_ROOT,
|
||||
GID_WHEEL, 0440, "simsw");
|
||||
if (sc->sc_sw[IDX_SW_SIM].cdev == NULL) {
|
||||
device_printf( dev, "Unable to make simsw\n" );
|
||||
} else {
|
||||
sc->sc_sw[IDX_SW_SIM].cdev->si_drv1 = &sc->sc_sw[IDX_SW_SIM];
|
||||
sc->sc_sw[IDX_SW_SIM].res = sc->sc_rid[IDX_RID_MODESW].res;
|
||||
sc->sc_sw[IDX_SW_SIM].offset = sizeof(uint32_t);
|
||||
sc->sc_sw[IDX_SW_SIM].devid = sc->sc_devid;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_led)/sizeof(sc->sc_led[0]); i++) {
|
||||
char name[30];
|
||||
|
||||
snprintf( name, sizeof(name), "led%d", i + 1 );
|
||||
|
||||
sc->sc_led[i].res = sc->sc_rid[IDX_RID_LED].res;
|
||||
sc->sc_led[i].devid = sc->sc_devid;
|
||||
|
||||
switch (sc->sc_devid) {
|
||||
case AMDSB_SMBUS_DEVID:
|
||||
sc->sc_led[i].offset = i;
|
||||
break;
|
||||
case AMDFCH_SMBUS_DEVID:
|
||||
sc->sc_led[i].offset = i * sizeof(uint32_t);
|
||||
fch_gpio_dir_set(sc->sc_led[i].res,
|
||||
sc->sc_led[i].offset, TRUE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Make sure power LED stays on by default */
|
||||
sc->sc_led[i].cdev = led_create_state(apu_led_callback,
|
||||
&sc->sc_led[i], name, i == 0);
|
||||
|
||||
if (sc->sc_led[i].cdev == NULL)
|
||||
device_printf(dev, "%s creation failed\n", name);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
apuled_detach(device_t dev)
|
||||
{
|
||||
struct apu_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_led)/sizeof(sc->sc_led[0]); i++)
|
||||
if (sc->sc_led[i].cdev != NULL) {
|
||||
/* Restore LEDs to stating state */
|
||||
if (i == 0)
|
||||
apu_led_callback(&sc->sc_led[i], TRUE);
|
||||
else
|
||||
apu_led_callback(&sc->sc_led[i], FALSE);
|
||||
|
||||
led_destroy(sc->sc_led[i].cdev);
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_sw)/sizeof(sc->sc_sw[0]); i++)
|
||||
if (sc->sc_sw[i].cdev != NULL)
|
||||
destroy_dev(sc->sc_sw[i].cdev);
|
||||
|
||||
for (i = 0; i < sizeof(sc->sc_rid)/sizeof(sc->sc_rid[0]); i++) {
|
||||
if (sc->sc_rid[i].res != NULL) {
|
||||
bus_release_resource(dev, sc->sc_rid[i].rid_type,
|
||||
sc->sc_rid[i].rid, sc->sc_rid[i].res);
|
||||
bus_delete_resource(dev, sc->sc_rid[i].rid_type,
|
||||
sc->sc_rid[i].rid );
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sw_open(struct cdev *dev __unused, int flags __unused, int fmt __unused,
|
||||
struct thread *td)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = priv_check(td, PRIV_IO);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
error = securelevel_gt(td->td_ucred, 0);
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
sw_read(struct cdev *dev, struct uio *uio, int ioflag) {
|
||||
struct apu_cdev *sw = (struct apu_cdev *)dev->si_drv1;
|
||||
char ch = '0';
|
||||
int error;
|
||||
|
||||
mtx_lock_spin(&gpio_lock);
|
||||
|
||||
switch (sw->devid) {
|
||||
case AMDSB_SMBUS_DEVID:
|
||||
ch = sb_gpio_read( sw->res, sw->offset );
|
||||
break;
|
||||
case AMDFCH_SMBUS_DEVID:
|
||||
fch_gpio_dir_set( sw->res, sw->offset, FALSE );
|
||||
ch = fch_gpio_read( sw->res, sw->offset );
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mtx_unlock_spin(&gpio_lock);
|
||||
|
||||
error = uiomove(&ch, sizeof(ch), uio);
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
sw_write(struct cdev *dev, struct uio *uio, int ioflag) {
|
||||
struct apu_cdev *sw = (struct apu_cdev *)dev->si_drv1;
|
||||
char ch;
|
||||
int error;
|
||||
|
||||
error = uiomove(&ch, sizeof(ch), uio);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
mtx_lock_spin(&gpio_lock);
|
||||
|
||||
switch (sw->devid) {
|
||||
case AMDSB_SMBUS_DEVID:
|
||||
break;
|
||||
case AMDFCH_SMBUS_DEVID:
|
||||
fch_gpio_dir_set( sw->res, sw->offset, TRUE );
|
||||
fch_gpio_write(sw->res, sw->offset, ch);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mtx_unlock_spin(&gpio_lock);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sw_close(struct cdev *dev __unused, int flags __unused, int fmt __unused,
|
||||
struct thread *td __unused)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
apu_led_callback(void *ptr, int onoff)
|
||||
{
|
||||
struct apu_cdev *led = (struct apu_cdev *)ptr;
|
||||
|
||||
mtx_lock_spin(&gpio_lock);
|
||||
|
||||
switch (led->devid) {
|
||||
case AMDSB_SMBUS_DEVID:
|
||||
sb_gpio_write( led->res, led->offset, onoff );
|
||||
break;
|
||||
case AMDFCH_SMBUS_DEVID:
|
||||
fch_gpio_write( led->res, led->offset, onoff );
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
mtx_unlock_spin(&gpio_lock);
|
||||
}
|
||||
|
||||
static device_method_t apuled_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, apuled_probe),
|
||||
DEVMETHOD(device_attach, apuled_attach),
|
||||
DEVMETHOD(device_detach, apuled_detach),
|
||||
DEVMETHOD(device_identify, apuled_identify),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t apuled_driver = {
|
||||
"apuled",
|
||||
apuled_methods,
|
||||
sizeof(struct apu_softc),
|
||||
};
|
||||
|
||||
DRIVER_MODULE(apuled, isa, apuled_driver, 0, 0);
|
||||
Loading…
Reference in a new issue