From f3075be88ac8a3b7db7c4e49c01097eb85dc4729 Mon Sep 17 00:00:00 2001
From: Peter Wemm <peter@FreeBSD.org>
Date: Sat, 25 Oct 2003 18:51:41 +0000
Subject: [PATCH] For the SMP case, flush the TLB at the beginning of the page
 zero/copy routines.  Otherwise we run into trouble with speculative tlb
 preloads on SMP systems.  This effectively defeats Jeff's revision 1.438
 optimization (for his pentium4-M laptop) in the SMP case.  It breaks other
 systems, particularly athlon-MP's.

---
 sys/i386/i386/pmap.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/sys/i386/i386/pmap.c b/sys/i386/i386/pmap.c
index f78e3ebd8a1..c908fa61542 100644
--- a/sys/i386/i386/pmap.c
+++ b/sys/i386/i386/pmap.c
@@ -2389,6 +2389,9 @@ pmap_zero_page(vm_page_t m)
 	curthread->td_pcb->pcb_switchout = pmap_zpi_switchout2;
 #endif
 	*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
+#ifdef SMP
+	invlpg((u_int)CADDR2);
+#endif
 	pagezero(CADDR2);
 	*CMAP2 = 0;
 	invlcaddr(CADDR2);
@@ -2415,6 +2418,9 @@ pmap_zero_page_area(vm_page_t m, int off, int size)
 	curthread->td_pcb->pcb_switchout = pmap_zpi_switchout2;
 #endif
 	*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
+#ifdef SMP
+	invlpg((u_int)CADDR2);
+#endif
 	if (off == 0 && size == PAGE_SIZE) 
 		pagezero(CADDR2);
 	else
@@ -2443,6 +2449,9 @@ pmap_zero_page_idle(vm_page_t m)
 	curthread->td_pcb->pcb_switchout = pmap_zpi_switchout3;
 #endif
 	*CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M;
+#ifdef SMP
+	invlpg((u_int)CADDR3);
+#endif
 	pagezero(CADDR3);
 	*CMAP3 = 0;
 	invlcaddr(CADDR3);
@@ -2471,6 +2480,10 @@ pmap_copy_page(vm_page_t src, vm_page_t dst)
 #endif
 	*CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A;
 	*CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M;
+#ifdef SMP
+	invlpg((u_int)CADDR1);
+	invlpg((u_int)CADDR2);
+#endif
 	bcopy(CADDR1, CADDR2, PAGE_SIZE);
 	*CMAP1 = 0;
 	*CMAP2 = 0;