From f16f1caffcc44f8d4c335541e2fc8a42f091bc9f Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Tue, 31 Mar 2009 01:59:47 +0000 Subject: [PATCH] Hmmmm... This can't be right... But it looks like the DL100xx chips don't have one of the clock cycles (the turn cycle) that the AX88x90 chips have. Make this conditional. But this seems totally crazy and can't possibly be right. Commit the fix for the moment until I can explore this mystery more deeply. On the plus side, the DL10022-based cards I have (D-Link DEF-670TXD and SMC8040TX) work after this fix. --- sys/dev/ed/if_ed_pccard.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sys/dev/ed/if_ed_pccard.c b/sys/dev/ed/if_ed_pccard.c index 05c5c07cfbb..924cc833adb 100644 --- a/sys/dev/ed/if_ed_pccard.c +++ b/sys/dev/ed/if_ed_pccard.c @@ -1115,7 +1115,9 @@ ed_miibus_readreg(device_t dev, int phy, int reg) (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); - (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); + if (sc->chip_type == ED_CHIP_TYPE_AX88790 || + sc->chip_type == ED_CHIP_TYPE_AX88190) + (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);