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powerpc64: clear low-order bits of ARPN

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PowerISA 2.07B says that the low-order p-12 bits of the real page number
contained in ARPN and LP fields of a PTE must be 0s and are ignored
by the hardware (Book III-S, 5.7.7.1), where 2^p is the actual page size
in bytes, but we were clearing only the LP field.

This worked on bare metal and QEMU with KVM, that ignore these bits,
but caused a kernel panic on QEMU with TCG, that expects them to be
cleared.

This fixes running FreeBSD with HPT superpages enabled on QEMU
with TCG.

Sponsored by:	Eldorado Research Institute (eldorado.org.br)

(cherry picked from commit 3d0399c718)
This commit is contained in:
Leandro Lupori 2021-03-25 13:30:56 -03:00
parent 0e0aa1eed8
commit f05174ed35
1 changed files with 2 additions and 2 deletions
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4
sys/powerpc/aim/mmu_oea64.c
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@ -3719,7 +3719,7 @@ moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
pvo = pvos[i];
pvo->pvo_pte.prot = prot;
pvo->pvo_pte.pa = (pa & ~LPTE_LP_MASK) | LPTE_LP_4K_16M |
pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M |
moea64_calc_wimg(pa, pmap_page_get_memattr(m));
if ((flags & PMAP_ENTER_WIRED) != 0)
@ -3876,7 +3876,7 @@ moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m)
for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE;
pvo != NULL && PVO_VADDR(pvo) < va_end;
pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) {
pvo->pvo_pte.pa &= ~LPTE_LP_MASK;
pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK;
pvo->pvo_pte.pa |= LPTE_LP_4K_16M;
pvo->pvo_vaddr |= PVO_LARGE;
}