upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-06-10 17:22:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Don't set the start ISOC ASAP bit for non-isochronous TRBs.

Browse source 
MFC after:	1 week
This commit is contained in:
Hans Petter Selasky 2013-06-02 10:54:47 +00:00
parent fe1831e06f
commit ef32af2180
1 changed files with 8 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
sys/dev/usb/controller/xhci.c
View file

@ -1700,14 +1700,17 @@ restart:
dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
XHCI_TRB_3_TYPE_SET(temp->trb_type) |
(temp->do_isoc_sync ?
XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) :
XHCI_TRB_3_ISO_SIA_BIT) |
XHCI_TRB_3_TBC_SET(temp->tbc) |
XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
temp->do_isoc_sync = 0;
if (temp->trb_type == XHCI_TRB_TYPE_ISOCH) {
if (temp->do_isoc_sync != 0) {
temp->do_isoc_sync = 0;
dword |= XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
} else {
dword |= XHCI_TRB_3_ISO_SIA_BIT;
}
}
if (temp->direction == UE_DIR_IN) {
dword |= XHCI_TRB_3_DIR_IN;