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Reformat for readability.
This commit is contained in:
Matthew N. Dodd
parent
81d9009a65
commit
ece0c30b62
1 changed files with 98 additions and 96 deletions
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@ -35,15 +35,15 @@
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* Several constants.
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*/
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#define CARD_TYPE_EX_10 1
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#define CARD_TYPE_EX_10_PLUS 2
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#define CARD_TYPE_EX_10 1
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#define CARD_TYPE_EX_10_PLUS 2
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/* Length of an ethernet address. */
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#define ETHER_ADDR_LEN 6
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#define ETHER_ADDR_LEN 6
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/* Default RAM size in board. */
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#define CARD_RAM_SIZE 0x8000
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#define CARD_RAM_SIZE 0x8000
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/* Number of I/O ports used. */
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#define EX_IOSIZE 16
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#define EX_IOSIZE 16
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/*
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* Intel EtherExpress Pro (i82595 based) registers
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@ -51,87 +51,87 @@
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/* Common registers to all banks. */
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#define CMD_REG 0
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#define REG1 1
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#define REG2 2
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#define REG3 3
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#define REG4 4
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#define REG5 5
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#define REG6 6
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#define REG7 7
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#define REG8 8
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#define REG9 9
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#define REG10 10
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#define REG11 11
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#define REG12 12
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#define REG13 13
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#define REG14 14
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#define REG15 15
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#define CMD_REG 0
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#define REG1 1
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#define REG2 2
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#define REG3 3
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#define REG4 4
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#define REG5 5
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#define REG6 6
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#define REG7 7
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#define REG8 8
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#define REG9 9
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#define REG10 10
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#define REG11 11
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#define REG12 12
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#define REG13 13
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#define REG14 14
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#define REG15 15
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/* Definitions for command register (CMD_REG). */
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#define Switch_Bank_CMD 0
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#define MC_Setup_CMD 3
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#define Transmit_CMD 4
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#define Diagnose_CMD 7
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#define Rcv_Enable_CMD 8
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#define Rcv_Stop 11
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#define Reset_CMD 14
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#define Resume_XMT_List_CMD 28
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#define Sel_Reset_CMD 30
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#define Abort 0x20
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#define Bank0_Sel 0x00
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#define Bank1_Sel 0x40
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#define Bank2_Sel 0x80
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#define Switch_Bank_CMD 0
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#define MC_Setup_CMD 3
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#define Transmit_CMD 4
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#define Diagnose_CMD 7
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#define Rcv_Enable_CMD 8
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#define Rcv_Stop 11
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#define Reset_CMD 14
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#define Resume_XMT_List_CMD 28
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#define Sel_Reset_CMD 30
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#define Abort 0x20
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#define Bank0_Sel 0x00
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#define Bank1_Sel 0x40
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#define Bank2_Sel 0x80
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/* Bank 0 specific registers. */
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#define STATUS_REG 1
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#define ID_REG 2
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#define Id_Mask 0x2c
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#define Id_Sig 0x24
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#define Counter_bits 0xc0
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#define MASK_REG 3
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#define Exec_Int 0x08
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#define Tx_Int 0x04
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#define Rx_Int 0x02
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#define Rx_Stp_Int 0x01
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#define All_Int 0x0f
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#define RCV_BAR 4
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#define RCV_BAR_Lo 4
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#define RCV_BAR_Hi 5
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#define RCV_STOP_REG 6
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#define XMT_BAR 10
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#define HOST_ADDR_REG 12 /* 16-bit register */
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#define IO_PORT_REG 14 /* 16-bit register */
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#define STATUS_REG 1
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#define ID_REG 2
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#define Id_Mask 0x2c
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#define Id_Sig 0x24
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#define Counter_bits 0xc0
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#define MASK_REG 3
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#define Exec_Int 0x08
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#define Tx_Int 0x04
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#define Rx_Int 0x02
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#define Rx_Stp_Int 0x01
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#define All_Int 0x0f
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#define RCV_BAR 4
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#define RCV_BAR_Lo 4
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#define RCV_BAR_Hi 5
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#define RCV_STOP_REG 6
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#define XMT_BAR 10
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#define HOST_ADDR_REG 12 /* 16-bit register */
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#define IO_PORT_REG 14 /* 16-bit register */
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/* Bank 1 specific registers. */
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#define TriST_INT 0x80
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#define INT_NO_REG 2
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#define RCV_LOWER_LIMIT_REG 8
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#define RCV_UPPER_LIMIT_REG 9
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#define XMT_LOWER_LIMIT_REG 10
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#define XMT_UPPER_LIMIT_REG 11
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#define TriST_INT 0x80
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#define INT_NO_REG 2
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#define RCV_LOWER_LIMIT_REG 8
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#define RCV_UPPER_LIMIT_REG 9
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#define XMT_LOWER_LIMIT_REG 10
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#define XMT_UPPER_LIMIT_REG 11
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/* Bank 2 specific registers. */
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#define Disc_Bad_Fr 0x80
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#define Tx_Chn_ErStp 0x40
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#define Tx_Chn_Int_Md 0x20
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#define Multi_IA 0x20
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#define No_SA_Ins 0x10
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#define RX_CRC_InMem 0x04
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#define Promisc_Mode 0x01
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#define BNC_bit 0x20
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#define TPE_bit 0x04
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#define I_ADDR_REG0 4
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#define EEPROM_REG 10
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#define Trnoff_Enable 0x10
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#define Disc_Bad_Fr 0x80
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#define Tx_Chn_ErStp 0x40
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#define Tx_Chn_Int_Md 0x20
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#define Multi_IA 0x20
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#define No_SA_Ins 0x10
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#define RX_CRC_InMem 0x04
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#define Promisc_Mode 0x01
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#define BNC_bit 0x20
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#define TPE_bit 0x04
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#define I_ADDR_REG0 4
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#define EEPROM_REG 10
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#define Trnoff_Enable 0x10
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/* EEPROM memory positions (16-bit wide). */
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#define EE_W0 0x00
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#define EE_W0 0x00
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# define EE_W0_PNP 0x0001
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# define EE_W0_BUS16 0x0004
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# define EE_W0_FLASH_ADDR_MASK 0x0038
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@ -142,10 +142,10 @@
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# define EE_W0_IO_MASK 0xFC00
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# define EE_W0_IO_SHIFT 10
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#define EE_IRQ_No 1
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#define IRQ_No_Mask 0x07
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#define EE_IRQ_No 1
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#define IRQ_No_Mask 0x07
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#define EE_W1 0x01
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#define EE_W1 0x01
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# define EE_W1_INT_SEL 0x0007
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# define EE_W1_NO_LINK_INT 0x0008 /* Link Integrity Off */
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# define EE_W1_NO_POLARITY 0x0010 /* Polarity Correction Off */
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@ -157,15 +157,15 @@
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# define EE_W1_ALT_READY 0x2000 /* Alternate Ready, 0=normal */
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# define EE_W1_FULL_DUPLEX 0x8000
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#define EE_W2 0x02
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#define EE_W3 0x03
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#define EE_W4 0x04
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#define EE_W2 0x02
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#define EE_W3 0x03
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#define EE_W4 0x04
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#define EE_Eth_Addr_Lo 2
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#define EE_Eth_Addr_Mid 3
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#define EE_Eth_Addr_Hi 4
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#define EE_Eth_Addr_Lo 2
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#define EE_Eth_Addr_Mid 3
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#define EE_Eth_Addr_Hi 4
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#define EE_W5 0x05
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#define EE_W5 0x05
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# define EE_W5_BNC_TPE 0x0001 /* 0 = TPE, 1 = BNC */
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# define EE_W5_BOOT_IPX 0x0002
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# define EE_W5_BOOT_ODI 0x0004
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@ -178,30 +178,32 @@
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# define EE_W5_PWR_MGT 0x0100 /* Power Management */
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# define EE_W5_CP 0x0200 /* COncurrent Processing */
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#define EE_W6 0x05
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#define EE_W6 0x05
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# define EE_W6_STEP_MASK 0x000F
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# define EE_W6_BOARD_MASK 0xFFF0
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# define EE_W6_BOARD_SHIFT 4
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/* EEPROM serial interface. */
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#define EESK 0x01
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#define EECS 0x02
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#define EEDI 0x04
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#define EEDO 0x08
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#define EE_READ_CMD (6 << 6)
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#define EESK 0x01
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#define EECS 0x02
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#define EEDI 0x04
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#define EEDO 0x08
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#define EE_READ_CMD (6 << 6)
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/* Frame chain constants. */
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/* Transmit header length (in board's ring buffer). */
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#define XMT_HEADER_LEN 8
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#define XMT_Chain_Point 4
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#define XMT_Byte_Count 6
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#define Done_bit 0x0080
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#define Ch_bit 0x8000
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#define XMT_HEADER_LEN 8
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#define XMT_Chain_Point 4
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#define XMT_Byte_Count 6
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#define Done_bit 0x0080
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#define Ch_bit 0x8000
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/* Transmit result bits. */
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#define No_Collisions_bits 0x000f
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#define TX_OK_bit 0x2000
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#define No_Collisions_bits 0x000f
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#define TX_OK_bit 0x2000
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/* Receive result bits. */
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#define RCV_Done 8
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#define RCV_OK_bit 0x2000
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#define RCV_Done 8
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#define RCV_OK_bit 0x2000
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