From e439ab9afefecfc2e521ea4da23fa2884c1073fd Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Thu, 13 Apr 2006 17:39:34 +0000 Subject: [PATCH] MFp4: For 32-bit SDRAM systems, enable D16 to D31 in the PIO controller. Otherwise they read back as 0xffff. Shave 8 bytes from the object size by using AT91C_BASE_PIOA directly and by not assigning PIO_BSR to 0 in the DBGU init. That's a nop in two ways (everything defaults to peripheral A, and writing 0 changes nothing). --- sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c b/sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c index ab3ae24e77c..d0f10a181b8 100644 --- a/sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c +++ b/sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c @@ -44,7 +44,6 @@ _init(void) { AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU; AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR); - AT91PS_PIO pPio = AT91C_BASE_PIOA; register unsigned value; int i; @@ -152,10 +151,14 @@ _init(void) AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD; *p = 0; +#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS + // Turn on the upper 16 bits on the SDRAM bus. + AT91C_BASE_PIOC->PIO_ASR = 0xffff0000; + AT91C_BASE_PIOC->PIO_PDR = 0xffff0000; +#endif // Configure DBGU -use local routine optimized for space - pPio->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; - pPio->PIO_BSR = 0; - pPio->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; pUSART->US_IDR = (unsigned int) -1; pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;