From e34135013bb6a4fca9051bf9c5576709336f6800 Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Mon, 28 Sep 2009 22:18:38 +0000 Subject: [PATCH] For AR8132 fast ethernet controller, do not report 1000baseT capability to mii(4). Even though AR8132 uses the same model/ revision number of F1 gigabit PHY, the PHY has no ability to establish 1000baseT link. I have no idea why Atheros use the same device/model id for this PHY. With this change atphy(4) does not report 1000baseT media capability and manual 1000baseT configuration is also disabled which is more desirable behavior for 10/100Mbps PHY. --- sys/dev/alc/if_alc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index a53af779b03..aeb46213811 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -234,6 +234,16 @@ alc_miibus_readreg(device_t dev, int phy, int reg) if (phy != sc->alc_phyaddr) return (0); + /* + * For AR8132 fast ethernet controller, do not report 1000baseT + * capability to mii(4). Even though AR8132 uses the same + * model/revision number of F1 gigabit PHY, the PHY has no + * ability to establish 1000baseT link. + */ + if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && + reg == MII_EXTSR) + return (0); + CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); for (i = ALC_PHY_TIMEOUT; i > 0; i--) {