mirror of
https://github.com/opnsense/src.git
synced 2026-06-12 10:10:24 -04:00
Import device-tree files from Linux 6.9
This commit is contained in:
Emmanuel Vadot
parent
48aa10e065
commit
e2e0a4ea3f
1227 changed files with 55993 additions and 9603 deletions
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@ -64,9 +64,6 @@ override DTC_FLAGS := \
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-Wno-unique_unit_address \
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-Wunique_unit_address_if_enabled
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# Disable undocumented compatible checks until warning free
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override DT_CHECKER_FLAGS ?=
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$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
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$(call if_changed_rule,chkdt)
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@ -7,19 +7,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic SoC based Platforms
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Kevin Hilman <khilman@baylibre.com>
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description: |+
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Work in progress statement:
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Device tree files and bindings applying to Amlogic SoCs and boards are
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considered "unstable". Any Amlogic device tree binding may change at
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any time. Be sure to use a device tree binary and a kernel image
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generated from the same source tree.
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Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
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stable binding/ABI.
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properties:
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$nodename:
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const: '/'
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@ -146,6 +138,7 @@ properties:
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- enum:
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- amediatech,x96-max
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- amlogic,u200
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- freebox,fbx8am
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- radxa,zero
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- seirobotics,sei510
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- const: amlogic,g12a
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@ -10,9 +10,9 @@ maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |+
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The ARM RealView series of reference designs were built to explore the ARM
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11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
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the earlier CPUs such as TrustZone and multicore (MPCore).
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The ARM RealView series of reference designs were built to explore the Arm11,
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Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
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earlier CPUs such as TrustZone and multicore (MPCore).
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properties:
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$nodename:
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@ -179,6 +179,12 @@ properties:
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- const: microchip,sama7g5
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- const: microchip,sama7
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- description: Microchip SAMA7G54 Curiosity Board
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items:
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- const: microchip,sama7g54-curiosity
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- const: microchip,sama7g5
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- const: microchip,sama7
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- description: Microchip LAN9662 Evaluation Boards.
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items:
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- enum:
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@ -384,7 +384,8 @@ properties:
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- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
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- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
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- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
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- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
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- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1
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- toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2
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- const: toradex,apalis_imx6q
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- const: fsl,imx6q
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@ -469,6 +470,7 @@ properties:
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- prt,prtvt7 # Protonic VT7 board
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- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
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- riot,imx6s-riotboard # RIoTboard i.MX6S
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- sielaff,imx6dl-board # Sielaff i.MX6 Solo Board
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- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
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- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
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- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
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@ -708,6 +710,7 @@ properties:
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- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
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- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
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- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
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- uni-t,uti260b # UNI-T UTi260B Thermal Camera
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- const: fsl,imx6ull
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- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
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@ -1026,7 +1029,7 @@ properties:
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items:
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- enum:
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- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
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- rve,rve-gateway # i.MX8MN RVE Gateway Board
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- rve,gateway # i.MX8MN RVE Gateway Board
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- variscite,var-som-mx8mn-symphony
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- const: variscite,var-som-mx8mn
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- const: fsl,imx8mn
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@ -1194,7 +1197,8 @@ properties:
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- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
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items:
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- enum:
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- toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board
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- toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board
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- toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board
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- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
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- const: toradex,apalis-imx8
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- const: fsl,imx8qm
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@ -1202,7 +1206,8 @@ properties:
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- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
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items:
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- enum:
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- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board
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- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
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- toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board
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- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
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- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
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- const: toradex,apalis-imx8-v1.1
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@ -1232,6 +1237,22 @@ properties:
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- const: toradex,colibri-imx8x
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- const: fsl,imx8qxp
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- description:
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TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip
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variants. It is designed to be clicked on different carrier boards
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MBa8Xx is the starterkit
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oneOf:
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- items:
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- enum:
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- tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx
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- const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP)
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- const: fsl,imx8dxp
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- items:
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- enum:
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- tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx
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- const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
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- const: fsl,imx8qxp
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- description: i.MX8ULP based Boards
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items:
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- enum:
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@ -1275,6 +1296,18 @@ properties:
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- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
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- const: fsl,imx93
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- description: PHYTEC phyCORE-i.MX93 SoM based boards
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items:
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- const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
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- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
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- const: fsl,imx93
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- description: Variscite VAR-SOM-MX93 based boards
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items:
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- const: variscite,var-som-mx93-symphony
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- const: variscite,var-som-mx93
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- const: fsl,imx93
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- description:
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Freescale Vybrid Platform Device Tree Bindings
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70
Bindings/arm/marvell/armada-38x.yaml
Normal file
70
Bindings/arm/marvell/armada-38x.yaml
Normal file
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@ -0,0 +1,70 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 38x Platforms
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maintainers:
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- Gregory CLEMENT <gregory.clement@bootlin.com>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description:
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Netgear Armada 380 GS110EM Managed Switch.
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items:
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- const: netgear,gs110emx
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- const: marvell,armada380
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- description:
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Marvell Armada 385 Development Boards.
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items:
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- enum:
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- marvell,a385-db-amc
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- marvell,a385-db-ap
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- const: marvell,armada385
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- const: marvell,armada380
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- description:
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SolidRun Armada 385 based single-board computers.
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items:
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- enum:
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- solidrun,clearfog-gtr-l8
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- solidrun,clearfog-gtr-s4
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- const: marvell,armada385
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- const: marvell,armada380
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- description:
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Kobol Armada 388 based Helios-4 NAS.
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items:
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- const: kobol,helios4
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- const: marvell,armada388
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- const: marvell,armada385
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- const: marvell,armada380
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- description:
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Marvell Armada 388 Development Boards.
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items:
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- enum:
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- marvell,a388-gp
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- const: marvell,armada388
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- const: marvell,armada385
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- const: marvell,armada380
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- description:
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SolidRun Armada 388 clearfog family single-board computers.
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items:
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- enum:
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- solidrun,clearfog-base-a1
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- solidrun,clearfog-pro-a1
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- const: solidrun,clearfog-a1
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- const: marvell,armada388
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- const: marvell,armada385
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- const: marvell,armada380
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additionalProperties: true
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@ -17,6 +17,7 @@ properties:
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const: '/'
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compatible:
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oneOf:
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# Sort by SoC (last) compatible, then board compatible
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- items:
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- enum:
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- mediatek,mt2701-evb
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@ -84,6 +85,11 @@ properties:
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- const: mediatek,mt7629
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- items:
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- enum:
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- xiaomi,ax3000t
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- const: mediatek,mt7981b
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- items:
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- enum:
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- acelink,ew-7886cax
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- bananapi,bpi-r3
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- mediatek,mt7986a-rfb
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- const: mediatek,mt7986a
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@ -91,6 +97,10 @@ properties:
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- enum:
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- mediatek,mt7986b-rfb
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- const: mediatek,mt7986b
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- items:
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- enum:
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- bananapi,bpi-r4
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- const: mediatek,mt7988a
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- items:
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- enum:
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- mediatek,mt8127-moose
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@ -129,75 +139,10 @@ properties:
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- enum:
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- mediatek,mt8173-evb
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- const: mediatek,mt8173
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- items:
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- enum:
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- mediatek,mt8183-evb
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- const: mediatek,mt8183
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- description: Google Hayato rev5
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items:
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- const: google,hayato-rev5-sku2
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- const: google,hayato-sku2
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- const: google,hayato
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- const: mediatek,mt8192
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- description: Google Hayato
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items:
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- const: google,hayato-rev1
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- const: google,hayato
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- const: mediatek,mt8192
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- description: Google Spherion rev4 (Acer Chromebook 514)
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items:
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- const: google,spherion-rev4
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- const: google,spherion
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- const: mediatek,mt8192
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- description: Google Spherion (Acer Chromebook 514)
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items:
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- const: google,spherion-rev3
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- const: google,spherion-rev2
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- const: google,spherion-rev1
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- const: google,spherion-rev0
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- const: google,spherion
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- const: mediatek,mt8192
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- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
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items:
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- enum:
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- google,tomato-rev2
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- google,tomato-rev1
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- const: google,tomato
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- const: mediatek,mt8195
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- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
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items:
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- const: google,tomato-rev4
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- const: google,tomato-rev3
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- const: google,tomato
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- const: mediatek,mt8195
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- items:
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||||
- enum:
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- mediatek,mt8186-evb
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- const: mediatek,mt8186
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- items:
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- enum:
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- mediatek,mt8188-evb
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- const: mediatek,mt8188
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- items:
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- enum:
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- mediatek,mt8192-evb
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- const: mediatek,mt8192
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- items:
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- enum:
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||||
- mediatek,mt8195-demo
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- mediatek,mt8195-evb
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- const: mediatek,mt8195
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||||
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
|
||||
items:
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||||
- const: google,burnet
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||||
- const: mediatek,mt8183
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||||
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
|
||||
items:
|
||||
- enum:
|
||||
- google,krane-sku0
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||||
- google,krane-sku176
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||||
- const: google,krane
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||||
- const: mediatek,mt8183
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||||
- description: Google Cozmo (Acer Chromebook 314)
|
||||
items:
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||||
- const: google,cozmo
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||||
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@ -255,6 +200,13 @@ properties:
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|||
- google,kodama-sku32
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||||
- const: google,kodama
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||||
- const: mediatek,mt8183
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||||
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
|
||||
items:
|
||||
- enum:
|
||||
- google,krane-sku0
|
||||
- google,krane-sku176
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||||
- const: google,krane
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -276,10 +228,125 @@ properties:
|
|||
- google,willow-sku1
|
||||
- const: google,willow
|
||||
- const: mediatek,mt8183
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-evb
|
||||
- const: mediatek,mt8183
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8183-pumpkin
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
|
||||
items:
|
||||
- const: google,steelix-sku393219
|
||||
- const: google,steelix-sku393216
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
|
||||
items:
|
||||
- const: google,steelix-sku393220
|
||||
- const: google,steelix-sku393217
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
|
||||
items:
|
||||
- const: google,steelix-sku393221
|
||||
- const: google,steelix-sku393218
|
||||
- const: google,steelix
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||||
- const: mediatek,mt8186
|
||||
- description: Google Rusty (Lenovo 100e Chromebook Gen 4)
|
||||
items:
|
||||
- const: google,steelix-sku196609
|
||||
- const: google,steelix-sku196608
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
|
||||
items:
|
||||
- enum:
|
||||
- google,steelix-sku131072
|
||||
- google,steelix-sku131073
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
|
||||
items:
|
||||
- const: google,tentacruel-sku262147
|
||||
- const: google,tentacruel-sku262146
|
||||
- const: google,tentacruel-sku262145
|
||||
- const: google,tentacruel-sku262144
|
||||
- const: google,tentacruel
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
|
||||
items:
|
||||
- const: google,tentacruel-sku262151
|
||||
- const: google,tentacruel-sku262150
|
||||
- const: google,tentacruel-sku262149
|
||||
- const: google,tentacruel-sku262148
|
||||
- const: google,tentacruel
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
|
||||
items:
|
||||
- const: google,tentacruel-sku327681
|
||||
- const: google,tentacruel
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
|
||||
items:
|
||||
- const: google,tentacruel-sku327683
|
||||
- const: google,tentacruel
|
||||
- const: mediatek,mt8186
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-evb
|
||||
- const: mediatek,mt8186
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-evb
|
||||
- const: mediatek,mt8188
|
||||
- description: Google Hayato
|
||||
items:
|
||||
- const: google,hayato-rev1
|
||||
- const: google,hayato
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Hayato rev5
|
||||
items:
|
||||
- const: google,hayato-rev5-sku2
|
||||
- const: google,hayato-sku2
|
||||
- const: google,hayato
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Spherion (Acer Chromebook 514)
|
||||
items:
|
||||
- const: google,spherion-rev3
|
||||
- const: google,spherion-rev2
|
||||
- const: google,spherion-rev1
|
||||
- const: google,spherion-rev0
|
||||
- const: google,spherion
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Spherion rev4 (Acer Chromebook 514)
|
||||
items:
|
||||
- const: google,spherion-rev4
|
||||
- const: google,spherion
|
||||
- const: mediatek,mt8192
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-evb
|
||||
- const: mediatek,mt8192
|
||||
- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
|
||||
items:
|
||||
- enum:
|
||||
- google,tomato-rev2
|
||||
- google,tomato-rev1
|
||||
- const: google,tomato
|
||||
- const: mediatek,mt8195
|
||||
- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
|
||||
items:
|
||||
- const: google,tomato-rev4
|
||||
- const: google,tomato-rev3
|
||||
- const: google,tomato
|
||||
- const: mediatek,mt8195
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-demo
|
||||
- mediatek,mt8195-evb
|
||||
- const: mediatek,mt8195
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8365-evk
|
||||
|
|
@ -287,6 +354,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8395-evk
|
||||
- radxa,nio-12l
|
||||
- const: mediatek,mt8395
|
||||
- const: mediatek,mt8195
|
||||
- items:
|
||||
|
|
|
|||
|
|
@ -44,14 +44,21 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
qcom,dsb-element-size:
|
||||
qcom,dsb-element-bits:
|
||||
description:
|
||||
Specifies the DSB(Discrete Single Bit) element size supported by
|
||||
the monitor. The associated aggregator will read this size before it
|
||||
is enabled. DSB element size currently only supports 32-bit and 64-bit.
|
||||
$ref: /schemas/types.yaml#/definitions/uint8
|
||||
enum: [32, 64]
|
||||
|
||||
qcom,cmb-element-bits:
|
||||
description:
|
||||
Specifies the CMB(Continuous Multi-Bit) element size supported by
|
||||
the monitor. The associated aggregator will read this size before it
|
||||
is enabled. CMB element size currently only supports 8-bit, 32-bit
|
||||
and 64-bit.
|
||||
enum: [8, 32, 64]
|
||||
|
||||
qcom,dsb-msrs-num:
|
||||
description:
|
||||
Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
|
||||
|
|
@ -61,6 +68,15 @@ properties:
|
|||
minimum: 0
|
||||
maximum: 32
|
||||
|
||||
qcom,cmb-msrs-num:
|
||||
description:
|
||||
Specifies the number of CMB MSR(mux select register) registers supported
|
||||
by the monitor. If this property is not configured or set to 0, it means
|
||||
this TPDM doesn't support CMB MSR.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 32
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
|
|
@ -94,7 +110,7 @@ examples:
|
|||
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
||||
reg = <0x0684c000 0x1000>;
|
||||
|
||||
qcom,dsb-element-size = /bits/ 8 <32>;
|
||||
qcom,dsb-element-bits = <32>;
|
||||
qcom,dsb-msrs-num = <16>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
|
|
@ -110,4 +126,22 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
tpdm@6c29000 {
|
||||
compatible = "qcom,coresight-tpdm", "arm,primecell";
|
||||
reg = <0x06c29000 0x1000>;
|
||||
|
||||
qcom,cmb-element-bits = <64>;
|
||||
qcom,cmb-msrs-num = <32>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
tpdm_ipcc_out_funnel_center: endpoint {
|
||||
remote-endpoint = <&funnel_center_in_tpdm_ipcc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -10,17 +10,10 @@ maintainers:
|
|||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Some qcom based bootloaders identify the dtb blob based on a set of
|
||||
device properties like SoC and platform and revisions of those components.
|
||||
To support this scheme, we encode this information into the board compatible
|
||||
string.
|
||||
|
||||
Each board must specify a top-level board compatible string with the following
|
||||
format:
|
||||
|
||||
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
|
||||
|
||||
The 'SoC' and 'board' elements are required. All other elements are optional.
|
||||
For devices using the Qualcomm SoC the "compatible" properties consists of
|
||||
one or several "manufacturer,model" strings, describing the device itself,
|
||||
followed by one or several "qcom,<SoC>" strings, describing the SoC used in
|
||||
the device.
|
||||
|
||||
The 'SoC' element must be one of the following strings:
|
||||
|
||||
|
|
@ -90,43 +83,9 @@ description: |
|
|||
sm8650
|
||||
x1e80100
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
adp
|
||||
cdp
|
||||
dragonboard
|
||||
idp
|
||||
liquid
|
||||
mtp
|
||||
qcp
|
||||
qrd
|
||||
rb2
|
||||
ride
|
||||
sbc
|
||||
x100
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
as v1. If all versions of the 'board_version' elements match, then a
|
||||
wildcard '*' should be used, e.g. 'v*'.
|
||||
|
||||
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
|
||||
|
||||
Examples:
|
||||
|
||||
"qcom,msm8916-v1-cdp-pm8916-v2.1"
|
||||
|
||||
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
|
||||
2.1.
|
||||
|
||||
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
|
||||
|
||||
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
|
||||
foundry 2.
|
||||
|
||||
There are many devices in the list below that run the standard ChromeOS
|
||||
bootloader setup and use the open source depthcharge bootloader to boot the
|
||||
OS. These devices do not use the scheme described above. For details, see:
|
||||
OS. These devices use the bootflow explained at
|
||||
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
|
||||
|
||||
properties:
|
||||
|
|
@ -187,6 +146,7 @@ properties:
|
|||
- microsoft,superman-lte
|
||||
- microsoft,tesla
|
||||
- motorola,peregrine
|
||||
- samsung,matisselte
|
||||
- const: qcom,msm8926
|
||||
- const: qcom,msm8226
|
||||
|
||||
|
|
@ -244,11 +204,15 @@ properties:
|
|||
- samsung,a5u-eur
|
||||
- samsung,e5
|
||||
- samsung,e7
|
||||
- samsung,fortuna3g
|
||||
- samsung,gprimeltecan
|
||||
- samsung,grandmax
|
||||
- samsung,grandprimelte
|
||||
- samsung,gt510
|
||||
- samsung,gt58
|
||||
- samsung,j5
|
||||
- samsung,j5x
|
||||
- samsung,rossa
|
||||
- samsung,serranove
|
||||
- thwc,uf896
|
||||
- thwc,ufi001c
|
||||
|
|
@ -988,6 +952,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- xiaomi,curtana
|
||||
- xiaomi,joyeuse
|
||||
- const: qcom,sm7125
|
||||
|
||||
|
|
@ -1035,6 +1000,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8550-hdk
|
||||
- qcom,sm8550-mtp
|
||||
- qcom,sm8550-qrd
|
||||
- const: qcom,sm8550
|
||||
|
|
|
|||
|
|
@ -37,29 +37,16 @@ properties:
|
|||
- anbernic,rg351v
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Anbernic RG353P
|
||||
- description: Anbernic RK3566 Handheld Gaming Console
|
||||
items:
|
||||
- const: anbernic,rg353p
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG353PS
|
||||
items:
|
||||
- const: anbernic,rg353ps
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG353V
|
||||
items:
|
||||
- const: anbernic,rg353v
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG353VS
|
||||
items:
|
||||
- const: anbernic,rg353vs
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG503
|
||||
items:
|
||||
- const: anbernic,rg503
|
||||
- enum:
|
||||
- anbernic,rg353p
|
||||
- anbernic,rg353ps
|
||||
- anbernic,rg353v
|
||||
- anbernic,rg353vs
|
||||
- anbernic,rg503
|
||||
- anbernic,rg-arc-d
|
||||
- anbernic,rg-arc-s
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Asus Tinker board
|
||||
|
|
@ -237,6 +224,13 @@ properties:
|
|||
- friendlyarm,nanopi-r5s
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: FriendlyElec NanoPi R6 series boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,nanopi-r6c
|
||||
- friendlyarm,nanopi-r6s
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: FriendlyElec NanoPC T6
|
||||
items:
|
||||
- const: friendlyarm,nanopc-t6
|
||||
|
|
@ -626,9 +620,9 @@ properties:
|
|||
- const: openailab,eaidk-610
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Orange Pi RK3399 board
|
||||
- description: Xunlong Orange Pi RK3399 board
|
||||
items:
|
||||
- const: rockchip,rk3399-orangepi
|
||||
- const: xunlong,rk3399-orangepi
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Phytec phyCORE-RK3288 Rapid Development Kit
|
||||
|
|
@ -655,6 +649,14 @@ properties:
|
|||
- const: pine64,pinephone-pro
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 PineTab2
|
||||
items:
|
||||
- enum:
|
||||
- pine64,pinetab2-v0.1
|
||||
- pine64,pinetab2-v2.0
|
||||
- const: pine64,pinetab2
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Pine64 Rock64
|
||||
items:
|
||||
- const: pine64,rock64
|
||||
|
|
@ -692,11 +694,17 @@ properties:
|
|||
- description: Powkiddy RK3566 Handheld Gaming Console
|
||||
items:
|
||||
- enum:
|
||||
- powkiddy,rgb10max3
|
||||
- powkiddy,rgb30
|
||||
- powkiddy,rk2023
|
||||
- powkiddy,x55
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: QNAP TS-433-4G 4-Bay NAS
|
||||
items:
|
||||
- const: qnap,ts433
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Radxa Compute Module 3(CM3)
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -878,6 +886,11 @@ properties:
|
|||
- const: rockchip,rv1108-evb
|
||||
- const: rockchip,rv1108
|
||||
|
||||
- description: Rockchip Toybrick TB-RK3588X board
|
||||
items:
|
||||
- const: rockchip,rk3588-toybrick-x0
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,px30-ringneck-haikou
|
||||
|
|
@ -898,6 +911,12 @@ properties:
|
|||
- const: tsd,rk3588-jaguar
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Theobroma Systems RK3588-Q7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3588-tiger-haikou
|
||||
- const: tsd,rk3588-tiger
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Tronsmart Orion R68 Meta
|
||||
items:
|
||||
- const: tronsmart,orion-r68-meta
|
||||
|
|
@ -940,9 +959,9 @@ properties:
|
|||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Rockchip RK3568 Banana Pi R2 Pro
|
||||
- description: Sinovoip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: rockchip,rk3568-bpi-r2pro
|
||||
- const: sinovoip,rk3568-bpi-r2pro
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sonoff iHost Smart Home Hub
|
||||
|
|
|
|||
|
|
@ -815,6 +815,12 @@ properties:
|
|||
- const: allwinner,r7-tv-dongle
|
||||
- const: allwinner,sun5i-a10s
|
||||
|
||||
- description: Remix Mini PC
|
||||
items:
|
||||
- const: jide,remix-mini-pc
|
||||
- const: allwinner,sun50i-h64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: RerVision H3-DVK
|
||||
items:
|
||||
- const: rervision,h3-dvk
|
||||
|
|
@ -835,6 +841,12 @@ properties:
|
|||
- const: sinlinx,sina33
|
||||
- const: allwinner,sun8i-a33
|
||||
|
||||
- description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H
|
||||
items:
|
||||
- const: sipeed,longan-pi-3h
|
||||
- const: sipeed,longan-module-3h
|
||||
- const: allwinner,sun50i-h618
|
||||
|
||||
- description: SourceParts PopStick v1.1
|
||||
items:
|
||||
- const: sourceparts,popstick-v1.1
|
||||
|
|
|
|||
|
|
@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now.
|
|||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Work in progress statement:
|
||||
|
||||
Device tree files and bindings applying to Marvell Berlin SoCs and boards are
|
||||
considered "unstable". Any Marvell Berlin device tree binding may change at any
|
||||
time. Be sure to use a device tree binary and a kernel image generated from the
|
||||
same source tree.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
|
||||
stable binding/ABI.
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
|
||||
shall have the following properties:
|
||||
|
||||
|
|
|
|||
|
|
@ -64,6 +64,14 @@ properties:
|
|||
- items:
|
||||
- const: asus,tf700t
|
||||
- const: nvidia,tegra30
|
||||
- description: LG Optimus 4X P880
|
||||
items:
|
||||
- const: lg,p880
|
||||
- const: nvidia,tegra30
|
||||
- description: LG Optimus Vu P895
|
||||
items:
|
||||
- const: lg,p895
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ properties:
|
|||
- const: pmc
|
||||
- const: wake
|
||||
- const: aotag
|
||||
- const: scratch
|
||||
- enum: [ scratch, misc ]
|
||||
- const: misc
|
||||
|
||||
interrupt-controller: true
|
||||
|
|
@ -41,25 +41,43 @@ properties:
|
|||
description: If present, inverts the PMU interrupt signal.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra186-pmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra186-pmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
contains:
|
||||
const: scratch
|
||||
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra194-pmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
reg-names:
|
||||
minItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra234-pmc
|
||||
then:
|
||||
properties:
|
||||
reg-names:
|
||||
contains:
|
||||
const: misc
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+-[a-z0-9]+$":
|
||||
|
|
|
|||
|
|
@ -87,12 +87,20 @@ properties:
|
|||
- const: tq,am642-tqma6442l
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 AM642 SoC SolidRun SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,am642-hummingboard-t
|
||||
- const: solidrun,am642-sr-som
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 AM654 SoC
|
||||
items:
|
||||
- enum:
|
||||
- siemens,iot2050-advanced
|
||||
- siemens,iot2050-advanced-m2
|
||||
- siemens,iot2050-advanced-pg2
|
||||
- siemens,iot2050-advanced-sm
|
||||
- siemens,iot2050-basic
|
||||
- siemens,iot2050-basic-pg2
|
||||
- ti,am654-evm
|
||||
|
|
@ -123,6 +131,12 @@ properties:
|
|||
- ti,j721s2-evm
|
||||
- const: ti,j721s2
|
||||
|
||||
- description: K3 J722S SoC and Boards
|
||||
items:
|
||||
- enum:
|
||||
- ti,j722s-evm
|
||||
- const: ti,j722s
|
||||
|
||||
- description: K3 J784s4 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
98
Bindings/ata/mediatek,mtk-ahci.yaml
Normal file
98
Bindings/ata/mediatek,mtk-ahci.yaml
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Serial ATA controller
|
||||
|
||||
maintainers:
|
||||
- Ryder Lee <ryder.lee@mediatek.com>
|
||||
|
||||
allOf:
|
||||
- $ref: ahci-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt7622-ahci
|
||||
- const: mediatek,mtk-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
const: hostc
|
||||
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ahb
|
||||
- const: axi
|
||||
- const: asic
|
||||
- const: rbc
|
||||
- const: pm
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 3
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi
|
||||
- const: sw
|
||||
- const: reg
|
||||
|
||||
mediatek,phy-mode:
|
||||
description: System controller phandle, used to enable SATA function
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- ports-implemented
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/power/mt7622-power.h>
|
||||
#include <dt-bindings/reset/mt7622-reset.h>
|
||||
|
||||
sata@1a200000 {
|
||||
compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
|
||||
reg = <0x1a200000 0x1100>;
|
||||
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hostc";
|
||||
clocks = <&pciesys CLK_SATA_AHB_EN>,
|
||||
<&pciesys CLK_SATA_AXI_EN>,
|
||||
<&pciesys CLK_SATA_ASIC_EN>,
|
||||
<&pciesys CLK_SATA_RBC_EN>,
|
||||
<&pciesys CLK_SATA_PM_EN>;
|
||||
clock-names = "ahb", "axi", "asic", "rbc", "pm";
|
||||
phys = <&u3port1 PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
ports-implemented = <0x1>;
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
|
||||
<&pciesys MT7622_SATA_PHY_SW_RST>,
|
||||
<&pciesys MT7622_SATA_PHY_REG_RST>;
|
||||
reset-names = "axi", "sw", "reg";
|
||||
mediatek,phy-mode = <&pciesys>;
|
||||
};
|
||||
|
|
@ -39,6 +39,6 @@ additionalProperties: false
|
|||
examples:
|
||||
- |
|
||||
lcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
};
|
||||
|
|
|
|||
55
Bindings/auxdisplay/gpio-7-segment.yaml
Normal file
55
Bindings/auxdisplay/gpio-7-segment.yaml
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/gpio-7-segment.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: GPIO based LED segment display
|
||||
|
||||
maintainers:
|
||||
- Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: gpio-7-segment
|
||||
|
||||
segment-gpios:
|
||||
description: |
|
||||
An array of GPIOs one per segment. The first GPIO corresponds to the A
|
||||
segment, the seventh GPIO corresponds to the G segment. Some LED blocks
|
||||
also have a decimal point which can be specified as an optional eighth
|
||||
segment.
|
||||
|
||||
-a-
|
||||
| |
|
||||
f b
|
||||
| |
|
||||
-g-
|
||||
| |
|
||||
e c
|
||||
| |
|
||||
-d- dp
|
||||
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
|
||||
required:
|
||||
- segment-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
led-7seg {
|
||||
compatible = "gpio-7-segment";
|
||||
segment-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 1 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 2 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 3 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 4 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 5 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -84,42 +84,44 @@ additionalProperties: false
|
|||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
auxdisplay {
|
||||
compatible = "hit,hd44780";
|
||||
display-controller {
|
||||
compatible = "hit,hd44780";
|
||||
|
||||
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 1 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 2 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 1 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 2 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcf8574: pcf8574@27 {
|
||||
compatible = "nxp,pcf8574";
|
||||
reg = <0x27>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
pcf8574: gpio-expander@27 {
|
||||
compatible = "nxp,pcf8574";
|
||||
reg = <0x27>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
hd44780 {
|
||||
compatible = "hit,hd44780";
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
data-gpios = <&pcf8574 4 0>,
|
||||
<&pcf8574 5 0>,
|
||||
<&pcf8574 6 0>,
|
||||
<&pcf8574 7 0>;
|
||||
enable-gpios = <&pcf8574 2 0>;
|
||||
rs-gpios = <&pcf8574 0 0>;
|
||||
rw-gpios = <&pcf8574 1 0>;
|
||||
backlight-gpios = <&pcf8574 3 0>;
|
||||
|
||||
display-controller {
|
||||
compatible = "hit,hd44780";
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
data-gpios = <&pcf8574 4 GPIO_ACTIVE_HIGH>,
|
||||
<&pcf8574 5 GPIO_ACTIVE_HIGH>,
|
||||
<&pcf8574 6 GPIO_ACTIVE_HIGH>,
|
||||
<&pcf8574 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&pcf8574 2 GPIO_ACTIVE_HIGH>;
|
||||
rs-gpios = <&pcf8574 0 GPIO_ACTIVE_HIGH>;
|
||||
rw-gpios = <&pcf8574 1 GPIO_ACTIVE_HIGH>;
|
||||
backlight-gpios = <&pcf8574 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -74,31 +74,31 @@ examples:
|
|||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ht16k33: ht16k33@70 {
|
||||
compatible = "holtek,ht16k33";
|
||||
reg = <0x70>;
|
||||
refresh-rate-hz = <20>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
|
||||
debounce-delay-ms = <50>;
|
||||
linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
|
||||
<MATRIX_KEY(3, 0, KEY_F8)>,
|
||||
<MATRIX_KEY(4, 0, KEY_F10)>,
|
||||
<MATRIX_KEY(5, 0, KEY_F4)>,
|
||||
<MATRIX_KEY(6, 0, KEY_F2)>,
|
||||
<MATRIX_KEY(2, 1, KEY_F5)>,
|
||||
<MATRIX_KEY(3, 1, KEY_F7)>,
|
||||
<MATRIX_KEY(4, 1, KEY_F9)>,
|
||||
<MATRIX_KEY(5, 1, KEY_F3)>,
|
||||
<MATRIX_KEY(6, 1, KEY_F1)>;
|
||||
display-controller@70 {
|
||||
compatible = "holtek,ht16k33";
|
||||
reg = <0x70>;
|
||||
refresh-rate-hz = <20>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
|
||||
debounce-delay-ms = <50>;
|
||||
linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
|
||||
<MATRIX_KEY(3, 0, KEY_F8)>,
|
||||
<MATRIX_KEY(4, 0, KEY_F10)>,
|
||||
<MATRIX_KEY(5, 0, KEY_F4)>,
|
||||
<MATRIX_KEY(6, 0, KEY_F2)>,
|
||||
<MATRIX_KEY(2, 1, KEY_F5)>,
|
||||
<MATRIX_KEY(3, 1, KEY_F7)>,
|
||||
<MATRIX_KEY(4, 1, KEY_F9)>,
|
||||
<MATRIX_KEY(5, 1, KEY_F3)>,
|
||||
<MATRIX_KEY(6, 1, KEY_F1)>;
|
||||
|
||||
led {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_BACKLIGHT;
|
||||
linux,default-trigger = "backlight";
|
||||
};
|
||||
led {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_BACKLIGHT;
|
||||
linux,default-trigger = "backlight";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,6 @@ additionalProperties: false
|
|||
examples:
|
||||
- |
|
||||
lcd: lcd@17fff000 {
|
||||
compatible = "img,boston-lcd";
|
||||
reg = <0x17fff000 0x8>;
|
||||
compatible = "img,boston-lcd";
|
||||
reg = <0x17fff000 0x8>;
|
||||
};
|
||||
|
|
|
|||
44
Bindings/auxdisplay/maxim,max6959.yaml
Normal file
44
Bindings/auxdisplay/maxim,max6959.yaml
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/maxim,max6959.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MAX6958/6959 7-segment LED display controller
|
||||
|
||||
maintainers:
|
||||
- Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
|
||||
description:
|
||||
The Maxim MAX6958/6959 7-segment LED display controller provides
|
||||
an I2C interface to up to four 7-segment LED digits. The MAX6959,
|
||||
in comparison to MAX6958, adds input support. Type of the chip can
|
||||
be autodetected via specific register read, and hence the features
|
||||
may be enabled in the driver at run-time, in case they are requested
|
||||
via Device Tree. A given hardware is simple and does not provide
|
||||
any additional pins, such as reset or power enable.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: maxim,max6959
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
display-controller@38 {
|
||||
compatible = "maxim,max6959";
|
||||
reg = <0x38>;
|
||||
};
|
||||
};
|
||||
|
|
@ -18,6 +18,7 @@ properties:
|
|||
- const: brcm,gisb-arb
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,bcm74165-gisb-arb # for V7 new style 16nm chips
|
||||
- brcm,bcm7278-gisb-arb # for V7 28nm chips
|
||||
- brcm,bcm7435-gisb-arb # for newer 40nm chips
|
||||
- brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
|
||||
|
|
|
|||
|
|
@ -30,14 +30,16 @@ properties:
|
|||
- google,gs101-cmu-top
|
||||
- google,gs101-cmu-apm
|
||||
- google,gs101-cmu-misc
|
||||
- google,gs101-cmu-peric0
|
||||
- google,gs101-cmu-peric1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 3
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
|
@ -88,6 +90,28 @@ allOf:
|
|||
- const: bus
|
||||
- const: sss
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-cmu-peric0
|
||||
- google,gs101-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24.576 MHz)
|
||||
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
|
||||
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: ip
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
Binding for Keystone gate control driver which uses PSC controller IP.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
Binding for keystone PLLs. The main PLL IP typically has a multiplier,
|
||||
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
|
||||
and PAPLL are controlled by the memory mapped register where as the Main
|
||||
|
|
|
|||
50
Bindings/clock/mediatek,mt2701-hifsys.yaml
Normal file
50
Bindings/clock/mediatek,mt2701-hifsys.yaml
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek HIFSYS clock and reset controller
|
||||
|
||||
description:
|
||||
The MediaTek HIFSYS controller provides various clocks and reset outputs to
|
||||
the system.
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt2701-hifsys
|
||||
- mediatek,mt7622-hifsys
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-hifsys
|
||||
- const: mediatek,mt2701-hifsys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1a000000 {
|
||||
compatible = "mediatek,mt2701-hifsys";
|
||||
reg = <0x1a000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
45
Bindings/clock/mediatek,mt7622-pciesys.yaml
Normal file
45
Bindings/clock/mediatek,mt7622-pciesys.yaml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek PCIESYS clock and reset controller
|
||||
|
||||
description:
|
||||
The MediaTek PCIESYS controller provides various clocks to the system.
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7622-pciesys
|
||||
- mediatek,mt7629-pciesys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1a100800 {
|
||||
compatible = "mediatek,mt7622-pciesys";
|
||||
reg = <0x1a100800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
45
Bindings/clock/mediatek,mt7622-ssusbsys.yaml
Normal file
45
Bindings/clock/mediatek,mt7622-ssusbsys.yaml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek SSUSBSYS clock and reset controller
|
||||
|
||||
description:
|
||||
The MediaTek SSUSBSYS controller provides various clocks to the system.
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7622-ssusbsys
|
||||
- mediatek,mt7629-ssusbsys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1a000000 {
|
||||
compatible = "mediatek,mt7622-ssusbsys";
|
||||
reg = <0x1a000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
51
Bindings/clock/mobileye,eyeq5-clk.yaml
Normal file
51
Bindings/clock/mobileye,eyeq5-clk.yaml
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mobileye EyeQ5 clock controller
|
||||
|
||||
description:
|
||||
The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
|
||||
crystal clock. It also exposes one divider clock, a child of one of the PLLs.
|
||||
Its registers live in a shared region called OLB.
|
||||
|
||||
maintainers:
|
||||
- Grégory Clement <gregory.clement@bootlin.com>
|
||||
- Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mobileye,eyeq5-clk
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: plls
|
||||
- const: ospi
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Input parent clock to all PLLs. Expected to be the main crystal.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -31,10 +31,15 @@ properties:
|
|||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: CX domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
@ -44,6 +49,7 @@ unevaluatedProperties: false
|
|||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8180x";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
|
|
@ -51,6 +57,7 @@ examples:
|
|||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
power-domains = <&rpmhpd SC8180X_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
vdd-gfx-supply:
|
||||
description: Regulator supply for the VDD_GFX pads
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
|
|
@ -74,6 +77,12 @@ required:
|
|||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
# Require that power-domains and vdd-gfx-supply are not both present
|
||||
not:
|
||||
required:
|
||||
- power-domains
|
||||
- vdd-gfx-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Q6SSTOP clock Controller
|
||||
|
||||
maintainers:
|
||||
- Govind Singh <govinds@codeaurora.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ description: |
|
|||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
@ -27,6 +28,7 @@ properties:
|
|||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ description: |
|
|||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8650-gpucc.h
|
||||
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -25,6 +26,7 @@ properties:
|
|||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
- qcom,x1e80100-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -14,12 +14,17 @@ description: |
|
|||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8550.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8550-dispcc
|
||||
- qcom,sm8650-dispcc
|
||||
- qcom,x1e80100-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ properties:
|
|||
- enum:
|
||||
- qcom,sm8550-tcsr
|
||||
- qcom,sm8650-tcsr
|
||||
- qcom,x1e80100-tcsr
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ properties:
|
|||
- renesas,r8a779a0-cpg-mssr # R-Car V3U
|
||||
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
|
||||
- renesas,r8a779g0-cpg-mssr # R-Car V4H
|
||||
- renesas,r8a779h0-cpg-mssr # R-Car V4M
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ properties:
|
|||
- samsung,exynos850-cmu-aud
|
||||
- samsung,exynos850-cmu-cmgp
|
||||
- samsung,exynos850-cmu-core
|
||||
- samsung,exynos850-cmu-cpucl0
|
||||
- samsung,exynos850-cmu-cpucl1
|
||||
- samsung,exynos850-cmu-dpu
|
||||
- samsung,exynos850-cmu-g3d
|
||||
- samsung,exynos850-cmu-hsi
|
||||
|
|
@ -152,6 +154,46 @@ allOf:
|
|||
- const: dout_core_mmc_embd
|
||||
- const: dout_core_sss
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-cpucl0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CPUCL0 switch clock (from CMU_TOP)
|
||||
- description: CPUCL0 debug clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_cpucl0_switch
|
||||
- const: dout_cpucl0_dbg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos850-cmu-cpucl1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CPUCL1 switch clock (from CMU_TOP)
|
||||
- description: CPUCL1 debug clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dout_cpucl1_switch
|
||||
- const: dout_cpucl1_dbg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ maintainers:
|
|||
|
||||
description: |
|
||||
FSD clock controller consist of several clock management unit
|
||||
(CMU), which generates clocks for various inteernal SoC blocks.
|
||||
(CMU), which generates clocks for various internal SoC blocks.
|
||||
The root clock comes from external OSC clock (24 MHz).
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments ADPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped ADPLL with two to three selectable input clocks
|
||||
and three to four children.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments APLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped APLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), with analog phase locked
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments autoidle clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a register mapped
|
||||
clock which can be put to idle automatically by hardware based on the usage
|
||||
and a configuration bit setting. Autoidle clock is never an individual
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments clockdomain.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1] in consumer role.
|
||||
Every clock on TI SoC belongs to one clockdomain, but software
|
||||
only needs this information for specific clocks which require
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for TI composite clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped composite clock with multiple different sub-types;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for TI divider clock
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped adjustable clock rate divider that does not gate and has
|
||||
only one input clock or parent. By default the value programmed into
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments DPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped DPLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), with digital phase locked
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments FAPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped FAPLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), and one or more child
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for TI fixed factor rate clock sources.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1], and also uses the autoidle
|
||||
support from TI autoidle clock [2].
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments gate clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features. If no register
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for Texas Instruments interface clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features, including
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
Binding for TI mux clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped multiplexer with multiple input clock signals or
|
||||
parents, one of which can be selected as output. This clock does not
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-aes
|
||||
oneOf:
|
||||
- const: atmel,at91sam9g46-aes
|
||||
- items:
|
||||
- const: microchip,sam9x7-aes
|
||||
- const: atmel,at91sam9g46-aes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-sha
|
||||
oneOf:
|
||||
- const: atmel,at91sam9g46-sha
|
||||
- items:
|
||||
- const: microchip,sam9x7-sha
|
||||
- const: atmel,at91sam9g46-sha
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-tdes
|
||||
oneOf:
|
||||
- const: atmel,at91sam9g46-tdes
|
||||
- items:
|
||||
- const: microchip,sam9x7-tdes
|
||||
- const: atmel,at91sam9g46-tdes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- qcom,sa8775p-inline-crypto-engine
|
||||
- qcom,sc7180-inline-crypto-engine
|
||||
- qcom,sm8450-inline-crypto-engine
|
||||
- qcom,sm8550-inline-crypto-engine
|
||||
- qcom,sm8650-inline-crypto-engine
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-qce
|
||||
- qcom,sm6350-qce
|
||||
- qcom,sm8250-qce
|
||||
- qcom,sm8350-qce
|
||||
- qcom,sm8450-qce
|
||||
|
|
|
|||
63
Bindings/display/atmel/atmel,hlcdc-display-controller.yaml
Normal file
63
Bindings/display/atmel/atmel,hlcdc-display-controller.yaml
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel's High LCD Controller (HLCDC)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The LCD Controller (LCDC) consists of logic for transferring LCD image
|
||||
data from an external display buffer to a TFT LCD panel. The LCDC has one
|
||||
display input buffer per layer that fetches pixels through the single bus
|
||||
host interface and a look-up table to allow palletized display
|
||||
configurations.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,hlcdc-display-controller
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Output endpoint of the controller, connecting the LCD panel signals.
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Endpoint connecting the LCD panel signals.
|
||||
|
||||
properties:
|
||||
bus-width:
|
||||
enum: [ 12, 16, 18, 24 ]
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- compatible
|
||||
- port@0
|
||||
|
||||
additionalProperties: false
|
||||
102
Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
Normal file
102
Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX8MP DWC HDMI TX Encoder
|
||||
|
||||
maintainers:
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
|
||||
description:
|
||||
The i.MX8MP HDMI transmitter is a Synopsys DesignWare
|
||||
HDMI 2.0a TX controller IP.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx8mp-hdmi-tx
|
||||
|
||||
reg-io-width:
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iahb
|
||||
- const: isfr
|
||||
- const: cec
|
||||
- const: pix
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Parallel RGB input port
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: HDMI output port
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/imx8mp-power.h>
|
||||
|
||||
hdmi@32fd8000 {
|
||||
compatible = "fsl,imx8mp-hdmi-tx";
|
||||
reg = <0x32fd8000 0x7eff>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
|
||||
<&clk IMX8MP_CLK_HDMI_REF_266M>,
|
||||
<&clk IMX8MP_CLK_32K>,
|
||||
<&hdmi_tx_phy>;
|
||||
clock-names = "iahb", "isfr", "cec", "pix";
|
||||
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
|
||||
reg-io-width = <1>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_tx_from_pvi: endpoint {
|
||||
remote-endpoint = <&pvi_to_hdmi_tx>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi_tx_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: SN65DSI86 DSI to eDP bridge chip
|
||||
|
||||
maintainers:
|
||||
- Sandeep Panda <spanda@codeaurora.org>
|
||||
- Douglas Anderson <dianders@chromium.org>
|
||||
|
||||
description: |
|
||||
The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
|
||||
|
|
|
|||
|
|
@ -120,13 +120,19 @@ allOf:
|
|||
maxItems: 1
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6sx-lcdif
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6sl-lcdif
|
||||
- fsl,imx6sx-lcdif
|
||||
- fsl,imx8mm-lcdif
|
||||
- fsl,imx8mn-lcdif
|
||||
- fsl,imx8mp-lcdif
|
||||
|
|
|
|||
84
Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
Normal file
84
Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX8MP HDMI Parallel Video Interface
|
||||
|
||||
maintainers:
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
|
||||
description:
|
||||
The HDMI parallel video interface is a timing and sync generator block in the
|
||||
i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-hdmi-pvi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Input from the LCDIF controller.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Output to the HDMI TX controller.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/imx8mp-power.h>
|
||||
|
||||
display-bridge@32fc4000 {
|
||||
compatible = "fsl,imx8mp-hdmi-pvi";
|
||||
reg = <0x32fc4000 0x44>;
|
||||
interrupt-parent = <&irqsteer_hdmi>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
pvi_from_lcdif3: endpoint {
|
||||
remote-endpoint = <&lcdif3_to_pvi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
pvi_to_hdmi_tx: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_from_pvi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
- qcom,msm8916-dsi-ctrl
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
- qcom,msm8974-dsi-ctrl
|
||||
- qcom,msm8976-dsi-ctrl
|
||||
- qcom,msm8996-dsi-ctrl
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
- qcom,qcm2290-dsi-ctrl
|
||||
|
|
@ -248,6 +249,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
- qcom,msm8976-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -224,6 +224,7 @@ allOf:
|
|||
enum:
|
||||
- qcom,adreno-gmu-730.1
|
||||
- qcom,adreno-gmu-740.1
|
||||
- qcom,adreno-gmu-750.1
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ properties:
|
|||
The driver is parsing the compat string for Adreno to
|
||||
figure out the gpu-id and patch level.
|
||||
items:
|
||||
- pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
|
||||
- pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
|
||||
- const: qcom,adreno
|
||||
- description: |
|
||||
The driver is parsing the compat string for Imageon to
|
||||
|
|
@ -127,7 +127,7 @@ allOf:
|
|||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
|
||||
pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
|
@ -203,7 +203,7 @@ allOf:
|
|||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
|
||||
pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
|
||||
|
||||
then: # Starting with A6xx, the clocks are usually defined in the GMU node
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -127,6 +127,7 @@ patternProperties:
|
|||
- qcom,dsi-phy-20nm
|
||||
- qcom,dsi-phy-28nm-8226
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-hpm-fam-b
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,hdmi-phy-8084
|
||||
- qcom,hdmi-phy-8660
|
||||
|
|
|
|||
|
|
@ -53,6 +53,15 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sm8150-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
|
|
|
|||
|
|
@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-dpu
|
||||
enum:
|
||||
- qcom,sm8650-dpu
|
||||
- qcom,x1e80100-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -37,18 +37,21 @@ properties:
|
|||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
|
|
@ -57,6 +60,7 @@ patternProperties:
|
|||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-dsi-phy-4nm
|
||||
|
|
|
|||
251
Bindings/display/msm/qcom,x1e80100-mdss.yaml
Normal file
251
Bindings/display/msm/qcom,x1e80100-mdss.yaml
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm X1E80100 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Abel Vesa <abel.vesa@linaro.org>
|
||||
|
||||
description:
|
||||
X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
|
||||
DPU display controller, DP interfaces, etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB
|
||||
- description: Display hf AXI
|
||||
- description: Display core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 3
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 3
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-dp
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-dp-phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
|
||||
#include <dt-bindings/phy/phy-qcom-qmp.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,x1e80100-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
|
||||
<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
|
||||
|
||||
resets = <&dispcc_core_bcr>;
|
||||
|
||||
power-domains = <&dispcc_gdsc>;
|
||||
|
||||
clocks = <&dispcc_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&dispcc_mdp_clk>;
|
||||
clock-names = "bus", "nrt_bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x1c00 0x2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,x1e80100-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc_axi_clk>,
|
||||
<&dispcc_ahb_clk>,
|
||||
<&dispcc_mdp_lut_clk>,
|
||||
<&dispcc_mdp_clk>,
|
||||
<&dispcc_mdp_vsync_clk>;
|
||||
clock-names = "nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc_mdp_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-325000000 {
|
||||
opp-hz = /bits/ 64 <325000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-375000000 {
|
||||
opp-hz = /bits/ 64 <375000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-514000000 {
|
||||
opp-hz = /bits/ 64 <514000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
compatible = "qcom,x1e80100-dp";
|
||||
reg = <0 0xae90000 0 0x200>,
|
||||
<0 0xae90200 0 0x200>,
|
||||
<0 0xae90400 0 0x600>,
|
||||
<0 0xae91000 0 0x400>,
|
||||
<0 0xae91400 0 0x400>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&dispcc_dptx0_aux_clk>,
|
||||
<&dispcc_dptx0_link_clk>,
|
||||
<&dispcc_dptx0_link_intf_clk>,
|
||||
<&dispcc_dptx0_pixel0_clk>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
|
||||
<&dispcc_mdss_dptx0_pixel0_clk_src>;
|
||||
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&mdss_dp0_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dp0_in: endpoint {
|
||||
remote-endpoint = <&mdss_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dp0_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
58
Bindings/display/panel/boe,th101mb31ig002-28a.yaml
Normal file
58
Bindings/display/panel/boe,th101mb31ig002-28a.yaml
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: BOE TH101MB31IG002-28A WXGA DSI Display Panel
|
||||
|
||||
maintainers:
|
||||
- Manuel Traut <manut@mecka.net>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
# BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel
|
||||
- boe,th101mb31ig002-28a
|
||||
|
||||
reg: true
|
||||
backlight: true
|
||||
enable-gpios: true
|
||||
power-supply: true
|
||||
port: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- enable-gpios
|
||||
- power-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "boe,th101mb31ig002-28a";
|
||||
reg = <0>;
|
||||
backlight = <&backlight_lcd0>;
|
||||
enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
|
||||
rotation = <90>;
|
||||
power-supply = <&vcc_3v3>;
|
||||
port {
|
||||
panel_in_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
74
Bindings/display/panel/himax,hx83112a.yaml
Normal file
74
Bindings/display/panel/himax,hx83112a.yaml
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Himax HX83112A-based DSI display panels
|
||||
|
||||
maintainers:
|
||||
- Luca Weiss <luca.weiss@fairphone.com>
|
||||
|
||||
description:
|
||||
The Himax HX83112A is a generic DSI Panel IC used to control
|
||||
LCD panels.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: djn,9a-3r063-1102b
|
||||
|
||||
vdd1-supply:
|
||||
description: Digital voltage rail
|
||||
|
||||
vsn-supply:
|
||||
description: Positive source voltage rail
|
||||
|
||||
vsp-supply:
|
||||
description: Negative source voltage rail
|
||||
|
||||
reg: true
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- vdd1-supply
|
||||
- vsn-supply
|
||||
- vsp-supply
|
||||
- port
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "djn,9a-3r063-1102b";
|
||||
reg = <0>;
|
||||
|
||||
backlight = <&pm6150l_wled>;
|
||||
reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vdd1-supply = <&vreg_l1e>;
|
||||
vsn-supply = <&pm6150l_lcdb_ncp>;
|
||||
vsp-supply = <&pm6150l_lcdb_ldo>;
|
||||
|
||||
port {
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -14,7 +14,9 @@ allOf:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: leadtek,ltk500hd1829
|
||||
enum:
|
||||
- leadtek,ltk101b4029w
|
||||
- leadtek,ltk500hd1829
|
||||
reg: true
|
||||
backlight: true
|
||||
reset-gpios: true
|
||||
|
|
|
|||
|
|
@ -15,7 +15,9 @@ allOf:
|
|||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: hydis,hva40wv1
|
||||
- enum:
|
||||
- frida,frd400b25025
|
||||
- hydis,hva40wv1
|
||||
- const: novatek,nt35510
|
||||
description: This indicates the panel manufacturer of the panel
|
||||
that is in turn using the NT35510 panel driver. The compatible
|
||||
|
|
@ -29,6 +31,7 @@ properties:
|
|||
vddi-supply:
|
||||
description: regulator that supplies the vddi voltage
|
||||
backlight: true
|
||||
port: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
66
Bindings/display/panel/novatek,nt36672e.yaml
Normal file
66
Bindings/display/panel/novatek,nt36672e.yaml
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/novatek,nt36672e.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Novatek NT36672E LCD DSI Panel
|
||||
|
||||
maintainers:
|
||||
- Ritesh Kumar <quic_riteshk@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: novatek,nt36672e
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: DSI virtual channel
|
||||
|
||||
vddi-supply: true
|
||||
avdd-supply: true
|
||||
avee-supply: true
|
||||
port: true
|
||||
reset-gpios: true
|
||||
backlight: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vddi-supply
|
||||
- avdd-supply
|
||||
- avee-supply
|
||||
- reset-gpios
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "novatek,nt36672e";
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vddi-supply = <&vreg_l8c_1p8>;
|
||||
avdd-supply = <&disp_avdd>;
|
||||
avee-supply = <&disp_avee>;
|
||||
|
||||
backlight = <&pwm_backlight>;
|
||||
|
||||
port {
|
||||
panel0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -39,9 +39,13 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# Admatec 9904379 10.1" 1024x600 LVDS panel
|
||||
- admatec,9904379
|
||||
- auo,b101ew05
|
||||
# Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
|
||||
- chunghwa,claa070wp03xg
|
||||
# EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
|
||||
- edt,etml0700z9ndha
|
||||
# HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel
|
||||
- hannstar,hsd101pww2
|
||||
# Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel
|
||||
|
|
|
|||
|
|
@ -73,6 +73,8 @@ properties:
|
|||
- auo,t215hvn01
|
||||
# Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
|
||||
- avic,tm070ddh03
|
||||
# BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel
|
||||
- boe,bp082wx1-100
|
||||
# BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel
|
||||
- boe,bp101wx1-100
|
||||
# BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
|
||||
|
|
@ -141,6 +143,8 @@ properties:
|
|||
- edt,etm0700g0edh6
|
||||
# Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch
|
||||
- edt,etml0700y5dha
|
||||
# Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch
|
||||
- edt,etml1010g3dra
|
||||
# Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with
|
||||
# capacitive touch
|
||||
- edt,etmv570g2dhu
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@ properties:
|
|||
enum:
|
||||
# Anberic RG353V-V2 5.0" 640x480 TFT LCD panel
|
||||
- anbernic,rg353v-panel-v2
|
||||
# Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel
|
||||
- powkiddy,rgb10max3-panel
|
||||
# Powkiddy RGB30 3.0" 720x720 TFT LCD panel
|
||||
- powkiddy,rgb30-panel
|
||||
# Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
|
||||
|
|
@ -43,6 +45,7 @@ properties:
|
|||
reset-gpios: true
|
||||
|
||||
backlight: true
|
||||
rotation: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml#
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Visionox model RM69299 Panels
|
||||
|
||||
maintainers:
|
||||
- Harigovindan P <harigovi@codeaurora.org>
|
||||
- Abhinav Kumar <quic_abhinavk@quicinc.com>
|
||||
- Jessica Zhang <quic_jesszhan@quicinc.com>
|
||||
|
||||
description: |
|
||||
This binding is for display panels using a Visionox RM692999 panel.
|
||||
|
|
|
|||
126
Bindings/display/renesas,rzg2l-du.yaml
Normal file
126
Bindings/display/renesas,rzg2l-du.yaml
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L Display Unit (DU)
|
||||
|
||||
maintainers:
|
||||
- Biju Das <biju.das.jz@bp.renesas.com>
|
||||
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
|
||||
and RZ/V2L SoCs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- renesas,r9a07g044-du # RZ/G2{L,LC}
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g054-du # RZ/V2L
|
||||
- const: renesas,r9a07g044-du # RZ/G2L fallback
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main clock
|
||||
- description: Register access clock
|
||||
- description: Video clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
- const: vclk
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
The connections to the DU output video ports are modeled using the OF
|
||||
graph bindings. The number of ports and their assignment are
|
||||
model-dependent. Each port shall have a single endpoint.
|
||||
|
||||
patternProperties:
|
||||
"^port@[0-1]$":
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
renesas,vsps:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle to VSP instance that serves the DU channel
|
||||
- description: Channel index identifying the LIF instance in that VSP
|
||||
description:
|
||||
A list of phandle and channel index tuples to the VSPs that handle the
|
||||
memory interfaces for the DU channels.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- power-domains
|
||||
- ports
|
||||
- renesas,vsps
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# RZ/G2L DU
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
display@10890000 {
|
||||
compatible = "renesas,r9a07g044-du";
|
||||
reg = <0x10890000 0x10000>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
|
||||
<&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
|
||||
<&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
|
||||
clock-names = "aclk", "pclk", "vclk";
|
||||
resets = <&cpg R9A07G044_LCDC_RESET_N>;
|
||||
power-domains = <&cpg>;
|
||||
|
||||
renesas,vsps = <&vspd0 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -94,11 +94,14 @@ properties:
|
|||
- const: default
|
||||
- const: unwedge
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
patternProperties:
|
||||
"^port(@0)?$":
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Input of the DWC HDMI TX
|
||||
properties:
|
||||
|
|
@ -108,11 +111,14 @@ properties:
|
|||
description: Connection to the VOPB
|
||||
endpoint@1:
|
||||
description: Connection to the VOPL
|
||||
properties:
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Output of the DWC HDMI TX
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
|
|
@ -135,19 +141,25 @@ examples:
|
|||
#include <dt-bindings/clock/rk3288-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/rk3288-power.h>
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
compatible = "rockchip,rk3288-dw-hdmi";
|
||||
reg = <0xff980000 0x20000>;
|
||||
reg-io-width = <4>;
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
rockchip,grf = <&grf>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
||||
clock-names = "iahb", "isfr";
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
power-domains = <&power RK3288_PD_VIO>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
ports {
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -155,11 +167,20 @@ examples:
|
|||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_hdmi>;
|
||||
};
|
||||
|
||||
hdmi_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -131,9 +131,9 @@ allOf:
|
|||
const: sinowealth,sh1106
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 132
|
||||
height:
|
||||
solomon,height:
|
||||
default: 64
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
|
|
@ -149,9 +149,9 @@ allOf:
|
|||
- solomon,ssd1305
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 132
|
||||
height:
|
||||
solomon,height:
|
||||
default: 64
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
|
|
@ -167,9 +167,9 @@ allOf:
|
|||
- solomon,ssd1306
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 128
|
||||
height:
|
||||
solomon,height:
|
||||
default: 64
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
|
|
@ -185,9 +185,9 @@ allOf:
|
|||
- solomon,ssd1307
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 128
|
||||
height:
|
||||
solomon,height:
|
||||
default: 39
|
||||
solomon,dclk-div:
|
||||
default: 2
|
||||
|
|
@ -205,9 +205,9 @@ allOf:
|
|||
- solomon,ssd1309
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 128
|
||||
height:
|
||||
solomon,height:
|
||||
default: 64
|
||||
solomon,dclk-div:
|
||||
default: 1
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@ allOf:
|
|||
const: solomon,ssd1322
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 480
|
||||
height:
|
||||
solomon,height:
|
||||
default: 128
|
||||
|
||||
- if:
|
||||
|
|
@ -42,9 +42,9 @@ allOf:
|
|||
const: solomon,ssd1325
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 128
|
||||
height:
|
||||
solomon,height:
|
||||
default: 80
|
||||
|
||||
- if:
|
||||
|
|
@ -54,9 +54,9 @@ allOf:
|
|||
const: solomon,ssd1327
|
||||
then:
|
||||
properties:
|
||||
width:
|
||||
solomon,width:
|
||||
default: 128
|
||||
height:
|
||||
solomon,height:
|
||||
default: 128
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
|
|
|||
45
Bindings/display/solomon,ssd133x.yaml
Normal file
45
Bindings/display/solomon,ssd133x.yaml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/solomon,ssd133x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Solomon SSD133x OLED Display Controllers
|
||||
|
||||
maintainers:
|
||||
- Javier Martinez Canillas <javierm@redhat.com>
|
||||
|
||||
allOf:
|
||||
- $ref: solomon,ssd-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- solomon,ssd1331
|
||||
|
||||
solomon,width:
|
||||
default: 96
|
||||
|
||||
solomon,height:
|
||||
default: 64
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
oled@0 {
|
||||
compatible = "solomon,ssd1331";
|
||||
reg = <0x0>;
|
||||
reset-gpios = <&gpio2 7>;
|
||||
dc-gpios = <&gpio2 8>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -37,6 +37,7 @@ properties:
|
|||
- description: OVR2 overlay manager for vp2
|
||||
- description: VP1 video port 1
|
||||
- description: VP2 video port 2
|
||||
- description: common1 DSS register area
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
|
|
@ -47,6 +48,7 @@ properties:
|
|||
- const: ovr2
|
||||
- const: vp1
|
||||
- const: vp2
|
||||
- const: common1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -147,9 +149,10 @@ examples:
|
|||
<0x04a07000 0x1000>, /* ovr1 */
|
||||
<0x04a08000 0x1000>, /* ovr2 */
|
||||
<0x04a0a000 0x1000>, /* vp1 */
|
||||
<0x04a0b000 0x1000>; /* vp2 */
|
||||
<0x04a0b000 0x1000>, /* vp2 */
|
||||
<0x04a01000 0x1000>; /* common1 */
|
||||
reg-names = "common", "vidl1", "vid",
|
||||
"ovr1", "ovr2", "vp1", "vp2";
|
||||
"ovr1", "ovr2", "vp1", "vp2", "common1";
|
||||
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
|
||||
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 67 1>,
|
||||
|
|
|
|||
|
|
@ -28,6 +28,9 @@ properties:
|
|||
- items:
|
||||
- const: allwinner,sun8i-r40-dma
|
||||
- const: allwinner,sun50i-a64-dma
|
||||
- items:
|
||||
- const: allwinner,sun50i-h616-dma
|
||||
- const: allwinner,sun50i-a100-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -59,10 +62,11 @@ required:
|
|||
if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun20i-d1-dma
|
||||
- allwinner,sun50i-a100-dma
|
||||
- allwinner,sun50i-h6-dma
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun20i-d1-dma
|
||||
- allwinner,sun50i-a100-dma
|
||||
- allwinner,sun50i-h6-dma
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ properties:
|
|||
- fsl,imx8qm-edma
|
||||
- fsl,imx93-edma3
|
||||
- fsl,imx93-edma4
|
||||
- fsl,imx95-edma5
|
||||
- items:
|
||||
- const: fsl,ls1028a-edma
|
||||
- const: fsl,vf610-edma
|
||||
|
|
@ -83,6 +84,7 @@ allOf:
|
|||
- fsl,imx8qm-edma
|
||||
- fsl,imx93-edma3
|
||||
- fsl,imx93-edma4
|
||||
- fsl,imx95-edma5
|
||||
then:
|
||||
properties:
|
||||
"#dma-cells":
|
||||
|
|
|
|||
|
|
@ -92,7 +92,8 @@ properties:
|
|||
description: needs firmware more than ver 2
|
||||
- Shared ASRC: 23
|
||||
- SAI: 24
|
||||
- HDMI Audio: 25
|
||||
- Multi SAI: 25
|
||||
- HDMI Audio: 26
|
||||
|
||||
The third cell: transfer priority ID
|
||||
enum:
|
||||
|
|
|
|||
72
Bindings/dma/marvell,mmp-dma.yaml
Normal file
72
Bindings/dma/marvell,mmp-dma.yaml
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MMP DMA controller
|
||||
|
||||
maintainers:
|
||||
- Duje Mihanović <duje.mihanovic@skole.hr>
|
||||
|
||||
description:
|
||||
Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,pdma-1.0
|
||||
- marvell,adma-1.0
|
||||
- marvell,pxa910-squ
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Interrupt lines for the controller, may be shared or one per DMA channel
|
||||
minItems: 1
|
||||
|
||||
asram:
|
||||
description:
|
||||
A phandle to the SRAM pool
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
'#dma-channels':
|
||||
deprecated: true
|
||||
|
||||
'#dma-requests':
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#dma-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- marvell,pdma-1.0
|
||||
then:
|
||||
properties:
|
||||
asram: false
|
||||
else:
|
||||
required:
|
||||
- asram
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-controller@d4000000 {
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0xd4000000 0x10000>;
|
||||
interrupts = <47>;
|
||||
#dma-cells = <2>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
63
Bindings/dma/mediatek,mt7622-hsdma.yaml
Normal file
63
Bindings/dma/mediatek,mt7622-hsdma.yaml
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek High-Speed DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Sean Wang <sean.wang@mediatek.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7622-hsdma
|
||||
- mediatek,mt7623-hsdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: hsdma
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#dma-cells":
|
||||
description: Channel number
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt2701-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/mt2701-power.h>
|
||||
|
||||
dma-controller@1b007000 {
|
||||
compatible = "mediatek,mt7623-hsdma";
|
||||
reg = <0x1b007000 0x1000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <ðsys CLK_ETHSYS_HSDMA>;
|
||||
clock-names = "hsdma";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
|
@ -46,6 +46,7 @@ properties:
|
|||
- renesas,dmac-r8a779a0 # R-Car V3U
|
||||
- renesas,dmac-r8a779f0 # R-Car S4-8
|
||||
- renesas,dmac-r8a779g0 # R-Car V4H
|
||||
- renesas,dmac-r8a779h0 # R-Car V4M
|
||||
- const: renesas,rcar-gen4-dmac # R-Car Gen4
|
||||
|
||||
reg: true
|
||||
|
|
|
|||
|
|
@ -144,6 +144,8 @@ Example::
|
|||
#dma-cells = <1>;
|
||||
clocks = <&clock_controller 0>, <&clock_controller 1>;
|
||||
clock-names = "bus", "host";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
vendor,custom-property = <2>;
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
|
|
@ -68,14 +68,10 @@ properties:
|
|||
pattern: cs16$
|
||||
- items:
|
||||
pattern: c32$
|
||||
- items:
|
||||
pattern: c32d-wl$
|
||||
- items:
|
||||
pattern: cs32$
|
||||
- items:
|
||||
pattern: c64$
|
||||
- items:
|
||||
pattern: c64d-wl$
|
||||
- items:
|
||||
pattern: cs64$
|
||||
- items:
|
||||
|
|
@ -136,6 +132,7 @@ properties:
|
|||
- renesas,r1ex24128
|
||||
- samsung,s524ad0xd1
|
||||
- const: atmel,24c128
|
||||
- pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st
|
||||
|
||||
label:
|
||||
description: Descriptive name of the EEPROM.
|
||||
|
|
|
|||
|
|
@ -26,6 +26,12 @@ properties:
|
|||
- description: For implementations complying for Versal.
|
||||
const: xlnx,versal-firmware
|
||||
|
||||
- description: For implementations complying for Versal NET.
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,versal-net-firmware
|
||||
- const: xlnx,versal-firmware
|
||||
|
||||
method:
|
||||
description: |
|
||||
The method of calling the PM-API firmware layer.
|
||||
|
|
@ -41,7 +47,53 @@ properties:
|
|||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
versal_fpga:
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/xlnx,versal-clk.yaml#
|
||||
description: The clock controller is a hardware block of Xilinx versal
|
||||
clock tree. It reads required input clock frequencies from the devicetree
|
||||
and acts as clock provider for all clock consumers of PS clocks.list of
|
||||
clock specifiers which are external input clocks to the given clock
|
||||
controller.
|
||||
type: object
|
||||
|
||||
gpio:
|
||||
$ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
|
||||
description: The gpio node describes connect to PS_MODE pins via firmware
|
||||
interface.
|
||||
type: object
|
||||
|
||||
soc-nvmem:
|
||||
$ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
|
||||
description: The ZynqMP MPSoC provides access to the hardware related data
|
||||
like SOC revision, IDCODE and specific purpose efuses.
|
||||
type: object
|
||||
|
||||
pcap:
|
||||
$ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
|
||||
description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
|
||||
configure the Programmable Logic (PL). The configuration uses the
|
||||
firmware interface.
|
||||
type: object
|
||||
|
||||
pinctrl:
|
||||
$ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
|
||||
description: The pinctrl node provides access to pinconfig and pincontrol
|
||||
functionality available in firmware.
|
||||
type: object
|
||||
|
||||
power-management:
|
||||
$ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
|
||||
description: The zynqmp-power node describes the power management
|
||||
configurations. It will control remote suspend/shutdown interfaces.
|
||||
type: object
|
||||
|
||||
reset-controller:
|
||||
$ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
|
||||
description: The reset-controller node describes connection to the reset
|
||||
functionality via firmware interface.
|
||||
type: object
|
||||
|
||||
versal-fpga:
|
||||
$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
|
||||
description: Compatible of the FPGA device.
|
||||
type: object
|
||||
|
|
@ -53,15 +105,6 @@ properties:
|
|||
vector.
|
||||
type: object
|
||||
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/xlnx,versal-clk.yaml#
|
||||
description: The clock controller is a hardware block of Xilinx versal
|
||||
clock tree. It reads required input clock frequencies from the devicetree
|
||||
and acts as clock provider for all clock consumers of PS clocks.list of
|
||||
clock specifiers which are external input clocks to the given clock
|
||||
controller.
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
@ -73,7 +116,38 @@ examples:
|
|||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
#power-domain-cells = <1>;
|
||||
soc-nvmem {
|
||||
compatible = "xlnx,zynqmp-nvmem-fw";
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
soc_revision: soc-revision@0 {
|
||||
reg = <0x0 0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
gpio {
|
||||
compatible = "xlnx,zynqmp-gpio-modepin";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
};
|
||||
pinctrl {
|
||||
compatible = "xlnx,zynqmp-pinctrl";
|
||||
};
|
||||
power-management {
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
interrupts = <0 35 4>;
|
||||
};
|
||||
reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
|
|
@ -84,7 +158,7 @@ examples:
|
|||
compatible = "xlnx,versal-firmware";
|
||||
method = "smc";
|
||||
|
||||
versal_fpga: versal_fpga {
|
||||
versal_fpga: versal-fpga {
|
||||
compatible = "xlnx,versal-fpga";
|
||||
};
|
||||
|
||||
|
|
|
|||
358
Bindings/fpga/fpga-region.yaml
Normal file
358
Bindings/fpga/fpga-region.yaml
Normal file
|
|
@ -0,0 +1,358 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: FPGA Region
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
description: |
|
||||
CONTENTS
|
||||
- Introduction
|
||||
- Terminology
|
||||
- Sequence
|
||||
- FPGA Region
|
||||
- Supported Use Models
|
||||
- Constraints
|
||||
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
|
||||
the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
|
||||
control.
|
||||
|
||||
The documentation hits some of the high points of FPGA usage and
|
||||
attempts to include terminology used by both major FPGA manufacturers. This
|
||||
document isn't a replacement for any manufacturers specifications for FPGA
|
||||
usage.
|
||||
|
||||
|
||||
Terminology
|
||||
===========
|
||||
|
||||
Full Reconfiguration
|
||||
* The entire FPGA is programmed.
|
||||
|
||||
Partial Reconfiguration (PR)
|
||||
* A section of an FPGA is reprogrammed while the rest of the FPGA is not
|
||||
affected.
|
||||
* Not all FPGA's support PR.
|
||||
|
||||
Partial Reconfiguration Region (PRR)
|
||||
* Also called a "reconfigurable partition"
|
||||
* A PRR is a specific section of an FPGA reserved for reconfiguration.
|
||||
* A base (or static) FPGA image may create a set of PRR's that later may
|
||||
be independently reprogrammed many times.
|
||||
* The size and specific location of each PRR is fixed.
|
||||
* The connections at the edge of each PRR are fixed. The image that is loaded
|
||||
into a PRR must fit and must use a subset of the region's connections.
|
||||
* The busses within the FPGA are split such that each region gets its own
|
||||
branch that may be gated independently.
|
||||
|
||||
Persona
|
||||
* Also called a "partial bit stream"
|
||||
* An FPGA image that is designed to be loaded into a PRR. There may be
|
||||
any number of personas designed to fit into a PRR, but only one at a time
|
||||
may be loaded.
|
||||
* A persona may create more regions.
|
||||
|
||||
FPGA Bridge
|
||||
* FPGA Bridges gate bus signals between a host and FPGA.
|
||||
* FPGA Bridges should be disabled while the FPGA is being programmed to
|
||||
prevent spurious signals on the cpu bus and to the soft logic.
|
||||
* FPGA bridges may be actual hardware or soft logic on an FPGA.
|
||||
* During Full Reconfiguration, hardware bridges between the host and FPGA
|
||||
will be disabled.
|
||||
* During Partial Reconfiguration of a specific region, that region's bridge
|
||||
will be used to gate the busses. Traffic to other regions is not affected.
|
||||
* In some implementations, the FPGA Manager transparently handles gating the
|
||||
buses, eliminating the need to show the hardware FPGA bridges in the
|
||||
device tree.
|
||||
* An FPGA image may create a set of reprogrammable regions, each having its
|
||||
own bridge and its own split of the busses in the FPGA.
|
||||
|
||||
FPGA Manager
|
||||
* An FPGA Manager is a hardware block that programs an FPGA under the control
|
||||
of a host processor.
|
||||
|
||||
Base Image
|
||||
* Also called the "static image"
|
||||
* An FPGA image that is designed to do full reconfiguration of the FPGA.
|
||||
* A base image may set up a set of partial reconfiguration regions that may
|
||||
later be reprogrammed.
|
||||
|
||||
---------------- ----------------------------------
|
||||
| Host CPU | | FPGA |
|
||||
| | | |
|
||||
| ----| | ----------- -------- |
|
||||
| | H | | |==>| Bridge0 |<==>| PRR0 | |
|
||||
| | W | | | ----------- -------- |
|
||||
| | | | | |
|
||||
| | B |<=====>|<==| ----------- -------- |
|
||||
| | R | | |==>| Bridge1 |<==>| PRR1 | |
|
||||
| | I | | | ----------- -------- |
|
||||
| | D | | | |
|
||||
| | G | | | ----------- -------- |
|
||||
| | E | | |==>| Bridge2 |<==>| PRR2 | |
|
||||
| ----| | ----------- -------- |
|
||||
| | | |
|
||||
---------------- ----------------------------------
|
||||
|
||||
Figure 1: An FPGA set up with a base image that created three regions. Each
|
||||
region (PRR0-2) gets its own split of the busses that is independently gated by
|
||||
a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
|
||||
reprogrammed independently while the rest of the system continues to function.
|
||||
|
||||
|
||||
Sequence
|
||||
========
|
||||
|
||||
When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
|
||||
do the following:
|
||||
|
||||
1. Disable appropriate FPGA bridges.
|
||||
2. Program the FPGA using the FPGA manager.
|
||||
3. Enable the FPGA bridges.
|
||||
4. The Device Tree overlay is accepted into the live tree.
|
||||
5. Child devices are populated.
|
||||
|
||||
When the overlay is removed, the child nodes will be removed and the FPGA Region
|
||||
will disable the bridges.
|
||||
|
||||
|
||||
FPGA Region
|
||||
===========
|
||||
|
||||
FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
|
||||
Region brings together the elements needed to program on a running system and
|
||||
add the child devices:
|
||||
|
||||
* FPGA Manager
|
||||
* FPGA Bridges
|
||||
* image-specific information needed to the programming.
|
||||
* child nodes
|
||||
|
||||
The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
|
||||
FPGA while an operating system is running.
|
||||
|
||||
An FPGA Region that exists in the live Device Tree reflects the current state.
|
||||
If the live tree shows a "firmware-name" property or child nodes under an FPGA
|
||||
Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
|
||||
and adds the "firmware-name" property is taken as a request to reprogram the
|
||||
FPGA. After reprogramming is successful, the overlay is accepted into the live
|
||||
tree.
|
||||
|
||||
The base FPGA Region in the device tree represents the FPGA and supports full
|
||||
reconfiguration. It must include a phandle to an FPGA Manager. The base
|
||||
FPGA region will be the child of one of the hardware bridges (the bridge that
|
||||
allows register access) between the cpu and the FPGA. If there are more than
|
||||
one bridge to control during FPGA programming, the region will also contain a
|
||||
list of phandles to the additional hardware FPGA Bridges.
|
||||
|
||||
For partial reconfiguration (PR), each PR region will have an FPGA Region.
|
||||
These FPGA regions are children of FPGA bridges which are then children of the
|
||||
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
|
||||
this.
|
||||
|
||||
If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
|
||||
Manager specified by its ancestor FPGA Region. This supports both the case
|
||||
where the same FPGA Manager is used for all of an FPGA as well the case where
|
||||
a different FPGA Manager is used for each region.
|
||||
|
||||
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
|
||||
shutting down bridges that are upstream from the other active regions while one
|
||||
region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
|
||||
hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
|
||||
within the static image of the FPGA.
|
||||
|
||||
|
||||
Supported Use Models
|
||||
====================
|
||||
|
||||
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
|
||||
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
|
||||
uses are specific to an FPGA device.
|
||||
|
||||
* No FPGA Bridges
|
||||
In this case, the FPGA Manager which programs the FPGA also handles the
|
||||
bridges behind the scenes. No FPGA Bridge devices are needed for full
|
||||
reconfiguration.
|
||||
|
||||
* Full reconfiguration with hardware bridges
|
||||
In this case, there are hardware bridges between the processor and FPGA that
|
||||
need to be controlled during full reconfiguration. Before the overlay is
|
||||
applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
|
||||
FPGA Region. The FPGA Region is the child of the bridge that allows
|
||||
register access to the FPGA. Additional bridges may be listed in a
|
||||
fpga-bridges property in the FPGA region or in the device tree overlay.
|
||||
|
||||
* Partial reconfiguration with bridges in the FPGA
|
||||
In this case, the FPGA will have one or more PRR's that may be programmed
|
||||
separately while the rest of the FPGA can remain active. To manage this,
|
||||
bridges need to exist in the FPGA that can gate the buses going to each FPGA
|
||||
region while the buses are enabled for other sections. Before any partial
|
||||
reconfiguration can be done, a base FPGA image must be loaded which includes
|
||||
PRR's with FPGA bridges. The device tree should have an FPGA region for each
|
||||
PRR.
|
||||
|
||||
Constraints
|
||||
===========
|
||||
|
||||
It is beyond the scope of this document to fully describe all the FPGA design
|
||||
constraints required to make partial reconfiguration work[1] [2] [3], but a few
|
||||
deserve quick mention.
|
||||
|
||||
A persona must have boundary connections that line up with those of the partition
|
||||
or region it is designed to go into.
|
||||
|
||||
During programming, transactions through those connections must be stopped and
|
||||
the connections must be held at a fixed logic level. This can be achieved by
|
||||
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
|
||||
|
||||
--
|
||||
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
|
||||
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
|
||||
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
|
||||
|
||||
compatible:
|
||||
const: fpga-region
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
"#address-cells": true
|
||||
"#size-cells": true
|
||||
|
||||
config-complete-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds time for the FPGA to go to operating
|
||||
mode after the region has been programmed.
|
||||
|
||||
encrypted-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if the bitstream is encrypted.
|
||||
|
||||
external-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if the FPGA has already been configured prior to OS boot up.
|
||||
|
||||
firmware-name:
|
||||
maxItems: 1
|
||||
description:
|
||||
Should contain the name of an FPGA image file located on the firmware
|
||||
search path. If this property shows up in a live device tree it indicates
|
||||
that the FPGA has already been programmed with this image.
|
||||
If this property is in an overlay targeting an FPGA region, it is
|
||||
a request to program the FPGA with that image.
|
||||
|
||||
fpga-bridges:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should contain a list of phandles to FPGA Bridges that must be
|
||||
controlled during FPGA programming along with the parent FPGA bridge.
|
||||
This property is optional if the FPGA Manager handles the bridges.
|
||||
If the fpga-region is the child of an fpga-bridge, the list should not
|
||||
contain the parent bridge.
|
||||
|
||||
fpga-mgr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Should contain a phandle to an FPGA Manager. Child FPGA Regions
|
||||
inherit this property from their ancestor regions. An fpga-mgr property
|
||||
in a region will override any inherited FPGA manager.
|
||||
|
||||
partial-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if partial reconfiguration is to be done, otherwise full
|
||||
reconfiguration is done.
|
||||
|
||||
region-freeze-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds to wait for bridges to successfully
|
||||
become disabled before the region has been programmed.
|
||||
|
||||
region-unfreeze-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds to wait for bridges to successfully
|
||||
become enabled after the region has been programmed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- fpga-mgr
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
/*
|
||||
* Full Reconfiguration without Bridges with DT overlay
|
||||
*/
|
||||
fpga_region0: fpga-region@0 {
|
||||
compatible = "fpga-region";
|
||||
reg = <0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
fpga-mgr = <&fpga_mgr0>;
|
||||
ranges = <0x10000000 0x20000000 0x10000000>;
|
||||
|
||||
/* DT Overlay contains: &fpga_region0 */
|
||||
firmware-name = "zynq-gpio.bin";
|
||||
gpio@40000000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = <0x40000000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/*
|
||||
* Partial reconfiguration with bridge
|
||||
*/
|
||||
fpga_region1: fpga-region@0 {
|
||||
compatible = "fpga-region";
|
||||
reg = <0 0>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
fpga-mgr = <&fpga_mgr1>;
|
||||
fpga-bridges = <&fpga_bridge1>;
|
||||
partial-fpga-config;
|
||||
|
||||
/* DT Overlay contains: &fpga_region1 */
|
||||
firmware-name = "zynq-gpio-partial.bin";
|
||||
clk: clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
gpio@40000000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = <0x40000000 0x10000>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
clocks = <&clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -26,7 +26,7 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
versal_fpga: versal_fpga {
|
||||
versal_fpga: versal-fpga {
|
||||
compatible = "xlnx,versal-fpga";
|
||||
};
|
||||
|
||||
|
|
|
|||
148
Bindings/gpio/aspeed,ast2400-gpio.yaml
Normal file
148
Bindings/gpio/aspeed,ast2400-gpio.yaml
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Aspeed GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Andrew Jeffery <andrew@codeconstruct.com.au>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- aspeed,ast2400-gpio
|
||||
- aspeed,ast2500-gpio
|
||||
- aspeed,ast2600-gpio
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: The clock to use for debounce timings
|
||||
|
||||
gpio-controller: true
|
||||
gpio-line-names:
|
||||
minItems: 36
|
||||
maxItems: 232
|
||||
|
||||
gpio-ranges: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
minimum: 36
|
||||
maximum: 232
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: aspeed,ast2400-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 220
|
||||
maxItems: 220
|
||||
ngpios:
|
||||
const: 220
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: aspeed,ast2500-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 232
|
||||
maxItems: 232
|
||||
ngpios:
|
||||
const: 232
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: aspeed,ast2600-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 36
|
||||
maxItems: 208
|
||||
ngpios:
|
||||
enum: [ 36, 208 ]
|
||||
required:
|
||||
- ngpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gpio@1e780000 {
|
||||
compatible = "aspeed,ast2400-gpio";
|
||||
reg = <0x1e780000 0x1000>;
|
||||
interrupts = <20>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
- |
|
||||
gpio: gpio@1e780000 {
|
||||
compatible = "aspeed,ast2500-gpio";
|
||||
reg = <0x1e780000 0x200>;
|
||||
interrupts = <20>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 232>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/clock/ast2600-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
gpio0: gpio@1e780000 {
|
||||
compatible = "aspeed,ast2600-gpio";
|
||||
reg = <0x1e780000 0x400>;
|
||||
clocks = <&syscon ASPEED_CLK_APB2>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 208>;
|
||||
ngpios = <208>;
|
||||
};
|
||||
gpio1: gpio@1e780800 {
|
||||
compatible = "aspeed,ast2600-gpio";
|
||||
reg = <0x1e780800 0x800>;
|
||||
clocks = <&syscon ASPEED_CLK_APB1>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 208 36>;
|
||||
ngpios = <36>;
|
||||
};
|
||||
|
|
@ -1,7 +1,6 @@
|
|||
Gateworks PLD GPIO controller bindings
|
||||
|
||||
The GPIO controller should be a child node on an I2C bus,
|
||||
see: i2c/i2c.txt for details.
|
||||
The GPIO controller should be a child node on an I2C bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "gateworks,pld-gpio"
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ allOf:
|
|||
required:
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: true
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue