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Bring over my FreeBSD modifications for the AR9300 HAL to make it

Browse source 
work in FreeBSD.

This is still heavily a work in progress but I'd rather it start
shipping in -HEAD sooner rather than later.

This doesn't (yet) link it into the build system either for a static
kernel or as a module; that will come later (after many, many make universe
tests.)
This commit is contained in:
Adrian Chadd 2013-04-28 00:57:47 +00:00
parent 76bd547b9c
commit e113789bdc
32 changed files with 4642 additions and 1172 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

174
sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h
View file

@ -17,11 +17,31 @@
#ifndef _ATH_AR9300_H_
#define _ATH_AR9300_H_
#include "ar9300_freebsd_inc.h"
#define AH_BIG_ENDIAN 4321
#define AH_LITTLE_ENDIAN 1234
#if _BYTE_ORDER == _BIG_ENDIAN
#define AH_BYTE_ORDER AH_BIG_ENDIAN
#else
#define AH_BYTE_ORDER AH_LITTLE_ENDIAN
#endif
/* XXX doesn't belong here */
#define AR_EEPROM_MODAL_SPURS 5
/*
* (a) this should be N(a),
* (b) FreeBSD does define nitems,
* (c) it doesn't have an AH_ prefix, sigh.
*/
#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0]))
#include "ah_internal.h"
#include "ah_eeprom.h"
#include "ah_devid.h"
#include "ar9300eep.h" /* For Eeprom definitions */
#include "asf_amem.h"
#define AR9300_MAGIC 0x19741014
@ -117,9 +137,9 @@ typedef struct {
/* RF HAL structures */
typedef struct rf_hal_funcs {
HAL_BOOL (*set_channel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, HAL_CHANNEL *chans,
u_int32_t nchancs);
HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *);
HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah,
struct ieee80211_channel *chan);
} RF_HAL_FUNCS;
struct ar9300_ani_default {
@ -143,7 +163,7 @@ struct ar9300_ani_default {
* Per-channel ANI state private to the driver.
*/
struct ar9300_ani_state {
HAL_CHANNEL c;
struct ieee80211_channel c; /* XXX ew? */
HAL_BOOL must_restore;
HAL_BOOL ofdms_turn;
u_int8_t ofdm_noise_immunity_level;
@ -256,7 +276,7 @@ struct ar9300_ar_state {
};
struct ar9300_radar_state {
HAL_CHANNEL_INTERNAL *rs_chan; /* Channel info */
struct ieee80211_channel *rs_chan; /* Channel info */
u_int8_t rs_chan_index; /* Channel index in radar structure */
u_int32_t rs_num_radar_events; /* Number of radar events */
int32_t rs_firpwr; /* Thresh to check radar sig is gone */
@ -380,9 +400,15 @@ struct ar9300_paprd_pwr_adjust {
u_int32_t sub_db; // offset value unit of dB
};
struct ar9300NfLimits {
int16_t max;
int16_t min;
int16_t nominal;
};
#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/
struct ath_hal_9300 {
struct ath_hal_private_tables ah_priv; /* base class */
struct ath_hal_private ah_priv; /* base class */
/*
* Information retrieved from EEPROM.
@ -582,6 +608,13 @@ struct ath_hal_9300 {
/* bb hang detection */
int ah_hang[6];
hal_hw_hangs_t ah_hang_wars;
/*
* Keytable type table
*/
#define AR_KEYTABLE_SIZE 128 /* XXX! */
uint8_t ah_keytype[AR_KEYTABLE_SIZE];
#undef AR_KEYTABLE_SIZE
/*
* Support for ar9300 multiple INIs
*/
@ -647,7 +680,6 @@ struct ath_hal_9300 {
/* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */
int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
/* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/
int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
@ -819,7 +851,33 @@ struct ath_hal_9300 {
u_int32_t ah_mcast_filter_l32_set;
u_int32_t ah_mcast_filter_u32_set;
#endif
HAL_BOOL ah_reduced_self_gen_mask;
HAL_BOOL ah_reduced_self_gen_mask;
/* Local additions for FreeBSD */
/*
* These fields are in the top level HAL in the atheros
* codebase; here we place them in the AR9300 HAL and
* access them via accessor methods if the driver requires them.
*/
u_int32_t ah_ob_db1[3];
u_int32_t ah_db2[3];
u_int32_t ah_bb_panic_timeout_ms;
u_int32_t ah_bb_panic_last_status;
u_int32_t ah_tx_trig_level;
u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2];
int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */
int ah_phyrestart_disabled;
HAL_RSSI_TX_POWER green_tx_status;
int green_ap_ps_on;
int ah_enable_keysearch_always;
int ah_fccaifs;
int ah_reset_reason;
int ah_dcs_enable;
struct ar9300NfLimits nf_2GHz;
struct ar9300NfLimits nf_5GHz;
struct ar9300NfLimits *nfp;
};
#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah))
@ -830,11 +888,7 @@ struct ath_hal_9300 {
#define ar9300_eep_data_in_flash(_ah) \
(!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM))
#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
(IS_CHAN_5GHZ(_c) && \
((AH_PRIVATE(_ah))->ah_config.ath_hal_fastClockEnable))
#if notyet
#ifdef notyet
// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents.
&& \
((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \
@ -880,9 +934,6 @@ struct ath_hal_9300 {
" not supported but called from %s\n", (func))
#endif /* AH_ASSERT */
extern void ar9300_detach(struct ath_hal *ah);
extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info);
/*
* Green Tx, Based on different RSSI of Received Beacon thresholds,
* using different tx power by modified register tx power related values.
@ -1129,15 +1180,10 @@ extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *);
struct ath_hal;
extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid,
HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype,
asf_amem_instance_handle amem_handle,
struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status);
HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status);
extern struct ath_hal * ar9300_attach(u_int16_t devid,
HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype,
asf_amem_instance_handle amem_handle,
struct hal_reg_parm *hal_conf_parm,
HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status);
extern void ar9300_detach(struct ath_hal *ah);
extern void ar9300_read_revisions(struct ath_hal *ah);
@ -1162,6 +1208,9 @@ extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah,
extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *);
extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry);
extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry);
extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah,
const struct ieee80211_channel *chan);
extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *,
u_int16_t entry, const u_int8_t *mac);
extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
@ -1173,13 +1222,12 @@ extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *);
extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac);
extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *);
extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg);
extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah,
u_int16_t reg_domain, HAL_STATUS *stats);
extern u_int ar9300_get_wireless_modes(struct ath_hal *ah);
extern void ar9300_enable_rf_kill(struct ath_hal *);
extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType);
extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType);
extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio);
extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val);
extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio);
@ -1200,7 +1248,6 @@ extern int ar9300_ppm_get_trigger(struct ath_hal *);
extern u_int32_t ar9300_ppm_force(struct ath_hal *);
extern void ar9300_ppm_un_force(struct ath_hal *);
extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *);
extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *);
extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t);
extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah);
extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah);
@ -1219,7 +1266,8 @@ extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah);
extern u_int ar9300_get_def_antenna(struct ath_hal *ah);
extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna);
extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah,
HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *, u_int8_t *, u_int8_t *);
HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
u_int8_t *, u_int8_t *, u_int8_t *);
extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah);
extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int);
extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int);
@ -1235,7 +1283,7 @@ extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request,
const void *args, u_int32_t argsize,
void **result, u_int32_t *resultsize);
extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info);
extern int8_t ar9300_get_11n_ext_busy(struct ath_hal *ah);
extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah);
extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode);
extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah);
extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear);
@ -1256,7 +1304,7 @@ extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_patter
u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len);
//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes);
extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable);
extern HAL_BOOL ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid,
extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid,
HAL_BOOL offloadEnable);
#if ATH_WOW_OFFLOAD
/* ARP offload */
@ -1318,24 +1366,25 @@ extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id
#endif /* ATH_WOW_OFFLOAD */
#endif
extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode,
HAL_CHANNEL *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask,
extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask,
u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing,
HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan);
extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan,
extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan,
HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask);
extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type);
extern void ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan);
extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan);
extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask);
extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah);
extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode);
extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah);
extern HAL_BOOL ar9300_disable(struct ath_hal *ah);
extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *);
extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan,
extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *);
extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals);
extern void ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan,
HAL_BOOL *isIQdone, u_int32_t cal_type);
extern void ar9300_reset_cal_valid(struct ath_hal *ah,
const struct ieee80211_channel *chan,
HAL_BOOL *isIQdone, u_int32_t cal_type);
extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains);
extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains);
extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah);
@ -1346,7 +1395,7 @@ extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfar
extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
u_int16_t extra_txpow, u_int16_t tpc_in_db);
extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf,
HAL_CHANNEL *chan, int is_scan);
struct ieee80211_channel *chan, int is_scan);
extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]);
extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah);
@ -1354,11 +1403,14 @@ extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode)
extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode,
u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode);
extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode,
HAL_CHANNEL_INTERNAL *chan,
const struct ieee80211_channel *chan,
u_int8_t powerPerRate[],
u_int8_t chainmask);
extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah,
u_int8_t powerPerRate[]);
extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah,
u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power);
extern void ar9300_reset_tx_status_ring(struct ath_hal *ah);
extern void ar9300_enable_mib_counters(struct ath_hal *);
extern void ar9300_disable_mib_counters(struct ath_hal *);
@ -1371,7 +1423,7 @@ struct ath_rx_status;
extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *);
extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *,
HAL_CHANNEL *, HAL_ANISTATS *);
const struct ieee80211_channel *, HAL_ANISTATS *);
extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning);
extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode);
extern void ar9300_enable_tpc(struct ath_hal *);
@ -1381,9 +1433,8 @@ extern void ar9300_rx_gain_table_apply(struct ath_hal *ah);
extern void ar9300_tx_gain_table_apply(struct ath_hal *ah);
extern void ar9300_mat_enable(struct ath_hal *ah, int enable);
extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry);
extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, HAL_CHANNEL * chan);
extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan);
#ifdef AH_SUPPORT_AR9300
/* BB Panic Watchdog declarations */
#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */
#define HAL_BB_PANIC_WD_TMO_HORNET 85
@ -1391,17 +1442,15 @@ extern void ar9300_config_bb_panic_watchdog(struct ath_hal *);
extern void ar9300_handle_bb_panic(struct ath_hal *);
extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic);
extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah);
#endif
extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason);
/* DFS declarations */
#ifdef ATH_SUPPORT_DFS
extern void ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan);
extern void ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan,
extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan);
extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan,
u_int64_t nolTime);
extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan);
extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan);
extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah,
u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses,
int *numb5radars, HAL_PHYERR_PARAM *pe);
@ -1409,9 +1458,8 @@ extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val);
extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable);
extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable);
extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start);
#endif
extern HAL_CHANNEL * ar9300_get_extension_channel(struct ath_hal *ah);
extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah);
extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah);
@ -1440,16 +1488,16 @@ extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, i
extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain);
extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode,
HAL_CHANNEL *chan, HAL_BOOL b_channel_change, HAL_STATUS *status);
struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status);
extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now);
extern void ar9300_get_channel_centers(struct ath_hal *ah,
HAL_CHANNEL_INTERNAL *chan,
const struct ieee80211_channel *chan,
CHAN_CENTERS *centers);
extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah,
HAL_CHANNEL_INTERNAL *chan);
const struct ieee80211_channel *chan);
extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah,
HAL_CHANNEL_INTERNAL *chan);
const struct ieee80211_channel *chan);
extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*);
extern void ar9300_dma_reg_dump(struct ath_hal *);
@ -1485,20 +1533,20 @@ extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi);
extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah);
extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah);
extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value);
extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah);
extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah);
extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah);
extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
u_int32_t rssi_threshold);
extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah);
extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on);
extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah);
extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats,
u_int8_t);
extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq);
extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq);
extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah);
extern void ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_COUNTERS*);
extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *);
extern void ar9300_clear_mib_counters(struct ath_hal *ah);
/* EEPROM interface functions */
@ -1512,12 +1560,12 @@ extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah,
u_int32_t val);
extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan,
ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan,
u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction,
u_int16_t twice_max_regulatory_power, u_int16_t power_limit);
extern void ar9300_eeprom_set_addac(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *);
extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value);
extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *);
extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data);
extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi);
@ -1526,7 +1574,7 @@ extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data)
extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data);
extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e);
extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band);
extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan,
extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan,
u_int8_t index, u_int16_t *config);
extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp);
extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz);
@ -1625,7 +1673,7 @@ extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah);
#ifdef ATH_TX99_DIAG
#ifndef ATH_SUPPORT_HTC
extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower);
extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower);
extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask);
extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype);
extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data);

67
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c
View file

@ -16,12 +16,10 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
#include "ah_desc.h"
#include "ah_pktlog.h"
//#include "ah_pktlog.h"
#include "ar9300/ar9300.h"
#include "ar9300/ar9300reg.h"
@ -30,7 +28,7 @@
extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits);
extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
#define HAL_ANI_DEBUG 0
#define HAL_ANI_DEBUG 1
/*
* Anti noise immunity support. We track phy errors and react
@ -47,7 +45,7 @@ extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
#define HAL_ANI_OFDM_TRIG_LOW 400 /* units are errors per second */
#define HAL_ANI_CCK_TRIG_HIGH 600 /* units are errors per second */
#define HAL_ANI_CCK_TRIG_LOW 300 /* units are errors per second */
#define HAL_ANI_USE_OFDM_WEAK_SIG true
#define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE
#define HAL_ANI_ENABLE_MRC_CCK AH_TRUE /* default is enabled */
#define HAL_ANI_DEF_SPUR_IMMUNE_LVL 3
#define HAL_ANI_DEF_FIRSTEP_LVL 2
@ -177,18 +175,20 @@ ar9300_disable_mib_counters(struct ath_hal *ah)
* ah_ani values and only the channel field needs to be set.
*/
static int
ar9300_get_ani_channel_index(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_get_ani_channel_index(struct ath_hal *ah,
const struct ieee80211_channel *chan)
{
struct ath_hal_9300 *ahp = AH9300(ah);
int i;
for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) {
if (ahp->ah_ani[i].c.channel == chan->channel) {
/* XXX this doesn't distinguish between 20/40 channels */
if (ahp->ah_ani[i].c.ic_freq == chan->ic_freq) {
return i;
}
if (ahp->ah_ani[i].c.channel == 0) {
ahp->ah_ani[i].c.channel = chan->channel;
ahp->ah_ani[i].c.channel_flags = chan->channel_flags;
if (ahp->ah_ani[i].c.ic_freq == 0) {
ahp->ah_ani[i].c.ic_freq = chan->ic_freq;
ahp->ah_ani[i].c.ic_flags = chan->ic_flags;
return i;
}
}
@ -268,7 +268,7 @@ ar9300_ani_attach(struct ath_hal *ah)
ar9300_enable_mib_counters(ah);
ahp->ah_ani_period = HAL_ANI_PERIOD;
if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_ani) {
if (ah->ah_config.ath_hal_enable_ani) {
ahp->ah_proc_phy_err |= HAL_PROCESS_ANI;
}
}
@ -295,7 +295,7 @@ ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int index;
u_int32_t val;
@ -307,7 +307,7 @@ ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode)
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ver %d.%d opmode %u chan %d Mhz/0x%x macmode %d\n",
__func__, AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev,
AH_PRIVATE(ah)->ah_opmode, chan->channel, chan->channel_flags, macmode);
AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, chan->ic_flags, macmode);
val = OS_REG_READ(ah, AR_PHY_SFCORR);
ani_state->ini_def.m1_thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@ -457,16 +457,16 @@ ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state = ahp->ah_curani;
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int32_t value, value2;
u_int level = param;
u_int is_on;
if (chan == NULL && cmd != HAL_ANI_MODE) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
if (chan == NULL && cmd != HAL_ANI_MODE) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: ignoring cmd 0x%02x - no channel\n", __func__, cmd);
return AH_FALSE;
}
return AH_FALSE;
}
switch (cmd & ahp->ah_ani_function) {
case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:
@ -538,7 +538,7 @@ ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (!is_on != ani_state->ofdm_weak_sig_detect_off) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: ofdm weak signal: %s=>%s\n",
__func__, chan->channel,
__func__, chan->ic_freq,
!ani_state->ofdm_weak_sig_detect_off ? "on" : "off",
is_on ? "on" : "off");
if (is_on) {
@ -592,12 +592,12 @@ ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (level != ani_state->firstep_level) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
__func__, chan->channel, ani_state->firstep_level, level,
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value, ani_state->ini_def.firstep);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"firstep_low[level]=%d ini=%d\n",
__func__, chan->channel, ani_state->firstep_level, level,
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value2,
ani_state->ini_def.firstep_low);
if (level > ani_state->firstep_level) {
@ -651,13 +651,13 @@ ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1[level]=%d ini=%d\n",
__func__, chan->channel, ani_state->spur_immunity_level, level,
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value,
ani_state->ini_def.cycpwr_thr1);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1_ext[level]=%d ini=%d\n",
__func__, chan->channel, ani_state->spur_immunity_level, level,
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value2,
ani_state->ini_def.cycpwr_thr1_ext);
if (level > ani_state->spur_immunity_level) {
@ -682,7 +682,7 @@ ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
}
if (!is_on != ani_state->mrc_cck_off) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->channel,
"%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->ic_freq,
!ani_state->mrc_cck_off ? "on" : "off", is_on ? "on" : "off");
if (is_on) {
ahp->ah_stats.ast_ani_ccklow++;
@ -857,7 +857,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int index;
HALASSERT(chan != AH_NULL);
@ -881,7 +882,7 @@ ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
/* only allow a subset of functions in AP mode */
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
if (IS_CHAN_2GHZ(chan)) {
if (IS_CHAN_2GHZ(ichan)) {
ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
HAL_ANI_FIRSTEP_LEVEL |
HAL_ANI_MRC_CCK);
@ -908,8 +909,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore defaults: opmode %u chan %d Mhz/0x%x "
"is_scanning=%d restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->channel,
chan->channel_flags, is_scanning, ani_state->must_restore,
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
/*
@ -941,8 +942,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d "
"restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->channel,
chan->channel_flags, is_scanning, ani_state->must_restore,
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
ar9300_ani_set_odfm_noise_immunity_level(
@ -1041,7 +1042,8 @@ ar9300_ani_lower_immunity(struct ath_hal *ah)
}
/* convert HW counter values to ms using mode specifix clock rate */
#define CLOCK_RATE(_ah) (ath_hal_chan_2_clock_rate_mhz(_ah) * 1000)
//#define CLOCK_RATE(_ah) (ath_hal_chan_2_clock_rate_mhz(_ah) * 1000)
#define CLOCK_RATE(_ah) (ath_hal_mac_clks(ah, 1000))
/*
* Return an approximation of the time spent ``listening'' by
@ -1098,7 +1100,7 @@ ar9300_ani_get_listen_time(struct ath_hal *ah, HAL_ANISTATS *ani_stats)
*/
void
ar9300_ani_ar_poll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
HAL_CHANNEL *chan, HAL_ANISTATS *ani_stats)
const struct ieee80211_channel *chan, HAL_ANISTATS *ani_stats)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
@ -1274,4 +1276,3 @@ ar9300_is_ani_noise_spur(struct ath_hal *ah)
return ani_state->phy_noise_spur;
}
#endif /* AH_SUPPORT_AR9300 */

655
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c
View file

File diff suppressed because it is too large Load diff

11
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_beacon.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -25,6 +23,7 @@
#include "ar9300/ar9300reg.h"
#define TU_TO_USEC(_tu) ((_tu) << 10)
#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
@ -37,7 +36,6 @@ void
ar9300_beacon_init(struct ath_hal *ah,
u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode)
{
struct ath_hal_private *ap = AH_PRIVATE(ah);
u_int32_t beacon_period_usec;
HALASSERT(opmode == HAL_M_IBSS || opmode == HAL_M_HOSTAP);
@ -47,10 +45,10 @@ ar9300_beacon_init(struct ath_hal *ah,
OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, ONE_EIGHTH_TU_TO_USEC(next_beacon));
OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
(ONE_EIGHTH_TU_TO_USEC(next_beacon) -
ap->ah_config.ath_hal_dma_beacon_response_time));
ah->ah_config.ah_dma_beacon_response_time));
OS_REG_WRITE(ah, AR_NEXT_SWBA,
(ONE_EIGHTH_TU_TO_USEC(next_beacon) -
ap->ah_config.ath_hal_sw_beacon_response_time));
ah->ah_config.ah_sw_beacon_response_time));
beacon_period_usec =
ONE_EIGHTH_TU_TO_USEC(beacon_period & HAL_BEACON_PERIOD_TU8);
@ -164,7 +162,7 @@ ar9300_set_sta_beacon_timers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
| AR_SLEEP1_ASSUME_DTIM);
/* beacon timeout is now in 1/8 TU */
if (p_cap->hal_auto_sleep_support) {
if (p_cap->halAutoSleepSupport) {
beacontimeout = (BEACON_TIMEOUT_VAL << 3);
} else {
/*
@ -195,4 +193,3 @@ ar9300_set_sta_beacon_timers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
#undef BEACON_TIMEOUT_VAL
#undef SLEEP_SLOP
}
#endif /* AH_SUPPORT_AR9300 */

77
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_devid.h Normal file
View file

@ -0,0 +1,77 @@
/*
* Copyright (c) 2012, Qualcomm Atheros, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
* provided that the following conditions are met:
* 1. The materials contained herein are unmodified and are used
* unmodified.
* 2. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following NO
* ''WARRANTY'' disclaimer below (''Disclaimer''), without
* modification.
* 3. Redistributions in binary form must reproduce at minimum a
* disclaimer similar to the Disclaimer below and any redistribution
* must be conditioned upon including a substantially similar
* Disclaimer requirement for further binary redistribution.
* 4. Neither the names of the above-listed copyright holders nor the
* names of any contributors may be used to endorse or promote
* product derived from this software without specific prior written
* permission.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
* $FreeBSD$
*
*/
#ifndef __AR9300_DEVID_H__
#define __AR9300_DEVID_H__
/*
* AR9380 HAL device IDs.
*/
/*
* MAC Version and Revision
*/
#define AR_SREV_VERSION_AR9380 0x1C0
#define AR_SREV_VERSION_AR9580 0x1C0
#define AR_SREV_VERSION_AR9460 0x280
#define AR_SREV_VERSION_AR9330 0x200
#define AR_SREV_VERSION_AR9340 0x300
#define AR_SREV_VERSION_QCA9550 0x400
#define AR_SREV_VERSION_AR9485 0x240
#define AR_SREV_REVISION_AR9380_10 0 /* AR9380 1.0 */
#define AR_SREV_REVISION_AR9380_20 2 /* AR9380 2.0/2.1 */
#define AR_SREV_REVISION_AR9380_22 3 /* AR9380 2.2 */
#define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */
#define AR_SREV_REVISION_AR9330_10 0 /* AR9330 1.0 */
#define AR_SREV_REVISION_AR9330_11 1 /* AR9330 1.1 */
#define AR_SREV_REVISION_AR9330_12 2 /* AR9330 1.2 */
#define AR_SREV_REVISION_AR9330_11_MASK 0xf /* AR9330 1.1 revision mask */
#define AR_SREV_REVISION_AR9485_10 0 /* AR9485 1.0 */
#define AR_SREV_REVISION_AR9485_11 1 /* AR9485 1.1 */
#define AR_SREV_REVISION_AR9340_10 0 /* AR9340 1.0 */
#define AR_SREV_REVISION_AR9340_11 1 /* AR9340 1.1 */
#define AR_SREV_REVISION_AR9340_12 2 /* AR9340 1.2 */
#define AR_SREV_REVISION_AR9340_MASK 0xf /* AR9340 revision mask */
#define AR_SREV_REVISION_AR9460_10 0 /* AR946x 1.0 */
#endif /* __AR9300_DEVID_H__ */

174
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
@ -47,7 +45,7 @@ void ar9300_eeprom_template_swap(void);
#endif
static u_int16_t ar9300_eeprom_get_spur_chan(struct ath_hal *ah,
u_int16_t spur_chan, HAL_BOOL is_2ghz);
int spur_chan, HAL_BOOL is_2ghz);
#ifdef UNUSED
static inline HAL_BOOL ar9300_fill_eeprom(struct ath_hal *ah);
static inline HAL_STATUS ar9300_check_eeprom(struct ath_hal *ah);
@ -233,7 +231,7 @@ ar9300_eeprom_read_word(struct ath_hal *ah, u_int off, u_int16_t *data)
if (!ath_hal_wait(ah,
AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA),
AR_EEPROM_STATUS_DATA_BUSY | AR_EEPROM_STATUS_DATA_PROT_ACCESS,
0, AH_WAIT_TIMEOUT))
0))
{
return AH_FALSE;
}
@ -295,6 +293,9 @@ ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi
static HAL_STATUS
ar9300_flash_map(struct ath_hal *ah)
{
/* XXX disable flash remapping for now (ie, SoC support) */
ath_hal_printf(ah, "%s: unimplemented for now\n", __func__);
#if 0
struct ath_hal_9300 *ahp = AH9300(ah);
#if defined(AR9100) || defined(__NetBSD__)
ahp->ah_cal_mem = OS_REMAP(ah, AR9300_EEPROM_START_ADDR, AR9300_EEPROM_MAX);
@ -307,6 +308,7 @@ ar9300_flash_map(struct ath_hal *ah)
"%s: cannot remap eeprom region \n", __func__);
return HAL_EIO;
}
#endif
return HAL_OK;
}
@ -328,9 +330,6 @@ ar9300_flash_write(struct ath_hal *ah, u_int off, u_int16_t data)
return AH_TRUE;
}
#ifdef UNUSED
#endif
HAL_STATUS
ar9300_eeprom_attach(struct ath_hal *ah)
{
@ -358,7 +357,7 @@ ar9300_eeprom_attach(struct ath_hal *ah)
* This is not AH_TRUE for many board designs.
* Does anyone use this?
*/
AH_PRIVATE(ah)->ah_eeprom_get_spur_chan = ar9300_eeprom_get_spur_chan;
AH_PRIVATE(ah)->ah_getSpurChan = ar9300_eeprom_get_spur_chan;
#ifdef OLDCODE
/* XXX Needs to be moved for dynamic selection */
@ -458,7 +457,7 @@ ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param)
OSPREY_BASE_EXTENSION_1 *base_ext1 = &eep->base_ext1;
switch (param) {
#if NOTYET
#ifdef NOTYET
case EEP_NFTHRESH_5:
return p_modal[0].noise_floor_thresh_ch[0];
case EEP_NFTHRESH_2:
@ -480,7 +479,7 @@ ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param)
return p_base->op_cap_flags.op_flags;
case EEP_RF_SILENT:
return p_base->rf_silent;
#if NOTYET
#ifdef NOTYET
case EEP_OB_5:
return p_modal[0].ob;
case EEP_DB_5:
@ -496,7 +495,7 @@ ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param)
return (p_base->txrx_mask >> 4) & 0xf;
case EEP_RX_MASK:
return p_base->txrx_mask & 0xf;
#if NOTYET
#ifdef NOTYET
case EEP_FSTCLK_5G:
return p_base->fast_clk5g;
case EEP_RXGAIN_TYPE:
@ -929,7 +928,7 @@ ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array)
}
static void
ar9300_selfgen_tpc_reg_write(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
ar9300_selfgen_tpc_reg_write(struct ath_hal *ah, const struct ieee80211_channel *chan,
u_int8_t *p_pwr_array)
{
u_int32_t tpc_reg_val;
@ -940,7 +939,7 @@ ar9300_selfgen_tpc_reg_write(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
* MIN( TPC reg, BB_powertx_rate register)
*/
if (IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
tpc_reg_val = (SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) |
SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) |
SM(0x3f, AR_TPC_CHIRP) |
@ -1544,12 +1543,12 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
u_int8_t i;
if (AR_SREV_POSEIDON(ah)) {
xlan_gpio_cfg = ahpriv->ah_config.ath_hal_ext_lna_ctl_gpio;
xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio;
if (xlan_gpio_cfg) {
for (i = 0; i < 32; i++) {
if (xlan_gpio_cfg & (1 << i)) {
ath_hal_gpio_cfg_output(ah, i,
HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED);
ath_hal_gpioCfgOutput(ah, i,
HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED);
}
}
}
@ -1606,7 +1605,7 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
#if ATH_ANT_DIV_COMB
if ( AR_SREV_POSEIDON(ah) && (ahp->ah_lna_div_use_bt_ant_enable == TRUE) ) {
value &= ~AR_SWITCH_TABLE_COM2_ALL;
value |= ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable;
value |= ah->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable;
}
#endif /* ATH_ANT_DIV_COMB */
OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
@ -1658,7 +1657,7 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
#if ATH_ANT_DIV_COMB
if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) {
if (pcap->hal_ant_div_comb_support) {
if (pcap->halAntDivCombSupport) {
/* If support DivComb, set MAIN to LNA1, ALT to LNA2 at beginning */
regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
/* clear bit 25~30 main_lnaconf, alt_lnaconf, main_tb, alt_tb */
@ -1713,7 +1712,7 @@ HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
* This will not affect HB125 LNA diversity feature.
*/
OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL,
ahpriv->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable);
ah->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable);
break;
default:
break;
@ -1780,7 +1779,7 @@ ar9300_attenuation_margin_chain_get(struct ath_hal *ah, int chain,
HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel)
{
u_int32_t value;
struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
/* Test value. if 0 then attenuation is unused. Don't load anything. */
value = ar9300_attenuation_chain_get(ah, 0, channel);
@ -1788,7 +1787,7 @@ HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel)
AR_PHY_EXT_ATTEN_CTL_0, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
value = ar9300_attenuation_margin_chain_get(ah, 0, channel);
if (ar9300_rx_gain_index_get(ah) == 0
&& ahpriv->ah_config.ath_hal_ext_atten_margin_cfg)
&& ah->ah_config.ath_hal_ext_atten_margin_cfg)
{
value = 5;
}
@ -1934,6 +1933,8 @@ ar9300_eeprom_cal_pier_get(struct ath_hal *ah, int mode, int ipier, int ichain,
static int
ar9300_calibration_apply(struct ath_hal *ah, int frequency)
{
struct ath_hal_9300 *ahp = AH9300(ah);
int ichain, ipier, npier;
int mode;
int fdiff;
@ -2066,11 +2067,12 @@ ar9300_calibration_apply(struct ath_hal *ah, int frequency)
}
}
/* GreenTx isn't currently supported */
/* GreenTx */
if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) {
if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
if (AR_SREV_POSEIDON(ah)) {
/* Get calibrated OLPC gain delta value for GreenTx */
AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET] =
ahp->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET] =
(u_int32_t) correction[0];
}
}
@ -2294,7 +2296,7 @@ HAL_BOOL
ar9300_eeprom_set_power_per_rate_table(
struct ath_hal *ah,
ar9300_eeprom_t *p_eep_data,
HAL_CHANNEL_INTERNAL *chan,
const struct ieee80211_channel *chan,
u_int8_t *p_pwr_array,
u_int16_t cfg_ctl,
u_int16_t antenna_reduction,
@ -2333,12 +2335,15 @@ ar9300_eeprom_set_power_per_rate_table(
u_int8_t ctl_num;
u_int16_t twice_min_edge_power;
u_int16_t twice_max_edge_power = AR9300_MAX_RATE_POWER;
#ifdef AH_DEBUG
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
#endif
tx_chainmask = chainmask ? chainmask : ahp->ah_tx_chainmask;
ar9300_get_channel_centers(ah, chan, &centers);
if (IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ahp->twice_antenna_gain = p_eep_data->modal_header_2g.antenna_gain;
} else {
ahp->twice_antenna_gain = p_eep_data->modal_header_5g.antenna_gain;
@ -2353,9 +2358,9 @@ ar9300_eeprom_set_power_per_rate_table(
max_reg_allowed_power = twice_max_regulatory_power + twice_largest_antenna;
/* Use ah_tp_scale - see bug 30070. */
if (AH_PRIVATE(ah)->ah_tp_scale != HAL_TP_SCALE_MAX) {
if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
max_reg_allowed_power -=
(tp_scale_reduction_table[(AH_PRIVATE(ah)->ah_tp_scale)] * 2);
(tp_scale_reduction_table[(AH_PRIVATE(ah)->ah_tpScale)] * 2);
}
scaled_power = AH_MIN(power_limit, max_reg_allowed_power);
@ -2384,14 +2389,14 @@ ar9300_eeprom_set_power_per_rate_table(
scaled_power = AH_MAX(0, scaled_power);
/* Get target powers from EEPROM - our baseline for TX Power */
if (IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
/* Setup for CTL modes */
/* CTL_11B, CTL_11G, CTL_2GHT20 */
num_ctl_modes =
ARRAY_LENGTH(ctl_modes_for11g) - SUB_NUM_CTL_MODES_AT_2G_40;
p_ctl_mode = ctl_modes_for11g;
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
num_ctl_modes = ARRAY_LENGTH(ctl_modes_for11g); /* All 2G CTL's */
}
} else {
@ -2401,7 +2406,7 @@ ar9300_eeprom_set_power_per_rate_table(
ARRAY_LENGTH(ctl_modes_for11a) - SUB_NUM_CTL_MODES_AT_5G_40;
p_ctl_mode = ctl_modes_for11a;
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
num_ctl_modes = ARRAY_LENGTH(ctl_modes_for11a); /* All 5G CTL's */
}
}
@ -2433,7 +2438,7 @@ ar9300_eeprom_set_power_per_rate_table(
ctl_mode, num_ctl_modes, is_ht40_ctl_mode,
(p_ctl_mode[ctl_mode] & EXT_ADDITIVE));
/* walk through each CTL index stored in EEPROM */
if (IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ctl_index = p_eep_data->ctl_index_2g;
ctl_num = OSPREY_NUM_CTLS_2G;
} else {
@ -2446,7 +2451,8 @@ ar9300_eeprom_set_power_per_rate_table(
" LOOP-Ctlidx %d: cfg_ctl 0x%2.2x p_ctl_mode 0x%2.2x "
"ctl_index 0x%2.2x chan %d chanctl 0x%x\n",
i, cfg_ctl, p_ctl_mode[ctl_mode], ctl_index[i],
chan->channel, chan->conformance_test_limit);
ichan->channel, ath_hal_getctl(ah, chan));
/*
* compare test group from regulatory channel list
@ -2460,12 +2466,12 @@ ar9300_eeprom_set_power_per_rate_table(
{
twice_min_edge_power =
ar9300_eep_def_get_max_edge_power(
p_eep_data, freq, i, IS_CHAN_2GHZ(chan));
p_eep_data, freq, i, IEEE80211_IS_CHAN_2GHZ(chan));
HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
" MATCH-EE_IDX %d: ch %d is2 %d "
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
i, freq, IEEE80211_IS_CHAN_2GHZ(chan),
twice_min_edge_power, tx_chainmask,
ar9300_get_ntxchains(tx_chainmask));
@ -2646,7 +2652,7 @@ ar9300_eeprom_set_power_per_rate_table(
*/
HAL_STATUS
ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan, u_int16_t cfg_ctl,
ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, u_int16_t cfg_ctl,
u_int16_t antenna_reduction, u_int16_t twice_max_regulatory_power,
u_int16_t power_limit)
{
@ -2660,6 +2666,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
int i = 0;
u_int32_t tmp_paprd_rate_mask = 0, *tmp_ptr = NULL;
int paprd_scale_factor = 5;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
u_int8_t *ptr_mcs_rate2power_table_index;
u_int8_t mcs_rate2power_table_index_ht20[24] =
@ -2722,13 +2729,13 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
"%s[%d] +++chan %d,cfgctl 0x%04x "
"antenna_reduction 0x%04x, twice_max_regulatory_power 0x%04x "
"power_limit 0x%04x\n",
__func__, __LINE__, chan->channel, cfg_ctl,
__func__, __LINE__, ichan->channel, cfg_ctl,
antenna_reduction, twice_max_regulatory_power, power_limit);
ar9300_set_target_power_from_eeprom(ah, chan->channel, target_power_val_t2);
ar9300_set_target_power_from_eeprom(ah, ichan->channel, target_power_val_t2);
if (ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED)) {
if (IS_CHAN_2GHZ(chan)) {
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
tmp_paprd_rate_mask =
p_eep_data->modal_header_2g.paprd_rate_mask_ht40;
tmp_ptr = &AH9300(ah)->ah_2g_paprd_rate_mask_ht40;
@ -2738,7 +2745,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
tmp_ptr = &AH9300(ah)->ah_2g_paprd_rate_mask_ht20;
}
} else {
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
tmp_paprd_rate_mask =
p_eep_data->modal_header_5g.paprd_rate_mask_ht40;
tmp_ptr = &AH9300(ah)->ah_5g_paprd_rate_mask_ht40;
@ -2749,18 +2756,18 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
}
}
AH_PAPRD_GET_SCALE_FACTOR(
paprd_scale_factor, p_eep_data, IS_CHAN_2GHZ(chan), chan->channel);
paprd_scale_factor, p_eep_data, IEEE80211_IS_CHAN_2GHZ(chan), ichan->channel);
HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] paprd_scale_factor %d\n",
__func__, __LINE__, paprd_scale_factor);
/* PAPRD is not done yet, Scale down the EEP power */
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
ptr_mcs_rate2power_table_index =
&mcs_rate2power_table_index_ht40[0];
} else {
ptr_mcs_rate2power_table_index =
&mcs_rate2power_table_index_ht20[0];
}
if (!chan->paprd_table_write_done) {
if (! ichan->paprd_table_write_done) {
for (i = 0; i < 24; i++) {
/* PAPRD is done yet, so Scale down Power for PAPRD Rates*/
if (tmp_paprd_rate_mask & (1 << i)) {
@ -2770,7 +2777,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
"%s[%d]: Chan %d "
"Scale down target_power_val_t2[%d] = 0x%04x\n",
__func__, __LINE__,
chan->channel, i, target_power_val_t2[i]);
ichan->channel, i, target_power_val_t2[i]);
}
}
} else {
@ -2789,7 +2796,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
power_limit, 0);
/* Save this for quick lookup */
ahp->reg_dmn = chan->conformance_test_limit;
ahp->reg_dmn = ath_hal_getctl(ah, chan);
/*
* Always use CDD/direct per rate power table for register based approach.
@ -2797,6 +2804,9 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
* this adjust call. ETSI and MKK does not have this requirement.
*/
if (is_reg_dmn_fcc(ahp->reg_dmn)) {
HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
"%s: FCC regdomain, calling reg_txpower_cdd\n",
__func__);
ar9300_adjust_reg_txpower_cdd(ah, target_power_val_t2);
}
@ -2825,7 +2835,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
}
HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
"%s: Chan %d After tmp_paprd_rate_mask = 0x%08x\n",
__func__, chan->channel, tmp_paprd_rate_mask);
__func__, ichan->channel, tmp_paprd_rate_mask);
if (tmp_ptr) {
*tmp_ptr = tmp_paprd_rate_mask;
}
@ -2838,8 +2848,8 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
ar9300_selfgen_tpc_reg_write(ah, chan, target_power_val_t2);
/* GreenTx or Paprd */
if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable ||
AH_PRIVATE(ah)->ah_caps.hal_paprd_enabled)
if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable ||
AH_PRIVATE(ah)->ah_caps.halPaprdEnabled)
{
if (AR_SREV_POSEIDON(ah)) {
/*For HAL_RSSI_TX_POWER_NONE array*/
@ -2848,13 +2858,13 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
sizeof(target_power_val_t2));
/* Get defautl tx related register setting for GreenTx */
/* Record OB/DB */
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB] =
ahp->ah_ob_db1[POSEIDON_STORED_REG_OBDB] =
OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2);
/* Record TPC settting */
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC] =
ahp->ah_ob_db1[POSEIDON_STORED_REG_TPC] =
OS_REG_READ(ah, AR_TPC);
/* Record BB_powertx_rate9 setting */
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9] =
ahp->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9] =
OS_REG_READ(ah, AR_PHY_BB_POWERTX_RATE9);
}
}
@ -2868,9 +2878,9 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
* as CCK power is less interesting (?).
*/
i = ALL_TARGET_LEGACY_6_24; /* legacy */
if (IS_CHAN_HT40(chan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
i = ALL_TARGET_HT40_0_8_16; /* ht40 */
} else if (IS_CHAN_HT20(chan)) {
} else if (IEEE80211_IS_CHAN_HT20(chan)) {
i = ALL_TARGET_HT20_0_8_16; /* ht20 */
}
max_power_level = target_power_val_t2[i];
@ -2901,13 +2911,13 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
default:
HALASSERT(0); /* Unsupported number of chains */
}
AH_PRIVATE(ah)->ah_max_power_level = (int8_t)max_power_level;
AH_PRIVATE(ah)->ah_maxPowerLevel = (int8_t)max_power_level;
ar9300_calibration_apply(ah, chan->channel);
ar9300_calibration_apply(ah, ichan->channel);
#undef ABS
/* Handle per packet TPC initializations */
if (AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) {
if (ah->ah_config.ath_hal_desc_tpc) {
/* Transmit Power per-rate per-chain are computed here. A separate
* power table is maintained for different MIMO modes (i.e. TXBF ON,
* STBC) to enable easy lookup during packet transmit.
@ -2930,7 +2940,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
power_limit, chainmasks[i]);
HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
" Channel = %d Chainmask = %d, Upper Limit = [%2d.%1d dBm]\n",
chan->channel, i, ahp->upper_limit[i]/2,
ichan->channel, i, ahp->upper_limit[i]/2,
ahp->upper_limit[i]%2 * 5);
ar9300_init_rate_txpower(ah, mode, chan, target_power_val_t2,
chainmasks[i]);
@ -2962,7 +2972,7 @@ ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
* Set the ADDAC from eeprom.
*/
void
ar9300_eeprom_set_addac(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_eeprom_set_addac(struct ath_hal *ah, struct ieee80211_channel *chan)
{
HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
@ -2988,7 +2998,7 @@ ar9300_eeprom_set_addac(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
return;
}
p_modal = &(eep->modal_header[IS_CHAN_2GHZ(chan)]);
p_modal = &(eep->modal_header[IEEE80211_IS_CHAN_2GHZ(chan)]);
if (p_modal->xpa_bias_lvl != 0xff) {
biaslevel = p_modal->xpa_bias_lvl;
@ -2999,7 +3009,7 @@ ar9300_eeprom_set_addac(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_get_channel_centers(ah, chan, &centers);
reset_freq_bin = FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
reset_freq_bin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan));
freq_bin = p_modal->xpa_bias_lvl_freq[0] & 0xff;
biaslevel = (u_int8_t)(p_modal->xpa_bias_lvl_freq[0] >> 14);
@ -3022,7 +3032,7 @@ ar9300_eeprom_set_addac(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
}
/* Apply bias level to the ADDAC values in the INI array */
if (IS_CHAN_2GHZ(chan)) {
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
INI_RA(&ahp->ah_ini_addac, 7, 1) =
(INI_RA(&ahp->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3;
} else {
@ -3065,12 +3075,13 @@ ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp,
}
HAL_STATUS
ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan,
u_int8_t index, u_int16_t *config)
ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp,
const struct ieee80211_channel *chan,
u_int8_t index, u_int16_t *config)
{
#if 0
ar9300_eeprom_t *eep = &ahp->ah_eeprom.def;
MODAL_EEPDEF_HEADER *p_modal = &(eep->modal_header[IS_CHAN_2GHZ(chan)]);
MODAL_EEPDEF_HEADER *p_modal = &(eep->modal_header[IEEE80211_IS_CHAN_2GHZ(chan)]);
BASE_EEPDEF_HEADER *p_base = &eep->base_eep_header;
switch (index) {
@ -3289,7 +3300,7 @@ ar9300_check_eeprom(struct ath_hal *ah)
#endif
static u_int16_t
ar9300_eeprom_get_spur_chan(struct ath_hal *ah, u_int16_t i, HAL_BOOL is_2ghz)
ar9300_eeprom_get_spur_chan(struct ath_hal *ah, int i, HAL_BOOL is_2ghz)
{
u_int16_t spur_val = AR_NO_SPUR;
#if 0
@ -3387,7 +3398,6 @@ ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address,
unsigned long eep_addr;
unsigned long byte_addr;
u_int16_t *svalue;
struct ath_hal_9300 *ahp = AH9300(ah);
if (((address) < 0) || ((address + many) > AR9300_EEPROM_SIZE)) {
return AH_FALSE;
@ -3397,7 +3407,7 @@ ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address,
eep_addr = (u_int16_t) (address + i) / 2;
byte_addr = (u_int16_t) (address + i) % 2;
svalue = (u_int16_t *) value;
if (!ahp->ah_priv.priv.ah_eeprom_read(ah, eep_addr, svalue)) {
if (! ath_hal_eepromRead(ah, eep_addr, svalue)) {
HALDEBUG(ah, HAL_DEBUG_EEPROM,
"%s: Unable to read eeprom region \n", __func__);
return AH_FALSE;
@ -3542,7 +3552,6 @@ ar9300_eeprom_size(struct ath_hal *ah)
* 1024 and 2048 are normal sizes.
* 0 means there is no eeprom.
*/
int32_t ar9300_otp_size(struct ath_hal *ah);
int32_t
ar9300_otp_size(struct ath_hal *ah)
{
@ -3822,7 +3831,6 @@ ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr,
char *cal_ptr;
#endif
HALASSERT(mdata_size > 0);
/* if cal_in_flash is AH_TRUE, the address sent by LMAC to HAL
@ -3831,16 +3839,20 @@ ar9300_eeprom_restore_from_dram(struct ath_hal *ah, ar9300_eeprom_t *mptr,
if(ar9300_eep_data_in_flash(ah))
return -1;
#if 0
/* check if LMAC sent DRAM address is valid */
if (!(uintptr_t)(AH_PRIVATE(ah)->ah_st)) {
return -1;
}
#endif
/* When calibration data is from host, Host will copy the
compressed data to the predefined DRAM location saved at ah->ah_st */
#if 0
ath_hal_printf(ah, "Restoring Cal data from DRAM\n");
ahp->ah_cal_mem = OS_REMAP((uintptr_t)(AH_PRIVATE(ah)->ah_st),
HOST_CALDATA_SIZE);
#endif
if (!ahp->ah_cal_mem)
{
HALDEBUG(ah, HAL_DEBUG_EEPROM,"%s: can't remap dram region\n", __func__);
@ -3928,6 +3940,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr,
AH9300(ah)->calibration_data_try == calibration_data_dram) &&
AH9300(ah)->try_dram && nptr < 0)
{
ath_hal_printf(ah, "Restoring Cal data from DRAM\n");
AH9300(ah)->calibration_data_source = calibration_data_dram;
AH9300(ah)->calibration_data_source_address = 0;
nptr = ar9300_eeprom_restore_from_dram(ah, mptr, mdata_size);
@ -3945,6 +3958,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr,
* need to look at highest eeprom address as well as at
* base_address=0x3ff where we used to write the data
*/
ath_hal_printf(ah, "Restoring Cal data from EEPROM\n");
AH9300(ah)->calibration_data_source = calibration_data_eeprom;
if (AH9300(ah)->calibration_data_try_address != 0) {
AH9300(ah)->calibration_data_source_address =
@ -3981,6 +3995,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr,
AH9300(ah)->calibration_data_try == calibration_data_flash) &&
AH9300(ah)->try_flash && nptr < 0)
{
ath_hal_printf(ah, "Restoring Cal data from Flash\n");
AH9300(ah)->calibration_data_source = calibration_data_flash;
/* how are we supposed to set this for flash? */
AH9300(ah)->calibration_data_source_address = 0;
@ -3995,6 +4010,7 @@ ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr,
AH9300(ah)->calibration_data_try == calibration_data_otp) &&
AH9300(ah)->try_otp && nptr < 0)
{
ath_hal_printf(ah, "Restoring Cal data from OTP\n");
AH9300(ah)->calibration_data_source = calibration_data_otp;
if (AH9300(ah)->calibration_data_try_address != 0) {
AH9300(ah)->calibration_data_source_address =
@ -4364,16 +4380,18 @@ HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz)
* given the channel value.
*/
HAL_BOOL
ar9300_eeprom_set_board_values(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_eeprom_set_board_values(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
ar9300_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
ar9300_xpa_timing_control_apply(ah, IS_CHAN_2GHZ(chan));
ar9300_xpa_bias_level_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
ar9300_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
ar9300_xpa_timing_control_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
ar9300_ant_ctrl_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
ar9300_drive_strength_apply(ah);
ar9300_x_lNA_bias_strength_apply(ah, IS_CHAN_2GHZ(chan));
ar9300_x_lNA_bias_strength_apply(ah, IEEE80211_IS_CHAN_2GHZ(chan));
/* wait for Poseidon internal regular turnning */
/* for Hornet we move it before initPLL to avoid an access issue */
@ -4382,15 +4400,15 @@ ar9300_eeprom_set_board_values(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_internal_regulator_apply(ah);
}
ar9300_attenuation_apply(ah, chan->channel);
ar9300_quick_drop_apply(ah, chan->channel);
ar9300_attenuation_apply(ah, ichan->channel);
ar9300_quick_drop_apply(ah, ichan->channel);
ar9300_thermometer_apply(ah);
if(!AR_SREV_WASP(ah))
{
ar9300_tuning_caps_apply(ah);
}
ar9300_tx_end_to_xpab_off_apply(ah, chan->channel);
ar9300_tx_end_to_xpab_off_apply(ah, ichan->channel);
return AH_TRUE;
}
@ -4518,5 +4536,3 @@ u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah,
}
return AH_TRUE;
}
#endif /* AH_SUPPORT_AR9300 */

637
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c Normal file
View file

@ -0,0 +1,637 @@
/*
* Copyright (c) 2012, 2013 Adrian Chadd <adrian@FreeBSD.org>.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
#include "ah_desc.h"
#include "ar9300.h"
#include "ar9300reg.h"
#include "ar9300phy.h"
#include "ar9300desc.h"
#include "ar9300_freebsd.h"
#include "ar9300_stub.h"
#include "ar9300_stub_funcs.h"
#define FIX_NOISE_FLOOR 1
#define NEXT_TBTT_NOW 5
static HAL_BOOL ar9300ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix);
static HAL_BOOL ar9300SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix);
static void
ar9300SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,
uint32_t rx_chainmask)
{
AH9300(ah)->ah_tx_chainmask =
tx_chainmask & AH_PRIVATE(ah)->ah_caps.halTxChainMask;
AH9300(ah)->ah_rx_chainmask =
rx_chainmask & AH_PRIVATE(ah)->ah_caps.halRxChainMask;
}
static u_int
ar9300GetSlotTime(struct ath_hal *ah)
{
u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
return (ath_hal_mac_usec(ah, clks)); /* convert from system clocks */
}
static HAL_BOOL
ar9300_freebsd_set_tx_power_limit(struct ath_hal *ah, uint32_t limit)
{
return (ar9300_set_tx_power_limit(ah, limit, 0, 0));
}
void
ar9300_attach_freebsd_ops(struct ath_hal *ah)
{
/* stub everything first */
ar9300_set_stub_functions(ah);
/* Global functions */
ah->ah_detach = ar9300_detach;
ah->ah_getRateTable = ar9300_get_rate_table;
/* Reset functions */
ah->ah_reset = ar9300_reset_freebsd;
ah->ah_phyDisable = ar9300_phy_disable;
ah->ah_disable = ar9300_disable;
ah->ah_configPCIE = ar9300_config_pcie_freebsd;
// ah->ah_disablePCIE = ar9300_disable_pcie_phy;
ah->ah_setPCUConfig = ar9300_set_pcu_config;
// perCalibration
ah->ah_perCalibrationN = ar9300_per_calibration_freebsd;
ah->ah_resetCalValid = ar9300_reset_cal_valid_freebsd;
ah->ah_setTxPowerLimit = ar9300_freebsd_set_tx_power_limit;
ah->ah_getChanNoise = ath_hal_getChanNoise;
/* Transmit functions */
ah->ah_setupTxQueue = ar9300_setup_tx_queue;
ah->ah_setTxQueueProps = ar9300_set_tx_queue_props;
ah->ah_getTxQueueProps = ar9300_get_tx_queue_props;
ah->ah_releaseTxQueue = ar9300_release_tx_queue;
ah->ah_resetTxQueue = ar9300_reset_tx_queue;
ah->ah_getTxDP = ar9300_get_tx_dp;
ah->ah_setTxDP = ar9300_set_tx_dp;
ah->ah_numTxPending = ar9300_num_tx_pending;
ah->ah_startTxDma = ar9300_start_tx_dma;
ah->ah_stopTxDma = ar9300_stop_tx_dma_freebsd;
ah->ah_setupTxDesc = ar9300_freebsd_setup_tx_desc;
ah->ah_setupXTxDesc = ar9300_freebsd_setup_x_tx_desc;
ah->ah_fillTxDesc = ar9300_freebsd_fill_tx_desc;
ah->ah_procTxDesc = ar9300_freebsd_proc_tx_desc;
ah->ah_getTxIntrQueue = ar9300_get_tx_intr_queue;
// reqTxIntrDesc
ah->ah_getTxCompletionRates = ar9300_freebsd_get_tx_completion_rates;
ah->ah_setTxDescLink = ar9300_set_desc_link;
ah->ah_getTxDescLink = ar9300_freebsd_get_desc_link;
ah->ah_getTxDescLinkPtr = ar9300_get_desc_link_ptr;
ah->ah_setupTxStatusRing = ar9300_setup_tx_status_ring;
ah->ah_getTxRawTxDesc = ar9300_get_raw_tx_desc;
ah->ah_updateTxTrigLevel = ar9300_update_tx_trig_level;
/* RX functions */
ah->ah_getRxDP = ar9300_get_rx_dp;
ah->ah_setRxDP = ar9300_set_rx_dp;
ah->ah_enableReceive = ar9300_enable_receive;
ah->ah_stopDmaReceive = ar9300_stop_dma_receive_freebsd;
ah->ah_startPcuReceive = ar9300_start_pcu_receive_freebsd;
ah->ah_stopPcuReceive = ar9300_stop_pcu_receive;
ah->ah_setMulticastFilter = ar9300_set_multicast_filter;
ah->ah_setMulticastFilterIndex = ar9300SetMulticastFilterIndex;
ah->ah_clrMulticastFilterIndex = ar9300ClrMulticastFilterIndex;
ah->ah_getRxFilter = ar9300_get_rx_filter;
ah->ah_setRxFilter = ar9300_set_rx_filter;
/* setupRxDesc */
ah->ah_procRxDesc = ar9300_proc_rx_desc_freebsd;
ah->ah_rxMonitor = ar9300_ani_rxmonitor_freebsd;
ah->ah_aniPoll = ar9300_ani_poll_freebsd;
ah->ah_procMibEvent = ar9300_process_mib_intr;
/* Misc functions */
ah->ah_getCapability = ar9300_get_capability;
ah->ah_setCapability = ar9300_set_capability;
ah->ah_getDiagState = ar9300_get_diag_state;
ah->ah_getMacAddress = ar9300_get_mac_address;
ah->ah_setMacAddress = ar9300_set_mac_address;
ah->ah_getBssIdMask = ar9300_get_bss_id_mask;
ah->ah_setBssIdMask = ar9300_set_bss_id_mask;
ah->ah_setRegulatoryDomain = ar9300_set_regulatory_domain;
ah->ah_setLedState = ar9300_set_led_state;
ah->ah_writeAssocid = ar9300_write_associd;
ah->ah_gpioCfgInput = ar9300_gpio_cfg_input;
ah->ah_gpioCfgOutput = ar9300_gpio_cfg_output;
ah->ah_gpioGet = ar9300_gpio_get;
ah->ah_gpioSet = ar9300_gpio_set;
ah->ah_gpioSetIntr = ar9300_gpio_set_intr;
/* polarity */
/* mask */
ah->ah_getTsf32 = ar9300_get_tsf32;
ah->ah_getTsf64 = ar9300_get_tsf64;
ah->ah_resetTsf = ar9300_reset_tsf;
ah->ah_detectCardPresent = ar9300_detect_card_present;
// ah->ah_updateMibCounters = ar9300_update_mib_counters;
ah->ah_getRfGain = ar9300_get_rfgain;
ah->ah_getDefAntenna = ar9300_get_def_antenna;
ah->ah_setDefAntenna = ar9300_set_def_antenna;
// ah->ah_getAntennaSwitch = ar9300_get_antenna_switch;
// ah->ah_setAntennaSwitch = ar9300_set_antenna_switch;
// ah->ah_setSifsTime = ar9300_set_sifs_time;
// ah->ah_getSifsTime = ar9300_get_sifs_time;
ah->ah_setSlotTime = ar9300_set_slot_time;
ah->ah_getSlotTime = ar9300GetSlotTime;
ah->ah_getAckTimeout = ar9300_get_ack_timeout;
ah->ah_setAckTimeout = ar9300_set_ack_timeout;
// XXX ack/ctsrate
// XXX CTS timeout
// XXX decompmask
// coverageclass
ah->ah_setQuiet = ar9300_set_quiet;
ah->ah_getMibCycleCounts = ar9300_freebsd_get_mib_cycle_counts;
/* DFS functions */
ah->ah_enableDfs = ar9300_enable_dfs;
ah->ah_getDfsThresh = ar9300_get_dfs_thresh;
ah->ah_getDfsDefaultThresh = ar9300_freebsd_get_dfs_default_thresh;
// procradarevent
ah->ah_isFastClockEnabled = ar9300_is_fast_clock_enabled;
ah->ah_get11nExtBusy = ar9300_get_11n_ext_busy;
/* Key cache functions */
ah->ah_getKeyCacheSize = ar9300_get_key_cache_size;
ah->ah_resetKeyCacheEntry = ar9300_reset_key_cache_entry;
ah->ah_isKeyCacheEntryValid = ar9300_is_key_cache_entry_valid;
ah->ah_setKeyCacheEntry = ar9300_set_key_cache_entry;
ah->ah_setKeyCacheEntryMac = ar9300_set_key_cache_entry_mac;
/* Power management functions */
ah->ah_setPowerMode = ar9300_set_power_mode;
ah->ah_getPowerMode = ar9300_get_power_mode;
/* Beacon functions */
/* ah_setBeaconTimers */
ah->ah_beaconInit = ar9300_freebsd_beacon_init;
/* ah_setBeaconTimers */
ah->ah_setStationBeaconTimers = ar9300_set_sta_beacon_timers;
/* ah_resetStationBeaconTimers */
/* ah_getNextTBTT */
/* Interrupt functions */
ah->ah_isInterruptPending = ar9300_is_interrupt_pending;
ah->ah_getPendingInterrupts = ar9300_get_pending_interrupts_freebsd;
ah->ah_getInterrupts = ar9300_get_interrupts;
ah->ah_setInterrupts = ar9300_set_interrupts_freebsd;
/* Regulatory/internal functions */
// AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust;
AH_PRIVATE(ah)->ah_eepromRead = ar9300_eeprom_read_word;
// AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits;
AH_PRIVATE(ah)->ah_getWirelessModes = ar9300_get_wireless_modes;
AH_PRIVATE(ah)->ah_getChannelEdges = ar9300_get_channel_edges;
AH_PRIVATE(ah)->ah_eepromRead = ar9300_eeprom_read_word;
/* XXX ah_eeprom */
/* XXX ah_eeversion */
/* XXX ah_eepromDetach */
/* XXX ah_eepromGet */
AH_PRIVATE(ah)->ah_eepromGet = ar9300_eeprom_get_freebsd;
/* XXX ah_eepromSet */
/* XXX ah_getSpurChan */
/* XXX ah_eepromDiag */
/* 802.11n functions */
ah->ah_chainTxDesc = ar9300_freebsd_chain_tx_desc;
ah->ah_setupFirstTxDesc= ar9300_freebsd_setup_first_tx_desc;
ah->ah_setupLastTxDesc = ar9300_freebsd_setup_last_tx_desc;
ah->ah_set11nRateScenario = ar9300_freebsd_set_11n_rate_scenario;
ah->ah_set11nTxDesc = ar9300_freebsd_setup_11n_desc;
ah->ah_set11nAggrFirst = ar9300_set_11n_aggr_first;
ah->ah_set11nAggrMiddle = ar9300_set_11n_aggr_middle;
ah->ah_set11nAggrLast = ar9300_set_11n_aggr_last;
ah->ah_clr11nAggr = ar9300_clr_11n_aggr;
ah->ah_set11nBurstDuration = ar9300_set_11n_burst_duration;
/* ah_get11nExtBusy */
ah->ah_set11nMac2040 = ar9300_set_11n_mac2040;
ah->ah_setChainMasks = ar9300SetChainMasks;
/* ah_get11nRxClear */
/* ah_set11nRxClear */
}
HAL_BOOL
ar9300_reset_freebsd(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_STATUS *status)
{
HAL_BOOL r;
HAL_HT_MACMODE macmode;
struct ath_hal_private *ap = AH_PRIVATE(ah);
macmode =
IEEE80211_IS_CHAN_HT40(chan) ?
HAL_HT_MACMODE_2040 : HAL_HT_MACMODE_20;
r = ar9300_reset(ah, opmode, chan, macmode,
ap->ah_caps.halTxChainMask,
ap->ah_caps.halRxChainMask,
HAL_HT_EXTPROTSPACING_20, /* always 20Mhz channel spacing */
bChannelChange,
status,
AH_FALSE); /* XXX should really extend ath_hal_reset() */
return (r);
}
void
ar9300_config_pcie_freebsd(struct ath_hal *ah, HAL_BOOL restore,
HAL_BOOL powerOff)
{
ar9300_config_pci_power_save(ah, restore ? 1 : 0, powerOff ? 1 : 0);
}
/*
* This is a copy from ar9300_eeprom_get(), purely because the FreeBSD
* API is very silly and inconsistent.
*
* The AR93xx HAL doesn't call the eepromGetFlag() function, so this
* only occurs for FreeBSD code.
*
* When I fix this particular API, I'll undo this.
*/
HAL_STATUS
ar9300_eeprom_get_freebsd(struct ath_hal *ah, int param, void *val)
{
switch (param) {
case AR_EEP_FSTCLK_5G:
return HAL_OK;
default:
ath_hal_printf(ah, "%s: called, param=%d\n",
__func__, param);
return HAL_EIO;
}
}
HAL_BOOL
ar9300_stop_tx_dma_freebsd(struct ath_hal *ah, u_int q)
{
return ar9300_stop_tx_dma(ah, q, 1000);
}
void
ar9300_ani_poll_freebsd(struct ath_hal *ah,
const struct ieee80211_channel *chan)
{
HAL_NODE_STATS stats;
HAL_ANISTATS anistats;
OS_MEMZERO(&stats, sizeof(stats));
OS_MEMZERO(&anistats, sizeof(anistats));
ar9300_ani_ar_poll(ah, &stats, chan, &anistats);
}
/*
* Setup the configuration parameters in the style the AR9300 HAL
* wants.
*/
void
ar9300_config_defaults_freebsd(struct ath_hal *ah)
{
ah->ah_config.ath_hal_enable_ani = AH_TRUE;
}
HAL_BOOL
ar9300_stop_dma_receive_freebsd(struct ath_hal *ah)
{
return ar9300_stop_dma_receive(ah, 1000);
}
HAL_BOOL
ar9300_get_pending_interrupts_freebsd(struct ath_hal *ah, HAL_INT *masked)
{
/* Non-MSI, so no MSI vector; and 'nortc' = 0 */
return ar9300_get_pending_interrupts(ah, masked, HAL_INT_LINE, 0, 0);
}
HAL_INT
ar9300_set_interrupts_freebsd(struct ath_hal *ah, HAL_INT ints)
{
/* nortc = 0 */
return ar9300_set_interrupts(ah, ints, 0);
}
HAL_BOOL
ar9300_per_calibration_freebsd(struct ath_hal *ah,
struct ieee80211_channel *chan, u_int rxchainmask, HAL_BOOL long_cal,
HAL_BOOL *isCalDone)
{
/* XXX fake scheduled calibrations for now */
u_int32_t sched_cals = 0xfffffff;
return ar9300_calibration(ah, chan,
AH_PRIVATE(ah)->ah_caps.halRxChainMask,
long_cal,
isCalDone,
0, /* is_scan */
&sched_cals);
}
HAL_BOOL
ar9300_reset_cal_valid_freebsd(struct ath_hal *ah,
const struct ieee80211_channel *chan)
{
HAL_BOOL is_cal_done = AH_TRUE;
ar9300_reset_cal_valid(ah, chan, &is_cal_done, 0xffffffff);
return (is_cal_done);
}
void
ar9300_start_pcu_receive_freebsd(struct ath_hal *ah)
{
/* is_scanning flag == NULL */
ar9300_start_pcu_receive(ah, AH_FALSE);
}
/*
* FreeBSD will just pass in the descriptor value as 'pa'.
* The Atheros HAL treats 'pa' as the physical address of the RX
* descriptor and 'bufaddr' as the physical address of the RX buffer.
* I'm not sure why they didn't collapse them - the AR9300 RX descriptor
* routine doesn't check 'pa'.
*/
HAL_STATUS
ar9300_proc_rx_desc_freebsd(struct ath_hal *ah, struct ath_desc *ds,
uint32_t pa, struct ath_desc *ds_next, uint64_t tsf,
struct ath_rx_status *rxs)
{
return (ar9300_proc_rx_desc_fast(ah, ds, 0, ds_next, rxs,
(void *) ds));
}
void
ar9300_ani_rxmonitor_freebsd(struct ath_hal *ah, const HAL_NODE_STATS *stats,
const struct ieee80211_channel *chan)
{
}
void
ar9300_freebsd_get_desc_link(struct ath_hal *ah, void *ds, uint32_t *link)
{
struct ar9300_txc *ads = AR9300TXC(ds);
(*link) = ads->ds_link;
}
/*
* TX descriptor field setting wrappers - eek.
*/
HAL_BOOL
ar9300_freebsd_setup_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags,
u_int rtsctsRate, u_int rtsCtsDuration, u_int compicvLen,
u_int compivLen, u_int comp)
{
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_KEY_TYPE keyType = 0; /* XXX No padding */
if (keyIx != HAL_TXKEYIX_INVALID)
keyType = ahp->ah_keytype[keyIx];
/* XXX bounds check keyix */
ar9300_set_11n_tx_desc(ah, ds, pktLen, type, txPower, keyIx,
keyType, flags);
return AH_TRUE;
}
HAL_BOOL
ar9300_freebsd_setup_x_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
u_int txRate1, u_int txTries1,
u_int txRate2, u_int txTries2,
u_int txRate3, u_int txTries3)
{
ath_hal_printf(ah, "%s: called, 0x%x/%d, 0x%x/%d, 0x%x/%d\n",
__func__,
txRate1, txTries1,
txRate2, txTries2,
txRate3, txTries3);
/* XXX should only be called during probe */
return (AH_TRUE);
}
HAL_BOOL
ar9300_freebsd_fill_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
HAL_DMA_ADDR *bufListPtr, uint32_t *segLenPtr, u_int descId, u_int qid,
HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0)
{
HAL_KEY_TYPE keyType = 0;
const struct ar9300_txc *ads = AR9300TXC_CONST(ds0);
/*
* FreeBSD's HAL doesn't pass the keytype to fill_tx_desc();
* it's copied as part of the descriptor chaining.
*
* So, extract it from ds0.
*/
keyType = MS(ads->ds_ctl17, AR_encr_type);
return ar9300_fill_tx_desc(ah, ds, bufListPtr, segLenPtr, descId,
qid, keyType, firstSeg, lastSeg, ds0);
}
HAL_BOOL
ar9300_freebsd_get_tx_completion_rates(struct ath_hal *ah,
const struct ath_desc *ds0, int *rates, int *tries)
{
ath_hal_printf(ah, "%s: called\n", __func__);
return AH_FALSE; /* XXX for now */
}
/*
* 802.11n TX descriptor wrappers
*/
void
ar9300_freebsd_set_11n_rate_scenario(struct ath_hal *ah, struct ath_desc *ds,
u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[],
u_int nseries, u_int flags)
{
/* lastds=NULL, rtscts_duration is 0, smart antenna is 0 */
ar9300_set_11n_rate_scenario(ah, (void *) ds, (void *)ds, durUpdateEn,
rtsctsRate, 0, series, nseries, flags, 0);
}
/* chaintxdesc */
HAL_BOOL
ar9300_freebsd_chain_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
HAL_DMA_ADDR *bufLenList, uint32_t *segLenList,
u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int keyIx,
HAL_CIPHER cipher, uint8_t numDelims,
HAL_BOOL firstSeg, HAL_BOOL lastSeg, HAL_BOOL lastAggr)
{
ath_hal_printf(ah, "%s: called\n", __func__);
return AH_FALSE;
}
/* setupfirsttxdesc */
HAL_BOOL
ar9300_freebsd_setup_first_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
u_int aggrLen, u_int flags, u_int txPower, u_int txRate0,
u_int txTries0, u_int antMode, u_int rtsctsRate, u_int rtsctsDuration)
{
ath_hal_printf(ah, "%s: called\n", __func__);
return AH_FALSE;
}
/* setuplasttxdesc */
/*
* This gets called but for now let's not log anything;
* it's only used to update the rate control information.
*/
HAL_BOOL
ar9300_freebsd_setup_last_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
const struct ath_desc *ds0)
{
// ath_hal_printf(ah, "%s: called\n", __func__);
return AH_FALSE;
}
void
ar9300_freebsd_setup_11n_desc(struct ath_hal *ah, void *ds, u_int pktLen,
HAL_PKT_TYPE type, u_int txPower, u_int keyIx, u_int flags)
{
ath_hal_printf(ah, "%s: called\n", __func__);
#if 0
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_KEY_TYPE keyType = 0; /* XXX No padding */
if (keyIx != HAL_TXKEYIX_INVALID)
keyType = ahp->ah_keytype[keyIx];
/* XXX bounds check keyix */
ar9300_set_11n_tx_desc(ah, ds, pktLen, type, txPower, keyIx,
keyType, flags);
#endif
}
HAL_STATUS
ar9300_freebsd_proc_tx_desc(struct ath_hal *ah, struct ath_desc *ds,
struct ath_tx_status *ts)
{
return ar9300_proc_tx_desc(ah, ts);
}
void
ar9300_freebsd_beacon_init(struct ath_hal *ah, uint32_t next_beacon,
uint32_t beacon_period)
{
ar9300_beacon_init(ah, AH_PRIVATE(ah)->ah_opmode,
next_beacon, beacon_period);
}
HAL_BOOL
ar9300_freebsd_get_mib_cycle_counts(struct ath_hal *ah,
HAL_SURVEY_SAMPLE *hs)
{
return (AH_FALSE);
}
HAL_BOOL
ar9300_freebsd_get_dfs_default_thresh(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe)
{
/* XXX not yet */
return (AH_FALSE);
}
/*
* Clear multicast filter by index - from FreeBSD ar5212_recv.c
*/
static HAL_BOOL
ar9300ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
{
uint32_t val;
if (ix >= 64)
return (AH_FALSE);
if (ix >= 32) {
val = OS_REG_READ(ah, AR_MCAST_FIL1);
OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
} else {
val = OS_REG_READ(ah, AR_MCAST_FIL0);
OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
}
return AH_TRUE;
}
/*
* Set multicast filter by index - from FreeBSD ar5212_recv.c
*/
static HAL_BOOL
ar9300SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
{
uint32_t val;
if (ix >= 64)
return (AH_FALSE);
if (ix >= 32) {
val = OS_REG_READ(ah, AR_MCAST_FIL1);
OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
} else {
val = OS_REG_READ(ah, AR_MCAST_FIL0);
OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
}
return (AH_TRUE);
}

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#ifndef __AR9300_FREEBSD_H__
#define __AR9300_FREEBSD_H__
extern void ar9300_attach_freebsd_ops(struct ath_hal *ah);
extern HAL_BOOL ar9300_reset_freebsd(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_STATUS *status);
extern void ar9300_config_pcie_freebsd(struct ath_hal *, HAL_BOOL, HAL_BOOL);
extern HAL_STATUS ar9300_eeprom_get_freebsd(struct ath_hal *, int param,
void *val);
extern HAL_BOOL ar9300_stop_tx_dma_freebsd(struct ath_hal *ah, u_int q);
extern void ar9300_ani_poll_freebsd(struct ath_hal *ah,
const struct ieee80211_channel *chan);
extern void ar9300_config_defaults_freebsd(struct ath_hal *ah);
extern HAL_BOOL ar9300_stop_dma_receive_freebsd(struct ath_hal *ah);
extern HAL_BOOL ar9300_get_pending_interrupts_freebsd(struct ath_hal *ah,
HAL_INT *masked);
extern HAL_INT ar9300_set_interrupts_freebsd(struct ath_hal *ah,
HAL_INT mask);
extern HAL_BOOL ar9300_per_calibration_freebsd(struct ath_hal *ah,
struct ieee80211_channel *chan, u_int rxchainmask,
HAL_BOOL longCal, HAL_BOOL *isCalDone);
extern HAL_BOOL ar9300_reset_cal_valid_freebsd(struct ath_hal *ah,
const struct ieee80211_channel *chan);
extern void ar9300_start_pcu_receive_freebsd(struct ath_hal *ah);
extern HAL_STATUS ar9300_proc_rx_desc_freebsd(struct ath_hal *ah,
struct ath_desc *ds, uint32_t pa, struct ath_desc *ds_next,
uint64_t tsf, struct ath_rx_status *rxs);
extern void ar9300_ani_rxmonitor_freebsd(struct ath_hal *ah,
const HAL_NODE_STATS *stats, const struct ieee80211_channel *chan);
extern void ar9300_freebsd_get_desc_link(struct ath_hal *, void *ds,
uint32_t *);
extern HAL_BOOL ar9300_freebsd_setup_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type,
u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx,
u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsCtsDuration,
u_int compicvLen, u_int compivLen, u_int comp);
extern HAL_BOOL ar9300_freebsd_setup_x_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, u_int txRate1, u_int txTries1,
u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3);
extern HAL_BOOL ar9300_freebsd_fill_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, HAL_DMA_ADDR *bufAddrList,
uint32_t *segLenList, u_int descId, u_int qId, HAL_BOOL firstSeg,
HAL_BOOL lastSeg, const struct ath_desc *ds0);
extern HAL_BOOL ar9300_freebsd_get_tx_completion_rates(struct ath_hal *ah,
const struct ath_desc *ds0, int *rates, int *tries);
extern void ar9300_freebsd_set_11n_rate_scenario(struct ath_hal *,
struct ath_desc *, u_int, u_int, HAL_11N_RATE_SERIES series[],
u_int, u_int);
extern HAL_BOOL ar9300_freebsd_chain_tx_desc(struct ath_hal *ah,
struct ath_desc *ds,
HAL_DMA_ADDR *bufAddrList,
uint32_t *segLenList,
u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type,
u_int keyIx, HAL_CIPHER cipher, uint8_t numDelims,
HAL_BOOL firstSeg, HAL_BOOL lastSeg, HAL_BOOL lastAggr);
extern HAL_BOOL ar9300_freebsd_setup_first_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, u_int aggrLen, u_int flags, u_int txPower,
u_int txRate0, u_int txTries0, u_int antMode, u_int rtsctsRate,
u_int rtsctsDuration);
extern HAL_BOOL ar9300_freebsd_setup_last_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, const struct ath_desc *ds0);
extern void ar9300_freebsd_setup_11n_desc(struct ath_hal *ah,
void *ds, u_int pktLen, HAL_PKT_TYPE type, u_int txPower,
u_int keyIx, u_int flags);
extern HAL_STATUS ar9300_freebsd_proc_tx_desc(struct ath_hal *ah,
struct ath_desc *ds, struct ath_tx_status *ts);
extern void ar9300_freebsd_beacon_init(struct ath_hal *ah,
uint32_t next_beacon, uint32_t beacon_period);
extern HAL_BOOL ar9300_freebsd_get_mib_cycle_counts(struct ath_hal *ah,
HAL_SURVEY_SAMPLE *);
extern HAL_BOOL ar9300_freebsd_get_dfs_default_thresh(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
#endif /* __AR9300_FREEBSD_H__ */

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#ifndef __AR9300_FREEBSD_INC_H__
#define __AR9300_FREEBSD_INC_H__
/*
* Define some configuration entries for the AR9300 HAL, so #if entries
* don't have to be removed.
*/
#define ATH_DRIVER_SIM 0 /* SIM */
#define ATH_WOW 0 /* Wake on Wireless */
#define ATH_SUPPORT_MCI 1 /* MCI btcoex */
#define ATH_SUPPORT_AIC 0 /* XXX to do with btcoex? */
#define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */
#define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */
#define ATH_SUPPORT_WIRESHARK 0 /* Radiotap HAL code */
#define AH_SUPPORT_WRITE_EEPROM 0 /* EEPROM write support */
#define ATH_SUPPORT_WAPI 0 /* China WAPI support */
#define ATH_ANT_DIV_COMB 1 /* Antenna combining */
#define ATH_SUPPORT_RAW_ADC_CAPTURE 0 /* Raw ADC capture support */
#define ATH_TRAFFIC_FAST_RECOVER 0 /* XXX not sure yet */
#define ATH_SUPPORT_SPECTRAL 0 /* Spectral scan support */
#define ATH_BT_COEX 1 /* Enable BT Coex code */
#define ATH_PCIE_ERROR_MONITOR 0 /* ??? */
#define ATH_SUPPORT_CRDC 0 /* ??? */
#define ATH_LOW_POWER_ENABLE 0 /* ??? */
#define ATH_SUPPORT_VOW_DCS 0 /* Video over wireless dynamic channel select */
#define REMOVE_PKT_LOG 1
#define ATH_VC_MODE_PROXY_STA 0 /* Azimuth + proxysta? */
#define ATH_GEN_RANDOMNESS 0
#define __PKT_SERIOUS_ERRORS__ 0
#define HAL_INTR_REFCOUNT_DISABLE 1 /* XXX wha? And atomics in the HAL!? */
#define UMAC_SUPPORT_SMARTANTENNA 0 /* sigh.. */
#define ATH_SMARTANTENNA_DISABLE_JTAG 0
#define ATH_SUPPORT_WIRESHARK 0
#define ATH_SUPPORT_WIFIPOS 0
#define ATH_SUPPORT_PAPRD 1
#define ATH_SUPPORT_TxBF 0
/* XXX need to reverify these; they came in with qcamain */
#define ATH_SUPPORT_FAST_CC 0
#define ATH_SUPPORT_RADIO_RETENTION 0
#define ATH_SUPPORT_CAL_REUSE 0
#define ATH_WOW_OFFLOAD 0
#define HAL_NO_INTERSPERSED_READS
/* Required or things will probe/attach, but not work right */
#define AH_SUPPORT_OSPREY 1
#define AH_SUPPORT_POSEIDON 1
#define AH_SUPPORT_AR9300 1
/* These are the embedded boards; we don't currently support these */
//#define AH_SUPPORT_HORNET 1
//#define AH_SUPPORT_WASP 1
//#define AH_SUPPORT_SCORPION 1
#define FIX_NOISE_FLOOR 1
/* XXX this needs to be removed! No atomics in the HAL! */
typedef int os_atomic_t; /* XXX shouldn't do atomics here! */
#define OS_ATOMIC_INC(a) (*a)++
#define OS_ATOMIC_DEC(a) (*a)--
/*
* HAL definitions which aren't necessarily for public consumption (yet).
*/
enum {
HAL_TRUE_CHIP = 1,
HAL_MAC_TO_MAC_EMU,
HAL_MAC_BB_EMU,
};
/* HAL_KEY_TYPE */
enum {
HAL_KEY_PROXY_STA_MASK = 0x10,
};
typedef enum {
HAL_SMPS_DEFAULT = 0,
HAL_SMPS_SW_CTRL_LOW_PWR, /* Software control, low power setting */
HAL_SMPS_SW_CTRL_HIGH_PWR, /* Software control, high power setting */
HAL_SMPS_HW_CTRL /* Hardware Control */
} HAL_SMPS_MODE;
/*
* Green Tx, Based on different RSSI of Received Beacon thresholds,
* using different tx power by modified register tx power related values.
* The thresholds are decided by system team.
*/
#define GreenTX_thres1 56 /* in dB */
#define GreenTX_thres2 36 /* in dB */
typedef enum {
HAL_RSSI_TX_POWER_NONE = 0,
HAL_RSSI_TX_POWER_SHORT = 1, /* short range, reduce OB/DB bias current and disable PAL */
HAL_RSSI_TX_POWER_MIDDLE = 2, /* middle range, reduce OB/DB bias current and PAL is enabled */
HAL_RSSI_TX_POWER_LONG = 3, /* long range, orig. OB/DB bias current and PAL is enabled */
} HAL_RSSI_TX_POWER;
struct dfs_pulse {
u_int32_t rp_numpulses ; /* Num of pulses in radar burst */
u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */
u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */
u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
u_int32_t rp_patterntype; /* fixed or variable pattern type*/
u_int32_t rp_pulsevar; /* Time variation of pulse duration for
matched filter (single-sided) in usecs */
u_int32_t rp_threshold; /* Threshold for MF output to indicate
radar match */
u_int32_t rp_mindur; /* Min pulse duration to be considered for
this pulse type */
u_int32_t rp_maxdur; /* Max pusle duration to be considered for
this pulse type */
u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */
u_int32_t rp_meanoffset; /* Offset for timing adjustment */
int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */
/* lower than in non TURBO mode.
This will be used to offset that diff.*/
u_int32_t rp_ignore_pri_window;
u_int32_t rp_pulseid; /* Unique ID for identifying filter */
};
struct dfs_staggered_pulse {
u_int32_t rp_numpulses; /* Num of pulses in radar burst */
u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */
u_int32_t rp_min_pulsefreq; /* Frequency of pulses in burst */
u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
u_int32_t rp_patterntype; /* fixed or variable pattern type*/
u_int32_t rp_pulsevar; /* Time variation of pulse duration for
matched filter (single-sided) in usecs */
u_int32_t rp_threshold; /* Thershold for MF output to indicateC
radar match */
u_int32_t rp_mindur; /* Min pulse duration to be considered for
this pulse type */
u_int32_t rp_maxdur; /* Max pusle duration to be considered for
this pulse type */
u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */
u_int32_t rp_meanoffset; /* Offset for timing adjustment */
int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */
/* lower than in non TURBO mode. This will be used to offset that diff.*/
u_int32_t rp_pulseid; /* Unique ID for identifying filter */
};
struct dfs_bin5pulse {
u_int32_t b5_threshold; /* Number of bin5 pulses to indicate detection */
u_int32_t b5_mindur; /* Min duration for a bin5 pulse */
u_int32_t b5_maxdur; /* Max duration for a bin5 pulse */
u_int32_t b5_timewindow; /* Window over which to count bin5 pulses */
u_int32_t b5_rssithresh; /* Min rssi to be considered a pulse */
u_int32_t b5_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dB */
};
#if 0
/* SPECTRAL SCAN defines begin */
typedef struct {
u_int16_t ss_fft_period; /* Skip interval for FFT reports */
u_int16_t ss_period; /* Spectral scan period */
u_int16_t ss_count; /* # of reports to return from ss_active */
u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */
u_int8_t radar_bin_thresh_sel;
u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */
int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */
int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */
int32_t ss_nf_temp_data; /* temperature data taken during nf scan */
} HAL_SPECTRAL_PARAM;
#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF
#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
#endif
/*
* Noise power data definitions
* units are: 4 x dBm - NOISE_PWR_DATA_OFFSET (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
* range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
* resolution (2 bits) is 0.25dBm
*/
#define NOISE_PWR_DATA_OFFSET -90 /* dbm - all pwr report data is represented offset by this */
#define INT_2_NOISE_PWR_DBM(_p) (((_p) - NOISE_PWR_DATA_OFFSET) << 2)
#define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET)
#define NOISE_PWR_DBM_2_DEC(_p) (((-(_p)) & 3) * 25)
#define N2DBM(_x,_y) ((((_x) - NOISE_PWR_DATA_OFFSET) << 2) - (_y)/25)
/* SPECTRAL SCAN defines end */
typedef struct halvowstats {
u_int32_t tx_frame_count;
u_int32_t rx_frame_count;
u_int32_t rx_clear_count;
u_int32_t cycle_count;
u_int32_t ext_cycle_count;
} HAL_VOWSTATS;
#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */
#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */
#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
/*
* Weight table configurations.
*/
#define AR9300_BT_WGHT 0xcccc4444
#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0
#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0
#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880
#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880
#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000
#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000
#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff // Stomp BT even when WLAN is idle
#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff
#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 // Stomp BT even when WLAN is idle
#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888
#define JUPITER_STOMP_ALL_WLAN_WGHT0 0x01017d01
#define JUPITER_STOMP_ALL_WLAN_WGHT1 0x41414101
#define JUPITER_STOMP_ALL_WLAN_WGHT2 0x41414101
#define JUPITER_STOMP_ALL_WLAN_WGHT3 0x41414141
#define JUPITER_STOMP_LOW_WLAN_WGHT0 0x01017d01
#define JUPITER_STOMP_LOW_WLAN_WGHT1 0x3b3b3b01
#define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b01
#define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b
#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT0 0x01017d01
#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT1 0x013b0101
#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT2 0x3b3b0101
#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT3 0x3b3b013b
#define JUPITER_STOMP_NONE_WLAN_WGHT0 0x01017d01
#define JUPITER_STOMP_NONE_WLAN_WGHT1 0x01010101
#define JUPITER_STOMP_NONE_WLAN_WGHT2 0x01010101
#define JUPITER_STOMP_NONE_WLAN_WGHT3 0x01010101
#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x01017d7d
#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d01
#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d
#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d
#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x01013b3b
#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b01
#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b
#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b
#define MCI_CONCUR_TX_WLAN_WGHT1_MASK 0xff000000
#define MCI_CONCUR_TX_WLAN_WGHT1_MASK_S 24
#define MCI_CONCUR_TX_WLAN_WGHT2_MASK 0x00ff0000
#define MCI_CONCUR_TX_WLAN_WGHT2_MASK_S 16
#define MCI_CONCUR_TX_WLAN_WGHT3_MASK 0x000000ff
#define MCI_CONCUR_TX_WLAN_WGHT3_MASK_S 0
#define MCI_CONCUR_TX_WLAN_WGHT3_MASK2 0x00ff0000
#define MCI_CONCUR_TX_WLAN_WGHT3_MASK2_S 16
#define MCI_QUERY_BT_VERSION_VERBOSE 0
#define MCI_LINKID_INDEX_MGMT_PENDING 1
#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
typedef enum mci_message_header {
MCI_LNA_CTRL = 0x10, /* len = 0 */
MCI_CONT_NACK = 0x20, /* len = 0 */
MCI_CONT_INFO = 0x30, /* len = 4 */
MCI_CONT_RST = 0x40, /* len = 0 */
MCI_SCHD_INFO = 0x50, /* len = 16 */
MCI_CPU_INT = 0x60, /* len = 4 */
MCI_SYS_WAKING = 0x70, /* len = 0 */
MCI_GPM = 0x80, /* len = 16 */
MCI_LNA_INFO = 0x90, /* len = 1 */
MCI_LNA_STATE = 0x94,
MCI_LNA_TAKE = 0x98,
MCI_LNA_TRANS = 0x9c,
MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
MCI_REQ_WAKE = 0xc0, /* len = 0 */
MCI_DEBUG_16 = 0xfe, /* len = 2 */
MCI_REMOTE_RESET = 0xff /* len = 16 */
} MCI_MESSAGE_HEADER;
/* Default remote BT device MCI COEX version */
#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
/* Local WLAN MCI COEX version */
#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
typedef enum mci_gpm_subtype {
MCI_GPM_BT_CAL_REQ = 0,
MCI_GPM_BT_CAL_GRANT = 1,
MCI_GPM_BT_CAL_DONE = 2,
MCI_GPM_WLAN_CAL_REQ = 3,
MCI_GPM_WLAN_CAL_GRANT = 4,
MCI_GPM_WLAN_CAL_DONE = 5,
MCI_GPM_COEX_AGENT = 0x0C,
MCI_GPM_RSVD_PATTERN = 0xFE,
MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE,
MCI_GPM_BT_DEBUG = 0xFF
} MCI_GPM_SUBTYPE_T;
typedef enum mci_gpm_coex_opcode {
MCI_GPM_COEX_VERSION_QUERY = 0,
MCI_GPM_COEX_VERSION_RESPONSE = 1,
MCI_GPM_COEX_STATUS_QUERY = 2,
MCI_GPM_COEX_HALT_BT_GPM = 3,
MCI_GPM_COEX_WLAN_CHANNELS = 4,
MCI_GPM_COEX_BT_PROFILE_INFO = 5,
MCI_GPM_COEX_BT_STATUS_UPDATE = 6,
MCI_GPM_COEX_BT_UPDATE_FLAGS = 7
} MCI_GPM_COEX_OPCODE_T;
typedef enum mci_gpm_coex_query_type {
/* WLAN information */
MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01,
/* BT information */
MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01,
MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02,
MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04
} MCI_GPM_COEX_QUERY_TYPE_T;
typedef enum mci_gpm_coex_halt_bt_gpm {
MCI_GPM_COEX_BT_GPM_UNHALT = 0,
MCI_GPM_COEX_BT_GPM_HALT = 1
} MCI_GPM_COEX_HALT_BT_GPM_T;
typedef enum mci_gpm_coex_profile_type {
MCI_GPM_COEX_PROFILE_UNKNOWN = 0,
MCI_GPM_COEX_PROFILE_RFCOMM = 1,
MCI_GPM_COEX_PROFILE_A2DP = 2,
MCI_GPM_COEX_PROFILE_HID = 3,
MCI_GPM_COEX_PROFILE_BNEP = 4,
MCI_GPM_COEX_PROFILE_VOICE = 5,
MCI_GPM_COEX_PROFILE_MAX
} MCI_GPM_COEX_PROFILE_TYPE_T;
typedef enum mci_gpm_coex_profile_state {
MCI_GPM_COEX_PROFILE_STATE_END = 0,
MCI_GPM_COEX_PROFILE_STATE_START = 1
} MCI_GPM_COEX_PROFILE_STATE_T;
typedef enum mci_gpm_coex_profile_role {
MCI_GPM_COEX_PROFILE_SLAVE = 0,
MCI_GPM_COEX_PROFILE_MASTER = 1
} MCI_GPM_COEX_PROFILE_ROLE_T;
typedef enum mci_gpm_coex_bt_status_type {
MCI_GPM_COEX_BT_NONLINK_STATUS = 0,
MCI_GPM_COEX_BT_LINK_STATUS = 1
} MCI_GPM_COEX_BT_STATUS_TYPE_T;
typedef enum mci_gpm_coex_bt_status_state {
MCI_GPM_COEX_BT_NORMAL_STATUS = 0,
MCI_GPM_COEX_BT_CRITICAL_STATUS = 1
} MCI_GPM_COEX_BT_STATUS_STATE_T;
#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
typedef enum mci_gpm_coex_bt_updata_flags_op {
MCI_GPM_COEX_BT_FLAGS_READ = 0x00,
MCI_GPM_COEX_BT_FLAGS_SET = 0x01,
MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02
} MCI_GPM_COEX_BT_FLAGS_OP_T;
/* MCI GPM/Coex opcode/type definitions */
enum {
MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
MCI_GPM_COEX_B_GPM_TYPE = 4,
MCI_GPM_COEX_B_GPM_OPCODE = 5,
/* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
/* MCI_GPM_COEX_VERSION_QUERY */
/* MCI_GPM_COEX_VERSION_RESPONSE */
MCI_GPM_COEX_B_MAJOR_VERSION = 6,
MCI_GPM_COEX_B_MINOR_VERSION = 7,
/* MCI_GPM_COEX_STATUS_QUERY */
MCI_GPM_COEX_B_BT_BITMAP = 6,
MCI_GPM_COEX_B_WLAN_BITMAP = 7,
/* MCI_GPM_COEX_HALT_BT_GPM */
MCI_GPM_COEX_B_HALT_STATE = 6,
/* MCI_GPM_COEX_WLAN_CHANNELS */
MCI_GPM_COEX_B_CHANNEL_MAP = 6,
/* MCI_GPM_COEX_BT_PROFILE_INFO */
MCI_GPM_COEX_B_PROFILE_TYPE = 6,
MCI_GPM_COEX_B_PROFILE_LINKID = 7,
MCI_GPM_COEX_B_PROFILE_STATE = 8,
MCI_GPM_COEX_B_PROFILE_ROLE = 9,
MCI_GPM_COEX_B_PROFILE_RATE = 10,
MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
MCI_GPM_COEX_H_PROFILE_T = 12,
MCI_GPM_COEX_B_PROFILE_W = 14,
MCI_GPM_COEX_B_PROFILE_A = 15,
/* MCI_GPM_COEX_BT_STATUS_UPDATE */
MCI_GPM_COEX_B_STATUS_TYPE = 6,
MCI_GPM_COEX_B_STATUS_LINKID = 7,
MCI_GPM_COEX_B_STATUS_STATE = 8,
/* MCI_GPM_COEX_BT_UPDATE_FLAGS */
MCI_GPM_COEX_B_BT_FLAGS_OP = 10,
MCI_GPM_COEX_W_BT_FLAGS = 6
};
#define MCI_GPM_RECYCLE(_p_gpm) \
{ \
*(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \
}
#define MCI_GPM_TYPE(_p_gpm) \
(*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
#define MCI_GPM_OPCODE(_p_gpm) \
(*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \
{ \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
}
#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \
{ \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \
}
#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
#define MCI_NUM_BT_CHANNELS 79
#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \
{ \
if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
(_bt_chan / 8)) |= 1 << (_bt_chan & 7); \
} \
}
#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \
{ \
if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
(_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \
} \
}
#define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
#define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
#define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004
#define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
#define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
#define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
#define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
#define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
#define HAL_MCI_INTERRUPT_RX_MSG 0x00000200
#define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
#define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
#define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL )
#define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
#define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
#define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
#define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
#define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
#define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
#define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
#define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
#define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
#define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_RST)
typedef enum mci_bt_state {
MCI_BT_SLEEP,
MCI_BT_AWAKE,
MCI_BT_CAL_START,
MCI_BT_CAL
} MCI_BT_STATE_T;
/* Type of state query */
typedef enum mci_state_type {
HAL_MCI_STATE_ENABLE,
HAL_MCI_STATE_INIT_GPM_OFFSET,
HAL_MCI_STATE_NEXT_GPM_OFFSET,
HAL_MCI_STATE_LAST_GPM_OFFSET,
HAL_MCI_STATE_BT,
HAL_MCI_STATE_SET_BT_SLEEP,
HAL_MCI_STATE_SET_BT_AWAKE,
HAL_MCI_STATE_SET_BT_CAL_START,
HAL_MCI_STATE_SET_BT_CAL,
HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET,
HAL_MCI_STATE_REMOTE_SLEEP,
HAL_MCI_STATE_CONT_RSSI_POWER,
HAL_MCI_STATE_CONT_PRIORITY,
HAL_MCI_STATE_CONT_TXRX,
HAL_MCI_STATE_RESET_REQ_WAKE,
HAL_MCI_STATE_SEND_WLAN_COEX_VERSION,
HAL_MCI_STATE_SET_BT_COEX_VERSION,
HAL_MCI_STATE_SEND_WLAN_CHANNELS,
HAL_MCI_STATE_SEND_VERSION_QUERY,
HAL_MCI_STATE_SEND_STATUS_QUERY,
HAL_MCI_STATE_NEED_FLUSH_BT_INFO,
HAL_MCI_STATE_SET_CONCUR_TX_PRI,
HAL_MCI_STATE_RECOVER_RX,
HAL_MCI_STATE_NEED_FTP_STOMP,
HAL_MCI_STATE_NEED_TUNING,
HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX,
HAL_MCI_STATE_DEBUG,
HAL_MCI_STATE_MAX
} HAL_MCI_STATE_TYPE;
#define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
#define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
#define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020
#define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
#define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
#define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
#define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
#define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
#define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800
#define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000
#define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000
#define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
/*
HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1
HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1
HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1
HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1
HAL_MCI_BT_MCI_FLAGS_DEBUG = 0
HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1
HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1
HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1
HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0
HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1
HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1
HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1
HAL_MCI_BT_MCI_FLAGS_OTHER = 1
*/
#define HAL_MCI_TOGGLE_BT_MCI_FLAGS \
( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \
HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \
HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \
HAL_MCI_BT_MCI_FLAGS_MCI_MODE )
#define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000
#define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
#define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS
#define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
#define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000
#define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \
~HAL_MCI_TOGGLE_BT_MCI_FLAGS)
#define HAL_MCI_GPM_NOMORE 0
#define HAL_MCI_GPM_MORE 1
#define HAL_MCI_GPM_INVALID 0xffffffff
#define ATH_AIC_MAX_BT_CHANNEL 79
/*
* Default value for Jupiter is 0x00002201
* Default value for Aphrodite is 0x00002282
*/
#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
#define ATH_MCI_CONFIG_AGGR_THRESH_S 8
#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
#define ATH_MCI_CONFIG_CLK_DIV 0x00003000
#define ATH_MCI_CONFIG_CLK_DIV_S 12
#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
#define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \
ATH_MCI_CONFIG_MCI_OBS_TXRX | \
ATH_MCI_CONFIG_MCI_OBS_BT )
#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
#define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01
#define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02
#define ATH_MCI_CONCUR_TX_DEBUG 0x03
/*
* The values below come from the system team test result.
* For Jupiter, BT tx power level is from 0(-20dBm) to 6(4dBm).
* Lowest WLAN tx power would be in bit[23:16] of dword 1.
*/
static const u_int32_t mci_concur_tx_max_pwr[4][8] =
{ /* No limit */
{0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f},
/* 11G */
{0x16161616, 0x12121516, 0x12121212, 0x12121212,
0x12121212, 0x12121212, 0x12121212, 0x7f121212},
/* HT20 */
{0x15151515, 0x14141515, 0x14141414, 0x14141414,
0x14141414, 0x14141414, 0x14141414, 0x7f141414},
/* HT40 */
{0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x7f101010}};
#define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK 0x00ff0000
#define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK_S 16
#endif /* __AR9300_FREEBSD_INC_H__ */

31
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
@ -34,7 +32,7 @@
/*
* Configure GPIO Output Mux control
*/
#ifdef UMAC_SUPPORT_SMARTANTENNA
#if UMAC_SUPPORT_SMARTANTENNA
static void ar9340_soc_gpio_cfg_output_mux(
struct ath_hal *ah,
u_int32_t gpio,
@ -112,7 +110,7 @@ HAL_BOOL
ar9300_gpio_cfg_output(
struct ath_hal *ah,
u_int32_t gpio,
HAL_GPIO_OUTPUT_MUX_TYPE hal_signal_type)
HAL_GPIO_MUX_TYPE hal_signal_type)
{
u_int32_t ah_signal_type;
u_int32_t gpio_shift;
@ -162,7 +160,7 @@ ar9300_gpio_cfg_output(
AR_GPIO_OUTPUT_MUX_AS_SWCOM3,
};
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
(gpio == AR9382_GPIO_9_INPUT_ONLY))
@ -171,7 +169,7 @@ ar9300_gpio_cfg_output(
}
/* Convert HAL signal type definitions to hardware-specific values. */
if (hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
if ((int) hal_signal_type < ARRAY_LENGTH(mux_signal_conversion_table))
{
ah_signal_type = mux_signal_conversion_table[hal_signal_type];
} else {
@ -216,7 +214,7 @@ ar9300_gpio_cfg_output(
if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)))
{
#ifdef UMAC_SUPPORT_SMARTANTENNA
#if UMAC_SUPPORT_SMARTANTENNA
ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
#endif
return AH_TRUE;
@ -243,7 +241,7 @@ HAL_BOOL
ar9300_gpio_cfg_output_led_off(
struct ath_hal *ah,
u_int32_t gpio,
HAL_GPIO_OUTPUT_MUX_TYPE halSignalType)
HAL_GPIO_MUX_TYPE halSignalType)
{
#define N(a) (sizeof(a) / sizeof(a[0]))
u_int32_t ah_signal_type;
@ -290,7 +288,7 @@ ar9300_gpio_cfg_output_led_off(
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
/* Convert HAL signal type definitions to hardware-specific values. */
if (halSignalType < ARRAY_LENGTH(mux_signal_conversion_table))
if ((int) halSignalType < ARRAY_LENGTH(mux_signal_conversion_table))
{
ah_signal_type = mux_signal_conversion_table[halSignalType];
} else {
@ -348,7 +346,7 @@ ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
{
u_int32_t gpio_shift;
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
(gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM))
@ -378,7 +376,7 @@ ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
HAL_BOOL
ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
{
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
(gpio == AR9382_GPIO_9_INPUT_ONLY))
@ -398,7 +396,7 @@ u_int32_t
ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
{
u_int32_t gpio_in;
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
(gpio == AR9382_GPIO_PIN_11_RESERVED))
{
@ -452,7 +450,7 @@ ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel)
shifts[1] = AR_INTR_SYNC_MASK_GPIO_S;
#endif
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
if ((gpio == AR9382_GPIO_PIN_8_RESERVED) ||
(gpio == AR9382_GPIO_PIN_11_RESERVED) ||
@ -462,9 +460,8 @@ ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel)
}
#ifdef AH_ASSERT
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
#endif
if (ilevel == HAL_GPIO_INTR_DISABLE) {
/* clear this GPIO's bit in the interrupt registers */
for (i = 0; i < ARRAY_LENGTH(regs); i++) {
@ -523,7 +520,7 @@ ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map,
{
u_int32_t gpio_mask;
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins) - 1;
gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map);
#ifndef ATH_GPIO_USE_ASYNC_CAUSE
@ -648,5 +645,3 @@ void ar9300_gpio_show(struct ath_hal *ah)
}
#endif /*AH_DEBUG*/
#endif /* AH_SUPPORT_AR9300 */

40
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -153,6 +151,13 @@ ar9300_get_pending_interrupts(
goto end;
}
HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
"%s: isr=0x%x, sync_cause=0x%x, async_cause=0x%x\n",
__func__,
isr,
sync_cause,
async_cause);
if (isr) {
if (isr & AR_ISR_BCNMISC) {
u_int32_t isr2;
@ -168,7 +173,7 @@ ar9300_get_pending_interrupts(
mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> MAP_ISR_S2_HAL_TSFOOR);
mask2 |= ((isr2 & AR_ISR_S2_BBPANIC) >> MAP_ISR_S2_HAL_BBPANIC);
if (!p_cap->hal_isr_rac_support) {
if (!p_cap->halIsrRacSupport) {
/*
* EV61133 (missing interrupts due to ISR_RAC):
* If not using ISR_RAC, clear interrupts by writing to ISR_S2.
@ -185,7 +190,7 @@ ar9300_get_pending_interrupts(
/* Use AR_ISR_RAC only if chip supports it.
* See EV61133 (missing interrupts due to ISR_RAC)
*/
if (p_cap->hal_isr_rac_support) {
if (p_cap->halIsrRacSupport) {
isr = OS_REG_READ(ah, AR_ISR_RAC);
}
if (isr == 0xffffffff) {
@ -222,7 +227,7 @@ ar9300_get_pending_interrupts(
if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
*masked |= HAL_INT_TX;
if (!p_cap->hal_isr_rac_support) {
if (!p_cap->halIsrRacSupport) {
u_int32_t s0, s1;
/*
* EV61133 (missing interrupts due to ISR_RAC):
@ -254,7 +259,7 @@ ar9300_get_pending_interrupts(
#if 0
/* XXX Verify if this is fixed for Osprey */
if (!p_cap->hal_auto_sleep_support) {
if (!p_cap->halAutoSleepSupport) {
u_int32_t isr5 = OS_REG_READ(ah, AR_ISR_S5_S);
if (isr5 & AR_ISR_S5_TIM_TIMER) {
*masked |= HAL_INT_TIM_TIMER;
@ -264,7 +269,7 @@ ar9300_get_pending_interrupts(
if (isr & AR_ISR_GENTMR) {
u_int32_t s5;
if (p_cap->hal_isr_rac_support) {
if (p_cap->halIsrRacSupport) {
/* Use secondary shadow registers if using ISR_RAC */
s5 = OS_REG_READ(ah, AR_ISR_S5_S);
} else {
@ -283,7 +288,7 @@ ar9300_get_pending_interrupts(
*masked |= HAL_INT_GENTIMER;
}
}
if (!p_cap->hal_isr_rac_support) {
if (!p_cap->halIsrRacSupport) {
/*
* EV61133 (missing interrupts due to ISR_RAC):
* If not using ISR_RAC, clear interrupts by writing to ISR_S5.
@ -299,7 +304,7 @@ ar9300_get_pending_interrupts(
*masked |= mask2;
if (!p_cap->hal_isr_rac_support) {
if (!p_cap->halIsrRacSupport) {
/*
* EV61133 (missing interrupts due to ISR_RAC):
* If not using ISR_RAC, clear the interrupts we've read by
@ -338,7 +343,7 @@ ar9300_get_pending_interrupts(
#if ATH_SUPPORT_MCI
if ((async_cause & AR_INTR_ASYNC_CAUSE_MCI) &&
p_cap->hal_mci_support)
p_cap->halMciSupport)
{
u_int32_t int_raw, int_rx_msg;
@ -489,7 +494,7 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
if (omask & HAL_INT_GLOBAL) {
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) {
if (ah->ah_config.ath_hal_enable_msi) {
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE), 0);
/* flush write to HW */
(void)OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE));
@ -514,6 +519,7 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
"%s: Request HAL_INT_GLOBAL ENABLED\n", __func__);
#if 0
if (OS_ATOMIC_READ(&ahp->ah_ier_ref_count) == 0) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: WARNING: ah_ier_ref_count is 0 "
@ -521,9 +527,12 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
__func__);
}
#endif
#endif
#if 0
if (OS_ATOMIC_READ(&ahp->ah_ier_ref_count) > 0) {
OS_ATOMIC_DEC(&ahp->ah_ier_ref_count);
}
#endif
} else {
HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
"%s: Request HAL_INT_GLOBAL DISABLED\n", __func__);
@ -559,7 +568,7 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
mask |= AR_IMR_RXOK_LP;
}
msi_mask |= AR_INTR_PRIO_RXLP | AR_INTR_PRIO_RXHP;
if (! p_cap->hal_auto_sleep_support) {
if (! p_cap->halAutoSleepSupport) {
mask |= AR_IMR_GENTMR;
}
}
@ -621,7 +630,7 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
OS_REG_WRITE(ah, AR_IMR_S2, ahp->ah_mask2Reg );
ahp->ah_mask_reg = ints;
if (! p_cap->hal_auto_sleep_support) {
if (! p_cap->halAutoSleepSupport) {
if (ints & HAL_INT_TIM_TIMER) {
OS_REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
}
@ -661,7 +670,7 @@ ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL nortc)
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE), mask);
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK), mask);
if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_msi) {
if (ah->ah_config.ath_hal_enable_msi) {
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE),
msi_mask);
OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK),
@ -762,6 +771,3 @@ ar9300_get_intr_mitigation_timer(struct ath_hal* ah, HAL_INT_MITIGATION reg)
#endif
return val;
}
#endif /* AH_SUPPORT_AR9300 */

43
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_keycache.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -35,13 +33,26 @@
#define IS_MIC_ENABLED(ah) \
(AH9300(ah)->ah_sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
/*
* This isn't the keytable type; this is actually something separate
* for the TX descriptor.
*/
static const int keyType[] = {
1, /* HAL_CIPHER_WEP */
0, /* HAL_CIPHER_AES_OCB */
2, /* HAL_CIPHER_AES_CCM */
0, /* HAL_CIPHER_CKIP */
3, /* HAL_CIPHER_TKIP */
0 /* HAL_CIPHER_CLR */
};
/*
* Return the size of the hardware key cache.
*/
u_int32_t
ar9300_get_key_cache_size(struct ath_hal *ah)
{
return AH_PRIVATE(ah)->ah_caps.hal_key_cache_size;
return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;
}
/*
@ -50,7 +61,7 @@ ar9300_get_key_cache_size(struct ath_hal *ah)
HAL_BOOL
ar9300_is_key_cache_entry_valid(struct ath_hal *ah, u_int16_t entry)
{
if (entry < AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) {
if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
u_int32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
if (val & AR_KEYTABLE_VALID) {
return AH_TRUE;
@ -68,11 +79,14 @@ ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry)
u_int32_t key_type;
struct ath_hal_9300 *ahp = AH9300(ah);
if (entry >= AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) {
if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry);
return AH_FALSE;
}
ahp->ah_keytype[entry] = keyType[HAL_CIPHER_CLR];
key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
/* XXX why not clear key type/valid bit first? */
@ -87,7 +101,7 @@ ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry)
if (key_type == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
u_int16_t micentry = entry + 64; /* MIC goes at slot+64 */
HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.hal_key_cache_size);
HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);
OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
@ -130,7 +144,7 @@ ar9300_set_key_cache_entry_mac(
u_int32_t mac_hi, mac_lo;
u_int32_t unicast_addr = AR_KEYTABLE_VALID;
if (entry >= AH_PRIVATE(ah)->ah_caps.hal_key_cache_size) {
if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry);
return AH_FALSE;
@ -186,7 +200,7 @@ ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
int is_proxysta_key = k->kv_type & HAL_KEY_PROXY_STA_MASK;
if (entry >= p_cap->hal_key_cache_size) {
if (entry >= p_cap->halKeyCacheSize) {
HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
"%s: entry %u out of range\n", __func__, entry);
return AH_FALSE;
@ -200,7 +214,7 @@ ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
key_type = AR_KEYTABLE_TYPE_AES;
break;
case HAL_CIPHER_AES_CCM:
if (!p_cap->hal_cipher_aes_ccm_support) {
if (!p_cap->halCipherAesCcmSupport) {
HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: AES-CCM not supported by "
"mac rev 0x%x\n",
__func__, AH_PRIVATE(ah)->ah_macRev);
@ -210,7 +224,7 @@ ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
break;
case HAL_CIPHER_TKIP:
key_type = AR_KEYTABLE_TYPE_TKIP;
if (IS_MIC_ENABLED(ah) && entry + 64 >= p_cap->hal_key_cache_size) {
if (IS_MIC_ENABLED(ah) && entry + 64 >= p_cap->halKeyCacheSize) {
HALDEBUG(ah, HAL_DEBUG_KEYCACHE,
"%s: entry %u inappropriate for TKIP\n",
__func__, entry);
@ -258,7 +272,7 @@ ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
if (is_proxysta_key) {
u_int8_t bcast_mac[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
if (!mac || adf_os_mem_cmp(mac, bcast_mac, 6)) {
if (!mac || OS_MEMCMP(mac, bcast_mac, 6)) {
psta = AR_KEYTABLE_DIR_ACK_BIT;
}
}
@ -363,6 +377,11 @@ ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
ar9300_set_key_cache_entry_mac(ah, entry, mac);
}
ahp->ah_keytype[entry] = keyType[k->kv_type];
HALDEBUG(ah, HAL_DEBUG_KEYCACHE, "%s: entry=%d, k->kv_type=%d,"
"keyType=%d\n", __func__, entry, k->kv_type, keyType[k->kv_type]);
if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
return AH_TRUE;
}
@ -417,5 +436,3 @@ void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry)
}
#undef AH_KEY_REG_SIZE
}
#endif /* AH_SUPPORT_AR9300 */

55
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c
View file

@ -17,8 +17,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -34,7 +32,7 @@
static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
int len, u_int32_t *pl)
{
#if DBG
#if 0
char s[128];
char *p = s;
int i;
@ -65,17 +63,17 @@ static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
static
void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
{
struct ath_hal_9300 *ahp = AH9300(ah);
// struct ath_hal_9300 *ahp = AH9300(ah);
u_int32_t thresh;
if (enable) {
OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (!(ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_DISABLE_AGGR_THRESH))
{
thresh = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
thresh = MS(ah->ah_config.ath_hal_mci_config,
ATH_MCI_CONFIG_AGGR_THRESH);
OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
@ -119,7 +117,7 @@ static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
u_int32_t bit_position,
int32_t time_out)
{
int data, loop;
int data; //, loop;
while (time_out) {
data = OS_REG_READ(ah, address);
@ -316,7 +314,7 @@ void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah,
static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
u_int8_t opcode, u_int32_t bt_flags)
{
struct ath_hal_9300 *ahp = AH9300(ah);
// struct ath_hal_9300 *ahp = AH9300(ah);
u_int32_t pld[4] = {0, 0, 0, 0};
MCI_GPM_SET_TYPE_OPCODE(pld,
@ -410,7 +408,7 @@ void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done)
if (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) {
OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
if (!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (!(ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_DISABLE_OSLA))
{
ar9300_mci_osla_setup(ah, AH_TRUE);
@ -491,7 +489,7 @@ static void ar9300_mci_observation_set_up(struct ath_hal *ah)
OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
*/
if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_MCI)
{
ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
@ -499,7 +497,7 @@ static void ar9300_mci_observation_set_up(struct ath_hal *ah)
ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
}
else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
else if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_TXRX)
{
ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
@ -508,7 +506,7 @@ static void ar9300_mci_observation_set_up(struct ath_hal *ah)
ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
}
else if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
else if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_BT)
{
ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
@ -919,7 +917,7 @@ void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
HAL_BOOL is_full_sleep)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
u_int32_t regval;
HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
@ -964,7 +962,7 @@ void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
if (is_2g && (AR_SREV_JUPITER_20(ah) || AR_SREV_APHRODITE(ah)) &&
!(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
!(ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_DISABLE_OSLA))
{
ar9300_mci_osla_setup(ah, AH_TRUE);
@ -984,11 +982,11 @@ void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
if (ahpriv->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
u_int8_t i;
u_int32_t const *pmax_tx_pwr;
if ((ahpriv->ah_config.ath_hal_mci_config &
if ((ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
{
ahp->ah_mci_concur_tx_en = (ahp->ah_bt_coex_flag &
@ -1030,7 +1028,7 @@ void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
#endif
}
else if ((ahpriv->ah_config.ath_hal_mci_config &
else if ((ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_UNSHARED_CHN)
{
pmax_tx_pwr = &mci_concur_tx_max_pwr[0][0];
@ -1053,7 +1051,7 @@ void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
}
}
regval = MS(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config,
regval = MS(ah->ah_config.ath_hal_mci_config,
ATH_MCI_CONFIG_CLK_DIV);
OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
@ -1341,7 +1339,7 @@ ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
switch (state_type) {
case HAL_MCI_STATE_ENABLE:
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support && ahp->ah_mci_ready) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
if ((value == 0xdeadbeef) || (value == 0xffffffff)) {
// HALDEBUG(ah, HAL_DEBUG_BT_COEX,
@ -1548,7 +1546,7 @@ ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
ahp->ah_mci_coex_2g5g_update = AH_TRUE;
if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
(AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
(ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_MASK))
{
/* Check if we still have control of the GPIOs */
@ -1636,7 +1634,7 @@ ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
value = 0;
}
if (p_data != NULL) {
ahp->ah_mci_need_flush_btinfo = (*p_data != 0)?true:false;
ahp->ah_mci_need_flush_btinfo = (*p_data != 0)? AH_TRUE : AH_FALSE;
}
break;
@ -1673,17 +1671,17 @@ ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
break;
case HAL_MCI_STATE_NEED_FTP_STOMP:
value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
value = (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_DISABLE_FTP_STOMP) ? 0 : 1;
break;
case HAL_MCI_STATE_NEED_TUNING:
value = (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
value = (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_DISABLE_TUNING) ? 0 : 1;
break;
case HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX:
value = ((AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
value = ((ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_CONCUR_TX) ==
ATH_MCI_CONCUR_TX_SHARED_CHN)? 1 : 0;
break;
@ -1744,7 +1742,7 @@ void ar9300_mci_detach(struct ath_hal *ah)
void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
// struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
u_int32_t tx_priority = 0;
switch (stomp_type) {
@ -1773,7 +1771,7 @@ void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_low_tx_pri) {
tx_priority = ahp->ah_mci_stomp_low_tx_pri;
}
if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_TXRX)
{
ar9300_gpio_set(ah, 5, 1);
@ -1803,7 +1801,7 @@ void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
if (ahp->ah_mci_concur_tx_en && ahp->ah_mci_stomp_none_tx_pri) {
tx_priority = ahp->ah_mci_stomp_none_tx_pri;
}
if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_OBS_TXRX)
{
ar9300_gpio_set(ah, 5, 0);
@ -1830,7 +1828,7 @@ void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
ahp->ah_bt_coex_wlan_weight[3] |=
SM(tx_priority, MCI_CONCUR_TX_WLAN_WGHT3_MASK2);
}
if (AH_PRIVATE(ah)->ah_config.ath_hal_mci_config &
if (ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_MCI_WEIGHT_DBG)
{
HALDEBUG(ah, HAL_DEBUG_BT_COEX,
@ -1889,4 +1887,3 @@ int ar9300_mci_bt_coex_enable(struct ath_hal *ah)
}
#endif /* ATH_SUPPORT_MCI */
#endif /* AH_SUPPORT_AR9300 */

263
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
@ -59,28 +57,38 @@ ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
ahp->ah_hang_wars = *hangs;
}
/*
* XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
* HT20, HT40, fast-clock, turbo mode, etc.
*/
static u_int
ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
{
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
#if 0
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
if (chan && IS_CHAN_HT40(chan)) {
if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
return (ath_hal_mac_usec(ah, clks) / 2);
} else {
return (ath_hal_mac_usec(ah, clks));
}
#endif
return (ath_hal_mac_usec(ah, clks));
}
u_int
ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
{
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
#if 0
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
if (chan && IS_CHAN_HT40(chan)) {
if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
return (ath_hal_mac_clks(ah, usecs) * 2);
} else {
return (ath_hal_mac_clks(ah, usecs));
}
#endif
return (ath_hal_mac_clks(ah, usecs));
}
void
@ -132,13 +140,13 @@ ar9300_set_regulatory_domain(struct ath_hal *ah,
{
HAL_STATUS ecode;
if (AH_PRIVATE(ah)->ah_current_rd == 0) {
AH_PRIVATE(ah)->ah_current_rd = reg_domain;
if (AH_PRIVATE(ah)->ah_currentRD == 0) {
AH_PRIVATE(ah)->ah_currentRD = reg_domain;
return AH_TRUE;
}
ecode = HAL_EIO;
#if tbd
#if 0
bad:
#endif
if (status) {
@ -157,7 +165,7 @@ bad:
u_int
ar9300_get_wireless_modes(struct ath_hal *ah)
{
return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes;
return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
}
/*
@ -201,7 +209,7 @@ ar9300_enable_rf_kill(struct ath_hal *ah)
* Configure the desired GPIO port for input and
* enable baseband rf silence
*/
ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select);
ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
}
@ -357,12 +365,12 @@ ar9300_reset_tsf(struct ath_hal *ah)
void
ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
{
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
u_int32_t reg;
u_int8_t xset;
int i;
if (chan == AH_NULL || !IS_CHAN_CCK(chan)) {
if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
return;
}
xset = 0;
@ -515,8 +523,8 @@ ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
HAL_BOOL
ar9300_set_antenna_switch(struct ath_hal *ah,
HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask,
u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
{
struct ath_hal_9300 *ahp = AH9300(ah);
@ -603,6 +611,7 @@ HAL_STATUS
ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
u_int32_t next_start, HAL_QUIET_FLAG flag)
{
#define TU_TO_USEC(_tu) ((_tu) << 10)
HAL_STATUS status = HAL_EIO;
u_int32_t tsf = 0, j, next_start_us = 0;
if (flag & HAL_QUIET_ENABLE) {
@ -614,7 +623,7 @@ ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
}
if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
next_start_us +=
AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time;
ah->ah_config.ah_sw_beacon_response_time;
}
OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
@ -636,6 +645,7 @@ ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
}
return status;
#undef TU_TO_USEC
}
#ifdef ATH_SUPPORT_DFS
void
@ -698,9 +708,15 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return HAL_ENOTSUPP;
}
case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
/* XXX check rev when new parts are available */
return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
HAL_ENXIO : HAL_OK;
switch (capability) {
case 0: /* hardware capability */
return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
case 1: /* current setting */
return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
HAL_ENXIO : HAL_OK;
default:
return HAL_ENOTSUPP;
}
case HAL_CAP_WME_TKIPMIC:
/* hardware can do TKIP MIC when WMM is turned on */
return HAL_OK;
@ -721,7 +737,7 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case 0: /* hardware capability */
return HAL_OK;
case 1:
return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ?
return ah->ah_config.ath_hal_desc_tpc ?
HAL_OK : HAL_ENXIO;
}
return HAL_OK;
@ -748,7 +764,7 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
switch (capability) {
case 0: /* hardware capability */
return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP;
return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
case 1:
return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
HAL_OK : HAL_ENXIO;
@ -782,11 +798,12 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_RIFS_RX_ENABLED:
/* Is RIFS RX currently enabled */
return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
#if 0
case HAL_CAP_ANT_CFG_2GHZ:
*result = p_cap->hal_num_ant_cfg_2ghz;
*result = p_cap->halNumAntCfg2Ghz;
return HAL_OK;
case HAL_CAP_ANT_CFG_5GHZ:
*result = p_cap->hal_num_ant_cfg_5ghz;
*result = p_cap->halNumAntCfg5Ghz;
return HAL_OK;
case HAL_CAP_RX_STBC:
*result = p_cap->hal_rx_stbc_support;
@ -794,20 +811,21 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_TX_STBC:
*result = p_cap->hal_tx_stbc_support;
return HAL_OK;
#endif
case HAL_CAP_LDPC:
*result = p_cap->hal_ldpc_support;
*result = p_cap->halLDPCSupport;
return HAL_OK;
case HAL_CAP_DYNAMIC_SMPS:
return HAL_OK;
case HAL_CAP_DS:
return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
(p_cap->hal_tx_chain_mask & 0x3) != 0x3 ||
(p_cap->hal_rx_chain_mask & 0x3) != 0x3) ?
(p_cap->halTxChainMask & 0x3) != 0x3 ||
(p_cap->halRxChainMask & 0x3) != 0x3) ?
HAL_ENOTSUPP : HAL_OK;
case HAL_CAP_TS:
return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
(p_cap->hal_tx_chain_mask & 0x7) != 0x7 ||
(p_cap->hal_rx_chain_mask & 0x7) != 0x7) ?
(p_cap->halTxChainMask & 0x7) != 0x7 ||
(p_cap->halRxChainMask & 0x7) != 0x7) ?
HAL_ENOTSUPP : HAL_OK;
case HAL_CAP_OL_PWRCTRL:
return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
@ -815,17 +833,19 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_CRDC:
#if ATH_SUPPORT_CRDC
return (AR_SREV_WASP(ah) &&
AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ?
ah->ah_config.ath_hal_crdc_enable) ?
HAL_OK : HAL_ENOTSUPP;
#else
return HAL_ENOTSUPP;
#endif
#if 0
case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
*result = (u_int32_t)(-1);
return HAL_OK;
case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
*result = (u_int32_t)(-1);
return HAL_OK;
#endif
case HAL_CAP_BB_PANIC_WATCHDOG:
return HAL_OK;
case HAL_CAP_PHYRESTART_CLR_WAR:
@ -846,7 +866,7 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
*
* Bug fixed in AR9580/Peacock, Wasp1.1 and later
*/
if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
!AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
AR_SREV_WASP_10(ah))) {
*result |= AH_ENT_RTSCTS_DELIM_WAR;
@ -858,7 +878,7 @@ ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
*/
return HAL_OK;
case HAL_CAP_ENABLE_APM:
*result = p_cap->hal_enable_apm;
*result = p_cap->halApmEnable;
return HAL_OK;
case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
@ -905,6 +925,18 @@ ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
u_int32_t v;
switch (type) {
case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
if (! p_cap->halTkipMicTxRxKeySupport)
return AH_FALSE;
if (setting)
ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
else
ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
return AH_TRUE;
case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
if (setting) {
ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
@ -935,7 +967,7 @@ ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
return AH_TRUE;
case HAL_CAP_TPC:
AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0);
ah->ah_config.ath_hal_desc_tpc = (setting != 0);
return AH_TRUE;
case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
if (setting) {
@ -945,7 +977,7 @@ ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
}
return AH_TRUE;
case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
if (p_cap->hal_tsf_add_support) {
if (p_cap->halTsfAddSupport) {
if (setting) {
ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
} else {
@ -1158,9 +1190,11 @@ ar9300_get_diag_state(struct ath_hal *ah, int request,
return AH_TRUE;
#endif /* AH_PRIVATE_DIAG */
case HAL_DIAG_CHANNELS:
#if 0
*result = &(ahp->ah_priv.ah_channels[0]);
*resultsize =
sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
#endif
return AH_TRUE;
#ifdef AH_DEBUG
case HAL_DIAG_PRINT_REG:
@ -1185,8 +1219,11 @@ ar9300_dma_reg_dump(struct ath_hal *ah)
int qcu_offset = 0, dcu_offset = 0;
u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
int i, j, k;
int16_t nfarray[NUM_NF_READINGS];
HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah);
int16_t nfarray[HAL_NUM_NF_READINGS];
#ifdef ATH_NF_PER_CHAN
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
#endif /* ATH_NF_PER_CHAN */
HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
/* selecting DMA OBS 8 */
OS_REG_WRITE(ah, AR_MACMISC,
@ -1268,7 +1305,7 @@ ar9300_dma_reg_dump(struct ath_hal *ah)
ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
nfarray[3], nfarray[4], nfarray[5]);
for (i = 0; i < NUM_NF_READINGS; i++) {
for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
ath_hal_printf(ah, "%s Chain %d NF History:\n",
((i < 3) ? "Control " : "Extension "), i%3);
for (j = 0, k = h->base.curr_index;
@ -1490,7 +1527,7 @@ ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
* 0% (clear) -> 100% (busy)
* -1 for invalid estimate
*/
int8_t
uint32_t
ar9300_get_11n_ext_busy(struct ath_hal *ah)
{
/*
@ -1577,8 +1614,8 @@ void
ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
{
#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
u_int32_t val, idle_count;
if (idle_tmo_ms != 0) {
@ -1591,7 +1628,7 @@ ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
if (idle_tmo_ms > 10000) {
idle_tmo_ms = 10000;
}
if (chan != AH_NULL && IS_CHAN_HT40(chan)) {
if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
} else {
idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
@ -1620,7 +1657,7 @@ ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
}
HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
__func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
#undef HAL_BB_PANIC_IDLE_TIME_OUT
}
@ -1634,7 +1671,7 @@ ar9300_handle_bb_panic(struct ath_hal *ah)
* we want to avoid printing in ISR context so we save
* panic watchdog status to be printed later in DPC context
*/
AH_PRIVATE(ah)->ah_bb_panic_last_status = status =
AH9300(ah)->ah_bb_panic_last_status = status =
OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
/*
* panic watchdog timer should reset on status read
@ -1646,7 +1683,7 @@ ar9300_handle_bb_panic(struct ath_hal *ah)
int
ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
{
bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
/*
* For signature 04000539 do not print anything.
@ -1684,7 +1721,7 @@ ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
&bb_panic->rxf_pcnt,
&bb_panic->txf_pcnt);
if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) {
if (ah->ah_config.ath_hal_show_bb_panic) {
ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
"tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
@ -1711,7 +1748,7 @@ ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
void
ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
{
AH_PRIVATE(ah)->ah_reset_reason = resetreason;
AH9300(ah)->ah_reset_reason = resetreason;
}
/*
@ -1730,7 +1767,7 @@ ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
/* Configure MAC for 20/40 operation */
if (mode == HAL_HT_MACMODE_2040 &&
!AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) {
!ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
macmode = AR_2040_JOINED_RX_CLEAR;
} else {
macmode = 0;
@ -1849,7 +1886,7 @@ ar9300_ppm_force(struct ath_hal *ah)
}
if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
{
HALDEBUG(ah, HAL_DEBUG_REG_IO,
HALDEBUG(ah, HAL_DEBUG_REGIO,
"%s Correcting ppm out of range %x\n",
__func__, (data_fine & 0x7ff));
data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
@ -1928,9 +1965,13 @@ ar9300_ppm_get_force_state(struct ath_hal *ah)
/*
* Return the Cycle counts for rx_frame, rx_clear, and tx_frame
*/
void
ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts)
HAL_BOOL
ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
{
/*
* XXX FreeBSD todo: reimplement this
*/
#if 0
p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
@ -1939,6 +1980,8 @@ ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts)
p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
#endif
return AH_FALSE;
}
void
@ -1957,8 +2000,10 @@ HAL_BOOL
ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
{
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan);
u_int32_t tmp = 0;
HAL_CHANNEL_INTERNAL *ichan =
ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
u_int32_t tmp = 0;
if (enable) {
if (ahp->ah_rifs_enabled == AH_TRUE) {
@ -1982,13 +2027,13 @@ ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
(ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
if (is_chan_2g) {
if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
} else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
}
} else {
if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
} else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
@ -2175,13 +2220,14 @@ HAL_STATUS
ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
{
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
u_int16_t ant_config;
u_int32_t hal_num_ant_config;
hal_num_ant_config = IS_CHAN_2GHZ(chan) ?
p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz;
hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
if (cfg < hal_num_ant_config) {
if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
@ -2199,16 +2245,16 @@ ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
void
ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
{
AH_PRIVATE(ah)->ah_dcs_enable = mode;
AH9300(ah)->ah_dcs_enable = mode;
}
u_int32_t
ar9300_get_dcs_mode(struct ath_hal *ah)
{
return AH_PRIVATE(ah)->ah_dcs_enable;
return AH9300(ah)->ah_dcs_enable;
}
#ifdef ATH_BT_COEX
#if ATH_BT_COEX
void
ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
{
@ -2319,8 +2365,8 @@ ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
{
struct ath_hal_9300 *ahp = AH9300(ah);
#if ATH_ANT_DIV_COMB
struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan;
//struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
#endif
if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
@ -2350,8 +2396,8 @@ ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
} else {
ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
}
ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
ahpriv->ah_extra_txpow, 0);
ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
ahpriv->ah_extraTxPow, 0);
break;
case HAL_BT_COEX_ANTENNA_DIVERSITY:
@ -2373,12 +2419,12 @@ ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
else {
ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
}
ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
ahpriv->ah_extra_txpow, 0);
ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
ahpriv->ah_extraTxPow, 0);
break;
#if ATH_SUPPORT_MCI
case HAL_BT_COEX_MCI_MAX_TX_PWR:
if ((ahpriv->ah_config.ath_hal_mci_config &
if ((ah->ah_config.ath_hal_mci_config &
ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
{
if (value) {
@ -2389,8 +2435,8 @@ ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
ahp->ah_mci_concur_tx_en = AH_FALSE;
}
ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit,
ahpriv->ah_extra_txpow, 0);
ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
ahpriv->ah_extraTxPow, 0);
}
HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
ahp->ah_mci_concur_tx_en);
@ -2415,7 +2461,7 @@ ar9300_bt_coex_disable(struct ath_hal *ah)
struct ath_hal_9300 *ahp = AH9300(ah);
/* Always drive rx_clear_external output as 0 */
ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select,
ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
@ -2465,7 +2511,7 @@ ar9300_bt_coex_enable(struct ath_hal *ah)
if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
/* For 3-wire, configure the desired GPIO port for rx_clear */
ath_hal_gpio_cfg_output(ah,
ath_hal_gpioCfgOutput(ah,
ahp->ah_wlan_active_gpio_select,
HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
}
@ -2473,7 +2519,7 @@ ar9300_bt_coex_enable(struct ath_hal *ah)
(ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
{
/* For 2-wire, configure the desired GPIO port for TX_FRAME output */
ath_hal_gpio_cfg_output(ah,
ath_hal_gpioCfgOutput(ah,
ahp->ah_wlan_active_gpio_select,
HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
}
@ -2525,8 +2571,8 @@ ar9300_init_bt_coex(struct ath_hal *ah)
ahp->ah_bt_priority_gpio_select);
/* Configure the desired GPIO ports for input */
ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select);
ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
if (ahp->ah_bt_coex_enabled) {
ar9300_bt_coex_enable(ah);
@ -2558,7 +2604,7 @@ ar9300_init_bt_coex(struct ath_hal *ah)
ahp->ah_bt_active_gpio_select);
/* Configure the desired GPIO ports for input */
ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select);
ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
/* Enable coexistence on initialization */
ar9300_bt_coex_enable(ah);
@ -2647,6 +2693,7 @@ HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
return HAL_OK;
}
#if 0
void ar9300_mat_enable(struct ath_hal *ah, int enable)
{
/*
@ -2675,16 +2722,16 @@ void ar9300_mat_enable(struct ath_hal *ah, int enable)
OS_REG_WRITE(ah, AR_RIMT, 0);
}
ap->ah_enable_keysearch_always = !!enable;
ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always);
ahp->ah_enable_keysearch_always = !!enable;
ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
}
#endif
void ar9300_enable_tpc(struct ath_hal *ah)
{
u_int32_t val = 0;
AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1;
ah->ah_config.ath_hal_desc_tpc = 1;
/* Enable TPC */
OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
@ -2730,11 +2777,11 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
int8_t tmp_rss1_thr1, tmp_rss1_thr2;
if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
!AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) {
!ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
return;
}
old_greentx_status = AH_PRIVATE(ah)->green_tx_status;
old_greentx_status = AH9300(ah)->green_tx_status;
if (ahp->ah_hw_green_tx_enable) {
tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
@ -2743,35 +2790,35 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
}
if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
&& (rssi > tmp_rss1_thr1))
{
if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
}
} else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
} else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
&& (rssi > tmp_rss1_thr2))
{
if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
}
} else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
} else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
}
}
/* If status is not change, don't do anything */
if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) {
if (old_greentx_status == AH9300(ah)->green_tx_status) {
return;
}
/* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
&& AR_SREV_POSEIDON(ah))
{
if (ahp->ah_hw_green_tx_enable) {
switch (AH_PRIVATE(ah)->green_tx_status) {
switch (AH9300(ah)->green_tx_status) {
case HAL_RSSI_TX_POWER_SHORT:
/* 1. TxPower Config */
OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
@ -2814,14 +2861,14 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
/* 2. Store OB/DB1/DB2 */
/* 3. Store TPC settting */
temp_tcp_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
/* 4. Store BB_powertx_rate9 value */
temp_powertx_rate9_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
break;
}
} else {
switch (AH_PRIVATE(ah)->green_tx_status) {
switch (AH9300(ah)->green_tx_status) {
case HAL_RSSI_TX_POWER_SHORT:
/* 1. TxPower Config */
OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
@ -2832,7 +2879,7 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
/* 2. Store OB/DB */
temp_obdb_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
@ -2863,7 +2910,7 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
/* 2. Store OB/DB */
temp_obdb_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
@ -2895,19 +2942,19 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
/* 2. Store OB/DB1/DB2 */
temp_obdb_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
/* 3. Store TPC settting */
temp_tcp_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
/* 4. Store BB_powertx_rate9 value */
temp_powertx_rate9_reg_val =
AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
break;
}
}
/* 1.1 Do OLPC Delta Calibration Offset */
tmp_olpc_val =
(int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
(int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
tmp_olpc_val += olpc_power_offset;
OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
(tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
@ -2926,6 +2973,7 @@ void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
}
}
#if 0
void
ar9300_get_vow_stats(
struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
@ -2946,19 +2994,21 @@ ar9300_get_vow_stats(
p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
}
}
#endif
/*
* ar9300_is_skip_paprd_by_greentx
*
* This function check if we need to skip PAPRD tuning
* when GreenTx in specific state.
*/
HAL_BOOL
HAL_BOOL
ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
{
if (AR_SREV_POSEIDON(ah) &&
AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable &&
((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
(AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
(AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
{
return AH_TRUE;
}
@ -3058,7 +3108,7 @@ ar9300_print_keycache(struct ath_hal *ah)
ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) {
for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
@ -3108,7 +3158,8 @@ ar9300_print_keycache(struct ath_hal *ah)
}
/* enable/disable smart antenna mode */
HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
HAL_BOOL
ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
{
struct ath_hal_9300 *ahp = AH9300(ah);
@ -3137,7 +3188,7 @@ HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
#ifdef ATH_TX99_DIAG
#ifndef ATH_SUPPORT_HTC
void
void
ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
u_int32_t txpower)
{
@ -3710,5 +3761,3 @@ ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
{
return AH_FALSE;
}
#endif /* AH_SUPPORT_AR9300 */

56
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_paprd.c
View file

@ -47,12 +47,11 @@ HAL_BOOL create_pa_curve(u_int32_t * paprd_train_data_l,
u_int32_t *paprd_train_data_u, u_int32_t *pa_table, u_int32_t *g_fxp_ext,
int * pa_in);
#define AR9300_IS_CHAN(_c, _f) (((_c)->channel_flags & _f) || 0)
static int
ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan)
ar9300_paprd_setup_single_table(struct ath_hal *ah, struct ieee80211_channel * chan)
{
int is_2g = AR9300_IS_CHAN(chan, CHANNEL_2GHZ);
int is_2g = IEEE80211_IS_CHAN_2GHZ(chan);
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
struct ath_hal_9300 *ahp = AH9300(ah);
int is_ht40 = 0;
u_int32_t am_mask = 0;
@ -76,7 +75,7 @@ ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan)
#define ABS(_x, _y) ((int)_x > (int)_y ? (int)_x - (int)_y : (int)_y - (int)_x)
ar9300_set_target_power_from_eeprom(ah, chan->channel, target_power_val_t2);
ar9300_set_target_power_from_eeprom(ah, ichan->channel, target_power_val_t2);
if (val & HAL_HT_MACMODE_2040) {
is_ht40 = 1;
}
@ -94,7 +93,7 @@ ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan)
* For 2G there is only one scale factor. It is saved in bits 25-27 of
* modal_header_2g.paprd_rate_mask_ht20.
*/
AH_PAPRD_GET_SCALE_FACTOR(paprd_scale_factor, eep, is_2g, chan->channel);
AH_PAPRD_GET_SCALE_FACTOR(paprd_scale_factor, eep, is_2g, ichan->channel);
if (is_2g) {
if (is_ht40) {
am_mask = ahp->ah_2g_paprd_rate_mask_ht40 & AH_PAPRD_AM_PM_MASK;
@ -122,7 +121,7 @@ ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan)
{
HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
"%s[%d]: Chan %d paprd failing EEP PWR 0x%08x"
"TGT PWR 0x%08x\n", __func__, __LINE__, chan->channel,
"TGT PWR 0x%08x\n", __func__, __LINE__, ichan->channel,
target_power_val_t2[power_tblindex],
ahp->paprd_training_power);
goto FAILED;
@ -193,7 +192,7 @@ ar9300_paprd_setup_single_table(struct ath_hal *ah, HAL_CHANNEL * chan)
{
HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
"%s[%d]: Chan %d paprd failing EEP PWR 0x%08x TGT PWR 0x%08x\n",
__func__, __LINE__, chan->channel,
__func__, __LINE__, ichan->channel,
target_power_val_t2[power_tblindex], ahp->paprd_training_power);
goto FAILED;
}
@ -405,6 +404,10 @@ FAILED:
#undef ABS
}
/*
* XXX There's another copy of this in ar9300_reset.c, use that!
*/
#if 0
static inline HAL_CHANNEL_INTERNAL*
ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan)
{
@ -432,14 +435,16 @@ ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan)
return (ath_hal_checkchannel(ah, chan));
}
#endif
void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag,
HAL_CHANNEL * chan)
struct ieee80211_channel * chan)
{
HAL_BOOL enable = enable_flag;
u_int32_t am_mask = 0;
u_int32_t val = OS_REG_READ(ah, AR_2040_MODE);
int is_2g = AR9300_IS_CHAN(chan, CHANNEL_2GHZ);
int is_2g = IEEE80211_IS_CHAN_2GHZ(chan);
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int is_ht40 = 0;
struct ath_hal_9300 *ahp = AH9300(ah);
@ -462,11 +467,11 @@ void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag,
* to one -- disable paprd for lower 5G
* u_int32_t am_mask = eep->modal_header_5g.paprd_rate_mask_ht20;
*/
if (chan->channel >= UPPER_5G_SUB_BANDSTART) {
if (ichan->channel >= UPPER_5G_SUB_BANDSTART) {
if (eep->modal_header_5g.paprd_rate_mask_ht20 & (1 << 30)) {
enable = AH_FALSE;
}
} else if (chan->channel >= MID_5G_SUB_BANDSTART) {
} else if (ichan->channel >= MID_5G_SUB_BANDSTART) {
if (eep->modal_header_5g.paprd_rate_mask_ht20 & (1 << 29)) {
enable = AH_FALSE;
}
@ -509,17 +514,17 @@ void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag,
*/
ichan = ar9300_check_chan(ah, chan);
ichan->paprd_table_write_done = 1;
chan->paprd_table_write_done = 1;
// chan->paprd_table_write_done = 1;
/*
ath_hal_printf(ah, "%s[%d] eeprom_set_transmit_power PAPRD\n",
__func__, __LINE__);
*/
if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, ichan,
if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan),
AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_power_limit)) != HAL_OK) {
AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit)) != HAL_OK) {
ichan->paprd_table_write_done = 0;
chan->paprd_table_write_done = 0;
// chan->paprd_table_write_done = 0;
/* Intentional print */
ath_hal_printf(ah,
"%s[%d] eeprom_set_transmit_power failed ABORT PAPRD\n",
@ -1848,17 +1853,20 @@ void ar9300_swizzle_paprd_entries(struct ath_hal *ah, unsigned int txchain)
}
void ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL * chan,
int chain_num)
void ar9300_populate_paprd_single_table(struct ath_hal *ah,
struct ieee80211_channel *chan, int chain_num)
{
int i, j, bad_read = 0;
#ifdef AH_DEBUG
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
#endif
u_int32_t *paprd_table_val = &AH9300(ah)->pa_table[chain_num][0];
u_int32_t small_signal_gain = AH9300(ah)->small_signal_gain[chain_num];
u_int32_t reg = 0;
HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
"%s[%d]: channel %d paprd_done %d write %d\n", __func__, __LINE__,
chan->channel, chan->paprd_done, chan->paprd_table_write_done);
ichan->channel, ichan->paprd_done, ichan->paprd_table_write_done);
if (chain_num == 0) {
reg = AR_PHY_PAPRD_MEM_TAB_B0;
@ -2180,8 +2188,8 @@ static HAL_BOOL ar9300_paprd_retrain_pain(struct ath_hal * ah, int * pa_in)
return AH_FALSE;
}
HAL_STATUS ar9300_paprd_create_curve(struct ath_hal * ah, HAL_CHANNEL * chan,
int chain_num)
HAL_STATUS ar9300_paprd_create_curve(struct ath_hal * ah,
struct ieee80211_channel * chan, int chain_num)
{
int status = 0;
u_int32_t *pa_table, small_signal_gain;
@ -2214,9 +2222,11 @@ HAL_STATUS ar9300_paprd_create_curve(struct ath_hal * ah, HAL_CHANNEL * chan,
return HAL_OK;
}
int ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL * chan)
int ar9300_paprd_init_table(struct ath_hal *ah, struct ieee80211_channel * chan)
{
if ((AR_SREV_WASP(ah) && IS_CHAN_5GHZ(chan)) ||
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
if ((AR_SREV_WASP(ah) && IS_CHAN_5GHZ(ichan)) ||
ar9300_paprd_setup_single_table(ah, chan)) {
goto FAIL;
}

67
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -161,8 +159,8 @@ HAL_RATE_TABLE ar9300_11g_table = {
/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80 | 11), 2 },
/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80 | 22), 3 },
/* Hardware workaround - remove rates 6, 9 from rate ctrl */
/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
/* 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
/* 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 },
/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 },
/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 },
@ -172,6 +170,7 @@ HAL_RATE_TABLE ar9300_11g_table = {
},
};
#if 0
HAL_RATE_TABLE ar9300_xr_table = {
13, /* number of rates */
{ 0 },
@ -193,6 +192,7 @@ HAL_RATE_TABLE ar9300_xr_table = {
/* 54 Mb */ {AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8, 44, 44 },
},
};
#endif
#define AR9300_11NG_RT_OFDM_OFFSET 4
#define AR9300_11NG_RT_HT_SS_OFFSET 12
@ -210,8 +210,8 @@ HAL_RATE_TABLE ar9300_11ng_table = {
/* 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80 | 11), 2 },
/* 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80 | 22), 3 },
/* Hardware workaround - remove rates 6, 9 from rate ctrl */
/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
/* 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 },
/* 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 },
/* 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 },
/* 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 },
/* 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 },
@ -316,13 +316,13 @@ ar9300_get_rate_table(struct ath_hal *ah, u_int mode)
rt = &ar9300_11a_table;
break;
case HAL_MODE_11A_HALF_RATE:
if (p_cap->hal_chan_half_rate) {
if (p_cap->halChanHalfRate) {
rt = &ar9300_11a_half_table;
break;
}
return AH_NULL;
case HAL_MODE_11A_QUARTER_RATE:
if (p_cap->hal_chan_quarter_rate) {
if (p_cap->halChanQuarterRate) {
rt = &ar9300_11a_quarter_table;
break;
}
@ -337,9 +337,11 @@ ar9300_get_rate_table(struct ath_hal *ah, u_int mode)
case HAL_MODE_108G:
rt = &ar9300_turbo_table;
break;
#if 0
case HAL_MODE_XR:
rt = &ar9300_xr_table;
break;
#endif
case HAL_MODE_11NG_HT20:
case HAL_MODE_11NG_HT40PLUS:
case HAL_MODE_11NG_HT40MINUS:
@ -388,7 +390,6 @@ ar9300_invalid_stbc_cfg(int tx_chains, u_int8_t rate_code)
return AH_TRUE;
}
int16_t
ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, u_int8_t rate_index,
u_int8_t chainmask, u_int8_t xmit_mode)
@ -503,11 +504,11 @@ ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah,
extern void
ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode,
HAL_CHANNEL_INTERNAL *chan,
const struct ieee80211_channel *chan,
u_int8_t power_per_rate[], u_int8_t chainmask)
{
const HAL_RATE_TABLE *rt;
HAL_BOOL is40 = IS_CHAN_HT40(chan);
HAL_BOOL is40 = IEEE80211_IS_CHAN_HT40(chan);
rt = ar9300_get_rate_table(ah, mode);
HALASSERT(rt != NULL);
@ -531,7 +532,7 @@ ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode,
AR9300_11NA_RT_HT_DS_OFFSET,
AR9300_11NA_RT_HT_TS_OFFSET, chainmask);
/* For FCC the array gain has to be factored for CDD mode */
if (is_reg_dmn_fcc(chan->conformance_test_limit)) {
if (is_reg_dmn_fcc(ath_hal_getctl(ah, chan))) {
ar9300_adjust_rate_txpower_cdd(ah, rt, is40,
AR9300_11NA_RT_HT_SS_OFFSET,
AR9300_11NA_RT_HT_DS_OFFSET,
@ -561,7 +562,7 @@ ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode,
AR9300_11NG_RT_HT_DS_OFFSET,
AR9300_11NG_RT_HT_TS_OFFSET, chainmask);
/* For FCC the array gain needs to be factored for CDD mode */
if (is_reg_dmn_fcc(chan->conformance_test_limit)) {
if (is_reg_dmn_fcc(ath_hal_getctl(ah, chan))) {
ar9300_adjust_rate_txpower_cdd(ah, rt, is40,
AR9300_11NG_RT_HT_SS_OFFSET,
AR9300_11NG_RT_HT_DS_OFFSET,
@ -828,7 +829,6 @@ ar9300_init_rate_txpower_ht(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
}
}
static inline void
ar9300_init_rate_txpower_stbc(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
HAL_BOOL is40,
@ -1041,13 +1041,13 @@ ar9300_adjust_rate_txpower_cdd(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
void ar9300_disp_tpc_tables(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
u_int mode = ath_hal_get_curmode(ah, chan);
const HAL_RATE_TABLE *rt;
int i, j;
/* Check whether TPC is enabled */
if (!AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) {
if (!ah->ah_config.ath_hal_desc_tpc) {
ath_hal_printf(ah, "\n TPC Register method in use\n");
return;
}
@ -1062,13 +1062,12 @@ void ar9300_disp_tpc_tables(struct ath_hal *ah)
txpower[j] = ahp->txpower[i][j];
ath_hal_printf(ah, " Index[%2d] Rate[0x%02x] %6d kbps "
"Power (%d Chain) [%2d.%1d dBm]\n",
i, rt->info[i].rate_code, rt->info[i].rateKbps,
i, rt->info[i].rateCode, rt->info[i].rateKbps,
j + 1, txpower[j] / 2, txpower[j]%2 * 5);
}
}
ath_hal_printf(ah, "\n");
ath_hal_printf(ah, "\n\n===TARGET POWER TABLE with STBC===\n");
for ( j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) {
for (i = 0; i < rt->rateCount; i++) {
@ -1076,15 +1075,15 @@ void ar9300_disp_tpc_tables(struct ath_hal *ah)
txpower[j] = ahp->txpower_stbc[i][j];
/* Do not display invalid configurations */
if ((rt->info[i].rate_code < AR9300_MCS0_RATE_CODE) ||
(rt->info[i].rate_code > AR9300_MCS23_RATE_CODE) ||
ar9300_invalid_stbc_cfg(j, rt->info[i].rate_code) == AH_TRUE) {
if ((rt->info[i].rateCode < AR9300_MCS0_RATE_CODE) ||
(rt->info[i].rateCode > AR9300_MCS23_RATE_CODE) ||
ar9300_invalid_stbc_cfg(j, rt->info[i].rateCode) == AH_TRUE) {
continue;
}
ath_hal_printf(ah, " Index[%2d] Rate[0x%02x] %6d kbps "
"Power (%d Chain) [%2d.%1d dBm]\n",
i, rt->info[i].rate_code, rt->info[i].rateKbps,
i, rt->info[i].rateCode , rt->info[i].rateKbps,
j + 1, txpower[j] / 2, txpower[j]%2 * 5);
}
}
@ -1113,7 +1112,7 @@ struct rate_power_tbl {
u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
u_int mode = ath_hal_get_curmode(ah, chan);
const HAL_RATE_TABLE *rt;
u_int8_t *data;
@ -1121,15 +1120,15 @@ u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah)
int i, j;
/* Check whether TPC is enabled */
if (!AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc) {
if (! ah->ah_config.ath_hal_desc_tpc) {
ath_hal_printf(ah, "\n TPC Register method in use\n");
return NULL;
}
rt = ar9300_get_rate_table(ah, mode);
rt = (const HAL_RATE_TABLE *)ar9300_get_rate_table(ah, mode);
HALASSERT(rt != NULL);
data = (u_int8_t *)ath_hal_malloc(ah,
data = (u_int8_t *)ath_hal_malloc(
1 + rt->rateCount * sizeof(struct rate_power_tbl));
if (data == NULL)
return NULL;
@ -1142,14 +1141,14 @@ u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah)
for (j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) {
for (i = 0; i < rt->rateCount; i++) {
table[i].rateIdx = i;
table[i].rateCode = rt->info[i].rate_code;
table[i].rateCode = rt->info[i].rateCode;
table[i].rateKbps = rt->info[i].rateKbps;
switch (j) {
case 0:
table[i].chain1 = rt->info[i].rate_code <= 0x87 ? 1 : 0;
table[i].chain1 = rt->info[i].rateCode <= 0x87 ? 1 : 0;
break;
case 1:
table[i].chain2 = rt->info[i].rate_code <= 0x8f ? 1 : 0;
table[i].chain2 = rt->info[i].rateCode <= 0x8f ? 1 : 0;
break;
case 2:
table[i].chain3 = 1;
@ -1164,13 +1163,12 @@ u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah)
}
}
for ( j = 0 ; j < ar9300_get_ntxchains(ahp->ah_tx_chainmask) ; j++ ) {
for (i = 0; i < rt->rateCount; i++) {
/* Do not display invalid configurations */
if ((rt->info[i].rate_code < AR9300_MCS0_RATE_CODE) ||
(rt->info[i].rate_code > AR9300_MCS23_RATE_CODE) ||
ar9300_invalid_stbc_cfg(j, rt->info[i].rate_code) == AH_TRUE) {
if ((rt->info[i].rateCode < AR9300_MCS0_RATE_CODE) ||
(rt->info[i].rateCode > AR9300_MCS23_RATE_CODE) ||
ar9300_invalid_stbc_cfg(j, rt->info[i].rateCode) == AH_TRUE) {
continue;
}
@ -1190,7 +1188,7 @@ ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, u_int16_t freq,
/*
* Used for AR9300 series chip only
*/
if (AH_PRIVATE(ah)->ah_magic == AR9300_MAGIC) {
if (ah->ah_magic == AR9300_MAGIC) {
u_int8_t target_rate_power_limit_val_t2[ar9300_rate_size];
int i;
@ -1212,4 +1210,3 @@ ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, u_int16_t freq,
return HAL_OK;
}
#endif /* AH_SUPPORT_AR9300 */

25
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -603,7 +601,7 @@ ar9300_set_power_mode_network_sleep(struct ath_hal *ah, int set_chip)
if (set_chip) {
HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
if (! p_cap->hal_auto_sleep_support) {
if (! p_cap->halAutoSleepSupport) {
/* Set wake_on_interrupt bit; clear force_wake bit */
OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
}
@ -655,7 +653,7 @@ HAL_BOOL
ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip)
{
struct ath_hal_9300 *ahp = AH9300(ah);
#if AH_DEBUG || AH_PRINT_FILTER
#if defined(AH_DEBUG) || defined(AH_PRINT_FILTER)
static const char* modes[] = {
"AWAKE",
"FULL-SLEEP",
@ -673,14 +671,14 @@ ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip)
case HAL_PM_AWAKE:
status = ar9300_set_power_mode_awake(ah, set_chip);
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
break;
case HAL_PM_FULL_SLEEP:
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) {
if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) &&
(ahp->ah_mci_bt_state != MCI_BT_SLEEP) &&
@ -695,7 +693,7 @@ ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip)
}
#endif
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
@ -704,7 +702,7 @@ ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip)
break;
case HAL_PM_NETWORK_SLEEP:
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
@ -992,7 +990,7 @@ ar9300_set_power_mode_wow_sleep(struct ath_hal *ah)
"%s: TODO How to disable RXDP!!\n", __func__);
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
@ -1051,7 +1049,7 @@ ar9300_wow_enable(
* PCI-E reset. We also need to tie the PCI-E Phy reset to the PCI-E
* reset.
*/
HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
HAL_DEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
"%s: Untie POR and PCIE reset\n", __func__);
wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA));
wa_reg_val = wa_reg_val & ~(AR_WA_UNTIE_RESET_EN);
@ -1361,7 +1359,6 @@ ar9300_wow_enable(
OS_REG_WRITE(ah, AR_STA_ID1,
OS_REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_PRESERVE_SEQNUM);
AH_PRIVATE(ah)->ah_wow_event_mask = wow_event_mask;
#if ATH_WOW_OFFLOAD
@ -1369,7 +1366,7 @@ ar9300_wow_enable(
/* Force MAC awake before entering SW WoW mode */
OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
@ -1396,7 +1393,7 @@ ar9300_wow_enable(
#endif /* ATH_WOW_OFFLOAD */
{
#if ATH_SUPPORT_MCI
if (AH_PRIVATE(ah)->ah_caps.hal_mci_support) {
if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
}
#endif
@ -1555,5 +1552,3 @@ ar9300_wow_set_gpio_reset_low(struct ath_hal *ah)
/* val = OS_REG_READ(ah,AR_GPIO_IN_OUT ); */
}
#endif /* ATH_WOW */
#endif /* AH_SUPPORT_AR9300 */

76
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c
View file

@ -17,8 +17,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_desc.h"
#include "ah_internal.h"
@ -39,9 +37,11 @@
#define AR9300_DFS_RELPWR 8
#define AR9300_DFS_RELSTEP 12
#define AR9300_DFS_MAXLEN 255
#define AR9300_DFS_PRSSI_CAC 10
#ifdef ATH_SUPPORT_DFS
/*
* This PRSSI value should be used during CAC.
*/
#define AR9300_DFS_PRSSI_CAC 10
/*
* make sure that value matches value in ar9300_osprey_2p2_mac_core[][2]
@ -125,13 +125,14 @@ struct dfs_bin5pulse ar9300_bin5pulses[] = {
};
#if 0
/*
* Find the internal HAL channel corresponding to the
* public HAL channel specified in c
*/
static HAL_CHANNEL_INTERNAL *
getchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
getchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
{
#define CHAN_FLAGS (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)
HAL_CHANNEL_INTERNAL *base, *cc;
@ -180,7 +181,7 @@ getchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
* mark the channel as clear and reset the internal tsf time
*/
void
ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan)
ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan)
{
HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
@ -203,7 +204,7 @@ ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan)
* be increased
*/
void
ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, u_int64_t nol_time)
ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nol_time)
{
HAL_CHANNEL_INTERNAL *ichan;
@ -218,6 +219,7 @@ ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, u_int64_t nol_time)
ichan->priv_flags |= CHANNEL_INTERFERENCE;
chan->priv_flags |= CHANNEL_INTERFERENCE;
}
#endif
/*
* Enable radar detection and set the radar parameters per the
@ -228,7 +230,7 @@ ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
u_int32_t val;
struct ath_hal_private *ahp = AH_PRIVATE(ah);
HAL_CHANNEL_INTERNAL *ichan = ahp->ah_curchan;
const struct ieee80211_channel *chan = ahp->ah_curchan;
struct ath_hal_9300 *ah9300 = AH9300(ah);
int reg_writes = 0;
@ -249,11 +251,13 @@ ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_PRSSI;
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
#if 0
if (ah->ah_use_cac_prssi) {
val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
} else {
#endif
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
// }
} else {
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
@ -282,7 +286,7 @@ ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) {
val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
if (IS_CHAN_HT40(ichan)) {
if (IEEE80211_IS_CHAN_HT40(chan)) {
/* Enable extension channel radar detection */
OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA);
} else {
@ -296,12 +300,12 @@ ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
*/
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) {
REG_WRITE_ARRAY(&ah9300->ah_ini_dfs,IS_CHAN_HT40(ichan)? 2:1, reg_writes);
REG_WRITE_ARRAY(&ah9300->ah_ini_dfs, IEEE80211_IS_CHAN_HT40(chan)? 2:1, reg_writes);
}
#ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128
HALDEBUG(ah, HAL_DEBUG_DFS,"DFS change the timing value\n");
if (AR_SREV_AR9580(ah) && IS_CHAN_HT40(ichan)) {
OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
ath_hal_printf(ah, "DFS change the timing value\n");
if (AR_SREV_AR9580(ah) && IEEE80211_IS_CHAN_HT40(chan)) {
OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
}
#endif
@ -328,18 +332,17 @@ ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH);
if (val & AR_PHY_RADAR_1_RELPWR_ENA) {
pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE;
}
pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_1_RELPWR_ENA);
pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH);
if (val & AR_PHY_RADAR_1_RELSTEP_CHECK) {
pe->pe_relstep |= HAL_PHYERR_PARAM_ENABLE;
}
pe->pe_en_relstep_check = !! (val & AR_PHY_RADAR_1_RELSTEP_CHECK);
pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN);
}
#if 0
HAL_BOOL
ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan)
ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan)
{
struct ath_hal_private *ahp = AH_PRIVATE(ah);
@ -360,6 +363,7 @@ ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan)
return AH_FALSE;
}
#endif
struct dfs_pulse *
ar9300_get_dfs_radars(
@ -372,7 +376,7 @@ ar9300_get_dfs_radars(
{
struct dfs_pulse *dfs_radars = AH_NULL;
switch (dfsdomain) {
case DFS_FCC_DOMAIN:
case HAL_DFS_FCC_DOMAIN:
dfs_radars = &ar9300_fcc_radars[AR9300_FCC_RADARS_FCC_OFFSET];
*numradars =
ARRAY_LENGTH(ar9300_fcc_radars) - AR9300_FCC_RADARS_FCC_OFFSET;
@ -380,14 +384,14 @@ ar9300_get_dfs_radars(
*numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__);
break;
case DFS_ETSI_DOMAIN:
case HAL_DFS_ETSI_DOMAIN:
dfs_radars = &ar9300_etsi_radars[0];
*numradars = ARRAY_LENGTH(ar9300_etsi_radars);
*bin5pulses = &ar9300_bin5pulses[0];
*numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__);
break;
case DFS_MKK4_DOMAIN:
case HAL_DFS_MKK4_DOMAIN:
dfs_radars = &ar9300_fcc_radars[0];
*numradars = ARRAY_LENGTH(ar9300_fcc_radars);
*bin5pulses = &ar9300_bin5pulses[0];
@ -412,7 +416,7 @@ ar9300_get_dfs_radars(
We use this flag to keep track of change in PRSSI.
*/
ah->ah_use_cac_prssi = 0;
// ah->ah_use_cac_prssi = 0;
pe->pe_inband = AR9300_DFS_INBAND;
pe->pe_relpwr = AR9300_DFS_RELPWR;
@ -434,7 +438,7 @@ void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val)
HAL_TX_QUEUE_INFO *qi;
int q;
ah->ah_fccaifs = 0;
AH9300(ah)->ah_fccaifs = 0;
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__);
for (q = 0; q < 4; q++) {
qi = &ahp->ah_txq[q];
@ -449,7 +453,7 @@ void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val)
* FCC domain. They are yet to be determined for other domains.
*/
ah->ah_fccaifs = 1;
AH9300(ah)->ah_fccaifs = 1;
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__);
/*printk("%s: modify DIFS\n", __func__);*/
@ -495,12 +499,12 @@ ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start)
val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
ah->ah_use_cac_prssi = start;
// ah->ah_use_cac_prssi = start;
}
}
#endif /* ATH_SUPPORT_DFS */
HAL_CHANNEL *
#if 0
struct ieee80211_channel *
ar9300_get_extension_channel(struct ath_hal *ah)
{
struct ath_hal_private *ahp = AH_PRIVATE(ah);
@ -518,12 +522,12 @@ ar9300_get_extension_channel(struct ath_hal *ah)
for (i = 0; i < ahp->ah_nchan; i++) {
ichan = &aht->ah_channels[i];
if (ichan->channel == centers.ext_center) {
return (HAL_CHANNEL*)ichan;
return (struct ieee80211_channel*)ichan;
}
}
return AH_NULL;
}
#endif
HAL_BOOL
ar9300_is_fast_clock_enabled(struct ath_hal *ah)
@ -536,6 +540,11 @@ ar9300_is_fast_clock_enabled(struct ath_hal *ah)
return AH_FALSE;
}
/*
* This should be enabled and linked into the build once
* radar support is enabled.
*/
#if 0
HAL_BOOL
ar9300_handle_radar_bb_panic(struct ath_hal *ah)
{
@ -583,11 +592,10 @@ ar9300_handle_radar_bb_panic(struct ath_hal *ah)
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n",
__func__, status, ahp->ah_rifs_enabled);
#endif
ar9300_set_rifs_delay(ah, AH_FALSE);
}
return AH_FALSE;
}
}
#endif
#endif

43
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -81,15 +79,20 @@ static const u_int32_t ar9300_chansel_xtal_40M[] = {
* (freq_ref = 40MHz)
*/
static HAL_BOOL
ar9300_set_channel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
ar9300_set_channel(struct ath_hal *ah, struct ieee80211_channel *chan)
{
u_int16_t b_mode, frac_mode = 0, a_mode_ref_sel = 0;
u_int32_t freq, channel_sel, reg32;
u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz;
CHAN_CENTERS centers;
int load_synth_channel;
#ifdef AH_DEBUG
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
#endif
OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
#ifdef AH_DEBUG
OS_MARK(ah, AH_MARK_SETCHANNEL, ichan->channel);
#endif
ar9300_get_channel_centers(ah, chan, &centers);
freq = centers.synth_center;
@ -99,13 +102,25 @@ ar9300_set_channel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
b_mode = 1; /* 2 GHz */
if (AR_SREV_HORNET(ah)) {
u_int32_t ichan = ath_hal_mhz2ieee(ah, freq, chan->channel_flags);
/*
* XXX TODO: this should call ieee80211_mhz2ieee which will
* take care of the up/down conversion and GSM mapping.
* However, the HAL _can't_ call that, so we'll need to
* introduce it in ah_osdep or something.
*/
#if 0
u_int32_t ichan =
ieee80211_mhz2ieee(ah, chan->ic_freq, chan->ic_flags);
HALASSERT(ichan > 0 && ichan <= 14);
if (clk_25mhz) {
channel_sel = ar9300_chansel_xtal_25M[ichan - 1];
} else {
channel_sel = ar9300_chansel_xtal_40M[ichan - 1];
}
#else
ath_hal_printf(ah, "%s: unimplemented, implement!\n", __func__);
return AH_FALSE;
#endif
} else if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
u_int32_t channel_frac;
/*
@ -193,7 +208,7 @@ ar9300_set_channel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
(a_mode_ref_sel << 28) |
(frac_mode << 30) |
(load_synth_channel << 31);
if (IS_CHAN_QUARTER_RATE(chan)) {
if (IEEE80211_IS_CHAN_QUARTER(chan)) {
reg32 += CHANSEL_5G_DOT5MHZ;
}
OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
@ -209,6 +224,7 @@ ar9300_set_channel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
}
#if 0
static HAL_BOOL
ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans,
u_int32_t nchans)
@ -221,6 +237,19 @@ ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans,
}
return AH_TRUE;
}
#endif
/* XXX FreeBSD */
static HAL_BOOL
ar9300_get_chip_power_limits(struct ath_hal *ah,
struct ieee80211_channel *chan)
{
/* XXX ? */
chan->ic_minpower = 0;
chan->ic_maxpower = AR9300_MAX_RATE_POWER;
return AH_TRUE;
}
HAL_BOOL
ar9300_rf_attach(struct ath_hal *ah, HAL_STATUS *status)
@ -234,5 +263,3 @@ ar9300_rf_attach(struct ath_hal *ah, HAL_STATUS *status)
return AH_TRUE;
}
#endif /* AH_SUPPORT_AR9300 */

12
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_desc.h"
#include "ah_internal.h"
@ -73,15 +71,15 @@ ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL set)
/* Set the force_rx_abort bit */
OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
if ( AH_PRIVATE(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){
if ( AH9300(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){
/* depending upon the BB panic status, rx state may not return to 0,
* so skipping the wait for BB panic reset */
OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
return AH_FALSE;
return AH_FALSE;
} else {
HAL_BOOL okay;
okay = ath_hal_wait(
ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0, AH_WAIT_TIMEOUT);
ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0);
/* Wait for Rx state to return to 0 */
if (!okay) {
/* abort: chip rx failed to go idle in 10 ms */
@ -126,7 +124,7 @@ ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout)
(AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
okay = ath_hal_wait(
ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0, AH_WAIT_TIMEOUT);
ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0);
/* wait for Rx DMA state machine to become idle */
if (!okay) {
HALDEBUG(ah, HAL_DEBUG_RX,
@ -337,5 +335,3 @@ ar9300_write_pktlog_reg(
enable, rxfilter_val, rxcfg_val,
phy_err_mask_val, mac_pcu_phy_err_reg_val);
}
#endif /* AH_SUPPORT_AR9300 */

32
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv_ds.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_desc.h"
#include "ah_internal.h"
@ -27,7 +25,6 @@
#include "ar9300/ar9300desc.h"
/*
* Process an RX descriptor, and return the status to the caller.
* Copy some hardware specific items into the software portion
@ -77,12 +74,12 @@ ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *ds,
/* XXX what about key_cache_miss? */
rxs->rs_rssi = MS(rxsp->status5, AR_rx_rssi_combined);
rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_rx_rssi_ant00);
rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_rx_rssi_ant01);
rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_rx_rssi_ant02);
rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_rx_rssi_ant10);
rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_rx_rssi_ant11);
rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_rx_rssi_ant12);
rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_rx_rssi_ant00);
rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_rx_rssi_ant01);
rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_rx_rssi_ant02);
rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_rx_rssi_ant10);
rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_rx_rssi_ant11);
rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_rx_rssi_ant12);
if (rxsp->status11 & AR_rx_key_idx_valid) {
rxs->rs_keyix = MS(rxsp->status11, AR_key_idx);
} else {
@ -95,16 +92,16 @@ ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *ds,
rxs->rs_isaggr = (rxsp->status11 & AR_rx_aggr) ? 1 : 0;
rxs->rs_moreaggr = (rxsp->status11 & AR_rx_more_aggr) ? 1 : 0;
rxs->rs_antenna = (MS(rxsp->status4, AR_rx_antenna) & 0x7);
rxs->rs_isapsd = (rxsp->status11 & AR_apsd_trig) ? 1 : 0;
rxs->rs_flags = (rxsp->status4 & AR_gi) ? HAL_RX_GI : 0;
rxs->rs_flags = (rxsp->status11 & AR_apsd_trig) ? HAL_RX_IS_APSD : 0;
rxs->rs_flags |= (rxsp->status4 & AR_gi) ? HAL_RX_GI : 0;
rxs->rs_flags |= (rxsp->status4 & AR_2040) ? HAL_RX_2040 : 0;
/* Copy EVM information */
rxs->evm0 = rxsp->status6;
rxs->evm1 = rxsp->status7;
rxs->evm2 = rxsp->status8;
rxs->evm3 = rxsp->status9;
rxs->evm4 = (rxsp->status10 & 0xffff);
rxs->rs_evm0 = rxsp->status6;
rxs->rs_evm1 = rxsp->status7;
rxs->rs_evm2 = rxsp->status8;
rxs->rs_evm3 = rxsp->status9;
rxs->rs_evm4 = (rxsp->status10 & 0xffff);
if (rxsp->status11 & AR_pre_delim_crc_err) {
rxs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
@ -196,6 +193,3 @@ ar9300_get_rx_key_idx(struct ath_hal *ah, struct ath_desc *ds, u_int8_t *keyix,
*keyix = HAL_RXKEYIX_INVALID;
return HAL_ENOTSUPP;
}
#endif

615
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c
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File diff suppressed because it is too large Load diff

171
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c Normal file
View file

@ -0,0 +1,171 @@
/*
* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 235972 2012-05-25 05:01:27Z adrian $
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
#include "ar9300/ar9300.h"
#include "ar9300/ar9300reg.h"
#include "ar9300/ar9300phy.h"
#include "ar9300/ar9300_stub.h"
#include "ar9300/ar9300_stub_funcs.h"
void
ar9300_set_stub_functions(struct ath_hal *ah)
{
ath_hal_printf(ah, "%s: setting stub functions\n", __func__);
ah->ah_getRateTable = ar9300_Stub_GetRateTable;
// ah->ah_detach = ar9300_Stub_detach;
/* Reset Functions */
ah->ah_reset = ar9300_Stub_Reset;
ah->ah_phyDisable = ar9300_Stub_PhyDisable;
ah->ah_disable = ar9300_Stub_Disable;
ah->ah_configPCIE = ar9300_Stub_ConfigPCIE;
ah->ah_disablePCIE = ar9300_Stub_DisablePCIE;
ah->ah_setPCUConfig = ar9300_Stub_SetPCUConfig;
ah->ah_perCalibration = ar9300_Stub_PerCalibration;
ah->ah_perCalibrationN = ar9300_Stub_PerCalibrationN;
ah->ah_resetCalValid = ar9300_Stub_ResetCalValid;
ah->ah_setTxPowerLimit = ar9300_Stub_SetTxPowerLimit;
ah->ah_getChanNoise = ath_hal_getChanNoise;
/* Transmit functions */
ah->ah_updateTxTrigLevel = ar9300_Stub_UpdateTxTrigLevel;
ah->ah_setupTxQueue = ar9300_Stub_SetupTxQueue;
ah->ah_setTxQueueProps = ar9300_Stub_SetTxQueueProps;
ah->ah_getTxQueueProps = ar9300_Stub_GetTxQueueProps;
ah->ah_releaseTxQueue = ar9300_Stub_ReleaseTxQueue;
ah->ah_resetTxQueue = ar9300_Stub_ResetTxQueue;
ah->ah_getTxDP = ar9300_Stub_GetTxDP;
ah->ah_setTxDP = ar9300_Stub_SetTxDP;
ah->ah_numTxPending = ar9300_Stub_NumTxPending;
ah->ah_startTxDma = ar9300_Stub_StartTxDma;
ah->ah_stopTxDma = ar9300_Stub_StopTxDma;
ah->ah_setupTxDesc = ar9300_Stub_SetupTxDesc;
ah->ah_setupXTxDesc = ar9300_Stub_SetupXTxDesc;
ah->ah_fillTxDesc = ar9300_Stub_FillTxDesc;
ah->ah_procTxDesc = ar9300_Stub_ProcTxDesc;
ah->ah_getTxIntrQueue = ar9300_Stub_GetTxIntrQueue;
ah->ah_reqTxIntrDesc = ar9300_Stub_IntrReqTxDesc;
ah->ah_getTxCompletionRates = ar9300_Stub_GetTxCompletionRates;
/* RX Functions */
ah->ah_getRxDP = ar9300_Stub_GetRxDP;
ah->ah_setRxDP = ar9300_Stub_SetRxDP;
ah->ah_enableReceive = ar9300_Stub_EnableReceive;
ah->ah_stopDmaReceive = ar9300_Stub_StopDmaReceive;
ah->ah_startPcuReceive = ar9300_Stub_StartPcuReceive;
ah->ah_stopPcuReceive = ar9300_Stub_StopPcuReceive;
ah->ah_setMulticastFilter = ar9300_Stub_SetMulticastFilter;
ah->ah_setMulticastFilterIndex = ar9300_Stub_SetMulticastFilterIndex;
ah->ah_clrMulticastFilterIndex = ar9300_Stub_ClrMulticastFilterIndex;
ah->ah_getRxFilter = ar9300_Stub_GetRxFilter;
ah->ah_setRxFilter = ar9300_Stub_SetRxFilter;
ah->ah_setupRxDesc = ar9300_Stub_SetupRxDesc;
ah->ah_procRxDesc = ar9300_Stub_ProcRxDesc;
ah->ah_rxMonitor = ar9300_Stub_RxMonitor;
ah->ah_aniPoll = ar9300_Stub_AniPoll;
ah->ah_procMibEvent = ar9300_Stub_ProcessMibIntr;
/* Misc Functions */
ah->ah_getCapability = ar9300_Stub_GetCapability;
ah->ah_setCapability = ar9300_Stub_SetCapability;
ah->ah_getDiagState = ar9300_Stub_GetDiagState;
ah->ah_getMacAddress = ar9300_Stub_GetMacAddress;
ah->ah_setMacAddress = ar9300_Stub_SetMacAddress;
ah->ah_getBssIdMask = ar9300_Stub_GetBssIdMask;
ah->ah_setBssIdMask = ar9300_Stub_SetBssIdMask;
ah->ah_setRegulatoryDomain = ar9300_Stub_SetRegulatoryDomain;
ah->ah_setLedState = ar9300_Stub_SetLedState;
ah->ah_writeAssocid = ar9300_Stub_WriteAssocid;
ah->ah_gpioCfgInput = ar9300_Stub_GpioCfgInput;
ah->ah_gpioCfgOutput = ar9300_Stub_GpioCfgOutput;
ah->ah_gpioGet = ar9300_Stub_GpioGet;
ah->ah_gpioSet = ar9300_Stub_GpioSet;
ah->ah_gpioSetIntr = ar9300_Stub_GpioSetIntr;
ah->ah_getTsf32 = ar9300_Stub_GetTsf32;
ah->ah_getTsf64 = ar9300_Stub_GetTsf64;
ah->ah_resetTsf = ar9300_Stub_ResetTsf;
ah->ah_detectCardPresent = ar9300_Stub_DetectCardPresent;
ah->ah_updateMibCounters = ar9300_Stub_UpdateMibCounters;
ah->ah_getRfGain = ar9300_Stub_GetRfgain;
ah->ah_getDefAntenna = ar9300_Stub_GetDefAntenna;
ah->ah_setDefAntenna = ar9300_Stub_SetDefAntenna;
ah->ah_getAntennaSwitch = ar9300_Stub_GetAntennaSwitch;
ah->ah_setAntennaSwitch = ar9300_Stub_SetAntennaSwitch;
ah->ah_setSifsTime = ar9300_Stub_SetSifsTime;
ah->ah_getSifsTime = ar9300_Stub_GetSifsTime;
ah->ah_setSlotTime = ar9300_Stub_SetSlotTime;
ah->ah_getSlotTime = ar9300_Stub_GetSlotTime;
ah->ah_setAckTimeout = ar9300_Stub_SetAckTimeout;
ah->ah_getAckTimeout = ar9300_Stub_GetAckTimeout;
ah->ah_setAckCTSRate = ar9300_Stub_SetAckCTSRate;
ah->ah_getAckCTSRate = ar9300_Stub_GetAckCTSRate;
ah->ah_setCTSTimeout = ar9300_Stub_SetCTSTimeout;
ah->ah_getCTSTimeout = ar9300_Stub_GetCTSTimeout;
ah->ah_setDecompMask = ar9300_Stub_SetDecompMask;
ah->ah_setCoverageClass = ar9300_Stub_SetCoverageClass;
ah->ah_setQuiet = ar9300_Stub_SetQuiet;
ah->ah_getMibCycleCounts = ar9300_Stub_GetMibCycleCounts;
/* DFS Functions */
ah->ah_enableDfs = ar9300_Stub_EnableDfs;
ah->ah_getDfsThresh = ar9300_Stub_GetDfsThresh;
ah->ah_procRadarEvent = ar9300_Stub_ProcessRadarEvent;
ah->ah_isFastClockEnabled = ar9300_Stub_IsFastClockEnabled;
ah->ah_get11nExtBusy = ar9300_Stub_Get11nExtBusy;
/* Key Cache Functions */
ah->ah_getKeyCacheSize = ar9300_Stub_GetKeyCacheSize;
ah->ah_resetKeyCacheEntry = ar9300_Stub_ResetKeyCacheEntry;
ah->ah_isKeyCacheEntryValid = ar9300_Stub_IsKeyCacheEntryValid;
ah->ah_setKeyCacheEntry = ar9300_Stub_SetKeyCacheEntry;
ah->ah_setKeyCacheEntryMac = ar9300_Stub_SetKeyCacheEntryMac;
/* Power Management Functions */
ah->ah_setPowerMode = ar9300_Stub_SetPowerMode;
ah->ah_getPowerMode = ar9300_Stub_GetPowerMode;
/* Beacon Functions */
ah->ah_setBeaconTimers = ar9300_Stub_SetBeaconTimers;
ah->ah_beaconInit = ar9300_Stub_BeaconInit;
ah->ah_setStationBeaconTimers = ar9300_Stub_SetStaBeaconTimers;
ah->ah_resetStationBeaconTimers = ar9300_Stub_ResetStaBeaconTimers;
ah->ah_getNextTBTT = ar9300_Stub_GetNextTBTT;
/* Interrupt Functions */
ah->ah_isInterruptPending = ar9300_Stub_IsInterruptPending;
ah->ah_getPendingInterrupts = ar9300_Stub_GetPendingInterrupts;
ah->ah_getInterrupts = ar9300_Stub_GetInterrupts;
ah->ah_setInterrupts = ar9300_Stub_SetInterrupts;
AH_PRIVATE(ah)->ah_getChannelEdges = ar9300_Stub_GetChannelEdges;
AH_PRIVATE(ah)->ah_getWirelessModes = ar9300_Stub_GetWirelessModes;
AH_PRIVATE(ah)->ah_eepromRead = ar9300_Stub_EepromRead;
#ifdef AH_SUPPORT_WRITE_EEPROM
AH_PRIVATE(ah)->ah_eepromWrite = ar9300_Stub_EepromWrite;
#endif
AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_Stub_GetChipPowerLimits;
}

7
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub.h Normal file
View file

@ -0,0 +1,7 @@
#ifndef __AR9300_STUB_H__
#define __AR9300_STUB_H__
extern void ar9300_set_stub_functions(struct ath_hal *ah);
#endif /* __AR9300_STUB_H__ */

1256
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c Normal file
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File diff suppressed because it is too large Load diff

237
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.h Normal file
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@ -0,0 +1,237 @@
#ifndef __AR9300_STUB_FUNCS_H__
#define __AR9300_STUB_FUNCS_H__
extern uint32_t ar9300_Stub_GetRadioRev(struct ath_hal *ah);
#if 0
extern void ar9300_Stub_InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
#endif
extern void ar9300_Stub_Detach(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_ChipTest(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_GetChannelEdges(struct ath_hal *ah,
uint16_t flags, uint16_t *low, uint16_t *high);
extern HAL_BOOL ar9300_Stub_FillCapabilityInfo(struct ath_hal *ah);
extern void ar9300_Stub_SetBeaconTimers(struct ath_hal *ah,
const HAL_BEACON_TIMERS *);
extern void ar9300_Stub_BeaconInit(struct ath_hal *ah,
uint32_t next_beacon, uint32_t beacon_period);
extern void ar9300_Stub_ResetStaBeaconTimers(struct ath_hal *ah);
extern void ar9300_Stub_SetStaBeaconTimers(struct ath_hal *ah,
const HAL_BEACON_STATE *);
extern uint64_t ar9300_Stub_GetNextTBTT(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_IsInterruptPending(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
extern HAL_INT ar9300_Stub_GetInterrupts(struct ath_hal *ah);
extern HAL_INT ar9300_Stub_SetInterrupts(struct ath_hal *ah, HAL_INT ints);
extern uint32_t ar9300_Stub_GetKeyCacheSize(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
extern HAL_BOOL ar9300_Stub_ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
extern HAL_BOOL ar9300_Stub_SetKeyCacheEntryMac(struct ath_hal *,
uint16_t entry, const uint8_t *mac);
extern HAL_BOOL ar9300_Stub_SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
extern void ar9300_Stub_GetMacAddress(struct ath_hal *ah, uint8_t *mac);
extern HAL_BOOL ar9300_Stub_SetMacAddress(struct ath_hal *ah, const uint8_t *);
extern void ar9300_Stub_GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
extern HAL_BOOL ar9300_Stub_SetBssIdMask(struct ath_hal *, const uint8_t *);
extern HAL_BOOL ar9300_Stub_EepromRead(struct ath_hal *, u_int off, uint16_t *data);
extern HAL_BOOL ar9300_Stub_EepromWrite(struct ath_hal *, u_int off, uint16_t data);
extern HAL_BOOL ar9300_Stub_SetRegulatoryDomain(struct ath_hal *ah,
uint16_t regDomain, HAL_STATUS *stats);
extern u_int ar9300_Stub_GetWirelessModes(struct ath_hal *ah);
extern void ar9300_Stub_EnableRfKill(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar9300_Stub_GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar9300_Stub_GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar9300_Stub_GpioGet(struct ath_hal *ah, uint32_t gpio);
extern void ar9300_Stub_GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
extern void ar9300_Stub_SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
extern void ar9300_Stub_WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
uint16_t assocId);
extern uint32_t ar9300_Stub_GetTsf32(struct ath_hal *ah);
extern uint64_t ar9300_Stub_GetTsf64(struct ath_hal *ah);
extern void ar9300_Stub_SetTsf64(struct ath_hal *ah, uint64_t tsf64);
extern void ar9300_Stub_ResetTsf(struct ath_hal *ah);
extern void ar9300_Stub_SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
extern uint32_t ar9300_Stub_GetRandomSeed(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_DetectCardPresent(struct ath_hal *ah);
extern void ar9300_Stub_EnableMibCounters(struct ath_hal *);
extern void ar9300_Stub_DisableMibCounters(struct ath_hal *);
extern void ar9300_Stub_UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
extern HAL_BOOL ar9300_Stub_IsJapanChannelSpreadSupported(struct ath_hal *ah);
extern uint32_t ar9300_Stub_GetCurRssi(struct ath_hal *ah);
extern u_int ar9300_Stub_GetDefAntenna(struct ath_hal *ah);
extern void ar9300_Stub_SetDefAntenna(struct ath_hal *ah, u_int antenna);
extern HAL_ANT_SETTING ar9300_Stub_GetAntennaSwitch(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
extern HAL_BOOL ar9300_Stub_IsSleepAfterBeaconBroken(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_SetSifsTime(struct ath_hal *, u_int);
extern u_int ar9300_Stub_GetSifsTime(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetSlotTime(struct ath_hal *, u_int);
extern u_int ar9300_Stub_GetSlotTime(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetAckTimeout(struct ath_hal *, u_int);
extern u_int ar9300_Stub_GetAckTimeout(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetAckCTSRate(struct ath_hal *, u_int);
extern u_int ar9300_Stub_GetAckCTSRate(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetCTSTimeout(struct ath_hal *, u_int);
extern u_int ar9300_Stub_GetCTSTimeout(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_SetDecompMask(struct ath_hal *, uint16_t, int);
void ar9300_Stub_SetCoverageClass(struct ath_hal *, uint8_t, int);
extern void ar9300_Stub_SetPCUConfig(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar9300_Stub_SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar9300_Stub_RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern int16_t ar9300_Stub_GetNfAdjust(struct ath_hal *,
const HAL_CHANNEL_INTERNAL *);
extern void ar9300_Stub_SetCompRegs(struct ath_hal *ah);
extern HAL_STATUS ar9300_Stub_GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
uint32_t, uint32_t *);
extern HAL_BOOL ar9300_Stub_SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
uint32_t, uint32_t, HAL_STATUS *);
extern HAL_BOOL ar9300_Stub_GetDiagState(struct ath_hal *ah, int request,
const void *args, uint32_t argsize,
void **result, uint32_t *resultsize);
extern HAL_STATUS ar9300_Stub_SetQuiet(struct ath_hal *ah, uint32_t period,
uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
extern HAL_BOOL ar9300_Stub_GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern HAL_BOOL ar9300_Stub_SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
int setChip);
extern HAL_POWER_MODE ar9300_Stub_GetPowerMode(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_GetPowerStatus(struct ath_hal *ah);
extern uint32_t ar9300_Stub_GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE);
extern void ar9300_Stub_SetRxDP(struct ath_hal *ah, uint32_t rxdp,
HAL_RX_QUEUE);
extern void ar9300_Stub_EnableReceive(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_StopDmaReceive(struct ath_hal *ah);
extern void ar9300_Stub_StartPcuReceive(struct ath_hal *ah);
extern void ar9300_Stub_StopPcuReceive(struct ath_hal *ah);
extern void ar9300_Stub_SetMulticastFilter(struct ath_hal *ah,
uint32_t filter0, uint32_t filter1);
extern HAL_BOOL ar9300_Stub_ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
extern HAL_BOOL ar9300_Stub_SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
extern uint32_t ar9300_Stub_GetRxFilter(struct ath_hal *ah);
extern void ar9300_Stub_SetRxFilter(struct ath_hal *ah, uint32_t bits);
extern HAL_BOOL ar9300_Stub_SetupRxDesc(struct ath_hal *,
struct ath_desc *, uint32_t size, u_int flags);
extern HAL_STATUS ar9300_Stub_ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
uint32_t, struct ath_desc *, uint64_t,
struct ath_rx_status *);
extern HAL_BOOL ar9300_Stub_Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_STATUS *status);
extern HAL_BOOL ar9300_Stub_SetChannel(struct ath_hal *,
const struct ieee80211_channel *);
extern void ar9300_Stub_SetOperatingMode(struct ath_hal *ah, int opmode);
extern HAL_BOOL ar9300_Stub_PhyDisable(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_Disable(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_ChipReset(struct ath_hal *ah,
const struct ieee80211_channel *);
extern HAL_BOOL ar9300_Stub_PerCalibration(struct ath_hal *ah,
struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
extern HAL_BOOL ar9300_Stub_PerCalibrationN(struct ath_hal *ah,
struct ieee80211_channel *chan, u_int chainMask,
HAL_BOOL longCal, HAL_BOOL *isCalDone);
extern HAL_BOOL ar9300_Stub_ResetCalValid(struct ath_hal *ah,
const struct ieee80211_channel *);
extern int16_t ar9300_Stub_GetNoiseFloor(struct ath_hal *ah);
extern void ar9300_Stub_InitNfCalHistBuffer(struct ath_hal *);
extern int16_t ar9300_Stub_GetNfHistMid(const int16_t calData[]);
extern void ar9300_Stub_SetSpurMitigation(struct ath_hal *,
const struct ieee80211_channel *);
extern HAL_BOOL ar9300_Stub_SetAntennaSwitchInternal(struct ath_hal *ah,
HAL_ANT_SETTING settings, const struct ieee80211_channel *);
extern HAL_BOOL ar9300_Stub_SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
extern HAL_BOOL ar9300_Stub_GetChipPowerLimits(struct ath_hal *ah,
struct ieee80211_channel *chan);
extern void ar9300_Stub_InitializeGainValues(struct ath_hal *);
extern HAL_RFGAIN ar9300_Stub_GetRfgain(struct ath_hal *ah);
extern void ar9300_Stub_RequestRfgain(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_UpdateTxTrigLevel(struct ath_hal *,
HAL_BOOL IncTrigLevel);
extern HAL_BOOL ar9300_Stub_SetTxQueueProps(struct ath_hal *ah, int q,
const HAL_TXQ_INFO *qInfo);
extern HAL_BOOL ar9300_Stub_GetTxQueueProps(struct ath_hal *ah, int q,
HAL_TXQ_INFO *qInfo);
extern int ar9300_Stub_SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
const HAL_TXQ_INFO *qInfo);
extern HAL_BOOL ar9300_Stub_ReleaseTxQueue(struct ath_hal *ah, u_int q);
extern HAL_BOOL ar9300_Stub_ResetTxQueue(struct ath_hal *ah, u_int q);
extern uint32_t ar9300_Stub_GetTxDP(struct ath_hal *ah, u_int q);
extern HAL_BOOL ar9300_Stub_SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
extern HAL_BOOL ar9300_Stub_StartTxDma(struct ath_hal *ah, u_int q);
extern uint32_t ar9300_Stub_NumTxPending(struct ath_hal *ah, u_int q);
extern HAL_BOOL ar9300_Stub_StopTxDma(struct ath_hal *ah, u_int q);
extern HAL_BOOL ar9300_Stub_SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
u_int txRate0, u_int txTries0,
u_int keyIx, u_int antMode, u_int flags,
u_int rtsctsRate, u_int rtsctsDuration,
u_int compicvLen, u_int compivLen, u_int comp);
extern HAL_BOOL ar9300_Stub_SetupXTxDesc(struct ath_hal *, struct ath_desc *,
u_int txRate1, u_int txRetries1,
u_int txRate2, u_int txRetries2,
u_int txRate3, u_int txRetries3);
extern HAL_BOOL ar9300_Stub_FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
u_int descId, u_int qcuId,
HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0);
extern HAL_STATUS ar9300_Stub_ProcTxDesc(struct ath_hal *ah,
struct ath_desc *, struct ath_tx_status *);
extern void ar9300_Stub_GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
extern void ar9300_Stub_IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
extern HAL_BOOL ar9300_Stub_GetTxCompletionRates(struct ath_hal *ah,
const struct ath_desc *ds0, int *rates, int *tries);
extern const HAL_RATE_TABLE * ar9300_Stub_GetRateTable(struct ath_hal *, u_int mode);
#if 0
extern void ar9300_Stub_AniAttach(struct ath_hal *, const struct ar9300_Stub_AniParams *,
const struct ar9300_Stub_AniParams *, HAL_BOOL ena);
#endif
extern void ar9300_Stub_AniDetach(struct ath_hal *);
extern struct ar9300_Stub_AniState *ar5212AniGetCurrentState(struct ath_hal *);
extern struct ar9300_Stub_Stats *ar5212AniGetCurrentStats(struct ath_hal *);
extern HAL_BOOL ar9300_Stub_AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
#if 0
extern HAL_BOOL ar9300_Stub_AniSetParams(struct ath_hal *,
const struct ar9300_Stub_AniParams *, const struct ar9300_Stub_AniParams *);
#endif
struct ath_rx_status;
extern void ar9300_Stub_AniPhyErrReport(struct ath_hal *ah,
const struct ath_rx_status *rs);
extern void ar9300_Stub_ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
extern void ar9300_Stub_RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
const struct ieee80211_channel *);
extern void ar9300_Stub_AniPoll(struct ath_hal *, const struct ieee80211_channel *);
extern void ar9300_Stub_AniReset(struct ath_hal *, const struct ieee80211_channel *,
HAL_OPMODE, int);
extern HAL_BOOL ar9300_Stub_IsNFCalInProgress(struct ath_hal *ah);
extern HAL_BOOL ar9300_Stub_WaitNFCalComplete(struct ath_hal *ah, int i);
extern void ar9300_Stub_EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern void ar9300_Stub_GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern HAL_BOOL ar9300_Stub_ProcessRadarEvent(struct ath_hal *ah,
struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf,
HAL_DFS_EVENT *event);
extern HAL_BOOL ar9300_Stub_IsFastClockEnabled(struct ath_hal *ah);
extern uint32_t ar9300_Stub_Get11nExtBusy(struct ath_hal *ah);
extern void ar9300_Stub_ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
HAL_BOOL powerOff);
extern void ar9300_Stub_DisablePCIE(struct ath_hal *ah);
#endif /* __AR9300_STUB_FUNCS_H__ */

4
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_timer.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_internal.h"
@ -181,5 +179,3 @@ ar9300_get_gen_timer_interrupts(
*trigger = ahp->ah_intr_gen_timer_trigger;
*thresh = ahp->ah_intr_gen_timer_thresh;
}
#endif /* AH_SUPPORT_AR9300 */

105
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_desc.h"
#include "ah_internal.h"
@ -27,6 +25,9 @@
#include "ar9300/ar9300phy.h"
#include "ar9300/ar9300desc.h"
#define TU_TO_USEC(_tu) ((_tu) << 10)
#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7)
/*
* Update Tx FIFO trigger level.
*
@ -42,7 +43,7 @@ ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
u_int32_t txcfg, cur_level, new_level;
HAL_INT omask;
if (AH_PRIVATE(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD &&
b_inc_trig_level)
{
return AH_FALSE;
@ -74,7 +75,7 @@ ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
/* re-enable chip interrupts */
ar9300_set_interrupts(ah, omask, 0);
AH_PRIVATE(ah)->ah_tx_trig_level = new_level;
AH9300(ah)->ah_tx_trig_level = new_level;
return (new_level != cur_level);
}
@ -85,7 +86,7 @@ ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level)
u_int16_t
ar9300_get_tx_trig_level(struct ath_hal *ah)
{
return (AH_PRIVATE(ah)->ah_tx_trig_level);
return (AH9300(ah)->ah_tx_trig_level);
}
/*
@ -98,11 +99,11 @@ ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info)
struct ath_hal_9300 *ahp = AH9300(ah);
HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
if (q >= p_cap->hal_total_queues) {
if (q >= p_cap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
return AH_FALSE;
}
return ath_hal_set_tx_q_props(ah, &ahp->ah_txq[q], q_info);
return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info);
}
/*
@ -115,11 +116,11 @@ ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info)
HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
if (q >= p_cap->hal_total_queues) {
if (q >= p_cap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
return AH_FALSE;
}
return ath_hal_get_tx_q_props(ah, q_info, &ahp->ah_txq[q]);
return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]);
}
enum {
@ -145,17 +146,17 @@ ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
switch (type) {
case HAL_TX_QUEUE_BEACON:
/* highest priority */
q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON;
break;
case HAL_TX_QUEUE_CAB:
/* next highest priority */
q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB;
break;
case HAL_TX_QUEUE_UAPSD:
q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD;
break;
case HAL_TX_QUEUE_PAPRD:
q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
break;
case HAL_TX_QUEUE_DATA:
/*
@ -163,14 +164,14 @@ ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
* beacon, CAB, UAPSD, PAPRD
*/
for (q = 0;
q < p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD;
q++)
{
if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) {
break;
}
}
if (q == p_cap->hal_total_queues - 3) {
if (q == p_cap->halTotalQueues - 3) {
HALDEBUG(ah, HAL_DEBUG_QUEUE,
"%s: no available tx queue\n", __func__);
return -1;
@ -196,18 +197,18 @@ ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
if (q_info == AH_NULL) {
/* by default enable OK+ERR+DESC+URN interrupts */
qi->tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE
| TXQ_FLAG_TXERRINT_ENABLE
| TXQ_FLAG_TXDESCINT_ENABLE
| TXQ_FLAG_TXURNINT_ENABLE;
qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
| HAL_TXQ_TXERRINT_ENABLE
| HAL_TXQ_TXDESCINT_ENABLE
| HAL_TXQ_TXURNINT_ENABLE;
qi->tqi_aifs = INIT_AIFS;
qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
qi->tqi_cwmax = INIT_CWMAX;
qi->tqi_shretry = INIT_SH_RETRY;
qi->tqi_lgretry = INIT_LG_RETRY;
qi->tqi_phys_comp_buf = 0;
qi->tqi_physCompBuf = 0;
} else {
qi->tqi_phys_comp_buf = q_info->tqi_comp_buf;
qi->tqi_physCompBuf = q_info->tqi_compBuf;
(void) ar9300_set_tx_queue_props(ah, q, q_info);
}
/* NB: must be followed by ar9300_reset_tx_queue */
@ -250,7 +251,7 @@ ar9300_release_tx_queue(struct ath_hal *ah, u_int q)
HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
HAL_TX_QUEUE_INFO *qi;
if (q >= p_cap->hal_total_queues) {
if (q >= p_cap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
return AH_FALSE;
}
@ -282,13 +283,13 @@ HAL_BOOL
ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ath_hal_private *ap = AH_PRIVATE(ah);
// struct ath_hal_private *ap = AH_PRIVATE(ah);
HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
u_int32_t cw_min, chan_cw_min, value;
if (q >= p_cap->hal_total_queues) {
if (q >= p_cap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q);
return AH_FALSE;
}
@ -306,7 +307,7 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* Select cwmin according to channel type.
* NB: chan can be NULL during attach
*/
if (chan && IS_CHAN_B(chan)) {
if (chan && IEEE80211_IS_CHAN_B(chan)) {
chan_cw_min = INIT_CWMIN_11B;
} else {
chan_cw_min = INIT_CWMIN;
@ -318,7 +319,7 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
}
/* set cw_min/Max and AIFS values */
if (q > 3 || (!ah->ah_fccaifs))
if (q > 3 || (!AH9300(ah)->ah_fccaifs))
/* values should not be overwritten if domain is FCC and manual rate
less than 24Mb is set, this check is making sure this */
{
@ -348,41 +349,41 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
}
/* multiqueue support */
if (qi->tqi_cbr_period) {
if (qi->tqi_cbrPeriod) {
OS_REG_WRITE(ah,
AR_QCBRCFG(q),
SM(qi->tqi_cbr_period, AR_Q_CBRCFG_INTERVAL) |
SM(qi->tqi_cbr_overflow_limit,
SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
SM(qi->tqi_cbrOverflowLimit,
AR_Q_CBRCFG_OVF_THRESH));
OS_REG_WRITE(ah, AR_QMISC(q),
OS_REG_READ(ah, AR_QMISC(q)) |
AR_Q_MISC_FSP_CBR |
(qi->tqi_cbr_overflow_limit ?
(qi->tqi_cbrOverflowLimit ?
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
}
if (qi->tqi_ready_time && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
SM(qi->tqi_ready_time, AR_Q_RDYTIMECFG_DURATION) |
SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
AR_Q_RDYTIMECFG_EN);
}
OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burst_time, AR_D_CHNTIME_DUR) |
(qi->tqi_burst_time ? AR_D_CHNTIME_EN : 0));
OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
if (qi->tqi_burst_time &&
(qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
if (qi->tqi_burstTime &&
(qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
{
OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) |
AR_Q_MISC_RDYTIME_EXP_POLICY);
}
if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_POST_FR_BKOFF_DIS);
}
if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) |
AR_D_MISC_FRAG_BKOFF_EN);
}
@ -421,10 +422,10 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
| AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0);
value = TU_TO_USEC(qi->tqi_ready_time)
- (ap->ah_config.ath_hal_sw_beacon_response_time
- ap->ah_config.ath_hal_dma_beacon_response_time)
- ap->ah_config.ath_hal_additional_swba_backoff;
value = TU_TO_USEC(qi->tqi_readyTime)
- (ah->ah_config.ah_sw_beacon_response_time
- ah->ah_config.ah_dma_beacon_response_time)
- ah->ah_config.ah_additional_swba_backoff;
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q))
@ -459,7 +460,7 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* the meaning of queue_info->mode, or create something like
* queue_info->dcumode.
*/
if (qi->tqi_int_flags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
OS_REG_WRITE(ah, AR_DMISC(q),
OS_REG_READ(ah, AR_DMISC(q)) |
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
@ -480,22 +481,22 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
* tx interrupts are enabled/disabled for all queues collectively
* using the primary mask reg
*/
if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) {
if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) {
ahp->ah_tx_ok_interrupt_mask |= (1 << q);
} else {
ahp->ah_tx_ok_interrupt_mask &= ~(1 << q);
}
if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) {
if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) {
ahp->ah_tx_err_interrupt_mask |= (1 << q);
} else {
ahp->ah_tx_err_interrupt_mask &= ~(1 << q);
}
if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) {
if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) {
ahp->ah_tx_eol_interrupt_mask |= (1 << q);
} else {
ahp->ah_tx_eol_interrupt_mask &= ~(1 << q);
}
if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) {
if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) {
ahp->ah_tx_urn_interrupt_mask |= (1 << q);
} else {
ahp->ah_tx_urn_interrupt_mask &= ~(1 << q);
@ -511,7 +512,7 @@ ar9300_reset_tx_queue(struct ath_hal *ah, u_int q)
u_int32_t
ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
{
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
return OS_REG_READ(ah, AR_QTXDP(q));
}
@ -521,7 +522,7 @@ ar9300_get_tx_dp(struct ath_hal *ah, u_int q)
HAL_BOOL
ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp)
{
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
HALASSERT(txdp != 0);
@ -548,7 +549,7 @@ ar9300_num_tx_pending(struct ath_hal *ah, u_int q)
{
u_int32_t npend;
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues);
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
@ -906,5 +907,3 @@ ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start,
ar9300_reset_tx_status_ring(ah);
}
#endif /* AH_SUPPORT_AR9300 */

108
sys/contrib/dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c
View file

@ -16,8 +16,6 @@
#include "opt_ah.h"
#ifdef AH_SUPPORT_AR9300
#include "ah.h"
#include "ah_desc.h"
#include "ah_internal.h"
@ -56,12 +54,11 @@ ar9300_calc_ptr_chk_sum(struct ar9300_txc *ads)
return ptrchecksum;
}
HAL_BOOL
ar9300_fill_tx_desc(
struct ath_hal *ah,
void *ds,
dma_addr_t *buf_addr,
HAL_DMA_ADDR *buf_addr,
u_int32_t *seg_len,
u_int desc_id,
u_int qcu,
@ -201,22 +198,22 @@ ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts)
{
struct ar9300_txc *ads = AR9300TXC(ds);
switch (ts->ts_rateindex) {
switch (ts->ts_finaltsi) {
case 0:
ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate0);
ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate0);
break;
case 1:
ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate1);
ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate1);
break;
case 2:
ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate2);
ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate2);
break;
case 3:
ts->ts_ratecode = MS(ads->ds_ctl14, AR_xmit_rate3);
ts->ts_rate = MS(ads->ds_ctl14, AR_xmit_rate3);
break;
}
ar9300_set_selfgenrate_limit(ah, ts->ts_ratecode);
ar9300_set_selfgenrate_limit(ah, ts->ts_rate);
}
/*
@ -249,6 +246,28 @@ ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
if ((ads->status8 & AR_tx_done) == 0) {
return HAL_EINPROGRESS;
}
/*
* Sanity check
*/
#if 0
ath_hal_printf(ah,
"CHH: tail=%d\n", ahp->ts_tail);
ath_hal_printf(ah,
"CHH: ds_info 0x%x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
ads->ds_info,
ads->status1,
ads->status2,
ads->status3,
ads->status4,
ads->status5,
ads->status6,
ads->status7,
ads->status8);
#endif
/* Increment the tail to point to the next status element. */
ahp->ts_tail = (ahp->ts_tail + 1) & (ahp->ts_size-1);
@ -258,16 +277,6 @@ ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
** defined to "nothing" in little endian systems
*/
/*
* Sanity check
*/
#if 0
ath_hal_printf(ah,
"CHH: ds_info 0x%x status1: 0x%x status8: 0x%x\n",
ads->ds_info, ads->status1, ads->status8);
#endif
dsinfo = ads->ds_info;
if ((MS(dsinfo, AR_desc_id) != ATHEROS_VENDOR_ID) ||
@ -282,8 +291,8 @@ ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
}
/* Update software copies of the HW status */
ts->queue_id = MS(dsinfo, AR_tx_qcu_num);
ts->desc_id = MS(ads->status1, AR_tx_desc_id);
ts->ts_queue_id = MS(dsinfo, AR_tx_qcu_num);
ts->ts_desc_id = MS(ads->status1, AR_tx_desc_id);
ts->ts_seqnum = MS(ads->status8, AR_seq_num);
ts->ts_tstamp = ads->status4;
ts->ts_status = 0;
@ -318,29 +327,29 @@ ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
}
if (ads->status2 & AR_tx_ba_status) {
ts->ts_flags |= HAL_TX_BA;
ts->ba_low = ads->status5;
ts->ba_high = ads->status6;
ts->ts_ba_low = ads->status5;
ts->ts_ba_high = ads->status6;
}
/*
* Extract the transmit rate.
*/
ts->ts_rateindex = MS(ads->status8, AR_final_tx_idx);
ts->ts_finaltsi = MS(ads->status8, AR_final_tx_idx);
ts->ts_rssi = MS(ads->status7, AR_tx_rssi_combined);
ts->ts_rssi_ctl0 = MS(ads->status2, AR_tx_rssi_ant00);
ts->ts_rssi_ctl1 = MS(ads->status2, AR_tx_rssi_ant01);
ts->ts_rssi_ctl2 = MS(ads->status2, AR_tx_rssi_ant02);
ts->ts_rssi_ext0 = MS(ads->status7, AR_tx_rssi_ant10);
ts->ts_rssi_ext1 = MS(ads->status7, AR_tx_rssi_ant11);
ts->ts_rssi_ext2 = MS(ads->status7, AR_tx_rssi_ant12);
ts->ts_rssi_ctl[0] = MS(ads->status2, AR_tx_rssi_ant00);
ts->ts_rssi_ctl[1] = MS(ads->status2, AR_tx_rssi_ant01);
ts->ts_rssi_ctl[2] = MS(ads->status2, AR_tx_rssi_ant02);
ts->ts_rssi_ext[0] = MS(ads->status7, AR_tx_rssi_ant10);
ts->ts_rssi_ext[1] = MS(ads->status7, AR_tx_rssi_ant11);
ts->ts_rssi_ext[2] = MS(ads->status7, AR_tx_rssi_ant12);
ts->ts_shortretry = MS(ads->status3, AR_rts_fail_cnt);
ts->ts_longretry = MS(ads->status3, AR_data_fail_cnt);
ts->ts_virtcol = MS(ads->status3, AR_virt_retry_cnt);
ts->ts_antenna = 0;
/* extract TID from block ack */
ts->tid = MS(ads->status8, AR_tx_tid);
ts->ts_tid = MS(ads->status8, AR_tx_tid);
/* Zero out the status for reuse */
OS_MEMZERO(ads, sizeof(struct ar9300_txs));
@ -378,7 +387,7 @@ ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts,
* Calculate time of transmit on air for packet including retries
* at different rates.
*/
switch (ts->ts_rateindex) {
switch (ts->ts_finaltsi) {
case 0:
lastrate_dur = MS(ads->ds_ctl15, AR_packet_dur0);
airtime = (lastrate_dur * finalindex_tries);
@ -716,14 +725,14 @@ ar9300_set_11n_rate_scenario(
mode = ath_hal_get_curmode(ah, ap->ah_curchan);
cal_pkt = (ads->ds_ctl12 & AR_paprd_chain_mask)?1:0;
if (ap->ah_config.ath_hal_desc_tpc ) {
if (ah->ah_config.ath_hal_desc_tpc) {
int16_t txpower;
if (!cal_pkt) {
/* Series 0 TxPower */
tx_mode = ar9300_get_tx_mode(series[0].RateFlags);
txpower = ar9300_get_rate_txpower(ah, mode, series[0].rate_index,
series[0].ch_sel, tx_mode);
txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex,
series[0].ChSel, tx_mode);
} else {
txpower = AH9300(ah)->paprd_training_power;
}
@ -761,14 +770,14 @@ ar9300_set_11n_rate_scenario(
/* set not sounding for normal frame */
ads->ds_ctl19 = AR_not_sounding;
if (ap->ah_config.ath_hal_desc_tpc) {
if (ah->ah_config.ath_hal_desc_tpc) {
int16_t txpower;
if (!cal_pkt) {
/* Series 1 TxPower */
tx_mode = ar9300_get_tx_mode(series[1].RateFlags);
txpower = ar9300_get_rate_txpower(
ah, mode, series[1].rate_index, series[1].ch_sel, tx_mode);
ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode);
} else {
txpower = AH9300(ah)->paprd_training_power;
}
@ -780,7 +789,7 @@ ar9300_set_11n_rate_scenario(
if (!cal_pkt) {
tx_mode = ar9300_get_tx_mode(series[2].RateFlags);
txpower = ar9300_get_rate_txpower(
ah, mode, series[2].rate_index, series[2].ch_sel, tx_mode);
ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode);
} else {
txpower = AH9300(ah)->paprd_training_power;
}
@ -791,7 +800,7 @@ ar9300_set_11n_rate_scenario(
if (!cal_pkt) {
tx_mode = ar9300_get_tx_mode(series[3].RateFlags);
txpower = ar9300_get_rate_txpower(
ah, mode, series[3].rate_index, series[3].ch_sel, tx_mode);
ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode);
} else {
txpower = AH9300(ah)->paprd_training_power;
}
@ -828,18 +837,23 @@ ar9300_set_11n_rate_scenario(
}
void
ar9300_set_11n_aggr_first(struct ath_hal *ah, void *ds, u_int aggr_len)
ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
u_int aggr_len, u_int num_delims)
{
struct ar9300_txc *ads = AR9300TXC(ds);
ads->ds_ctl12 |= (AR_is_aggr | AR_more_aggr);
ads->ds_ctl17 &= ~AR_aggr_len;
ads->ds_ctl17 &= ~AR_pad_delim;
/* XXX should use a stack variable! */
ads->ds_ctl17 |= SM(aggr_len, AR_aggr_len);
ads->ds_ctl17 |= SM(num_delims, AR_pad_delim);
}
void
ar9300_set_11n_aggr_middle(struct ath_hal *ah, void *ds, u_int num_delims)
ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
u_int num_delims)
{
struct ar9300_txc *ads = AR9300TXC(ds);
unsigned int ctl17;
@ -857,7 +871,7 @@ ar9300_set_11n_aggr_middle(struct ath_hal *ah, void *ds, u_int num_delims)
}
void
ar9300_set_11n_aggr_last(struct ath_hal *ah, void *ds)
ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
{
struct ar9300_txc *ads = AR9300TXC(ds);
@ -867,7 +881,7 @@ ar9300_set_11n_aggr_last(struct ath_hal *ah, void *ds)
}
void
ar9300_clr_11n_aggr(struct ath_hal *ah, void *ds)
ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
{
struct ar9300_txc *ads = AR9300TXC(ds);
@ -875,7 +889,7 @@ ar9300_clr_11n_aggr(struct ath_hal *ah, void *ds)
}
void
ar9300_set_11n_burst_duration(struct ath_hal *ah, void *ds,
ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds,
u_int burst_duration)
{
struct ar9300_txc *ads = AR9300TXC(ds);
@ -918,7 +932,7 @@ ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds)
}
void
ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, void *ds,
ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds,
u_int vmf)
{
struct ar9300_txc *ads = AR9300TXC(ds);
@ -943,5 +957,3 @@ ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info)
desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah);
desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah);
}
#endif /* AH_SUPPORT_AR9300 */

40
sys/contrib/dev/ath/ath_hal/ar9300/ar9300desc.h
View file

@ -21,6 +21,9 @@
#ifndef _ATH_AR9300_DESC_H_
#define _ATH_AR9300_DESC_H_
#ifdef _KERNEL
#include "ar9300_freebsd_inc.h"
#endif
/* Osprey Status Descriptor. */
struct ar9300_txs {
@ -459,12 +462,11 @@ struct ar9300_txc {
((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
|((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \
|((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \
|SM((_series)[_index].ch_sel, AR_chain_sel##_index)
|SM((_series)[_index].ChSel, AR_chain_sel##_index)
#define set_11n_tx_power(_index, _txpower) \
SM(_txpower, AR_xmit_power##_index)
#define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7)
/*
* Descriptor Access Functions
@ -481,6 +483,8 @@ struct ar9300_txc {
(1<<0x1d)|(1<<0x18)|(1<<0x1c))
#define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES)
#ifdef _KERNEL
/* TX common functions */
extern HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *,
@ -504,7 +508,7 @@ extern HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah);
extern void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *);
extern void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds);
extern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, dma_addr_t *buf_addr,
extern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, HAL_DMA_ADDR *buf_addr,
u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg,
HAL_BOOL last_seg, const void *ds0);
extern void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link);
@ -534,20 +538,20 @@ extern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit);
extern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds,
void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[],
u_int nseries, u_int flags, u_int32_t smartAntenna);
extern void ar9300_set_11n_aggr_first(struct ath_hal *ah, void *ds,
u_int aggr_len);
extern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, void *ds,
extern void ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
u_int aggr_len, u_int num_delims);
extern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
u_int num_delims);
extern void ar9300_set_11n_aggr_last(struct ath_hal *ah, void *ds);
extern void ar9300_clr_11n_aggr(struct ath_hal *ah, void *ds);
extern void ar9300_set_11n_burst_duration(struct ath_hal *ah, void *ds,
u_int burst_duration);
extern void ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
extern void ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
extern void ar9300_set_11n_burst_duration(struct ath_hal *ah,
struct ath_desc *ds, u_int burst_duration);
extern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds);
extern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds);
extern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds);
extern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds);
extern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, void *ds,
u_int vmf);
extern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah,
struct ath_desc *ds, u_int vmf);
#ifdef AH_PRIVATE_DIAG
extern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode);
#endif
@ -565,7 +569,7 @@ extern void ar9300_set_multicast_filter(struct ath_hal *ah,
extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits);
extern HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL);
extern bool ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL);
extern HAL_BOOL ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL);
extern HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah,
struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *);
@ -578,14 +582,6 @@ extern void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable);
extern void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *);
extern void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t );
#endif
#endif /* _ATH_AR9300_DESC_H_ */

14
sys/contrib/dev/ath/ath_hal/ar9300/ar9300eep.h
View file

@ -25,6 +25,17 @@
#pragma pack (push, ar9300, 1)
#endif
/* FreeBSD extras - should be in ah_eeprom.h ? */
#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
#define AR_EEPROM_EEPCAP_MAXQCU_S 4
#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
#define MSTATE 100
#define MOUTPUT 2048
@ -626,7 +637,7 @@ extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t fr
u_int8_t *target_power_val_t2);
extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah,
ar9300_eeprom_t *p_eep_data,
HAL_CHANNEL_INTERNAL *chan,
const struct ieee80211_channel *chan,
u_int8_t *p_pwr_array,
u_int16_t cfg_ctl,
u_int16_t antenna_reduction,
@ -634,7 +645,6 @@ extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah,
u_int16_t power_limit,
u_int8_t chainmask);
extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array);
extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor);
extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);

30
sys/contrib/dev/ath/ath_hal/ar9300/ar9300paprd.h
View file

@ -13,42 +13,24 @@
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* Copyright (c) 2002-2010 Atheros Communications, Inc.
* All Rights Reserved.
*
* Copyright (c) 2011 Qualcomm Atheros, Inc.
* All Rights Reserved.
* Qualcomm Atheros Confidential and Proprietary.
*
*/
#ifndef __AR9300PAPRD_H__
#define __AR9300PAPRD_H__
#include <ah.h>
#include "ar9300.h"
#include "ar9300phy.h"
#define AH_PAPRD_AM_PM_MASK 0x1ffffff
#define AH_PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
extern int ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL *chan);
extern int ar9300_paprd_init_table(struct ath_hal *ah, struct ieee80211_channel *chan);
extern HAL_STATUS ar9300_paprd_setup_gain_table(struct ath_hal *ah, int chain_num);
extern HAL_STATUS ar9300_paprd_create_curve(struct ath_hal *ah, HAL_CHANNEL *chan, int chain_num);
extern HAL_STATUS ar9300_paprd_create_curve(struct ath_hal *ah, struct ieee80211_channel *chan, int chain_num);
extern int ar9300_paprd_is_done(struct ath_hal *ah);
extern void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, HAL_CHANNEL * chan);
extern void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, struct ieee80211_channel * chan);
extern void ar9300_swizzle_paprd_entries(struct ath_hal *ah, unsigned int txchain);
extern void ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL *chan, int chain_num);
extern void ar9300_populate_paprd_single_table(struct ath_hal *ah, struct ieee80211_channel *chan, int chain_num);
extern void ar9300_paprd_dec_tx_pwr(struct ath_hal *ah);
extern int ar9300_paprd_thermal_send(struct ath_hal *ah);
#endif
#endif