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Merge from projects/bhyve_svm all the changes outside vmm.ko or bhyve utilities:
Add support for AMD's nested page tables in pmap.c: - Provide the correct bit mask for various bit fields in a PTE (e.g. valid bit) for a pmap of type PT_RVI. - Add a function 'pmap_type_guest(pmap)' that returns TRUE if the pmap is of type PT_EPT or PT_RVI. Add CPU_SET_ATOMIC_ACQ(num, cpuset): This is used when activating a vcpu in the nested pmap. Using the 'acquire' variant guarantees that the load of the 'pm_eptgen' will happen only after the vcpu is activated in 'pm_active'. Add defines for various AMD-specific MSRs. Submitted by: Anish Gupta (akgupt3@gmail.com)
This commit is contained in:
Neel Natu
parent
71b37cb9ae
commit
e011dc962c
4 changed files with 43 additions and 5 deletions
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@ -145,6 +145,13 @@ __FBSDID("$FreeBSD$");
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#include <machine/smp.h>
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#endif
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static __inline boolean_t
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pmap_type_guest(pmap_t pmap)
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{
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return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
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}
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static __inline boolean_t
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pmap_emulate_ad_bits(pmap_t pmap)
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{
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@ -159,6 +166,7 @@ pmap_valid_bit(pmap_t pmap)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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mask = X86_PG_V;
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break;
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case PT_EPT:
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@ -181,6 +189,7 @@ pmap_rw_bit(pmap_t pmap)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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mask = X86_PG_RW;
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break;
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case PT_EPT:
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@ -205,6 +214,7 @@ pmap_global_bit(pmap_t pmap)
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case PT_X86:
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mask = X86_PG_G;
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break;
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case PT_RVI:
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case PT_EPT:
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mask = 0;
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break;
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@ -222,6 +232,7 @@ pmap_accessed_bit(pmap_t pmap)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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mask = X86_PG_A;
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break;
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case PT_EPT:
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@ -244,6 +255,7 @@ pmap_modified_bit(pmap_t pmap)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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mask = X86_PG_M;
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break;
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case PT_EPT:
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@ -1103,6 +1115,7 @@ pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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/* Verify that both PAT bits are not set at the same time */
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KASSERT((entry & x86_pat_bits) != x86_pat_bits,
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("Invalid PAT bits in entry %#lx", entry));
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@ -1138,6 +1151,7 @@ pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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/* The PAT bit is different for PTE's and PDE's. */
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pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
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@ -1172,6 +1186,7 @@ pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
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switch (pmap->pm_type) {
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case PT_X86:
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case PT_RVI:
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mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
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break;
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case PT_EPT:
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@ -1198,6 +1213,7 @@ pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
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switch (pmap->pm_type) {
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case PT_X86:
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break;
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case PT_RVI:
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case PT_EPT:
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/*
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* XXX
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@ -1233,7 +1249,7 @@ pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
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{
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pt_entry_t PG_G;
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if (pmap->pm_type == PT_EPT)
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if (pmap_type_guest(pmap))
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return;
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KASSERT(pmap->pm_type == PT_X86,
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@ -1347,7 +1363,7 @@ pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
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cpuset_t other_cpus;
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u_int cpuid;
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if (pmap->pm_type == PT_EPT) {
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if (pmap_type_guest(pmap)) {
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pmap_invalidate_ept(pmap);
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return;
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}
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@ -1425,7 +1441,7 @@ pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
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vm_offset_t addr;
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u_int cpuid;
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if (pmap->pm_type == PT_EPT) {
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if (pmap_type_guest(pmap)) {
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pmap_invalidate_ept(pmap);
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return;
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}
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@ -1484,7 +1500,7 @@ pmap_invalidate_all(pmap_t pmap)
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uint64_t cr3;
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u_int cpuid;
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if (pmap->pm_type == PT_EPT) {
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if (pmap_type_guest(pmap)) {
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pmap_invalidate_ept(pmap);
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return;
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}
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@ -1606,7 +1622,7 @@ pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
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cpuid = PCPU_GET(cpuid);
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other_cpus = all_cpus;
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CPU_CLR(cpuid, &other_cpus);
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if (pmap == kernel_pmap || pmap->pm_type == PT_EPT)
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if (pmap == kernel_pmap || pmap_type_guest(pmap))
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active = all_cpus;
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else {
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active = pmap->pm_active;
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@ -1644,6 +1660,7 @@ pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
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if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
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invlpg(va);
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break;
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case PT_RVI:
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case PT_EPT:
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pmap->pm_eptgen++;
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break;
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@ -1663,6 +1680,7 @@ pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
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for (addr = sva; addr < eva; addr += PAGE_SIZE)
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invlpg(addr);
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break;
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case PT_RVI:
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case PT_EPT:
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pmap->pm_eptgen++;
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break;
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@ -1680,6 +1698,7 @@ pmap_invalidate_all(pmap_t pmap)
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if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
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invltlb();
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break;
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case PT_RVI:
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case PT_EPT:
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pmap->pm_eptgen++;
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break;
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@ -135,6 +135,10 @@
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atomic_set_long(&(p)->__bits[__bitset_word(_s, n)], \
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__bitset_mask((_s), n))
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#define BIT_SET_ATOMIC_ACQ(_s, n, p) \
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atomic_set_acq_long(&(p)->__bits[__bitset_word(_s, n)], \
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__bitset_mask((_s), n))
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/* Convenience functions catering special cases. */
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#define BIT_AND_ATOMIC(_s, d, s) do { \
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__size_t __i; \
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@ -55,6 +55,7 @@
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#define CPU_NAND(d, s) BIT_NAND(CPU_SETSIZE, d, s)
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#define CPU_CLR_ATOMIC(n, p) BIT_CLR_ATOMIC(CPU_SETSIZE, n, p)
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#define CPU_SET_ATOMIC(n, p) BIT_SET_ATOMIC(CPU_SETSIZE, n, p)
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#define CPU_SET_ATOMIC_ACQ(n, p) BIT_SET_ATOMIC_ACQ(CPU_SETSIZE, n, p)
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#define CPU_AND_ATOMIC(n, p) BIT_AND_ATOMIC(CPU_SETSIZE, n, p)
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#define CPU_OR_ATOMIC(d, s) BIT_OR_ATOMIC(CPU_SETSIZE, d, s)
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#define CPU_COPY_STORE_REL(f, t) BIT_COPY_STORE_REL(CPU_SETSIZE, f, t)
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@ -81,6 +81,7 @@
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#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
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#define EFER_LMA 0x000000400 /* Long mode active (R) */
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#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
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#define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
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/*
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* Intel Extended Features registers
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@ -783,8 +784,21 @@
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#define MSR_IORRMASK1 0xc0010019
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#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
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#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
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#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
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#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
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#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
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#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
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#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
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#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
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#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
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#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
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#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
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#define MSR_MC0_CTL_MASK 0xc0010044
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#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
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#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
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/* MSR_VM_CR related */
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#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
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/* VIA ACE crypto featureset: for via_feature_rng */
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#define VIA_HAS_RNG 1 /* cpu has RNG */
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