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https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
Add basic support for RTL8168C, RTL8168CP, RTL8111C and RTL8111CP.
ATM Tx/Rx checksum offload is supported but TSO and jumbo frame is not yet supported. Because these newer controllers use different descriptor formats, a flag RL_FLAG_DESCV2 flag was introduced to handle that case in Tx/Rx handler. Also newer controllers seems to require to not touch 'enable Tx/Rx bit' in RL_CPLUS_CMD register so don't blindly try to set that bits. Note, it seems that there is still power-saving related issue where driver fails to attach PHY. Rebooting seems to fix that issue but number of required reboots varys. Many thanks to users that helped during developement. I really appreciate their patient and test/feedbacks.
This commit is contained in:
Pyun YongHyeon
parent
a810fc83f5
commit
deb5c680bb
2 changed files with 157 additions and 42 deletions
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@ -172,7 +172,8 @@ static struct rl_type re_devs[] = {
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{ RT_VENDORID, RT_DEVICEID_8101E, 0,
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"RealTek 8101E PCIe 10/100baseTX" },
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{ RT_VENDORID, RT_DEVICEID_8168, 0,
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"RealTek 8168/8168B/8111B PCIe Gigabit Ethernet" },
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"RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe "
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"Gigabit Ethernet" },
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{ RT_VENDORID, RT_DEVICEID_8169, 0,
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"RealTek 8169/8169S/8169SB/8110S/8110SB Gigabit Ethernet" },
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{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
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@ -206,6 +207,9 @@ static struct rl_hwrev re_hwrevs[] = {
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{ RL_HWREV_8101E, RL_8169, "8101E"},
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{ RL_HWREV_8168_SPIN2, RL_8169, "8168"},
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{ RL_HWREV_8168_SPIN3, RL_8169, "8168"},
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{ RL_HWREV_8168C, RL_8169, "8168C/8111C"},
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{ RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"},
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{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"},
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{ 0, 0, NULL }
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};
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@ -1240,7 +1244,25 @@ re_attach(dev)
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case RL_HWREV_8168_SPIN1:
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case RL_HWREV_8168_SPIN2:
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case RL_HWREV_8168_SPIN3:
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sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE;
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sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
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RL_FLAG_MACSTAT;
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break;
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case RL_HWREV_8168C:
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case RL_HWREV_8168C_SPIN2:
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case RL_HWREV_8168CP:
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sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
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RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT;
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/*
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* These controllers support jumbo frame but it seems
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* that enabling it requires touching additional magic
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* registers. Depending on MAC revisions some
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* controllers need to disable checksum offload. So
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* disable jumbo frame until I have better idea what
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* it really requires to make it support.
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* RTL8168C/CP : supports up to 6KB jumbo frame.
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* RTL8111C/CP : supports up to 9KB jumbo frame.
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*/
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sc->rl_flags |= RL_FLAG_NOJUMBO;
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break;
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case RL_HWREV_8169_8110SB:
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case RL_HWREV_8169_8110SC:
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@ -1250,18 +1272,37 @@ re_attach(dev)
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break;
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}
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sc->rl_eewidth = RL_9356_ADDR_LEN;
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re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
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if (re_did != 0x8129)
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sc->rl_eewidth = RL_9346_ADDR_LEN;
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/* Enable PME. */
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CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
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cfg = CSR_READ_1(sc, RL_CFG1);
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cfg |= RL_CFG1_PME;
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CSR_WRITE_1(sc, RL_CFG1, cfg);
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cfg = CSR_READ_1(sc, RL_CFG5);
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cfg &= RL_CFG5_PME_STS;
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CSR_WRITE_1(sc, RL_CFG5, cfg);
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CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
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/*
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* Get station address from the EEPROM.
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*/
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re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
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for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
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as[i] = le16toh(as[i]);
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bcopy(as, eaddr, sizeof(eaddr));
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if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
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/*
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* XXX Should have a better way to extract station
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* address from EEPROM.
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*/
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
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} else {
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sc->rl_eewidth = RL_9356_ADDR_LEN;
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re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
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if (re_did != 0x8129)
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sc->rl_eewidth = RL_9346_ADDR_LEN;
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/*
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* Get station address from the EEPROM.
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*/
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re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
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for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
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as[i] = le16toh(as[i]);
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bcopy(as, eaddr, sizeof(eaddr));
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}
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if (sc->rl_type == RL_8169) {
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/* Set RX length mask and number of descriptors. */
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@ -1307,8 +1348,8 @@ re_attach(dev)
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_ioctl = re_ioctl;
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ifp->if_start = re_start;
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ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO;
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ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
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ifp->if_hwassist = RE_CSUM_FEATURES;
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ifp->if_capabilities = IFCAP_HWCSUM;
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ifp->if_capenable = ifp->if_capabilities;
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ifp->if_init = re_init;
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IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
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@ -1318,6 +1359,16 @@ re_attach(dev)
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TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
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TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
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/*
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* XXX
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* Still have no idea how to make TSO work on 8168C, 8168CP,
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* 8111C and 8111CP.
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*/
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if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
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ifp->if_hwassist |= CSUM_TSO;
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ifp->if_capabilities |= IFCAP_TSO4;
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}
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/*
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* Call MI attach routine.
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*/
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@ -1838,21 +1889,44 @@ re_rxeof(sc)
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/* Do RX checksumming if enabled */
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if (ifp->if_capenable & IFCAP_RXCSUM) {
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if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
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/* Check IP header checksum */
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if (rxstat & RL_RDESC_STAT_PROTOID)
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m->m_pkthdr.csum_flags |=
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CSUM_IP_CHECKED;
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if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
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m->m_pkthdr.csum_flags |=
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CSUM_IP_VALID;
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/* Check IP header checksum */
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if (rxstat & RL_RDESC_STAT_PROTOID)
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m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
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if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
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m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
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/* Check TCP/UDP checksum */
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if ((RL_TCPPKT(rxstat) &&
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!(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
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(RL_UDPPKT(rxstat) &&
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!(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
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m->m_pkthdr.csum_flags |=
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CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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/* Check TCP/UDP checksum */
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if ((RL_TCPPKT(rxstat) &&
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!(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
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(RL_UDPPKT(rxstat) &&
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!(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
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m->m_pkthdr.csum_flags |=
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CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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}
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} else {
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/*
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* RTL8168C/RTL816CP/RTL8111C/RTL8111CP
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*/
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if ((rxstat & RL_RDESC_STAT_PROTOID) &&
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(rxvlan & RL_RDESC_IPV4))
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m->m_pkthdr.csum_flags |=
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CSUM_IP_CHECKED;
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if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
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(rxvlan & RL_RDESC_IPV4))
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m->m_pkthdr.csum_flags |=
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CSUM_IP_VALID;
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if (((rxstat & RL_RDESC_STAT_TCP) &&
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!(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
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((rxstat & RL_RDESC_STAT_UDP) &&
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!(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
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m->m_pkthdr.csum_flags |=
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CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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}
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}
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}
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maxpkt--;
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@ -2154,7 +2228,8 @@ re_encap(sc, m_head)
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* offload is enabled, we always manually pad short frames out
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* to the minimum ethernet frame size.
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*/
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if ((*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
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if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 &&
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(*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
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((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
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padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
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if (M_WRITABLE(*m_head) == 0) {
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@ -2230,6 +2305,7 @@ re_encap(sc, m_head)
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* attempt. This is according to testing done with an 8169
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* chip. This is a requirement.
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*/
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vlanctl = 0;
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csum_flags = 0;
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if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0)
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csum_flags = RL_TDESC_CMD_LGSEND |
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@ -2242,11 +2318,23 @@ re_encap(sc, m_head)
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* does't make effects.
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*/
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if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
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csum_flags |= RL_TDESC_CMD_IPCSUM;
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if (((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) != 0)
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csum_flags |= RL_TDESC_CMD_TCPCSUM;
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if (((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) != 0)
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csum_flags |= RL_TDESC_CMD_UDPCSUM;
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if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
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csum_flags |= RL_TDESC_CMD_IPCSUM;
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if (((*m_head)->m_pkthdr.csum_flags &
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CSUM_TCP) != 0)
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csum_flags |= RL_TDESC_CMD_TCPCSUM;
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if (((*m_head)->m_pkthdr.csum_flags &
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CSUM_UDP) != 0)
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csum_flags |= RL_TDESC_CMD_UDPCSUM;
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} else {
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vlanctl |= RL_TDESC_CMD_IPCSUMV2;
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if (((*m_head)->m_pkthdr.csum_flags &
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CSUM_TCP) != 0)
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vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
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if (((*m_head)->m_pkthdr.csum_flags &
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CSUM_UDP) != 0)
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vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
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}
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}
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}
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@ -2255,16 +2343,14 @@ re_encap(sc, m_head)
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* appear in all descriptors of a multi-descriptor
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* transmission attempt.
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*/
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vlanctl = 0;
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if ((*m_head)->m_flags & M_VLANTAG)
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vlanctl =
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htole32(htons((*m_head)->m_pkthdr.ether_vtag) |
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RL_TDESC_VLANCTL_TAG);
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vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) |
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RL_TDESC_VLANCTL_TAG;
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si = prod;
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for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
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desc = &sc->rl_ldata.rl_tx_list[prod];
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desc->rl_vlanctl = vlanctl;
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desc->rl_vlanctl = htole32(vlanctl);
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desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
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desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
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cmdstat = segs[i].ds_len;
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@ -2440,8 +2526,13 @@ re_init_locked(sc)
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cfg |= RL_CPLUSCMD_RXCSUM_ENB;
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if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
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cfg |= RL_CPLUSCMD_VLANSTRIP;
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CSR_WRITE_2(sc, RL_CPLUS_CMD,
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cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB);
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if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
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cfg |= RL_CPLUSCMD_MACSTAT_DIS;
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/* XXX magic. */
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cfg |= 0x0001;
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} else
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cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
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CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
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/*
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* Init our MAC address. Even though the chipset
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@ -161,6 +161,9 @@
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#define RL_HWREV_8101E 0x34000000
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#define RL_HWREV_8168_SPIN2 0x38000000
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#define RL_HWREV_8168_SPIN3 0x38400000
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#define RL_HWREV_8168C 0x3C000000
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#define RL_HWREV_8168C_SPIN2 0x3C400000
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#define RL_HWREV_8168CP 0x3C800000
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#define RL_HWREV_8139 0x60000000
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#define RL_HWREV_8139A 0x70000000
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#define RL_HWREV_8139AG 0x70800000
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@ -442,6 +445,15 @@
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#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
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#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
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#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
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#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
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#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
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#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
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#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
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#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
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#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
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#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
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#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
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#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
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/* C+ early transmit threshold */
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@ -598,6 +610,10 @@ struct rl_desc {
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#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
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#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
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/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
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#define RL_TDESC_CMD_UDPCSUMV2 0x80000000
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#define RL_TDESC_CMD_TCPCSUMV2 0x40000000
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#define RL_TDESC_CMD_IPCSUMV2 0x20000000
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/*
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* Error bits are valid only on the last descriptor of a frame
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@ -635,6 +651,8 @@ struct rl_desc {
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#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
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#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
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#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
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#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
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#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
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#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
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#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
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#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
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@ -646,6 +664,9 @@ struct rl_desc {
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#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
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(rl_vlandata valid)*/
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#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
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/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
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#define RL_RDESC_IPV6 0x80000000
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#define RL_RDESC_IPV4 0x40000000
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#define RL_PROTOID_NONIP 0x00000000
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#define RL_PROTOID_TCPIP 0x00010000
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@ -812,6 +833,9 @@ struct rl_softc {
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#define RL_FLAG_INVMAR 0x0004
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#define RL_FLAG_PHYWAKE 0x0008
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#define RL_FLAG_NOJUMBO 0x0010
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#define RL_FLAG_PAR 0x0020
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#define RL_FLAG_DESCV2 0x0040
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#define RL_FLAG_MACSTAT 0x0080
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#define RL_FLAG_LINK 0x8000
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};
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