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synced 2026-05-28 04:12:45 -04:00
Add preliminary Yukon Extreme support and register definitions.
Yukon Extreme uses new descriptor format for TSO and has Tx frame parser which greatly reduces CPU cycles spent in computing TCP/UDP payload offset calculation in Tx checksum offloading path. The new descriptor format also removed TCP/UDP payload computation for TSO which in turn results in better TSO performance. It seems Yukon Extreme has a lot of new (unknown) features but only basic offloading is supported at this time. So far there are two known issues. o Sometimes Rx overrun errors happen when pulling data over gigabit link. Running over 100Mbps seem to ok. o Ethernet hardware address shows all-zeroed value on 88E8070. Assigning ethernet address with ifconfig is necessary to make it work. Support for Yukon Extreme is not perfect but it would be better than having a non-working device. Special thanks to jbh who fixed several bugs of initial patch. Tested by: jhb, Warren Block ( wblock <> wonkity dot com )
This commit is contained in:
Pyun YongHyeon
parent
e1cfcbcb4e
commit
daf292270b
2 changed files with 198 additions and 34 deletions
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@ -226,7 +226,7 @@ static struct msk_product {
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static const char *model_name[] = {
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"Yukon XL",
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"Yukon EC Ultra",
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"Yukon Unknown",
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"Yukon EX",
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"Yukon EC",
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"Yukon FE",
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"Yukon FE+"
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@ -1116,16 +1116,19 @@ msk_phy_power(struct msk_softc *sc, int mode)
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val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
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val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
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switch (sc->msk_hw_id) {
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case CHIP_ID_YUKON_XL:
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if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
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if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
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/* Deassert Low Power for 1st PHY. */
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val |= PCI_Y2_PHY1_COMA;
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if (sc->msk_num_port > 1)
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val |= PCI_Y2_PHY2_COMA;
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}
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break;
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}
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/* Release PHY from PowerDown/COMA mode. */
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pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
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switch (sc->msk_hw_id) {
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case CHIP_ID_YUKON_EC_U:
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case CHIP_ID_YUKON_EX:
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case CHIP_ID_YUKON_FE_P:
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CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
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@ -1136,14 +1139,22 @@ msk_phy_power(struct msk_softc *sc, int mode)
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PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
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/* Set all bits to 0 except bits 15..12. */
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pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
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/* Set to default value. */
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pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
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our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4);
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our &= PCI_CTL_TIM_VMAIN_AV_MSK;
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pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4);
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pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4);
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/*
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* Disable status race, workaround for
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* Yukon EC Ultra & Yukon EX.
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*/
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val = CSR_READ_4(sc, B2_GP_IO);
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val |= GLB_GPIO_STAT_RACE_DIS;
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CSR_WRITE_4(sc, B2_GP_IO, val);
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CSR_READ_4(sc, B2_GP_IO);
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break;
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default:
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break;
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}
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/* Release PHY from PowerDown/COMA mode. */
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pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
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for (i = 0; i < sc->msk_num_port; i++) {
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CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
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GMLC_RST_SET);
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@ -1194,10 +1205,18 @@ mskc_reset(struct msk_softc *sc)
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CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
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/* Disable ASF. */
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if (sc->msk_hw_id < CHIP_ID_YUKON_XL) {
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CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
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CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
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}
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if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
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status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
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/* Clear AHB bridge & microcontroller reset. */
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status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
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Y2_ASF_HCU_CCSR_CPU_RST_MODE);
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/* Clear ASF microcontroller state. */
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status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
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CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
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} else
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CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
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CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
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/*
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* Since we disabled ASF, S/W reset is required for Power Management.
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*/
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@ -1249,6 +1268,10 @@ mskc_reset(struct msk_softc *sc)
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CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
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CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
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CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
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if (sc->msk_hw_id == CHIP_ID_YUKON_EX)
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CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
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GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
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GMC_BYP_RETR_ON);
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}
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CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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@ -1651,6 +1674,10 @@ mskc_attach(device_t dev)
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sc->msk_clock = 125; /* 125 Mhz */
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sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
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break;
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case CHIP_ID_YUKON_EX:
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sc->msk_clock = 125; /* 125 Mhz */
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sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
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break;
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case CHIP_ID_YUKON_FE:
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sc->msk_clock = 100; /* 100 Mhz */
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sc->msk_pflags |= MSK_FLAG_FASTETHER;
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@ -3541,6 +3568,48 @@ done:
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CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
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}
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static void
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msk_set_tx_stfwd(struct msk_if_softc *sc_if)
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{
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struct msk_softc *sc;
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struct ifnet *ifp;
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ifp = sc_if->msk_ifp;
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sc = sc_if->msk_softc;
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switch (sc->msk_hw_id) {
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case CHIP_ID_YUKON_EX:
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if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
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goto yukon_ex_workaround;
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if (ifp->if_mtu > ETHERMTU)
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CSR_WRITE_4(sc,
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MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_ENA | TX_STFW_ENA);
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else
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CSR_WRITE_4(sc,
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MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_DIS | TX_STFW_ENA);
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break;
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default:
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yukon_ex_workaround:
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if (ifp->if_mtu > ETHERMTU) {
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/* Set Tx GMAC FIFO Almost Empty Threshold. */
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CSR_WRITE_4(sc,
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MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
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MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
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/* Disable Store & Forward mode for Tx. */
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CSR_WRITE_4(sc,
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MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_ENA | TX_STFW_DIS);
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} else {
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/* Enable Store & Forward mode for Tx. */
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CSR_WRITE_4(sc,
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MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_DIS | TX_STFW_ENA);
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}
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break;
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}
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}
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static void
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msk_init(void *xsc)
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{
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@ -3590,6 +3659,10 @@ msk_init_locked(struct msk_if_softc *sc_if)
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
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if (sc->msk_hw_id == CHIP_ID_YUKON_EX)
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
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GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
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GMC_BYP_RETR_ON);
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/*
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* Initialize GMAC first such that speed/duplex/flow-control
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@ -3642,7 +3715,8 @@ msk_init_locked(struct msk_if_softc *sc_if)
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
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reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
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if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P)
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if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
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sc->msk_hw_id == CHIP_ID_YUKON_EX)
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reg |= GMF_RX_OVER_ON;
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
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@ -3678,20 +3752,8 @@ msk_init_locked(struct msk_if_softc *sc_if)
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MSK_ECU_LLPP);
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CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
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MSK_ECU_ULPP);
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if (ifp->if_mtu > ETHERMTU) {
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/*
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* Set Tx GMAC FIFO Almost Empty Threshold.
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*/
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
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MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
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/* Disable Store & Forward mode for Tx. */
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_ENA | TX_STFW_DIS);
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} else {
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/* Enable Store & Forward mode for Tx. */
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
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TX_JUMBO_DIS | TX_STFW_ENA);
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}
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/* Configure store-and-forward for Tx. */
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msk_set_tx_stfwd(sc_if);
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}
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if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
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@ -225,6 +225,8 @@
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#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
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#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
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#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
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#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
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#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
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/* PCI Express Capability */
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#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
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@ -325,6 +327,56 @@
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#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
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#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
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/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
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/* Bit 31..27: for A3 & later */
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#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */
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#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
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#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
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#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
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#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
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#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
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/* Bit 26..16: Release Clock on Event */
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#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
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#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
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#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
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#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
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#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
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#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
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#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */
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#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
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#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
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#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
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#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
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/* Bit 10.. 0: Mask for Gate Clock */
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#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */
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#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
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#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
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#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
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#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
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#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
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#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
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#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
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#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
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#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
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#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
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/* PCI_CFG_REG_1 32 bit Config Register 1 */
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#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */
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/* Bit 23..21: Release Clock on Event */
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#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */
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#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */
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#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
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/* Bit 20..18: Gate Clock on Event */
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#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */
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#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
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#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
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#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
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#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
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#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */
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#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
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#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
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/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
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#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
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#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
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@ -621,6 +673,7 @@
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#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
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#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
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#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
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#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
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#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
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#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
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#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
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@ -830,6 +883,7 @@
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#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
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#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
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#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
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#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
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#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
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#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
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#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
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@ -848,6 +902,9 @@
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#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
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#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
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#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
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#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
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@ -912,6 +969,18 @@
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#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
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#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
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/* B2_GP_IO */
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#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */
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#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */
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#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
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#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */
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#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
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#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */
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#define GLB_GPIO_TEST_SEL_BASE BIT_11
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#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */
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||||
#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */
|
||||
|
||||
/* B2_I2C_CTRL 32 bit I2C HW Control Register */
|
||||
#define I2C_FLAG BIT_31 /* Start read/write if WR */
|
||||
#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
|
||||
|
|
@ -1033,13 +1102,16 @@
|
|||
/* Bit 10..0: same as for Rx */
|
||||
|
||||
/* Q_F 32 bit Flag Register */
|
||||
#define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
|
||||
#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
|
||||
#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
|
||||
#define F_WM_REACHED BIT_25 /* Watermark reached */
|
||||
#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
|
||||
#define F_FIFO_LEVEL (0x1f<<16) /* Bit 23..16: # of Qwords in FIFO */
|
||||
#define F_WATER_MARK 0x0007ff /* Bit 10.. 0: Watermark */
|
||||
#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
|
||||
#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
|
||||
#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */
|
||||
#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
|
||||
#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
|
||||
#define F_WM_REACHED BIT_25 /* Watermark reached */
|
||||
#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
|
||||
#define F_FIFO_LEVEL (0x1f<<16)
|
||||
/* Bit 23..16: # of Qwords in FIFO */
|
||||
#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
|
||||
|
||||
/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
|
||||
/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
|
||||
|
|
@ -1927,6 +1999,28 @@
|
|||
#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
|
||||
#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
|
||||
|
||||
/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */
|
||||
#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */
|
||||
#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */
|
||||
#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */
|
||||
#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */
|
||||
#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */
|
||||
#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */
|
||||
#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
|
||||
#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */
|
||||
/* Microcontroller State */
|
||||
#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3
|
||||
#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
|
||||
#define Y2_ASF_HCU_CCSR_ASF_RESET 0
|
||||
#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
|
||||
#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
|
||||
|
||||
/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
|
||||
/* This register is used by the ASF firmware */
|
||||
#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
|
||||
|
|
@ -1940,6 +2034,14 @@
|
|||
#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
|
||||
|
||||
/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
|
||||
#define GMC_SEC_RST BIT_15 /* MAC SEC RST */
|
||||
#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */
|
||||
#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
|
||||
#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */
|
||||
#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
|
||||
#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */
|
||||
#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */
|
||||
#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */
|
||||
#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
|
||||
#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
|
||||
#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
|
||||
|
|
|
|||
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Reference in a new issue