From da12fc2370b5b67cdfc7f52ff695e43c7239190b Mon Sep 17 00:00:00 2001
From: Andre Oppermann <andre@FreeBSD.org>
Date: Tue, 15 Nov 2005 20:18:13 +0000
Subject: [PATCH] Provide a link to the documentation of the I/O APIC at Intel.

---
 sys/i386/i386/io_apic.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sys/i386/i386/io_apic.c b/sys/i386/i386/io_apic.c
index ab426c73a80..e4f49c55a02 100644
--- a/sys/i386/i386/io_apic.c
+++ b/sys/i386/i386/io_apic.c
@@ -74,6 +74,10 @@ static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
  * IRQs behave as PCI IRQs by default.  We also assume that the pin for
  * IRQ 0 is actually an ExtINT pin.  The apic enumerators override the
  * configuration of individual pins as indicated by their tables.
+ *
+ * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
+ * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
+ * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
  */
 
 struct ioapic_intsrc {