From d9a80efdc2e69e9f2328b571ea679ea5df67baf1 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Mon, 7 Feb 2011 21:30:13 +0000 Subject: [PATCH] Add a new RMW macro for analog register writes which implements the needed wait period between operations. --- sys/dev/ath/ath_hal/ah_internal.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/dev/ath/ath_hal/ah_internal.h b/sys/dev/ath/ath_hal/ah_internal.h index f8c157db903..f3fd9e834c5 100644 --- a/sys/dev/ath/ath_hal/ah_internal.h +++ b/sys/dev/ath/ath_hal/ah_internal.h @@ -466,6 +466,10 @@ isBigEndian(void) #define OS_REG_CLR_BIT(_a, _r, _f) \ OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) +/* Analog register writes may require a delay between each one (eg Merlin?) */ +#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ + do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) + /* system-configurable parameters */ extern int ath_hal_dma_beacon_response_time; /* in TU's */ extern int ath_hal_sw_beacon_response_time; /* in TU's */