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Add registers for jz4780 audio and PDMA controllers.
Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
3af3efd115
commit
d9121bf564
2 changed files with 113 additions and 0 deletions
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sys/mips/ingenic/jz4780_aic.h
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74
sys/mips/ingenic/jz4780_aic.h
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define AICFR 0x00 /* AIC Configuration Register */
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#define AICFR_TFTH_S 16 /* Transmit FIFO threshold for interrupt or DMA request. */
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#define AICFR_TFTH_M (0x1f << AICFR_TFTH_S)
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#define AICFR_TFTH(x) ((x) << AICFR_TFTH_S)
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#define AICFR_RFTH_S 24 /* Receive FIFO threshold for interrupt or DMA request. */
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#define AICFR_RFTH_M (0x0f << AICFR_RFTH_S)
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#define AICFR_RFTH(x) ((x) << AICFR_RFTH_S)
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#define AICFR_ICDC (1 << 5) /* Internal CODEC used. */
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#define AICFR_AUSEL (1 << 4) /* Audio Unit Select */
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#define AICFR_RST (1 << 3) /* Reset AIC. */
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#define AICFR_BCKD (1 << 2) /* BIT_CLK Direction. */
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#define AICFR_SYNCD (1 << 1) /* SYNC is generated internally and driven out to the CODEC. */
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#define AICFR_ENB (1 << 0) /* Enable AIC Controller. */
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#define AICCR 0x04 /* AIC Common Control Register */
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#define AICCR_TFLUSH (1 << 8) /* Transmit FIFO Flush. */
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#define AICCR_RFLUSH (1 << 7) /* Receive FIFO Flush. */
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#define AICCR_CHANNEL_S 24
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#define AICCR_CHANNEL_M (0x7 << AICCR_CHANNEL_S)
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#define AICCR_CHANNEL_2 (0x1 << AICCR_CHANNEL_S) /* 2 channels, stereo */
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#define AICCR_ISS_S 16 /* Input Sample Size. */
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#define AICCR_ISS_M (0x7 << AICCR_ISS_S)
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#define AICCR_ISS_16 (0x1 << AICCR_ISS_S)
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#define AICCR_OSS_S 19 /* Output Sample Size. */
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#define AICCR_OSS_M (0x7 << AICCR_OSS_S)
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#define AICCR_OSS_16 (0x1 << AICCR_OSS_S)
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#define AICCR_RDMS (1 << 15) /* Receive DMA enable. */
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#define AICCR_TDMS (1 << 14) /* Transmit DMA enable. */
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#define AICCR_ENLBF (1 << 2) /* Enable AIC Loop Back Function. */
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#define AICCR_ERPL (1 << 1) /* Enable Playing Back function. */
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#define I2SCR 0x10 /* AIC I2S/MSB-justified Control */
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#define I2SCR_ESCLK (1 << 4) /* Enable SYSCLK output. */
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#define I2SCR_AMSL (1 << 0) /* Select MSB-Justified Operation Mode. */
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#define AICSR 0x14 /* AIC FIFO Status Register Register */
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#define I2SSR 0x1C /* AIC I2S/MSB-justified Status Register */
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#define I2SDIV 0x30 /* AIC I2S/MSB-justified Clock Divider Register */
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#define AICDR 0x34 /* AIC FIFO Data Port Register */
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#define SPENA 0x80 /* SPDIF Enable Register */
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#define SPCTRL 0x84 /* SPDIF Control Register */
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#define SPSTATE 0x88 /* SPDIF Status Register */
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#define SPCFG1 0x8C /* SPDIF Configure 1 Register */
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#define SPCFG2 0x90 /* SPDIF Configure 2 Register */
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#define SPFIFO 0x94 /* SPDIF FIFO Register */
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@ -35,13 +35,52 @@
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#define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */
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#define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */
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#define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */
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#define DRT_AUTO (1 << 3) /* Auto-request. */
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#define PDMA_DCS(n) (0x10 + 0x20 * n) /* Channel n Control/Status */
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#define DCS_DES8 (1 << 30) /* Descriptor 8 Word. */
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#define DCS_AR (1 << 4) /* Address Error. */
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#define DCS_TT (1 << 3) /* Transfer Terminate. */
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#define DCS_HLT (1 << 2) /* DMA halt. */
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#define DCS_CTE (1 << 0) /* Channel transfer enable. */
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#define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */
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#define DCM_SAI (1 << 23) /* Source Address Increment. */
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#define DCM_DAI (1 << 22) /* Destination Address Increment. */
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#define DCM_SP_S 14 /* Source port width. */
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#define DCM_SP_M (0x3 << DCM_SP_S)
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#define DCM_SP_1 (0x1 << DCM_SP_S) /* 1 byte */
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#define DCM_SP_2 (0x2 << DCM_SP_S) /* 2 bytes */
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#define DCM_SP_4 (0x0 << DCM_SP_S) /* 4 bytes */
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#define DCM_DP_S 12 /* Destination port width. */
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#define DCM_DP_M (0x3 << DCM_DP_S)
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#define DCM_DP_1 (0x1 << DCM_DP_S) /* 1 byte */
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#define DCM_DP_2 (0x2 << DCM_DP_S) /* 2 bytes */
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#define DCM_DP_4 (0x0 << DCM_DP_S) /* 4 bytes */
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#define DCM_TSZ_S 8 /* Transfer Data Size of a data unit. */
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#define DCM_TSZ_M (0x7 << DCM_TSZ_S)
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#define DCM_TSZ_1 (0x1 << DCM_TSZ_S)
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#define DCM_TSZ_2 (0x2 << DCM_TSZ_S)
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#define DCM_TSZ_4 (0x0 << DCM_TSZ_S)
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#define DCM_TSZ_16 (0x3 << DCM_TSZ_S)
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#define DCM_TSZ_32 (0x4 << DCM_TSZ_S)
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#define DCM_TSZ_64 (0x5 << DCM_TSZ_S)
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#define DCM_TSZ_128 (0x6 << DCM_TSZ_S)
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#define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE). */
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#define DCM_LINK (1 << 0) /* Descriptor Link Enable. */
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#define PDMA_DDA(n) (0x18 + 0x20 * n) /* Channel n Descriptor Address */
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#define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */
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/* Global Control Registers */
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#define PDMA_DMAC 0x1000 /* DMA Control */
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#define DMAC_FMSC (1 << 31)
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#define DMAC_INTCC_S 17
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#define DMAC_INTCC_M (0x1f << DMAC_INTCC_S)
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#define DMAC_INTCE (1 << 16) /* Permit INTC_IRQ to be bound to one of programmable channel. */
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#define DMAC_HLT (1 << 3) /* Global halt status */
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#define DMAC_AR (1 << 2) /* Global address error status */
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#define DMAC_DMAE (1 << 0) /* Enable DMA. */
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#define PDMA_DIRQP 0x1004 /* DMA Interrupt Pending */
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#define PDMA_DDB 0x1008 /* DMA Doorbell */
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#define PDMA_DDS 0x100C /* DMA Doorbell Set */
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