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arm64: make SPE regs use ALT_NAME macro
When the register is not defined in Armv8.0 i.e. added in a later
extension, like SPE added in v8.2, the alternative name format of:
S<op0>_<op1>_C<crn>_C<crm>_<op2>
should be used; otherwise, calls to {READ,WRITE}_SPECIALREG() will
fail.
Use the MRS_REG_ALT_NAME() macro for SPE changing hex to decimal as
required by the macro.
Reviewed by: andrew
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D45171
(cherry picked from commit f7bdaa103eb8906fc999c7fd5e8d6af440e26e6c)
This commit is contained in:
Zachary Leaf
Andrew Turner
parent
dd701489c8
commit
d8a9e188f2
1 changed files with 72 additions and 60 deletions
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@ -1636,11 +1636,12 @@
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/* PMBIDR_EL1 */
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#define PMBIDR_EL1 MRS_REG(PMBIDR_EL1)
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#define PMBIDR_EL1_op0 0x3
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#define PMBIDR_EL1_op1 0x0
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#define PMBIDR_EL1_CRn 0x9
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#define PMBIDR_EL1_CRm 0xa
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#define PMBIDR_EL1_op2 0x7
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#define PMBIDR_EL1_REG MRS_REG_ALT_NAME(PMBIDR_EL1)
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#define PMBIDR_EL1_op0 3
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#define PMBIDR_EL1_op1 0
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#define PMBIDR_EL1_CRn 9
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#define PMBIDR_EL1_CRm 10
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#define PMBIDR_EL1_op2 7
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#define PMBIDR_Align_SHIFT 0
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#define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT)
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#define PMBIDR_P_SHIFT 4
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@ -1650,11 +1651,12 @@
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/* PMBLIMITR_EL1 */
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#define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1)
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#define PMBLIMITR_EL1_op0 0x3
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#define PMBLIMITR_EL1_op1 0x0
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#define PMBLIMITR_EL1_CRn 0x9
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#define PMBLIMITR_EL1_CRm 0xa
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#define PMBLIMITR_EL1_op2 0x0
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#define PMBLIMITR_EL1_REG MRS_REG_ALT_NAME(PMBLIMITR_EL1)
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#define PMBLIMITR_EL1_op0 3
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#define PMBLIMITR_EL1_op1 0
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#define PMBLIMITR_EL1_CRn 9
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#define PMBLIMITR_EL1_CRm 10
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#define PMBLIMITR_EL1_op2 0
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#define PMBLIMITR_E_SHIFT 0
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#define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT)
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#define PMBLIMITR_FM_SHIFT 1
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@ -1667,22 +1669,24 @@
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/* PMBPTR_EL1 */
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#define PMBPTR_EL1 MRS_REG(PMBPTR_EL1)
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#define PMBPTR_EL1_op0 0x3
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#define PMBPTR_EL1_op1 0x0
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#define PMBPTR_EL1_CRn 0x9
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#define PMBPTR_EL1_CRm 0xa
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#define PMBPTR_EL1_op2 0x1
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#define PMBPTR_EL1_REG MRS_REG_ALT_NAME(PMBPTR_EL1)
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#define PMBPTR_EL1_op0 3
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#define PMBPTR_EL1_op1 0
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#define PMBPTR_EL1_CRn 9
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#define PMBPTR_EL1_CRm 10
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#define PMBPTR_EL1_op2 1
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#define PMBPTR_PTR_SHIFT 0
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#define PMBPTR_PTR_MASK \
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(UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
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/* PMBSR_EL1 */
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#define PMBSR_EL1 MRS_REG(PMBSR_EL1)
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#define PMBSR_EL1_op0 0x3
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#define PMBSR_EL1_op1 0x0
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#define PMBSR_EL1_CRn 0x9
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#define PMBSR_EL1_CRm 0xa
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#define PMBSR_EL1_op2 0x3
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#define PMBSR_EL1_REG MRS_REG_ALT_NAME(PMBSR_EL1)
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#define PMBSR_EL1_op0 3
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#define PMBSR_EL1_op1 0
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#define PMBSR_EL1_CRn 9
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#define PMBSR_EL1_CRm 10
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#define PMBSR_EL1_op2 3
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#define PMBSR_MSS_SHIFT 0
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#define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT)
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#define PMBSR_COLL_SHIFT 16
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@ -1848,11 +1852,12 @@
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/* PMSCR_EL1 */
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#define PMSCR_EL1 MRS_REG(PMSCR_EL1)
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#define PMSCR_EL1_op0 0x3
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#define PMSCR_EL1_op1 0x0
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#define PMSCR_EL1_CRn 0x9
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#define PMSCR_EL1_CRm 0x9
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#define PMSCR_EL1_op2 0x0
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#define PMSCR_EL1_REG MRS_REG_ALT_NAME(PMSCR_EL1)
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#define PMSCR_EL1_op0 3
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#define PMSCR_EL1_op1 0
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#define PMSCR_EL1_CRn 9
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#define PMSCR_EL1_CRm 9
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#define PMSCR_EL1_op2 0
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#define PMSCR_E0SPE_SHIFT 0
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#define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT)
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#define PMSCR_E1SPE_SHIFT 1
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@ -1877,19 +1882,21 @@
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/* PMSEVFR_EL1 */
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#define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1)
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#define PMSEVFR_EL1_op0 0x3
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#define PMSEVFR_EL1_op1 0x0
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#define PMSEVFR_EL1_CRn 0x9
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#define PMSEVFR_EL1_CRm 0x9
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#define PMSEVFR_EL1_op2 0x5
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#define PMSEVFR_EL1_REG MRS_REG_ALT_NAME(PMSEVFR_EL1)
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#define PMSEVFR_EL1_op0 3
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#define PMSEVFR_EL1_op1 0
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#define PMSEVFR_EL1_CRn 9
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#define PMSEVFR_EL1_CRm 9
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#define PMSEVFR_EL1_op2 5
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/* PMSFCR_EL1 */
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#define PMSFCR_EL1 MRS_REG(PMSFCR_EL1)
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#define PMSFCR_EL1_op0 0x3
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#define PMSFCR_EL1_op1 0x0
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#define PMSFCR_EL1_CRn 0x9
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#define PMSFCR_EL1_CRm 0x9
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#define PMSFCR_EL1_op2 0x4
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#define PMSFCR_EL1_REG MRS_REG_ALT_NAME(PMSFCR_EL1)
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#define PMSFCR_EL1_op0 3
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#define PMSFCR_EL1_op1 0
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#define PMSFCR_EL1_CRn 9
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#define PMSFCR_EL1_CRm 9
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#define PMSFCR_EL1_op2 4
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#define PMSFCR_FE_SHIFT 0
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#define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT)
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#define PMSFCR_FT_SHIFT 1
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@ -1907,11 +1914,12 @@
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/* PMSICR_EL1 */
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#define PMSICR_EL1 MRS_REG(PMSICR_EL1)
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#define PMSICR_EL1_op0 0x3
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#define PMSICR_EL1_op1 0x0
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#define PMSICR_EL1_CRn 0x9
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#define PMSICR_EL1_CRm 0x9
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#define PMSICR_EL1_op2 0x2
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#define PMSICR_EL1_REG MRS_REG_ALT_NAME(PMSICR_EL1)
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#define PMSICR_EL1_op0 3
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#define PMSICR_EL1_op1 0
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#define PMSICR_EL1_CRn 9
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#define PMSICR_EL1_CRm 9
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#define PMSICR_EL1_op2 2
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#define PMSICR_COUNT_SHIFT 0
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#define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT)
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#define PMSICR_ECOUNT_SHIFT 56
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@ -1919,11 +1927,12 @@
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/* PMSIDR_EL1 */
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#define PMSIDR_EL1 MRS_REG(PMSIDR_EL1)
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#define PMSIDR_EL1_op0 0x3
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#define PMSIDR_EL1_op1 0x0
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#define PMSIDR_EL1_CRn 0x9
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#define PMSIDR_EL1_CRm 0x9
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#define PMSIDR_EL1_op2 0x7
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#define PMSIDR_EL1_REG MRS_REG_ALT_NAME(PMSIDR_EL1)
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#define PMSIDR_EL1_op0 3
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#define PMSIDR_EL1_op1 0
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#define PMSIDR_EL1_CRn 9
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#define PMSIDR_EL1_CRm 9
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#define PMSIDR_EL1_op2 7
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#define PMSIDR_FE_SHIFT 0
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#define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT)
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#define PMSIDR_FT_SHIFT 1
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@ -1951,11 +1960,12 @@
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/* PMSIRR_EL1 */
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#define PMSIRR_EL1 MRS_REG(PMSIRR_EL1)
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#define PMSIRR_EL1_op0 0x3
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#define PMSIRR_EL1_op1 0x0
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#define PMSIRR_EL1_CRn 0x9
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#define PMSIRR_EL1_CRm 0x9
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#define PMSIRR_EL1_op2 0x3
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#define PMSIRR_EL1_REG MRS_REG_ALT_NAME(PMSIRR_EL1)
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#define PMSIRR_EL1_op0 3
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#define PMSIRR_EL1_op1 0
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#define PMSIRR_EL1_CRn 9
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#define PMSIRR_EL1_CRm 9
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#define PMSIRR_EL1_op2 3
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#define PMSIRR_RND_SHIFT 0
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#define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT)
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#define PMSIRR_INTERVAL_SHIFT 8
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@ -1963,21 +1973,23 @@
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/* PMSLATFR_EL1 */
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#define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1)
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#define PMSLATFR_EL1_op0 0x3
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#define PMSLATFR_EL1_op1 0x0
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#define PMSLATFR_EL1_CRn 0x9
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#define PMSLATFR_EL1_CRm 0x9
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#define PMSLATFR_EL1_op2 0x6
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#define PMSLATFR_EL1_REG MRS_REG_ALT_NAME(PMSLATFR_EL1)
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#define PMSLATFR_EL1_op0 3
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#define PMSLATFR_EL1_op1 0
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#define PMSLATFR_EL1_CRn 9
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#define PMSLATFR_EL1_CRm 9
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#define PMSLATFR_EL1_op2 6
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#define PMSLATFR_MINLAT_SHIFT 0
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#define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
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/* PMSNEVFR_EL1 */
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#define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1)
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#define PMSNEVFR_EL1_op0 0x3
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#define PMSNEVFR_EL1_op1 0x0
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#define PMSNEVFR_EL1_CRn 0x9
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#define PMSNEVFR_EL1_CRm 0x9
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#define PMSNEVFR_EL1_op2 0x1
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#define PMSNEVFR_EL1_REG MRS_REG_ALT_NAME(PMSNEVFR_EL1)
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#define PMSNEVFR_EL1_op0 3
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#define PMSNEVFR_EL1_op1 0
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#define PMSNEVFR_EL1_CRn 9
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#define PMSNEVFR_EL1_CRm 9
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#define PMSNEVFR_EL1_op2 1
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/* PMSWINC_EL0 */
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#define PMSWINC_EL0 MRS_REG(PMSWINC_EL0)
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