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o Work around bugs in the powerof2 macro: It thinks that 0 is a power of
2, but that's not the case. This fixes the case where there were slots in the PIR table that had no bits set, but we assumed they did and used strange results as a result. o Map invalid INTLINE registers to 255 in pci_cfgreg.c. This should allow us to remove the bogus checks in MI code for non-255 values. I put these changes out for review a while ago, but no one responded to them, so into current they go. This should help us work better on machines that don't route interrupts in the traditional way. MFC After: 4286 millifortnights
This commit is contained in:
Warner Losh
parent
e5d7e9c76c
commit
d5ccecfad7
3 changed files with 54 additions and 36 deletions
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@ -178,6 +178,7 @@ pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line, pin;
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#ifdef APIC_IO
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/*
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* If we are using the APIC, the contents of the intline register will probably
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@ -186,7 +187,6 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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* attempts to read them and translate to our private vector numbers.
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*/
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if ((reg == PCIR_INTLINE) && (bytes == 1)) {
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int pin, line;
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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@ -217,6 +217,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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}
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return(line);
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}
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#else
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. The rest of
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* the code uses 255 as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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if (pin != 0 && (line == 0 || line >= 128))
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return (255);
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}
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#endif /* APIC_IO */
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return(pci_do_cfgregread(bus, slot, func, reg, bytes));
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}
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@ -307,9 +319,11 @@ static int
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pci_cfgintr_unique(struct PIR_entry *pe, int pin)
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{
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int irq;
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uint32_t irqmask;
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if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
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irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
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irqmask = pe->pe_intpin[pin - 1].irqs;
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if (irqmask != 0 && powerof2(irqmask)) {
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irq = ffs(irqmask) - 1;
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PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
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return(irq);
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}
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@ -344,7 +358,7 @@ pci_cfgintr_linked(struct PIR_entry *pe, int pin)
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continue;
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/* link destination mapped to a unique interrupt? */
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if (powerof2(pi->irqs)) {
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if (pi->irqs != 0 && powerof2(pi->irqs)) {
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irq = ffs(pi->irqs) - 1;
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PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
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pi->link, irq));
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@ -394,14 +408,6 @@ pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int
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(pci_get_slot(*childp) == device) &&
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(pci_get_intpin(*childp) == matchpin)) {
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irq = pci_get_irq(*childp);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Once
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* we've found one that matches, we break because there can
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* be no others (which is why test looks a little odd).
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*/
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if (irq == 0)
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irq = 255;
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if (irq != 255)
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PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
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pe->pe_intpin[pin - 1].link, irq,
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@ -178,6 +178,7 @@ pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line, pin;
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#ifdef APIC_IO
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/*
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* If we are using the APIC, the contents of the intline register will probably
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@ -186,7 +187,6 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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* attempts to read them and translate to our private vector numbers.
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*/
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if ((reg == PCIR_INTLINE) && (bytes == 1)) {
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int pin, line;
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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@ -217,6 +217,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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}
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return(line);
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}
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#else
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. The rest of
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* the code uses 255 as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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if (pin != 0 && (line == 0 || line >= 128))
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return (255);
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}
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#endif /* APIC_IO */
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return(pci_do_cfgregread(bus, slot, func, reg, bytes));
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}
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@ -307,9 +319,11 @@ static int
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pci_cfgintr_unique(struct PIR_entry *pe, int pin)
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{
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int irq;
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uint32_t irqmask;
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if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
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irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
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irqmask = pe->pe_intpin[pin - 1].irqs;
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if (irqmask != 0 && powerof2(irqmask)) {
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irq = ffs(irqmask) - 1;
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PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
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return(irq);
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}
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@ -344,7 +358,7 @@ pci_cfgintr_linked(struct PIR_entry *pe, int pin)
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continue;
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/* link destination mapped to a unique interrupt? */
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if (powerof2(pi->irqs)) {
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if (pi->irqs != 0 && powerof2(pi->irqs)) {
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irq = ffs(pi->irqs) - 1;
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PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
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pi->link, irq));
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@ -394,14 +408,6 @@ pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int
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(pci_get_slot(*childp) == device) &&
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(pci_get_intpin(*childp) == matchpin)) {
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irq = pci_get_irq(*childp);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Once
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* we've found one that matches, we break because there can
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* be no others (which is why test looks a little odd).
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*/
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if (irq == 0)
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irq = 255;
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if (irq != 255)
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PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
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pe->pe_intpin[pin - 1].link, irq,
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@ -178,6 +178,7 @@ pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line, pin;
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#ifdef APIC_IO
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/*
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* If we are using the APIC, the contents of the intline register will probably
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@ -186,7 +187,6 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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* attempts to read them and translate to our private vector numbers.
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*/
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if ((reg == PCIR_INTLINE) && (bytes == 1)) {
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int pin, line;
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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@ -217,6 +217,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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}
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return(line);
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}
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#else
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. The rest of
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* the code uses 255 as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1);
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pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1);
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if (pin != 0 && (line == 0 || line >= 128))
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return (255);
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}
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#endif /* APIC_IO */
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return(pci_do_cfgregread(bus, slot, func, reg, bytes));
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}
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@ -307,9 +319,11 @@ static int
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pci_cfgintr_unique(struct PIR_entry *pe, int pin)
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{
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int irq;
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uint32_t irqmask;
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if (powerof2(pe->pe_intpin[pin - 1].irqs)) {
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irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1;
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irqmask = pe->pe_intpin[pin - 1].irqs;
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if (irqmask != 0 && powerof2(irqmask)) {
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irq = ffs(irqmask) - 1;
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PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
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return(irq);
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}
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@ -344,7 +358,7 @@ pci_cfgintr_linked(struct PIR_entry *pe, int pin)
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continue;
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/* link destination mapped to a unique interrupt? */
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if (powerof2(pi->irqs)) {
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if (pi->irqs != 0 && powerof2(pi->irqs)) {
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irq = ffs(pi->irqs) - 1;
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PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
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pi->link, irq));
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@ -394,14 +408,6 @@ pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int
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(pci_get_slot(*childp) == device) &&
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(pci_get_intpin(*childp) == matchpin)) {
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irq = pci_get_irq(*childp);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Once
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* we've found one that matches, we break because there can
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* be no others (which is why test looks a little odd).
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*/
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if (irq == 0)
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irq = 255;
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if (irq != 255)
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PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
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pe->pe_intpin[pin - 1].link, irq,
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