upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-06-09 08:43:19 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fill in feature control support:

Browse source 
o add definitions for more bits, for masking out IXP465-specific bits,
  and %b format string
o add ixp4xx_read_feature_bits to retrieve the mask of valid features
  (aka fuse bits)
o add cpu_is_ixp42x() macro
o print feature bits at boot
This commit is contained in:
Sam Leffler 2008-12-23 04:48:27 +00:00
parent b74f293f33
commit d463fa5387
3 changed files with 39 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
sys/arm/xscale/ixp425/ixp425.c
View file

@ -68,6 +68,21 @@ static int ixp425_probe(device_t);
static void ixp425_identify(driver_t *, device_t);
static int ixp425_attach(device_t);
/*
* Return a mask of the "fuse" bits that identify
* which h/w features are present.
* NB: assumes the expansion bus is mapped.
*/
uint32_t
ixp4xx_read_feature_bits(void)
{
uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET);
bits &= ~EXP_FCTRL_RESVD;
if (!cpu_is_ixp46x())
bits &= ~EXP_FCTRL_IXP46X_ONLY;
return bits;
}
struct arm32_dma_range *
bus_dma_get_range(void)
{
@ -190,6 +205,8 @@ ixp425_attach(device_t dev)
{
struct ixp425_softc *sc;
device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS);
sc = device_get_softc(dev);
sc->sc_iot = &ixp425_bs_tag;
KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__));

25
sys/arm/xscale/ixp425/ixp425reg.h
View file

@ -397,7 +397,7 @@
#define EXP_CNFG1_SW_INT1 (1 << 1)
#define EXP_FCTRL_RCOMP (1<<0)
#define EXP_FCTRL_USB (1<<1)
#define EXP_FCTRL_USB_DEVICE (1<<1)
#define EXP_FCTRL_HASH (1<<2)
#define EXP_FCTRL_AES (1<<3)
#define EXP_FCTRL_DES (1<<4)
@ -407,11 +407,26 @@
#define EXP_FCTRL_UTOPIA (1<<8)
#define EXP_FCTRL_ETH0 (1<<9)
#define EXP_FCTRL_ETH1 (1<<10)
#define EXP_FCTRL_NPEA (1<<11)
#define EXP_FCTRL_NPEB (1<<12)
#define EXP_FCTRL_NPEC (1<<13)
#define EXP_FCTRL_NPEA (1<<11) /* reset */
#define EXP_FCTRL_NPEB (1<<12) /* reset */
#define EXP_FCTRL_NPEC (1<<13) /* reset */
#define EXP_FCTRL_PCI (1<<14)
/* XXX more stuff we don't care about */
#define EXP_FCTRL_ECC_TIMESYNC (1<<15)
#define EXP_FCTRL_UTOPIA_PHY (3<<16) /* PHY limit */
#define EXP_FCTRL_USB_HOST (1<<18)
#define EXP_FCTRL_NPEA_ETH (1<<19)
#define EXP_FCTRL_NPEB_ETH (1<<20)
#define EXP_FCTRL_RSA (1<<21)
#define EXP_FCTRL_MAXFREQ (3<<22) /* XScale frequency */
#define EXP_FCTRL_RESVD (0xff<<24)
#define EXP_FCTRL_IXP46X_ONLY \
(EXP_FCTRL_ECC_TIMESYNC | EXP_FCTRL_USB_HOST | EXP_FCTRL_NPEA_ETH | \
EXP_FCTRL_NPEB_ETH | EXP_FCTRL_RSA | EXP_FCTRL_MAXFREQ)
#define EXP_FCTRL_BITS \
"\20\1RCOMP\2USB\3HASH\4AES\5DES\6HDLC\7AAL\10HSS\11UTOPIA\12ETH0" \
"\13ETH1\17PCI\20ECC\23USB_HOST\24NPEA_ETH\25NPEB_ETH\26RSA"
/*
* PCI

3
sys/arm/xscale/ixp425/ixp425var.h
View file

@ -48,6 +48,7 @@
#include <sys/rman.h>
/* NB: cputype is setup by set_cpufuncs */
#define cpu_is_ixp42x() (cputype == CPU_ID_IXP425)
#define cpu_is_ixp43x() (cputype == CPU_ID_IXP435)
#define cpu_is_ixp46x() (cputype == CPU_ID_IXP465)
@ -99,6 +100,7 @@ void ixp425_mem_bs_init(bus_space_tag_t, void *);
uint32_t ixp425_sdram_size(void);
uint32_t ixp435_ddram_size(void);
uint32_t ixp4xx_read_feature_bits(void);
int ixp425_md_route_interrupt(device_t, device_t, int);
void ixp425_md_attach(device_t);
@ -115,5 +117,4 @@ enum {
IXP425_IVAR_ADDR, /* base physical address */
IXP425_IVAR_IRQ /* irq/gpio pin assignment */
};
#endif /* _IXP425VAR_H_ */