mirror of
https://github.com/opnsense/src.git
synced 2026-06-11 09:41:03 -04:00
arm/mv: Remove pre-armv7 support
Armv4, Armv5, and Armv6 support has been removed. Remove the Marvell SoCs that used these cores. Reviewed by: cognet, imp Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D49497
This commit is contained in:
Andrew Turner
parent
c0dba117de
commit
d25a708ba7
9 changed files with 19 additions and 1053 deletions
File diff suppressed because it is too large
Load diff
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@ -36,23 +36,6 @@
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#include <arm/mv/mvwin.h>
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#if defined(SOC_MV_DISCOVERY)
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#define IRQ_CAUSE_ERROR 0x0
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#define IRQ_CAUSE 0x4
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#define IRQ_CAUSE_HI 0x8
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#define IRQ_MASK_ERROR 0xC
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#define IRQ_MASK 0x10
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#define IRQ_MASK_HI 0x14
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#define IRQ_CAUSE_SELECT 0x18
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#define FIQ_MASK_ERROR 0x1C
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#define FIQ_MASK 0x20
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#define FIQ_MASK_HI 0x24
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#define FIQ_CAUSE_SELECT 0x28
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#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
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#define ENDPOINT_IRQ_MASK(n) 0x30
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#define ENDPOINT_IRQ_MASK_HI(n) 0x34
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#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
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#else
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#define IRQ_CAUSE 0x0
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#define IRQ_MASK 0x4
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#define FIQ_MASK 0x8
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@ -64,7 +47,6 @@
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#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
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#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */
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#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
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#endif
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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@ -119,71 +101,16 @@
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/*
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* Power Control
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*/
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#if defined(SOC_MV_KIRKWOOD)
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#define CPU_PM_CTRL 0x18
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#else
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#define CPU_PM_CTRL 0x1C
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#endif
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#define CPU_PM_CTRL_NONE 0
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#define CPU_PM_CTRL_ALL ~0x0
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#if defined(SOC_MV_KIRKWOOD)
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#define CPU_PM_CTRL_GE0 (1 << 0)
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#define CPU_PM_CTRL_PEX0_PHY (1 << 1)
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#define CPU_PM_CTRL_PEX0 (1 << 2)
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#define CPU_PM_CTRL_USB0 (1 << 3)
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#define CPU_PM_CTRL_SDIO (1 << 4)
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#define CPU_PM_CTRL_TSU (1 << 5)
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#define CPU_PM_CTRL_DUNIT (1 << 6)
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#define CPU_PM_CTRL_RUNIT (1 << 7)
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#define CPU_PM_CTRL_XOR0 (1 << 8)
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#define CPU_PM_CTRL_AUDIO (1 << 9)
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#define CPU_PM_CTRL_SATA0 (1 << 14)
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#define CPU_PM_CTRL_SATA1 (1 << 15)
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#define CPU_PM_CTRL_XOR1 (1 << 16)
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#define CPU_PM_CTRL_CRYPTO (1 << 17)
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#define CPU_PM_CTRL_GE1 (1 << 19)
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#define CPU_PM_CTRL_TDM (1 << 20)
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#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
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#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0)
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
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(1 - (u)))
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#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
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#elif defined(SOC_MV_DISCOVERY)
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#define CPU_PM_CTRL_GE0 (1 << 1)
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#define CPU_PM_CTRL_GE1 (1 << 2)
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#define CPU_PM_CTRL_PEX00 (1 << 5)
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#define CPU_PM_CTRL_PEX01 (1 << 6)
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#define CPU_PM_CTRL_PEX02 (1 << 7)
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#define CPU_PM_CTRL_PEX03 (1 << 8)
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#define CPU_PM_CTRL_PEX10 (1 << 9)
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#define CPU_PM_CTRL_PEX11 (1 << 10)
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#define CPU_PM_CTRL_PEX12 (1 << 11)
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#define CPU_PM_CTRL_PEX13 (1 << 12)
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#define CPU_PM_CTRL_SATA0_PHY (1 << 13)
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#define CPU_PM_CTRL_SATA0 (1 << 14)
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#define CPU_PM_CTRL_SATA1_PHY (1 << 15)
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#define CPU_PM_CTRL_SATA1 (1 << 16)
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#define CPU_PM_CTRL_USB0 (1 << 17)
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#define CPU_PM_CTRL_USB1 (1 << 18)
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#define CPU_PM_CTRL_USB2 (1 << 19)
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#define CPU_PM_CTRL_IDMA (1 << 20)
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#define CPU_PM_CTRL_XOR (1 << 21)
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#define CPU_PM_CTRL_CRYPTO (1 << 22)
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#define CPU_PM_CTRL_DEVICE (1 << 23)
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#define CPU_PM_CTRL_USB(u) (1 << (17 + (u)))
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
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(1 - (u)))
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#else
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#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE)
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#endif
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/*
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* Timers
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@ -308,11 +235,6 @@
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#define MV_GPIO_OUT_OPEN_DRAIN 0x2
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#define MV_GPIO_OUT_OPEN_SRC 0x4
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#if defined(SOC_MV_ORION)
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#define SAMPLE_AT_RESET 0x10
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#elif defined(SOC_MV_KIRKWOOD)
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#define SAMPLE_AT_RESET 0x30
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#endif
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#define SAMPLE_AT_RESET_ARMADA38X 0x400
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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@ -320,13 +242,6 @@
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/*
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* Clocks
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*/
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#if defined(SOC_MV_ORION)
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#define TCLK_MASK 0x00000300
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#define TCLK_SHIFT 0x08
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#elif defined(SOC_MV_DISCOVERY)
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#define TCLK_MASK 0x00000180
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#define TCLK_SHIFT 0x07
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#endif
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#define TCLK_MASK_ARMADA38X 0x00008000
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#define TCLK_SHIFT_ARMADA38X 15
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@ -371,28 +286,14 @@
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/*
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* Chip ID
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*/
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#define MV_DEV_88F5181 0x5181
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#define MV_DEV_88F5182 0x5182
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#define MV_DEV_88F5281 0x5281
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#define MV_DEV_88F6281 0x6281
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#define MV_DEV_88F6282 0x6282
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#define MV_DEV_88F6781 0x6781
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#define MV_DEV_88F6828 0x6828
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#define MV_DEV_88F6820 0x6820
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#define MV_DEV_88F6810 0x6810
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#define MV_DEV_MV78100_Z0 0x6381
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#define MV_DEV_MV78100 0x7810
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#define MV_DEV_MV78130 0x7813
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#define MV_DEV_MV78160 0x7816
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#define MV_DEV_MV78230 0x7823
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#define MV_DEV_MV78260 0x7826
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#define MV_DEV_MV78460 0x7846
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#define MV_DEV_88RC8180 0x8180
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#define MV_DEV_88RC9480 0x9480
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#define MV_DEV_88RC9580 0x9580
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#define MV_DEV_FAMILY_MASK 0xff00
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#define MV_DEV_DISCOVERY 0x7800
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#define MV_DEV_ARMADA38X 0x6800
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/*
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@ -56,7 +56,6 @@
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enum soc_family{
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MV_SOC_ARMADA_38X = 0x00,
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MV_SOC_ARMADA_XP = 0x01,
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MV_SOC_ARMV5 = 0x02,
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MV_SOC_UNSUPPORTED = 0xff,
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};
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@ -84,7 +83,6 @@ extern int xor_wins_no;
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int soc_decode_win(void);
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void soc_id(uint32_t *dev, uint32_t *rev);
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void soc_dump_decode_win(void);
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uint32_t soc_power_ctrl_get(uint32_t mask);
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void soc_power_ctrl_set(uint32_t mask);
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int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
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@ -98,9 +96,7 @@ int ddr_is_active(int i);
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uint32_t ddr_base(int i);
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uint32_t ddr_size(int i);
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uint32_t ddr_attr(int i);
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uint32_t ddr_target(int i);
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uint32_t cpu_extra_feat(void);
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uint32_t get_tclk(void);
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uint32_t get_cpu_freq(void);
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uint32_t get_l2clk(void);
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@ -56,15 +56,7 @@
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* External devices: 0x80000000, 1 GB (VA == PA)
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* Includes Device Bus, PCI and PCIE.
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*/
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#if defined(SOC_MV_ORION)
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#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
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#elif defined(SOC_MV_KIRKWOOD)
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#define MV_PCI_PORTS 1 /* 1x PCIE */
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#elif defined(SOC_MV_DISCOVERY)
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#define MV_PCI_PORTS 8 /* 8x PCIE */
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#else
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#define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */
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#endif
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/* PCI/PCIE Memory */
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#define MV_PCI_MEM_PHYS_BASE 0x80000000
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@ -132,11 +124,7 @@
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#define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
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#define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CPU_MAX 14
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#else
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#define MV_WIN_CPU_MAX 8
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#endif
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#define MV_WIN_CPU_MAX_ARMV7 20
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#define MV_WIN_CPU_ATTR_SHIFT 8
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@ -154,13 +142,8 @@
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#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
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#define MV_WIN_DDR_TARGET 0x0
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CESA_TARGET 9
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#define MV_WIN_CESA_ATTR(eng_sel) 1
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#else
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#define MV_WIN_CESA_TARGET 3
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#define MV_WIN_CESA_ATTR(eng_sel) 0
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#endif
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#define MV_WIN_CESA_TARGET_ARMADAXP 9
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/*
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@ -227,19 +210,9 @@
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#define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
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#define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
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#define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
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#define MV_WIN_PCIE_IO_ATTR(n) 0xE0
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#elif defined(SOC_MV_ORION)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
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#define MV_WIN_PCIE_IO_ATTR(n) 0x51
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#else
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#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
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#endif
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#define MV_WIN_PCI_TARGET 3
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#define MV_WIN_PCI_MEM_ATTR 0x59
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@ -120,9 +120,7 @@ static int mv_timer_start(struct eventtimer *et,
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static int mv_timer_stop(struct eventtimer *et);
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static void mv_setup_timers(void);
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static void mv_watchdog_enable_armv5(void);
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static void mv_watchdog_enable_armadaxp(void);
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static void mv_watchdog_disable_armv5(void);
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static void mv_watchdog_disable_armadaxp(void);
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static void mv_delay(int usec, void* arg);
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@ -137,20 +135,9 @@ static struct mv_timer_config timer_armadaxp_config =
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IRQ_TIMER0_CLR_ARMADAXP,
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IRQ_TIMER_WD_CLR_ARMADAXP,
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};
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static struct mv_timer_config timer_armv5_config =
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{
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MV_SOC_ARMV5,
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&mv_watchdog_enable_armv5,
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&mv_watchdog_disable_armv5,
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0,
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BRIDGE_IRQ_CAUSE,
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IRQ_TIMER0_CLR,
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IRQ_TIMER_WD_CLR,
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};
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static struct ofw_compat_data mv_timer_soc_config[] = {
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{"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
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{"mrvl,timer", (uintptr_t)&timer_armv5_config },
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{NULL, (uintptr_t)NULL },
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};
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@ -380,28 +367,6 @@ mv_set_timer_rel(uint32_t timer, uint32_t val)
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timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
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}
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static void
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mv_watchdog_enable_armv5(void)
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{
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uint32_t val, irq_cause, irq_mask;
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irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
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irq_cause &= timer_softc->config->irq_timer_wd_clr;
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write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER_WD_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val |= WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_enable_armadaxp(void)
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{
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@ -424,28 +389,6 @@ mv_watchdog_enable_armadaxp(void)
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_disable_armv5(void)
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{
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uint32_t val, irq_cause,irq_mask;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val &= ~WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask &= ~(IRQ_TIMER_WD_MASK);
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
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irq_cause &= timer_softc->config->irq_timer_wd_clr;
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write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
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}
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static void
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mv_watchdog_disable_armadaxp(void)
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{
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@ -38,9 +38,6 @@ SOC_BRCM_BCM2837 opt_global.h
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SOC_IMX6 opt_global.h
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SOC_MV_ARMADAXP opt_global.h
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SOC_MV_ARMADA38X opt_global.h
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SOC_MV_DISCOVERY opt_global.h
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SOC_MV_KIRKWOOD opt_global.h
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SOC_MV_ORION opt_global.h
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SOC_OMAP3 opt_global.h
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SOC_OMAP4 opt_global.h
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SOC_TI_AM335X opt_global.h
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@ -1183,31 +1183,11 @@ cesa_attach_late(device_t dev)
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soc_id(&d, &r);
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switch (d) {
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case MV_DEV_88F6281:
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case MV_DEV_88F6282:
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/* Check if CESA peripheral device has power turned on */
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if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) ==
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CPU_PM_CTRL_CRYPTO) {
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device_printf(dev, "not powered on\n");
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return (ENXIO);
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}
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sc->sc_tperr = 0;
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break;
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case MV_DEV_88F6828:
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case MV_DEV_88F6820:
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case MV_DEV_88F6810:
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sc->sc_tperr = 0;
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break;
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case MV_DEV_MV78100:
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case MV_DEV_MV78100_Z0:
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/* Check if CESA peripheral device has power turned on */
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if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) !=
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CPU_PM_CTRL_CRYPTO) {
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device_printf(dev, "not powered on\n");
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return (ENXIO);
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}
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sc->sc_tperr = CESA_ICR_TPERR;
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break;
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default:
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return (ENXIO);
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}
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@ -398,33 +398,16 @@ mge_ver_params(struct mge_softc *sc)
|
|||
uint32_t d, r;
|
||||
|
||||
soc_id(&d, &r);
|
||||
if (d == MV_DEV_88F6281 || d == MV_DEV_88F6781 ||
|
||||
d == MV_DEV_88F6282 ||
|
||||
d == MV_DEV_MV78100 ||
|
||||
d == MV_DEV_MV78100_Z0 ||
|
||||
(d & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY) {
|
||||
sc->mge_ver = 2;
|
||||
sc->mge_mtu = 0x4e8;
|
||||
sc->mge_tfut_ipg_max = 0xFFFF;
|
||||
sc->mge_rx_ipg_max = 0xFFFF;
|
||||
sc->mge_tx_arb_cfg = 0xFC0000FF;
|
||||
sc->mge_tx_tok_cfg = 0xFFFF7FFF;
|
||||
sc->mge_tx_tok_cnt = 0x3FFFFFFF;
|
||||
} else {
|
||||
sc->mge_ver = 1;
|
||||
sc->mge_mtu = 0x458;
|
||||
sc->mge_tfut_ipg_max = 0x3FFF;
|
||||
sc->mge_rx_ipg_max = 0x3FFF;
|
||||
sc->mge_tx_arb_cfg = 0x000000FF;
|
||||
sc->mge_tx_tok_cfg = 0x3FFFFFFF;
|
||||
sc->mge_tx_tok_cnt = 0x3FFFFFFF;
|
||||
}
|
||||
if (d == MV_DEV_88RC8180)
|
||||
sc->mge_intr_cnt = 1;
|
||||
else
|
||||
sc->mge_intr_cnt = 2;
|
||||
sc->mge_ver = 1;
|
||||
sc->mge_mtu = 0x458;
|
||||
sc->mge_tfut_ipg_max = 0x3FFF;
|
||||
sc->mge_rx_ipg_max = 0x3FFF;
|
||||
sc->mge_tx_arb_cfg = 0x000000FF;
|
||||
sc->mge_tx_tok_cfg = 0x3FFFFFFF;
|
||||
sc->mge_tx_tok_cnt = 0x3FFFFFFF;
|
||||
sc->mge_intr_cnt = 2;
|
||||
|
||||
if (d == MV_DEV_MV78160 || d == MV_DEV_MV78260 || d == MV_DEV_MV78460)
|
||||
if (d == MV_DEV_MV78260 || d == MV_DEV_MV78460)
|
||||
sc->mge_hw_csum = 0;
|
||||
else
|
||||
sc->mge_hw_csum = 1;
|
||||
|
|
|
|||
|
|
@ -61,11 +61,6 @@ static struct {
|
|||
int ports;
|
||||
int quirks;
|
||||
} mvs_ids[] = {
|
||||
{MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC},
|
||||
{0, 0x00, NULL, 0, 0}
|
||||
|
|
|
|||
Loading…
Reference in a new issue