diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h index eee9e1a07ff..3563992e128 100644 --- a/sys/dev/cxgbe/adapter.h +++ b/sys/dev/cxgbe/adapter.h @@ -50,9 +50,6 @@ #include "offload.h" #include "firmware/t4fw_interface.h" -#define T4_CFGNAME "t4fw_cfg" -#define T4_FWNAME "t4fw" - MALLOC_DECLARE(M_CXGBE); #define CXGBE_UNIMPLEMENTED(s) \ panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) @@ -144,12 +141,6 @@ enum { TX_WR_FLITS = SGE_MAX_WR_LEN / 8 }; -#ifdef T4_PKT_TIMESTAMP -#define RX_COPY_THRESHOLD (MINCLSIZE - 8) -#else -#define RX_COPY_THRESHOLD MINCLSIZE -#endif - enum { /* adapter intr_type */ INTR_INTX = (1 << 0), @@ -327,6 +318,9 @@ enum { EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ }; +/* Listed in order of preference. Update t4_sysctls too if you change these */ +enum {DOORBELL_UDB, DOORBELL_WRWC, DOORBELL_UDBWC, DOORBELL_KDB}; + /* * Egress Queue: driver is producer, T4 is consumer. * @@ -344,6 +338,9 @@ struct sge_eq { struct tx_desc *desc; /* KVA of descriptor ring */ bus_addr_t ba; /* bus address of descriptor ring */ struct sge_qstat *spg; /* status page, for convenience */ + int doorbells; + volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ + u_int udb_qid; /* relative qid within the doorbell page */ uint16_t cap; /* max # of desc, for convenience */ uint16_t avail; /* available descriptors, for convenience */ uint16_t qsize; /* size (# of entries) of the queue */ @@ -496,6 +493,7 @@ struct sge { int timer_val[SGE_NTIMERS]; int counter_val[SGE_NCOUNTERS]; int fl_starve_threshold; + int s_qpp; int nrxq; /* total # of Ethernet rx queues */ int ntxq; /* total # of Ethernet tx tx queues */ @@ -541,6 +539,9 @@ struct adapter { bus_space_handle_t bh; bus_space_tag_t bt; bus_size_t mmio_len; + int udbs_rid; + struct resource *udbs_res; + volatile uint8_t *udbs_base; unsigned int pf; unsigned int mbox; @@ -570,6 +571,7 @@ struct adapter { struct l2t_data *l2t; /* L2 table */ struct tid_info tids; + int doorbells; int open_device_map; #ifdef TCP_OFFLOAD int offload_map; @@ -748,13 +750,15 @@ t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); } -static inline bool is_10G_port(const struct port_info *pi) +static inline bool +is_10G_port(const struct port_info *pi) { return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); } -static inline int tx_resume_threshold(struct sge_eq *eq) +static inline int +tx_resume_threshold(struct sge_eq *eq) { return (eq->qsize / 4); @@ -778,7 +782,9 @@ void end_synchronized_op(struct adapter *, int); /* t4_sge.c */ void t4_sge_modload(void); -int t4_sge_init(struct adapter *); +void t4_init_sge_cpl_handlers(struct adapter *); +void t4_tweak_chip_settings(struct adapter *); +int t4_read_chip_settings(struct adapter *); int t4_create_dma_tag(struct adapter *); int t4_destroy_dma_tag(struct adapter *); int t4_setup_adapter_queues(struct adapter *); diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h index ccd1195aa05..ce8a8d47de4 100644 --- a/sys/dev/cxgbe/common/common.h +++ b/sys/dev/cxgbe/common/common.h @@ -42,15 +42,19 @@ enum { MACADDR_LEN = 12, /* MAC Address length */ }; -enum { MEM_EDC0, MEM_EDC1, MEM_MC }; +enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; enum { MEMWIN0_APERTURE = 2048, MEMWIN0_BASE = 0x1b800, MEMWIN1_APERTURE = 32768, MEMWIN1_BASE = 0x28000, - MEMWIN2_APERTURE = 65536, - MEMWIN2_BASE = 0x30000, + + MEMWIN2_APERTURE_T4 = 65536, + MEMWIN2_BASE_T4 = 0x30000, + + MEMWIN2_APERTURE_T5 = 128 * 1024, + MEMWIN2_BASE_T5 = 0x60000, }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; @@ -63,15 +67,20 @@ enum { PAUSE_AUTONEG = 1 << 2 }; -#define FW_VERSION_MAJOR 1 -#define FW_VERSION_MINOR 8 -#define FW_VERSION_MICRO 4 -#define FW_VERSION_BUILD 0 +#define FW_VERSION_MAJOR_T4 1 +#define FW_VERSION_MINOR_T4 8 +#define FW_VERSION_MICRO_T4 4 +#define FW_VERSION_BUILD_T4 0 -#define FW_VERSION (V_FW_HDR_FW_VER_MAJOR(FW_VERSION_MAJOR) | \ - V_FW_HDR_FW_VER_MINOR(FW_VERSION_MINOR) | \ - V_FW_HDR_FW_VER_MICRO(FW_VERSION_MICRO) | \ - V_FW_HDR_FW_VER_BUILD(FW_VERSION_BUILD)) +#define FW_VERSION_MAJOR_T5 0 +#define FW_VERSION_MINOR_T5 5 +#define FW_VERSION_MICRO_T5 18 +#define FW_VERSION_BUILD_T5 0 + +struct memwin { + uint32_t base; + uint32_t aperture; +}; struct port_stats { u64 tx_octets; /* total # of octets in good frames */ @@ -267,18 +276,20 @@ struct adapter_params { unsigned int cim_la_size; - /* Used as int in sysctls, do not reduce size */ - unsigned int nports; /* # of ethernet ports */ - unsigned int portvec; - unsigned int rev; /* chip revision */ - unsigned int offload; + uint8_t nports; /* # of ethernet ports */ + uint8_t portvec; + unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ + unsigned int rev:4; /* chip revision */ + unsigned int fpga:1; /* this is an FPGA */ + unsigned int offload:1; /* hw is TOE capable, fw has divvied up card + resources for TOE operation. */ + unsigned int bypass:1; /* this is a bypass card */ unsigned int ofldq_wr_cred; }; -enum { /* chip revisions */ - T4_REV_A = 0, -}; +#define CHELSIO_T4 0x4 +#define CHELSIO_T5 0x5 struct trace_params { u32 data[TRACE_LEN / 4]; @@ -316,6 +327,31 @@ static inline int is_offload(const struct adapter *adap) return adap->params.offload; } +static inline int chip_id(struct adapter *adap) +{ + return adap->params.chipid; +} + +static inline int chip_rev(struct adapter *adap) +{ + return adap->params.rev; +} + +static inline int is_t4(struct adapter *adap) +{ + return adap->params.chipid == CHELSIO_T4; +} + +static inline int is_t5(struct adapter *adap) +{ + return adap->params.chipid == CHELSIO_T5; +} + +static inline int is_fpga(struct adapter *adap) +{ + return adap->params.fpga; +} + static inline unsigned int core_ticks_per_usec(const struct adapter *adap) { return adap->params.vpd.cclk / 1000; @@ -437,7 +473,8 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); -int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); +int t4_mc_read(struct adapter *adap, int idx, u32 addr, + __be32 *data, u64 *parity); int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, __be32 *data); diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c index e00e779c421..50e249063d7 100644 --- a/sys/dev/cxgbe/common/t4_hw.c +++ b/sys/dev/cxgbe/common/t4_hw.c @@ -312,6 +312,7 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, /** * t4_mc_read - read from MC through backdoor accesses * @adap: the adapter + * @idx: which MC to access * @addr: address of first byte requested * @data: 64 bytes of data containing the requested address * @ecc: where to store the corresponding 64-bit ECC word @@ -320,22 +321,40 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, * that covers the requested address @addr. If @parity is not %NULL it * is assigned the 64-bit ECC word for the read data. */ -int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) +int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; + u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; + u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; - if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST) + if (is_t4(adap)) { + mc_bist_cmd_reg = A_MC_BIST_CMD; + mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; + mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; + mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; + mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; + } else { + mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); + mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); + mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); + mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, + idx); + mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, + idx); + } + + if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) return -EBUSY; - t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU); - t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64); - t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc); - t4_write_reg(adap, A_MC_BIST_CMD, V_BIST_OPCODE(1) | F_START_BIST | - V_BIST_CMD_GAP(1)); - i = t4_wait_op_done(adap, A_MC_BIST_CMD, F_START_BIST, 0, 10, 1); + t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, mc_bist_cmd_len_reg, 64); + t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); + t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | + F_START_BIST | V_BIST_CMD_GAP(1)); + i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i) return i; -#define MC_DATA(i) MC_BIST_STATUS_REG(A_MC_BIST_STATUS_RDATA, i) +#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); @@ -360,20 +379,47 @@ int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; + u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; + u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; - idx *= EDC_STRIDE; - if (t4_read_reg(adap, A_EDC_BIST_CMD + idx) & F_START_BIST) + if (is_t4(adap)) { + edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, + idx); + } else { +/* + * These macro are missing in t4_regs.h file. + * Added temporarily for testing. + */ +#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) +#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) + edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, + idx); +#undef EDC_REG_T5 +#undef EDC_STRIDE_T5 + } + + if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) return -EBUSY; - t4_write_reg(adap, A_EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); - t4_write_reg(adap, A_EDC_BIST_CMD_LEN + idx, 64); - t4_write_reg(adap, A_EDC_BIST_DATA_PATTERN + idx, 0xc); - t4_write_reg(adap, A_EDC_BIST_CMD + idx, + t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, edc_bist_cmd_len_reg, 64); + t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); + t4_write_reg(adap, edc_bist_cmd_reg, V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); - i = t4_wait_op_done(adap, A_EDC_BIST_CMD + idx, F_START_BIST, 0, 10, 1); + i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i) return i; -#define EDC_DATA(i) (EDC_BIST_STATUS_REG(A_EDC_BIST_STATUS_RDATA, i) + idx) +#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); @@ -425,8 +471,8 @@ int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, /* * Read the chip's memory block and bail if there's an error. */ - if (mtype == MEM_MC) - ret = t4_mc_read(adap, pos, data, NULL); + if ((mtype == MEM_MC) || (mtype == MEM_MC1)) + ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); else ret = t4_edc_read(adap, mtype, pos, data, NULL); if (ret) @@ -464,7 +510,7 @@ struct t4_vpd_hdr { #define EEPROM_STAT_ADDR 0x7bfc #define VPD_BASE 0x400 #define VPD_BASE_OLD 0 -#define VPD_LEN 512 +#define VPD_LEN 1024 #define VPD_INFO_FLD_HDR_SIZE 3 /** @@ -914,6 +960,7 @@ int t4_get_tp_version(struct adapter *adapter, u32 *vers) int t4_check_fw_version(struct adapter *adapter) { int ret, major, minor, micro; + int exp_major, exp_minor, exp_micro; ret = t4_get_fw_version(adapter, &adapter->params.fw_vers); if (!ret) @@ -925,13 +972,30 @@ int t4_check_fw_version(struct adapter *adapter) minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers); micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers); - if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ - CH_ERR(adapter, "card FW has major version %u, driver wants " - "%u\n", major, FW_VERSION_MAJOR); + switch (chip_id(adapter)) { + case CHELSIO_T4: + exp_major = FW_VERSION_MAJOR_T4; + exp_minor = FW_VERSION_MINOR_T4; + exp_micro = FW_VERSION_MICRO_T4; + break; + case CHELSIO_T5: + exp_major = FW_VERSION_MAJOR_T5; + exp_minor = FW_VERSION_MINOR_T5; + exp_micro = FW_VERSION_MICRO_T5; + break; + default: + CH_ERR(adapter, "Unsupported chip type, %x\n", + chip_id(adapter)); return -EINVAL; } - if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) + if (major != exp_major) { /* major mismatch - fail */ + CH_ERR(adapter, "card FW has major version %u, driver wants " + "%u\n", major, exp_major); + return -EINVAL; + } + + if (minor == exp_minor && micro == exp_micro) return 0; /* perfect match */ /* Minor/micro version mismatch. Report it but often it's OK. */ @@ -1407,6 +1471,7 @@ out: void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) { unsigned int i, v; + int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; for (i = 0; i < CIM_NUM_IBQ; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | @@ -1416,7 +1481,7 @@ void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) *size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */ *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ } - for (i = 0; i < CIM_NUM_OBQ; i++) { + for (i = 0; i < cim_num_obq; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | V_QUENUMSELECT(i)); v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); @@ -1452,8 +1517,12 @@ int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) for (i = 0; i < n; i++, addr++) { t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | F_IBQDBGEN); + /* + * It might take 3-10ms before the IBQ debug read access is + * allowed. Wait for 1 Sec with a delay of 1 usec. + */ err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, - 2, 1); + 1000000, 1); if (err) return err; *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); @@ -1477,8 +1546,9 @@ int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) { int i, err; unsigned int addr, v, nwords; + int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; - if (qid > 5 || (n & 3)) + if (qid >= cim_num_obq || (n & 3)) return -EINVAL; t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | @@ -1933,6 +2003,47 @@ static void pcie_intr_handler(struct adapter *adapter) { 0 } }; + static struct intr_info t5_pcie_intr_info[] = { + { F_MSTGRPPERR, "Master Response Read Queue parity error", + -1, 1 }, + { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, + { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, + { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, + { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, + { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, + { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, + { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", + -1, 1 }, + { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", + -1, 1 }, + { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, + { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, + { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, + { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, + { F_DREQWRPERR, "PCI DMA channel write request parity error", + -1, 1 }, + { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, + { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, + { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, + { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, + { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, + { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, + { F_FIDPERR, "PCI FID parity error", -1, 1 }, + { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, + { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, + { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, + { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", + -1, 1 }, + { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", + -1, 1 }, + { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, + { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, + { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, + { F_READRSPERR, "Outbound read error", -1, + 0 }, + { 0 } + }; + int fat; fat = t4_handle_intr_status(adapter, @@ -1941,7 +2052,9 @@ static void pcie_intr_handler(struct adapter *adapter) t4_handle_intr_status(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, pcie_port_intr_info) + - t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, pcie_intr_info); + t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + is_t4(adapter) ? + pcie_intr_info : t5_pcie_intr_info); if (fat) t4_fatal_err(adapter); } @@ -2368,9 +2481,15 @@ static void ncsi_intr_handler(struct adapter *adap) */ static void xgmac_intr_handler(struct adapter *adap, int port) { - u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE)); + u32 v, int_cause_reg; - v &= F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; + if (is_t4(adap)) + int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); + else + int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); + + v = t4_read_reg(adap, int_cause_reg); + v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); if (!v) return; @@ -2378,7 +2497,7 @@ static void xgmac_intr_handler(struct adapter *adap, int port) CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port); if (v & F_RXFIFO_PRTY_ERR) CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port); - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v); + t4_write_reg(adap, int_cause_reg, v); t4_fatal_err(adap); } @@ -3531,7 +3650,10 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, int V_TFMINPKTSIZE(tp->min_len)); t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | - V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert)); + is_t4(adap) ? + V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert) : + V_T5_TFPORT(tp->port) | F_T5_TFEN | + V_T5_TFINVERTMATCH(tp->invert)); return 0; } @@ -3555,13 +3677,18 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); - *enabled = !!(ctla & F_TFEN); + if (is_t4(adap)) { + *enabled = !!(ctla & F_TFEN); + tp->port = G_TFPORT(ctla); + } else { + *enabled = !!(ctla & F_T5_TFEN); + tp->port = G_T5_TFPORT(ctla); + } tp->snap_len = G_TFCAPTUREMAX(ctlb); tp->min_len = G_TFMINPKTSIZE(ctlb); tp->skip_ofst = G_TFOFFSET(ctla); tp->skip_len = G_TFLENGTH(ctla); tp->invert = !!(ctla & F_TFINVERTMATCH); - tp->port = G_TFPORT(ctla); ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; @@ -3584,11 +3711,19 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + if (is_t4(adap)) + cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_TX_DBG_CTRL, + A_PM_TX_DBG_DATA, data, 2, + A_PM_TX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3603,11 +3738,19 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + if (is_t4(adap)) + cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_RX_DBG_CTRL, + A_PM_RX_DBG_DATA, data, 2, + A_PM_RX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3666,7 +3809,9 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) p->tx_pause = GET_STAT(TX_PORT_PAUSE); @@ -3745,13 +3890,19 @@ void t4_clr_port_stats(struct adapter *adap, int idx) { unsigned int i; u32 bgmap = get_mps_bg_map(adap, idx); + u32 port_base_addr; + + if (is_t4(adap)) + port_base_addr = PORT_BASE(idx); + else + port_base_addr = T5_PORT_BASE(idx); for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; - i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) + t4_write_reg(adap, port_base_addr + i, 0); for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; - i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) + t4_write_reg(adap, port_base_addr + i, 0); for (i = 0; i < 4; i++) if (bgmap & (1 << i)) { t4_write_reg(adap, @@ -3774,7 +3925,10 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap) ? \ + PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) p->octets = GET_STAT(BYTES); @@ -3791,8 +3945,7 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) p->frames_512_1023 = GET_STAT(512B_1023B); p->frames_1024_1518 = GET_STAT(1024B_1518B); p->frames_1519_max = GET_STAT(1519B_MAX); - p->drop = t4_read_reg(adap, PORT_REG(idx, - A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES)); + p->drop = GET_STAT(DROP_FRAMES); p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; @@ -3818,14 +3971,26 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr) { + u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; + + if (is_t4(adap)) { + mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); + mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); + port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); + } else { + mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); + mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); + port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); + } + if (addr) { - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO), + t4_write_reg(adap, mag_id_reg_l, (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]); - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI), + t4_write_reg(adap, mag_id_reg_h, (addr[0] << 8) | addr[1]); } - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), F_MAGICEN, + t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, V_MAGICEN(addr != NULL)); } @@ -3848,16 +4013,23 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, u64 mask0, u64 mask1, unsigned int crc, bool enable) { int i; + u32 port_cfg_reg; + + if (is_t4(adap)) + port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); + else + port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); if (!enable) { - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), - F_PATEN, 0); + t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); return 0; } if (map > 0xff) return -EINVAL; -#define EPIO_REG(name) PORT_REG(port, A_XGMAC_PORT_EPIO_##name) +#define EPIO_REG(name) \ + (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ + T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); t4_write_reg(adap, EPIO_REG(DATA2), mask1); @@ -3883,7 +4055,7 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, } #undef EPIO_REG - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), 0, F_PATEN); + t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); return 0; } @@ -4763,9 +4935,12 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, int offset, ret = 0; struct fw_vi_mac_cmd c; unsigned int nfilters = 0; + unsigned int max_naddr = is_t4(adap) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; unsigned int rem = naddr; - if (naddr > NUM_MPS_CLS_SRAM_L_INSTANCES) + if (naddr > max_naddr) return -EINVAL; for (offset = 0; offset < naddr ; /**/) { @@ -4806,10 +4981,10 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, u16 index = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); if (idx) - idx[offset+i] = (index >= NUM_MPS_CLS_SRAM_L_INSTANCES + idx[offset+i] = (index >= max_naddr ? 0xffff : index); - if (index < NUM_MPS_CLS_SRAM_L_INSTANCES) + if (index < max_naddr) nfilters++; else if (hash) *hash |= (1ULL << hash_mac_addr(addr[offset+i])); @@ -4853,6 +5028,9 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int ret, mode; struct fw_vi_mac_cmd c; struct fw_vi_mac_exact *p = c.u.exact; + unsigned int max_mac_addr = is_t4(adap) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; if (idx < 0) /* new allocation */ idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; @@ -4867,10 +5045,10 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, V_FW_VI_MAC_CMD_IDX(idx)); memcpy(p->macaddr, addr, sizeof(p->macaddr)); - ret = t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), &c); + ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); if (ret == 0) { ret = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); - if (ret >= NUM_MPS_CLS_SRAM_L_INSTANCES) + if (ret >= max_mac_addr) ret = -ENOMEM; } return ret; @@ -5188,21 +5366,6 @@ static void __devinit init_link_config(struct link_config *lc, } } -static int __devinit wait_dev_ready(struct adapter *adap) -{ - u32 whoami; - - whoami = t4_read_reg(adap, A_PL_WHOAMI); - - if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS) - return 0; - - msleep(500); - whoami = t4_read_reg(adap, A_PL_WHOAMI); - return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS - ? 0 : -EIO); -} - static int __devinit get_flash_params(struct adapter *adapter) { int ret; @@ -5255,21 +5418,26 @@ static void __devinit set_pcie_completion_timeout(struct adapter *adapter, int __devinit t4_prep_adapter(struct adapter *adapter) { int ret; - - ret = wait_dev_ready(adapter); - if (ret < 0) - return ret; + uint16_t device_id; + uint32_t pl_rev; get_pci_mode(adapter, &adapter->params.pci); - adapter->params.rev = t4_read_reg(adapter, A_PL_REV); - /* T4A1 chip is no longer supported */ - if (adapter->params.rev == 1) { - CH_ALERT(adapter, "T4 rev 1 chip is no longer supported\n"); - return -EINVAL; + pl_rev = t4_read_reg(adapter, A_PL_REV); + adapter->params.chipid = G_CHIPID(pl_rev); + adapter->params.rev = G_REV(pl_rev); + if (adapter->params.chipid == 0) { + /* T4 did not have chipid in PL_REV (T5 onwards do) */ + adapter->params.chipid = CHELSIO_T4; + + /* T4A1 chip is not supported */ + if (adapter->params.rev == 1) { + CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); + return -EINVAL; + } } adapter->params.pci.vpd_cap_addr = - t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); + t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); ret = get_flash_params(adapter); if (ret < 0) @@ -5279,12 +5447,14 @@ int __devinit t4_prep_adapter(struct adapter *adapter) if (ret < 0) return ret; - if (t4_read_reg(adapter, A_PCIE_REVISION) != 0) { - /* FPGA */ - adapter->params.cim_la_size = 2 * CIMLA_SIZE; - } else { - /* ASIC */ + /* Cards with real ASICs have the chipid in the PCIe device id */ + t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); + if (device_id >> 12 == adapter->params.chipid) adapter->params.cim_la_size = CIMLA_SIZE; + else { + /* FPGA */ + adapter->params.fpga = 1; + adapter->params.cim_la_size = 2 * CIMLA_SIZE; } init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h index acc383aaf62..8b94169c0d7 100644 --- a/sys/dev/cxgbe/common/t4_hw.h +++ b/sys/dev/cxgbe/common/t4_hw.h @@ -33,27 +33,32 @@ #include "osdep.h" enum { - NCHAN = 4, /* # of HW channels */ - MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ - EEPROMSIZE = 17408, /* Serial EEPROM physical size */ - EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ - EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ - RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ - TCB_SIZE = 128, /* TCB size */ - NMTUS = 16, /* size of MTU table */ - NCCTRL_WIN = 32, /* # of congestion control windows */ - NTX_SCHED = 8, /* # of HW Tx scheduling queues */ - PM_NSTATS = 5, /* # of PM stats */ - MBOX_LEN = 64, /* mailbox size in bytes */ - TRACE_LEN = 112, /* length of trace data and mask */ - FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ - NWOL_PAT = 8, /* # of WoL patterns */ - WOL_PAT_LEN = 128, /* length of WoL patterns */ + NCHAN = 4, /* # of HW channels */ + MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ + EEPROMSIZE = 17408, /* Serial EEPROM physical size */ + EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ + EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ + RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ + TCB_SIZE = 128, /* TCB size */ + NMTUS = 16, /* size of MTU table */ + NCCTRL_WIN = 32, /* # of congestion control windows */ + NTX_SCHED = 8, /* # of HW Tx scheduling queues */ + PM_NSTATS = 5, /* # of PM stats */ + MBOX_LEN = 64, /* mailbox size in bytes */ + TRACE_LEN = 112, /* length of trace data and mask */ + FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ + NWOL_PAT = 8, /* # of WoL patterns */ + WOL_PAT_LEN = 128, /* length of WoL patterns */ + UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ + UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ + UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ + UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ }; enum { CIM_NUM_IBQ = 6, /* # of CIM IBQs */ CIM_NUM_OBQ = 6, /* # of CIM OBQs */ + CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ @@ -80,6 +85,7 @@ enum { SGE_CTXT_SIZE = 24, /* size of SGE context */ SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ + SGE_MAX_IQ_SIZE = 65520, }; struct sge_qstat { /* data written to SGE queue status entries */ @@ -221,7 +227,7 @@ enum { * Location of firmware image in FLASH. */ FLASH_FW_START_SEC = 8, - FLASH_FW_NSECS = 8, + FLASH_FW_NSECS = 16, FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), diff --git a/sys/dev/cxgbe/common/t4_msg.h b/sys/dev/cxgbe/common/t4_msg.h index 2111d30ffb5..59880708979 100644 --- a/sys/dev/cxgbe/common/t4_msg.h +++ b/sys/dev/cxgbe/common/t4_msg.h @@ -104,6 +104,7 @@ enum { CPL_RX_ISCSI_DDP = 0x49, CPL_RX_FCOE_DIF = 0x4A, CPL_RX_DATA_DIF = 0x4B, + CPL_ERR_NOTIFY = 0x4D, CPL_RDMA_READ_REQ = 0x60, CPL_RX_ISCSI_DIF = 0x60, @@ -125,6 +126,7 @@ enum { CPL_RDMA_IMM_DATA_SE = 0xAD, CPL_TRACE_PKT = 0xB0, + CPL_TRACE_PKT_T5 = 0x48, CPL_RX2TX_DATA = 0xB1, CPL_ISCSI_DATA = 0xB2, CPL_FCOE_DATA = 0xB3, @@ -478,6 +480,11 @@ struct work_request_hdr { #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) +#define S_FILT_INFO 28 +#define M_FILT_INFO 0xfffffffffULL +#define V_FILT_INFO(x) ((x) << S_FILT_INFO) +#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) + /* option 2 fields */ #define S_RSS_QUEUE 0 #define M_RSS_QUEUE 0x3FF @@ -552,6 +559,10 @@ struct work_request_hdr { #define V_SACK_EN(x) ((x) << S_SACK_EN) #define F_SACK_EN V_SACK_EN(1U) +#define S_T5_OPT_2_VALID 31 +#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) +#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) + struct cpl_pass_open_req { WR_HDR; union opcode_tid ot; @@ -679,6 +690,10 @@ struct cpl_act_open_req { __be32 opt2; }; +#define S_FILTER_TUPLE 24 +#define M_FILTER_TUPLE 0xFFFFFFFFFF +#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) +#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) struct cpl_t5_act_open_req { WR_HDR; union opcode_tid ot; @@ -1053,6 +1068,12 @@ struct cpl_tx_pkt { #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) +#define S_TXPKT_T5_OVLAN_IDX 12 +#define M_TXPKT_T5_OVLAN_IDX 0x7 +#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) +#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ + M_TXPKT_T5_OVLAN_IDX) + #define S_TXPKT_INTF 16 #define M_TXPKT_INTF 0xF #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) @@ -1062,10 +1083,18 @@ struct cpl_tx_pkt { #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) +#define S_TXPKT_T5_FCS_DIS 21 +#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) +#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) + #define S_TXPKT_INS_OVLAN 21 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) +#define S_TXPKT_T5_INS_OVLAN 15 +#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) +#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) + #define S_TXPKT_STAT_DIS 22 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) @@ -1208,6 +1237,11 @@ struct cpl_tx_pkt_ufo { #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) +#define S_LSO_T5_XFER_SIZE 0 +#define M_LSO_T5_XFER_SIZE 0xFFFFFFF +#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) +#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) + /* cpl_tx_pkt_lso_core.mss fields */ #define S_LSO_MSS 0 #define M_LSO_MSS 0x3FFF @@ -1906,14 +1940,24 @@ struct cpl_l2t_write_req { #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) #define S_L2T_W_PORT 8 -#define M_L2T_W_PORT 0xF +#define M_L2T_W_PORT 0x3 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) +#define S_L2T_W_LPBK 10 +#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) +#define F_L2T_W_PKBK V_L2T_W_LPBK(1U) + +#define S_L2T_W_ARPMISS 11 +#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) +#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) + #define S_L2T_W_NOREPLY 15 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) +#define CPL_L2T_VLAN_NONE 0xfff + struct cpl_l2t_write_rpl { RSS_HDR union opcode_tid ot; @@ -2394,6 +2438,14 @@ struct ulp_mem_io { #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) +#define S_T5_ULP_MEMIO_IMM 23 +#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) +#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) + +#define S_T5_ULP_MEMIO_ORDER 22 +#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) +#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) + /* ulp_mem_io.lock_addr fields */ #define S_ULP_MEMIO_ADDR 0 #define M_ULP_MEMIO_ADDR 0x7FFFFFF @@ -2408,6 +2460,14 @@ struct ulp_mem_io { #define M_ULP_MEMIO_DATA_LEN 0x1F #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) +/* ULP_TXPKT field values */ +enum { + ULP_TXPKT_DEST_TP = 0, + ULP_TXPKT_DEST_SGE, + ULP_TXPKT_DEST_UP, + ULP_TXPKT_DEST_DEVNULL, +}; + struct ulp_txpkt { __be32 cmd_dest; __be32 len; diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h index dfe733b342b..f205298841f 100644 --- a/sys/dev/cxgbe/common/t4_regs.h +++ b/sys/dev/cxgbe/common/t4_regs.h @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2011 Chelsio Communications, Inc. + * Copyright (c) 2013 Chelsio Communications, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -60,6 +60,21 @@ #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) +#define VF_SGE_BASE 0x0 +#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr)) + +#define VF_MPS_BASE 0x100 +#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr)) + +#define VF_PL_BASE 0x200 +#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr)) + +#define VF_MBDATA_BASE 0x240 +#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) + +#define VF_CIM_BASE 0x300 +#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr)) + #define MYPORT_BASE 0x1c000 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) @@ -79,24 +94,6 @@ #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) -#define VF_SGE_BASE 0x0 -#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr)) - -#define VF_MPS_BASE 0x100 -#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr)) - -#define VF_PL_BASE 0x200 -#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr)) - -#define VF_MBDATA_BASE 0x240 -#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) - -#define VF_CIM_BASE 0x300 -#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr)) - -#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) -#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) - #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8) #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136 @@ -265,6 +262,115 @@ #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16 +#define T5_MYPORT_BASE 0x2c000 +#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) + +#define T5_PORT0_BASE 0x30000 +#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) + +#define T5_PORT1_BASE 0x34000 +#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr)) + +#define T5_PORT2_BASE 0x38000 +#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr)) + +#define T5_PORT3_BASE 0x3c000 +#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr)) + +#define T5_PORT_STRIDE 0x4000 +#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) +#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) + +#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) +#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) + +#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_PF_INT_INSTANCES 8 + +#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_VF_INT_INSTANCES 128 + +#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4) +#define NUM_PCIE_FID_VFID_INSTANCES 2048 + +#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_PCIE_COOKIE_INSTANCES 8 + +#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_DMA_INSTANCES 4 + +#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_CMD_INSTANCES 3 + +#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_HMA_INSTANCES 1 + +#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_PCIE_PHY_PRESET_INSTANCES 11 + +#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8) +#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 + +#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8) +#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512 + +#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4) +#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5 + +#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4) +#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5 + +#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5 + +#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12 + +#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5 + +#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12 + +#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5 + +#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5 + +#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5 + +#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) +#define NUM_MC_ADR_INSTANCES 2 + +#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) +#define NUM_MC_DDRPHY_DP18_INSTANCES 5 + +#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_CE_ERR_DATA_INSTANCES 8 + +#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_CE_COR_DATA_INSTANCES 8 + +#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_UE_ERR_DATA_INSTANCES 8 + +#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_UE_COR_DATA_INSTANCES 8 + +#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_P_BIST_STATUS_INSTANCES 18 + +#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_EDC_H_BIST_STATUS_INSTANCES 18 + +#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16 + +#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) +#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) + /* registers for module SGE */ #define SGE_BASE_ADDR 0x1000 @@ -285,6 +391,16 @@ #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX) #define A_SGE_VF_KDOORBELL 0x0 + +#define S_DBTYPE 13 +#define V_DBTYPE(x) ((x) << S_DBTYPE) +#define F_DBTYPE V_DBTYPE(1U) + +#define S_PIDX_T5 0 +#define M_PIDX_T5 0x1fffU +#define V_PIDX_T5(x) ((x) << S_PIDX_T5) +#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) + #define A_SGE_PF_GTS 0x4 #define S_INGRESSQID 16 @@ -307,6 +423,16 @@ #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC) #define A_SGE_VF_GTS 0x4 +#define A_SGE_PF_KTIMESTAMP_LO 0x8 +#define A_SGE_VF_KTIMESTAMP_LO 0x8 +#define A_SGE_PF_KTIMESTAMP_HI 0xc + +#define S_TSTAMPVAL 0 +#define M_TSTAMPVAL 0xfffffffU +#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL) +#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL) + +#define A_SGE_VF_KTIMESTAMP_HI 0xc #define A_SGE_CONTROL 0x1008 #define S_IGRALLCPLTOFL 31 @@ -663,6 +789,10 @@ #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP) #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U) +#define S_PERR_PC_CHPI_RSP2 31 +#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2) +#define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U) + #define A_SGE_INT_ENABLE1 0x1028 #define A_SGE_PERR_ENABLE1 0x102c #define A_SGE_INT_CAUSE2 0x1030 @@ -791,6 +921,22 @@ #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE) #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U) +#define S_PERR_DBP_HINT_FL_FIFO 24 +#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO) +#define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U) + +#define S_PERR_EGR_DBP_TX_COAL 23 +#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL) +#define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U) + +#define S_PERR_DBP_FL_FIFO 22 +#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO) +#define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U) + +#define S_PERR_PC_DBP2 15 +#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2) +#define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U) + #define A_SGE_INT_ENABLE2 0x1034 #define A_SGE_PERR_ENABLE2 0x1038 #define A_SGE_INT_CAUSE3 0x103c @@ -995,6 +1141,11 @@ #define V_NOEDRAM(x) ((x) << S_NOEDRAM) #define F_NOEDRAM V_NOEDRAM(1U) +#define S_CREDITCNTPACKING 2 +#define M_CREDITCNTPACKING 0x3U +#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING) +#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING) + #define A_SGE_CONM_CTRL 0x1094 #define S_EGRTHRESHOLD 8 @@ -1015,6 +1166,11 @@ #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE) #define F_TP_ENABLE V_TP_ENABLE(1U) +#define S_EGRTHRESHOLDPACKING 14 +#define M_EGRTHRESHOLDPACKING 0x3fU +#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING) +#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING) + #define A_SGE_TIMESTAMP_LO 0x1098 #define A_SGE_TIMESTAMP_HI 0x109c @@ -1072,6 +1228,24 @@ #define V_LP_COUNT(x) ((x) << S_LP_COUNT) #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) +#define S_BAR2VALID 31 +#define V_BAR2VALID(x) ((x) << S_BAR2VALID) +#define F_BAR2VALID V_BAR2VALID(1U) + +#define S_BAR2FULL 30 +#define V_BAR2FULL(x) ((x) << S_BAR2FULL) +#define F_BAR2FULL V_BAR2FULL(1U) + +#define S_LP_INT_THRESH_T5 18 +#define M_LP_INT_THRESH_T5 0xfffU +#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) +#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5) + +#define S_LP_COUNT_T5 0 +#define M_LP_COUNT_T5 0x3ffffU +#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5) +#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5) + #define A_SGE_DOORBELL_CONTROL 0x10a8 #define S_HINTDEPTHCTL 27 @@ -1153,6 +1327,23 @@ #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE) #define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U) +#define S_BAR2THROTTLECOUNT 16 +#define M_BAR2THROTTLECOUNT 0xffU +#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT) +#define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT) + +#define S_CLRCOALESCEDISABLE 15 +#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE) +#define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U) + +#define S_OPENBAR2GATEONCE 14 +#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE) +#define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U) + +#define S_FORCEOPENBAR2GATE 13 +#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE) +#define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U) + #define A_SGE_ITP_CONTROL 0x10b4 #define S_CRITICAL_TIME 10 @@ -1307,6 +1498,90 @@ #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER) #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U) +#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29 +#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR) +#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U) + +#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28 +#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1) +#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U) + +#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27 +#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0) +#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U) + +#define S_ERR_WR_LEN_TOO_LARGE3 26 +#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3) +#define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U) + +#define S_ERR_WR_LEN_TOO_LARGE2 25 +#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2) +#define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U) + +#define S_ERR_WR_LEN_TOO_LARGE1 24 +#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1) +#define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U) + +#define S_ERR_WR_LEN_TOO_LARGE0 23 +#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0) +#define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U) + +#define S_COAL_WITH_HP_DISABLE_ERR 18 +#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR) +#define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U) + +#define S_BAR2_EGRESS_COAL0_ERR 17 +#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR) +#define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U) + +#define S_BAR2_EGRESS_SIZE_ERR 16 +#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR) +#define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U) + +#define S_FLM_PC_RSP_ERR 15 +#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR) +#define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U) + +#define S_DBFIFO_HP_INT_LOW 14 +#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW) +#define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U) + +#define S_DBFIFO_LP_INT_LOW 13 +#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW) +#define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U) + +#define S_DBFIFO_FL_INT_LOW 12 +#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW) +#define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U) + +#define S_DBFIFO_FL_INT 11 +#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT) +#define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U) + +#define S_ERR_RX_CPL_PACKET_SIZE1 10 +#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1) +#define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U) + +#define S_ERR_RX_CPL_PACKET_SIZE0 9 +#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0) +#define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U) + #define A_SGE_INT_ENABLE4 0x10e0 #define A_SGE_STAT_TOTAL 0x10e4 #define A_SGE_STAT_MATCH 0x10e8 @@ -1336,6 +1611,11 @@ #define V_STATSOURCE(x) ((x) << S_STATSOURCE) #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE) +#define S_STATSOURCE_T5 9 +#define M_STATSOURCE_T5 0xfU +#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) +#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5) + #define A_SGE_HINT_CFG 0x10f0 #define S_HINTSALLOWEDNOHDR 6 @@ -1348,6 +1628,11 @@ #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR) #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR) +#define S_UPCUTOFFTHRESHLP 12 +#define M_UPCUTOFFTHRESHLP 0x7ffU +#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP) +#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP) + #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8 #define A_SGE_PD_WRR_CONFIG 0x10fc @@ -1372,6 +1657,16 @@ #define V_ERROR_QID(x) ((x) << S_ERROR_QID) #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID) +#define S_CAUSE_REGISTER 24 +#define M_CAUSE_REGISTER 0x7U +#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER) +#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER) + +#define S_CAUSE_BIT 19 +#define M_CAUSE_BIT 0x1fU +#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT) +#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT) + #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104 #define S_MINTAG3 24 @@ -1401,6 +1696,403 @@ #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL) #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL) +#define A_SGE_INT_CAUSE5 0x110c + +#define S_ERR_T_RXCRC 31 +#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC) +#define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U) + +#define S_PERR_MC_RSPDATA 30 +#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA) +#define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U) + +#define S_PERR_PC_RSPDATA 29 +#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA) +#define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U) + +#define S_PERR_PD_RDRSPDATA 28 +#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA) +#define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U) + +#define S_PERR_U_RXDATA 27 +#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA) +#define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U) + +#define S_PERR_UD_RXDATA 26 +#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA) +#define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U) + +#define S_PERR_UP_DATA 25 +#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA) +#define F_PERR_UP_DATA V_PERR_UP_DATA(1U) + +#define S_PERR_CIM2SGE_RXDATA 24 +#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA) +#define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U) + +#define S_PERR_HINT_DELAY_FIFO1_T5 23 +#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5) +#define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U) + +#define S_PERR_HINT_DELAY_FIFO0_T5 22 +#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5) +#define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U) + +#define S_PERR_IMSG_PD_FIFO_T5 21 +#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5) +#define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U) + +#define S_PERR_ULPTX_FIFO1_T5 20 +#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5) +#define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U) + +#define S_PERR_ULPTX_FIFO0_T5 19 +#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5) +#define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U) + +#define S_PERR_IDMA2IMSG_FIFO1_T5 18 +#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5) +#define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U) + +#define S_PERR_IDMA2IMSG_FIFO0_T5 17 +#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5) +#define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U) + +#define S_PERR_POINTER_DATA_FIFO0 16 +#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0) +#define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U) + +#define S_PERR_POINTER_DATA_FIFO1 15 +#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1) +#define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U) + +#define S_PERR_POINTER_HDR_FIFO0 14 +#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0) +#define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U) + +#define S_PERR_POINTER_HDR_FIFO1 13 +#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1) +#define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U) + +#define S_PERR_PAYLOAD_FIFO0 12 +#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0) +#define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U) + +#define S_PERR_PAYLOAD_FIFO1 11 +#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1) +#define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U) + +#define S_PERR_EDMA_INPUT_FIFO3 10 +#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3) +#define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U) + +#define S_PERR_EDMA_INPUT_FIFO2 9 +#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2) +#define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U) + +#define S_PERR_EDMA_INPUT_FIFO1 8 +#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1) +#define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U) + +#define S_PERR_EDMA_INPUT_FIFO0 7 +#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0) +#define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U) + +#define S_PERR_MGT_BAR2_FIFO 6 +#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO) +#define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U) + +#define S_PERR_HEADERSPLIT_FIFO1_T5 5 +#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5) +#define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U) + +#define S_PERR_HEADERSPLIT_FIFO0_T5 4 +#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5) +#define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U) + +#define S_PERR_CIM_FIFO1 3 +#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1) +#define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U) + +#define S_PERR_CIM_FIFO0 2 +#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0) +#define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U) + +#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1 +#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1) +#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U) + +#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0 +#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0) +#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U) + +#define A_SGE_INT_ENABLE5 0x1110 +#define A_SGE_PERR_ENABLE5 0x1114 +#define A_SGE_DBFIFO_STATUS2 0x1118 + +#define S_FL_INT_THRESH 24 +#define M_FL_INT_THRESH 0xfU +#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH) +#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH) + +#define S_FL_COUNT 14 +#define M_FL_COUNT 0x3ffU +#define V_FL_COUNT(x) ((x) << S_FL_COUNT) +#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT) + +#define S_HP_INT_THRESH_T5 10 +#define M_HP_INT_THRESH_T5 0xfU +#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) +#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5) + +#define S_HP_COUNT_T5 0 +#define M_HP_COUNT_T5 0x3ffU +#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5) +#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5) + +#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c + +#define S_FETCHBURSTMAX0 16 +#define M_FETCHBURSTMAX0 0x3ffU +#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0) +#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0) + +#define S_FETCHBURSTMAX1 0 +#define M_FETCHBURSTMAX1 0x3ffU +#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1) +#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1) + +#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120 + +#define S_FETCHBURSTMAX2 16 +#define M_FETCHBURSTMAX2 0x3ffU +#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2) +#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2) + +#define S_FETCHBURSTMAX3 0 +#define M_FETCHBURSTMAX3 0x3ffU +#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3) +#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3) + +#define A_SGE_CONTROL2 0x1124 + +#define S_UPFLCUTOFFDIS 21 +#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS) +#define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U) + +#define S_RXCPLSIZEAUTOCORRECT 20 +#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT) +#define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U) + +#define S_IDMAARBROUNDROBIN 19 +#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN) +#define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U) + +#define S_INGPACKBOUNDARY 16 +#define M_INGPACKBOUNDARY 0x7U +#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY) +#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY) + +#define S_CGEN_EGRESS_CONTEXT 15 +#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT) +#define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U) + +#define S_CGEN_INGRESS_CONTEXT 14 +#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT) +#define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U) + +#define S_CGEN_IDMA 13 +#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA) +#define F_CGEN_IDMA V_CGEN_IDMA(1U) + +#define S_CGEN_DBP 12 +#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP) +#define F_CGEN_DBP V_CGEN_DBP(1U) + +#define S_CGEN_EDMA 11 +#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA) +#define F_CGEN_EDMA V_CGEN_EDMA(1U) + +#define S_VFIFO_ENABLE 10 +#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE) +#define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U) + +#define S_FLM_RESCHEDULE_MODE 9 +#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE) +#define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U) + +#define S_HINTDEPTHCTLFL 4 +#define M_HINTDEPTHCTLFL 0x1fU +#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL) +#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL) + +#define S_FORCE_ORDERING 3 +#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING) +#define F_FORCE_ORDERING V_FORCE_ORDERING(1U) + +#define S_TX_COALESCE_SIZE 2 +#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE) +#define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U) + +#define S_COAL_STRICT_CIM_PRI 1 +#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI) +#define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U) + +#define S_TX_COALESCE_PRI 0 +#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI) +#define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U) + +#define A_SGE_DEEP_SLEEP 0x1128 + +#define S_IDMA1_SLEEP_STATUS 11 +#define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS) +#define F_IDMA1_SLEEP_STATUS V_IDMA1_SLEEP_STATUS(1U) + +#define S_IDMA0_SLEEP_STATUS 10 +#define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS) +#define F_IDMA0_SLEEP_STATUS V_IDMA0_SLEEP_STATUS(1U) + +#define S_IDMA1_SLEEP_REQ 9 +#define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ) +#define F_IDMA1_SLEEP_REQ V_IDMA1_SLEEP_REQ(1U) + +#define S_IDMA0_SLEEP_REQ 8 +#define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ) +#define F_IDMA0_SLEEP_REQ V_IDMA0_SLEEP_REQ(1U) + +#define S_EDMA3_SLEEP_STATUS 7 +#define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS) +#define F_EDMA3_SLEEP_STATUS V_EDMA3_SLEEP_STATUS(1U) + +#define S_EDMA2_SLEEP_STATUS 6 +#define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS) +#define F_EDMA2_SLEEP_STATUS V_EDMA2_SLEEP_STATUS(1U) + +#define S_EDMA1_SLEEP_STATUS 5 +#define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS) +#define F_EDMA1_SLEEP_STATUS V_EDMA1_SLEEP_STATUS(1U) + +#define S_EDMA0_SLEEP_STATUS 4 +#define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS) +#define F_EDMA0_SLEEP_STATUS V_EDMA0_SLEEP_STATUS(1U) + +#define S_EDMA3_SLEEP_REQ 3 +#define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ) +#define F_EDMA3_SLEEP_REQ V_EDMA3_SLEEP_REQ(1U) + +#define S_EDMA2_SLEEP_REQ 2 +#define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ) +#define F_EDMA2_SLEEP_REQ V_EDMA2_SLEEP_REQ(1U) + +#define S_EDMA1_SLEEP_REQ 1 +#define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ) +#define F_EDMA1_SLEEP_REQ V_EDMA1_SLEEP_REQ(1U) + +#define S_EDMA0_SLEEP_REQ 0 +#define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ) +#define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U) + +#define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c + +#define S_THROTTLE_THRESHOLD_FL 16 +#define M_THROTTLE_THRESHOLD_FL 0xfU +#define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL) +#define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL) + +#define S_THROTTLE_THRESHOLD_HP 12 +#define M_THROTTLE_THRESHOLD_HP 0xfU +#define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP) +#define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP) + +#define S_THROTTLE_THRESHOLD_LP 0 +#define M_THROTTLE_THRESHOLD_LP 0xfffU +#define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP) +#define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP) + +#define A_SGE_DBP_FETCH_THRESHOLD 0x1130 + +#define S_DBP_FETCH_THRESHOLD_FL 21 +#define M_DBP_FETCH_THRESHOLD_FL 0xfU +#define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL) +#define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL) + +#define S_DBP_FETCH_THRESHOLD_HP 17 +#define M_DBP_FETCH_THRESHOLD_HP 0xfU +#define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP) +#define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP) + +#define S_DBP_FETCH_THRESHOLD_LP 5 +#define M_DBP_FETCH_THRESHOLD_LP 0xfffU +#define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP) +#define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP) + +#define S_DBP_FETCH_THRESHOLD_MODE 4 +#define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE) +#define F_DBP_FETCH_THRESHOLD_MODE V_DBP_FETCH_THRESHOLD_MODE(1U) + +#define S_DBP_FETCH_THRESHOLD_EN3 3 +#define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3) +#define F_DBP_FETCH_THRESHOLD_EN3 V_DBP_FETCH_THRESHOLD_EN3(1U) + +#define S_DBP_FETCH_THRESHOLD_EN2 2 +#define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2) +#define F_DBP_FETCH_THRESHOLD_EN2 V_DBP_FETCH_THRESHOLD_EN2(1U) + +#define S_DBP_FETCH_THRESHOLD_EN1 1 +#define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1) +#define F_DBP_FETCH_THRESHOLD_EN1 V_DBP_FETCH_THRESHOLD_EN1(1U) + +#define S_DBP_FETCH_THRESHOLD_EN0 0 +#define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0) +#define F_DBP_FETCH_THRESHOLD_EN0 V_DBP_FETCH_THRESHOLD_EN0(1U) + +#define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134 + +#define S_DBP_FETCH_THRESHOLD_IQ1 16 +#define M_DBP_FETCH_THRESHOLD_IQ1 0xffffU +#define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1) +#define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1) + +#define S_DBP_FETCH_THRESHOLD_IQ0 0 +#define M_DBP_FETCH_THRESHOLD_IQ0 0xffffU +#define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0) +#define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0) + +#define A_SGE_DBVFIFO_BADDR 0x1138 +#define A_SGE_DBVFIFO_SIZE 0x113c + +#define S_DBVFIFO_SIZE 6 +#define M_DBVFIFO_SIZE 0xfffU +#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE) +#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE) + +#define A_SGE_DBFIFO_STATUS3 0x1140 + +#define S_LP_PTRS_EQUAL 21 +#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL) +#define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U) + +#define S_LP_SNAPHOT 20 +#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT) +#define F_LP_SNAPHOT V_LP_SNAPHOT(1U) + +#define S_FL_INT_THRESH_LOW 16 +#define M_FL_INT_THRESH_LOW 0xfU +#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW) +#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW) + +#define S_HP_INT_THRESH_LOW 12 +#define M_HP_INT_THRESH_LOW 0xfU +#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW) +#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW) + +#define S_LP_INT_THRESH_LOW 0 +#define M_LP_INT_THRESH_LOW 0xfffU +#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW) +#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW) + +#define A_SGE_CHANGESET 0x1144 +#define A_SGE_PC_RSP_ERROR 0x1148 #define A_SGE_PC0_REQ_BIST_CMD 0x1180 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184 #define A_SGE_PC1_REQ_BIST_CMD 0x1190 @@ -1446,6 +2138,891 @@ #define A_SGE_CTXT_MASK5 0x1234 #define A_SGE_CTXT_MASK6 0x1238 #define A_SGE_CTXT_MASK7 0x123c +#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280 + +#define S_CIM_WM 24 +#define M_CIM_WM 0x3U +#define V_CIM_WM(x) ((x) << S_CIM_WM) +#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM) + +#define S_DEBUG_UP_SOP_CNT 20 +#define M_DEBUG_UP_SOP_CNT 0xfU +#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT) +#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT) + +#define S_DEBUG_UP_EOP_CNT 16 +#define M_DEBUG_UP_EOP_CNT 0xfU +#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT) +#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT) + +#define S_DEBUG_CIM_SOP1_CNT 12 +#define M_DEBUG_CIM_SOP1_CNT 0xfU +#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT) +#define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT) + +#define S_DEBUG_CIM_EOP1_CNT 8 +#define M_DEBUG_CIM_EOP1_CNT 0xfU +#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT) +#define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT) + +#define S_DEBUG_CIM_SOP0_CNT 4 +#define M_DEBUG_CIM_SOP0_CNT 0xfU +#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT) +#define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT) + +#define S_DEBUG_CIM_EOP0_CNT 0 +#define M_DEBUG_CIM_EOP0_CNT 0xfU +#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT) +#define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284 + +#define S_DEBUG_T_RX_SOP1_CNT 28 +#define M_DEBUG_T_RX_SOP1_CNT 0xfU +#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT) +#define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT) + +#define S_DEBUG_T_RX_EOP1_CNT 24 +#define M_DEBUG_T_RX_EOP1_CNT 0xfU +#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT) +#define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT) + +#define S_DEBUG_T_RX_SOP0_CNT 20 +#define M_DEBUG_T_RX_SOP0_CNT 0xfU +#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT) +#define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT) + +#define S_DEBUG_T_RX_EOP0_CNT 16 +#define M_DEBUG_T_RX_EOP0_CNT 0xfU +#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT) +#define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT) + +#define S_DEBUG_U_RX_SOP1_CNT 12 +#define M_DEBUG_U_RX_SOP1_CNT 0xfU +#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT) +#define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT) + +#define S_DEBUG_U_RX_EOP1_CNT 8 +#define M_DEBUG_U_RX_EOP1_CNT 0xfU +#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT) +#define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT) + +#define S_DEBUG_U_RX_SOP0_CNT 4 +#define M_DEBUG_U_RX_SOP0_CNT 0xfU +#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT) +#define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT) + +#define S_DEBUG_U_RX_EOP0_CNT 0 +#define M_DEBUG_U_RX_EOP0_CNT 0xfU +#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT) +#define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288 + +#define S_DEBUG_UD_RX_SOP3_CNT 28 +#define M_DEBUG_UD_RX_SOP3_CNT 0xfU +#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT) +#define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT) + +#define S_DEBUG_UD_RX_EOP3_CNT 24 +#define M_DEBUG_UD_RX_EOP3_CNT 0xfU +#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT) +#define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT) + +#define S_DEBUG_UD_RX_SOP2_CNT 20 +#define M_DEBUG_UD_RX_SOP2_CNT 0xfU +#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT) +#define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT) + +#define S_DEBUG_UD_RX_EOP2_CNT 16 +#define M_DEBUG_UD_RX_EOP2_CNT 0xfU +#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT) +#define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT) + +#define S_DEBUG_UD_RX_SOP1_CNT 12 +#define M_DEBUG_UD_RX_SOP1_CNT 0xfU +#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT) +#define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT) + +#define S_DEBUG_UD_RX_EOP1_CNT 8 +#define M_DEBUG_UD_RX_EOP1_CNT 0xfU +#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT) +#define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT) + +#define S_DEBUG_UD_RX_SOP0_CNT 4 +#define M_DEBUG_UD_RX_SOP0_CNT 0xfU +#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT) +#define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT) + +#define S_DEBUG_UD_RX_EOP0_CNT 0 +#define M_DEBUG_UD_RX_EOP0_CNT 0xfU +#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT) +#define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c + +#define S_DEBUG_U_TX_SOP3_CNT 28 +#define M_DEBUG_U_TX_SOP3_CNT 0xfU +#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT) +#define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT) + +#define S_DEBUG_U_TX_EOP3_CNT 24 +#define M_DEBUG_U_TX_EOP3_CNT 0xfU +#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT) +#define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT) + +#define S_DEBUG_U_TX_SOP2_CNT 20 +#define M_DEBUG_U_TX_SOP2_CNT 0xfU +#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT) +#define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT) + +#define S_DEBUG_U_TX_EOP2_CNT 16 +#define M_DEBUG_U_TX_EOP2_CNT 0xfU +#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT) +#define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT) + +#define S_DEBUG_U_TX_SOP1_CNT 12 +#define M_DEBUG_U_TX_SOP1_CNT 0xfU +#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT) +#define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT) + +#define S_DEBUG_U_TX_EOP1_CNT 8 +#define M_DEBUG_U_TX_EOP1_CNT 0xfU +#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT) +#define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT) + +#define S_DEBUG_U_TX_SOP0_CNT 4 +#define M_DEBUG_U_TX_SOP0_CNT 0xfU +#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT) +#define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT) + +#define S_DEBUG_U_TX_EOP0_CNT 0 +#define M_DEBUG_U_TX_EOP0_CNT 0xfU +#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT) +#define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290 + +#define S_DEBUG_PC_RSP_SOP1_CNT 28 +#define M_DEBUG_PC_RSP_SOP1_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT) +#define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT) + +#define S_DEBUG_PC_RSP_EOP1_CNT 24 +#define M_DEBUG_PC_RSP_EOP1_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT) +#define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT) + +#define S_DEBUG_PC_RSP_SOP0_CNT 20 +#define M_DEBUG_PC_RSP_SOP0_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT) +#define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT) + +#define S_DEBUG_PC_RSP_EOP0_CNT 16 +#define M_DEBUG_PC_RSP_EOP0_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT) +#define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT) + +#define S_DEBUG_PC_REQ_SOP1_CNT 12 +#define M_DEBUG_PC_REQ_SOP1_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT) +#define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT) + +#define S_DEBUG_PC_REQ_EOP1_CNT 8 +#define M_DEBUG_PC_REQ_EOP1_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT) +#define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT) + +#define S_DEBUG_PC_REQ_SOP0_CNT 4 +#define M_DEBUG_PC_REQ_SOP0_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT) +#define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT) + +#define S_DEBUG_PC_REQ_EOP0_CNT 0 +#define M_DEBUG_PC_REQ_EOP0_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT) +#define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294 + +#define S_DEBUG_PD_RDREQ_SOP3_CNT 28 +#define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT) +#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT) + +#define S_DEBUG_PD_RDREQ_EOP3_CNT 24 +#define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT) +#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT) + +#define S_DEBUG_PD_RDREQ_SOP2_CNT 20 +#define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT) +#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT) + +#define S_DEBUG_PD_RDREQ_EOP2_CNT 16 +#define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT) +#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT) + +#define S_DEBUG_PD_RDREQ_SOP1_CNT 12 +#define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT) +#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT) + +#define S_DEBUG_PD_RDREQ_EOP1_CNT 8 +#define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT) +#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT) + +#define S_DEBUG_PD_RDREQ_SOP0_CNT 4 +#define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT) +#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT) + +#define S_DEBUG_PD_RDREQ_EOP0_CNT 0 +#define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT) +#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298 + +#define S_DEBUG_PD_RDRSP_SOP3_CNT 28 +#define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT) +#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT) + +#define S_DEBUG_PD_RDRSP_EOP3_CNT 24 +#define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT) +#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT) + +#define S_DEBUG_PD_RDRSP_SOP2_CNT 20 +#define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT) +#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT) + +#define S_DEBUG_PD_RDRSP_EOP2_CNT 16 +#define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT) +#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT) + +#define S_DEBUG_PD_RDRSP_SOP1_CNT 12 +#define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT) +#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT) + +#define S_DEBUG_PD_RDRSP_EOP1_CNT 8 +#define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT) +#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT) + +#define S_DEBUG_PD_RDRSP_SOP0_CNT 4 +#define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT) +#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT) + +#define S_DEBUG_PD_RDRSP_EOP0_CNT 0 +#define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT) +#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c + +#define S_DEBUG_PD_WRREQ_SOP3_CNT 28 +#define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT) +#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT) + +#define S_DEBUG_PD_WRREQ_EOP3_CNT 24 +#define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT) +#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT) + +#define S_DEBUG_PD_WRREQ_SOP2_CNT 20 +#define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT) +#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT) + +#define S_DEBUG_PD_WRREQ_EOP2_CNT 16 +#define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT) +#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT) + +#define S_DEBUG_PD_WRREQ_SOP1_CNT 12 +#define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT) +#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT) + +#define S_DEBUG_PD_WRREQ_EOP1_CNT 8 +#define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT) +#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT) + +#define S_DEBUG_PD_WRREQ_SOP0_CNT 4 +#define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT) +#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT) + +#define S_DEBUG_PD_WRREQ_EOP0_CNT 0 +#define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT) +#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0 + +#define S_GLOBALENABLE_OFF 29 +#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF) +#define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U) + +#define S_DEBUG_CIM2SGE_RXAFULL_D 27 +#define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U +#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D) +#define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D) + +#define S_DEBUG_CPLSW_CIM_TXAFULL_D 25 +#define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U +#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D) +#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D) + +#define S_DEBUG_UP_FULL 24 +#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL) +#define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U) + +#define S_DEBUG_M_REQVLD 18 +#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD) +#define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U) + +#define S_DEBUG_M_REQRDY 17 +#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY) +#define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U) + +#define S_DEBUG_M_RSPVLD 16 +#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD) +#define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U) + +#define S_DEBUG_PD_WRREQ_INT3_CNT 12 +#define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT) +#define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT) + +#define S_DEBUG_PD_WRREQ_INT2_CNT 8 +#define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT) +#define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT) + +#define S_DEBUG_PD_WRREQ_INT1_CNT 4 +#define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT) +#define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT) + +#define S_DEBUG_PD_WRREQ_INT0_CNT 0 +#define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT) +#define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4 + +#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28 +#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT) +#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT) + +#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24 +#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT) +#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT) + +#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20 +#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT) +#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT) + +#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16 +#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT) +#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT) + +#define S_DEBUG_CPLSW_CIM_SOP1_CNT 12 +#define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT) +#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT) + +#define S_DEBUG_CPLSW_CIM_EOP1_CNT 8 +#define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT) +#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT) + +#define S_DEBUG_CPLSW_CIM_SOP0_CNT 4 +#define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT) +#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT) + +#define S_DEBUG_CPLSW_CIM_EOP0_CNT 0 +#define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT) +#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 + +#define S_DEBUG_T_RXAFULL_D 30 +#define M_DEBUG_T_RXAFULL_D 0x3U +#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D) +#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D) + +#define S_DEBUG_PD_RDRSPAFULL_D 26 +#define M_DEBUG_PD_RDRSPAFULL_D 0xfU +#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D) +#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D) + +#define S_DEBUG_PD_RDREQAFULL_D 22 +#define M_DEBUG_PD_RDREQAFULL_D 0xfU +#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D) +#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D) + +#define S_DEBUG_PD_WRREQAFULL_D 18 +#define M_DEBUG_PD_WRREQAFULL_D 0xfU +#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D) +#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D) + +#define S_DEBUG_PC_RSPAFULL_D 15 +#define M_DEBUG_PC_RSPAFULL_D 0x7U +#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D) +#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D) + +#define S_DEBUG_PC_REQAFULL_D 12 +#define M_DEBUG_PC_REQAFULL_D 0x7U +#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D) +#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D) + +#define S_DEBUG_U_TXAFULL_D 8 +#define M_DEBUG_U_TXAFULL_D 0xfU +#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D) +#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D) + +#define S_DEBUG_UD_RXAFULL_D 4 +#define M_DEBUG_UD_RXAFULL_D 0xfU +#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D) +#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D) + +#define S_DEBUG_U_RXAFULL_D 2 +#define M_DEBUG_U_RXAFULL_D 0x3U +#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D) +#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D) + +#define S_DEBUG_CIM_AFULL_D 0 +#define M_DEBUG_CIM_AFULL_D 0x3U +#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D) +#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac + +#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24 +#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23 +#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22 +#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21 +#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U) + +#define S_DEBUG_ST_FLM_IDMA1_CACHE 19 +#define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U +#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE) +#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE) + +#define S_DEBUG_ST_FLM_IDMA1_CTXT 16 +#define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U +#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT) +#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT) + +#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8 +#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7 +#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6 +#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5 +#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U) + +#define S_DEBUG_ST_FLM_IDMA0_CACHE 3 +#define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U +#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE) +#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE) + +#define S_DEBUG_ST_FLM_IDMA0_CTXT 0 +#define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U +#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT) +#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0 + +#define S_DEBUG_CPLSW_SOP1_CNT 28 +#define M_DEBUG_CPLSW_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT) +#define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT) + +#define S_DEBUG_CPLSW_EOP1_CNT 24 +#define M_DEBUG_CPLSW_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT) +#define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT) + +#define S_DEBUG_CPLSW_SOP0_CNT 20 +#define M_DEBUG_CPLSW_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT) +#define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT) + +#define S_DEBUG_CPLSW_EOP0_CNT 16 +#define M_DEBUG_CPLSW_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT) +#define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT) + +#define S_DEBUG_PC_RSP_SOP2_CNT 12 +#define M_DEBUG_PC_RSP_SOP2_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT) +#define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT) + +#define S_DEBUG_PC_RSP_EOP2_CNT 8 +#define M_DEBUG_PC_RSP_EOP2_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT) +#define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT) + +#define S_DEBUG_PC_REQ_SOP2_CNT 4 +#define M_DEBUG_PC_REQ_SOP2_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT) +#define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT) + +#define S_DEBUG_PC_REQ_EOP2_CNT 0 +#define M_DEBUG_PC_REQ_EOP2_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT) +#define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc +#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0 + +#define S_DEBUG_ST_IDMA1_FLM_REQ 29 +#define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U +#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ) +#define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ) + +#define S_DEBUG_ST_IDMA0_FLM_REQ 26 +#define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U +#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ) +#define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ) + +#define S_DEBUG_ST_IMSG_CTXT 23 +#define M_DEBUG_ST_IMSG_CTXT 0x7U +#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT) +#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT) + +#define S_DEBUG_ST_IMSG 18 +#define M_DEBUG_ST_IMSG 0x1fU +#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG) +#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG) + +#define S_DEBUG_ST_IDMA1_IALN 16 +#define M_DEBUG_ST_IDMA1_IALN 0x3U +#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN) +#define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN) + +#define S_DEBUG_ST_IDMA1_IDMA_SM 9 +#define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU +#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM) +#define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM) + +#define S_DEBUG_ST_IDMA0_IALN 7 +#define M_DEBUG_ST_IDMA0_IALN 0x3U +#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN) +#define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN) + +#define S_DEBUG_ST_IDMA0_IDMA_SM 0 +#define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU +#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM) +#define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4 + +#define S_DEBUG_ITP_EMPTY 12 +#define M_DEBUG_ITP_EMPTY 0x3fU +#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY) +#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY) + +#define S_DEBUG_ITP_EXPIRED 6 +#define M_DEBUG_ITP_EXPIRED 0x3fU +#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED) +#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED) + +#define S_DEBUG_ITP_PAUSE 5 +#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE) +#define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U) + +#define S_DEBUG_ITP_DEL_DONE 4 +#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE) +#define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U) + +#define S_DEBUG_ITP_ADD_DONE 3 +#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE) +#define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U) + +#define S_DEBUG_ITP_EVR_STATE 0 +#define M_DEBUG_ITP_EVR_STATE 0x7U +#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE) +#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 + +#define S_DEBUG_ST_DBP_THREAD2_CIMFL 25 +#define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL) +#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD2_MAIN 20 +#define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN) +#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN) + +#define S_DEBUG_ST_DBP_THREAD1_CIMFL 15 +#define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL) +#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD1_MAIN 10 +#define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN) +#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN) + +#define S_DEBUG_ST_DBP_THREAD0_CIMFL 5 +#define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL) +#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD0_MAIN 0 +#define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN) +#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc + +#define S_DEBUG_ST_DBP_UPCP_MAIN 14 +#define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU +#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN) +#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN) + +#define S_DEBUG_ST_DBP_DBFIFO_MAIN 13 +#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN) +#define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U) + +#define S_DEBUG_ST_DBP_CTXT 10 +#define M_DEBUG_ST_DBP_CTXT 0x7U +#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT) +#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT) + +#define S_DEBUG_ST_DBP_THREAD3_CIMFL 5 +#define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL) +#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD3_MAIN 0 +#define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN) +#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0 + +#define S_DEBUG_ST_EDMA3_ALIGN_SUB 29 +#define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB) +#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA3_ALIGN 27 +#define M_DEBUG_ST_EDMA3_ALIGN 0x3U +#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN) +#define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN) + +#define S_DEBUG_ST_EDMA3_REQ 24 +#define M_DEBUG_ST_EDMA3_REQ 0x7U +#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ) +#define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ) + +#define S_DEBUG_ST_EDMA2_ALIGN_SUB 21 +#define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB) +#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA2_ALIGN 19 +#define M_DEBUG_ST_EDMA2_ALIGN 0x3U +#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN) +#define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN) + +#define S_DEBUG_ST_EDMA2_REQ 16 +#define M_DEBUG_ST_EDMA2_REQ 0x7U +#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ) +#define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ) + +#define S_DEBUG_ST_EDMA1_ALIGN_SUB 13 +#define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB) +#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA1_ALIGN 11 +#define M_DEBUG_ST_EDMA1_ALIGN 0x3U +#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN) +#define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN) + +#define S_DEBUG_ST_EDMA1_REQ 8 +#define M_DEBUG_ST_EDMA1_REQ 0x7U +#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ) +#define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ) + +#define S_DEBUG_ST_EDMA0_ALIGN_SUB 5 +#define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB) +#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA0_ALIGN 3 +#define M_DEBUG_ST_EDMA0_ALIGN 0x3U +#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN) +#define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN) + +#define S_DEBUG_ST_EDMA0_REQ 0 +#define M_DEBUG_ST_EDMA0_REQ 0x7U +#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ) +#define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4 + +#define S_DEBUG_ST_FLM_DBPTR 30 +#define M_DEBUG_ST_FLM_DBPTR 0x3U +#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR) +#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR) + +#define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23 +#define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU +#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT) +#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT) + +#define S_DEBUG_FLM_CACHE_AGENT 20 +#define M_DEBUG_FLM_CACHE_AGENT 0x7U +#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT) +#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT) + +#define S_DEBUG_ST_FLM_CACHE 16 +#define M_DEBUG_ST_FLM_CACHE 0xfU +#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE) +#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE) + +#define S_DEBUG_FLM_DBPTR_CIDX_STALL 12 +#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL) +#define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U) + +#define S_DEBUG_FLM_DBPTR_QID 0 +#define M_DEBUG_FLM_DBPTR_QID 0xfffU +#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID) +#define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8 + +#define S_DEBUG_DBP_THREAD0_QID 0 +#define M_DEBUG_DBP_THREAD0_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID) +#define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc + +#define S_DEBUG_DBP_THREAD1_QID 0 +#define M_DEBUG_DBP_THREAD1_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID) +#define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0 + +#define S_DEBUG_DBP_THREAD2_QID 0 +#define M_DEBUG_DBP_THREAD2_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID) +#define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4 + +#define S_DEBUG_DBP_THREAD3_QID 0 +#define M_DEBUG_DBP_THREAD3_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID) +#define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8 + +#define S_DEBUG_IMSG_CPL 16 +#define M_DEBUG_IMSG_CPL 0xffU +#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL) +#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL) + +#define S_DEBUG_IMSG_QID 0 +#define M_DEBUG_IMSG_QID 0xffffU +#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID) +#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec + +#define S_DEBUG_IDMA1_QID 16 +#define M_DEBUG_IDMA1_QID 0xffffU +#define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID) +#define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID) + +#define S_DEBUG_IDMA0_QID 0 +#define M_DEBUG_IDMA0_QID 0xffffU +#define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID) +#define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0 + +#define S_DEBUG_IDMA1_FLM_REQ_QID 16 +#define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU +#define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID) +#define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID) + +#define S_DEBUG_IDMA0_FLM_REQ_QID 0 +#define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU +#define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID) +#define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4 +#define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8 +#define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300 #define S_EGRESS_LOG2SIZE 27 @@ -1468,6 +3045,21 @@ #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE) #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE) +#define S_EGRESS_SIZE 27 +#define M_EGRESS_SIZE 0x1fU +#define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE) +#define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE) + +#define S_INGRESS2_SIZE 5 +#define M_INGRESS2_SIZE 0x1fU +#define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE) +#define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE) + +#define S_INGRESS1_SIZE 0 +#define M_INGRESS1_SIZE 0x1fU +#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE) +#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE) + #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304 #define S_INGRESS2_BASE 16 @@ -1721,6 +3313,94 @@ #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR) #define F_MSIADDRLPERR V_MSIADDRLPERR(1U) +#define S_IPGRPPERR 31 +#define V_IPGRPPERR(x) ((x) << S_IPGRPPERR) +#define F_IPGRPPERR V_IPGRPPERR(1U) + +#define S_READRSPERR 29 +#define V_READRSPERR(x) ((x) << S_READRSPERR) +#define F_READRSPERR V_READRSPERR(1U) + +#define S_TRGT1GRPPERR 28 +#define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR) +#define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U) + +#define S_IPSOTPERR 27 +#define V_IPSOTPERR(x) ((x) << S_IPSOTPERR) +#define F_IPSOTPERR V_IPSOTPERR(1U) + +#define S_IPRETRYPERR 26 +#define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR) +#define F_IPRETRYPERR V_IPRETRYPERR(1U) + +#define S_IPRXDATAGRPPERR 25 +#define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR) +#define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U) + +#define S_IPRXHDRGRPPERR 24 +#define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR) +#define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U) + +#define S_PIOTAGQPERR 23 +#define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR) +#define F_PIOTAGQPERR V_PIOTAGQPERR(1U) + +#define S_MAGRPPERR 22 +#define V_MAGRPPERR(x) ((x) << S_MAGRPPERR) +#define F_MAGRPPERR V_MAGRPPERR(1U) + +#define S_VFIDPERR 21 +#define V_VFIDPERR(x) ((x) << S_VFIDPERR) +#define F_VFIDPERR V_VFIDPERR(1U) + +#define S_HREQRDPERR 17 +#define V_HREQRDPERR(x) ((x) << S_HREQRDPERR) +#define F_HREQRDPERR V_HREQRDPERR(1U) + +#define S_HREQWRPERR 16 +#define V_HREQWRPERR(x) ((x) << S_HREQWRPERR) +#define F_HREQWRPERR V_HREQWRPERR(1U) + +#define S_DREQRDPERR 14 +#define V_DREQRDPERR(x) ((x) << S_DREQRDPERR) +#define F_DREQRDPERR V_DREQRDPERR(1U) + +#define S_DREQWRPERR 13 +#define V_DREQWRPERR(x) ((x) << S_DREQWRPERR) +#define F_DREQWRPERR V_DREQWRPERR(1U) + +#define S_CREQRDPERR 11 +#define V_CREQRDPERR(x) ((x) << S_CREQRDPERR) +#define F_CREQRDPERR V_CREQRDPERR(1U) + +#define S_MSTTAGQPERR 10 +#define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR) +#define F_MSTTAGQPERR V_MSTTAGQPERR(1U) + +#define S_TGTTAGQPERR 9 +#define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR) +#define F_TGTTAGQPERR V_TGTTAGQPERR(1U) + +#define S_PIOREQGRPPERR 8 +#define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR) +#define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U) + +#define S_PIOCPLGRPPERR 7 +#define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR) +#define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U) + +#define S_MSIXSTIPERR 2 +#define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR) +#define F_MSIXSTIPERR V_MSIXSTIPERR(1U) + +#define S_MSTTIMEOUTPERR 1 +#define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR) +#define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U) + +#define S_MSTGRPPERR 0 +#define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR) +#define F_MSTGRPPERR V_MSTGRPPERR(1U) + #define A_PCIE_INT_CAUSE 0x3004 #define A_PCIE_PERR_ENABLE 0x3008 #define A_PCIE_PERR_INJECT 0x300c @@ -1771,6 +3451,90 @@ #define V_CFGSNP(x) ((x) << S_CFGSNP) #define F_CFGSNP V_CFGSNP(1U) +#define S_MAREQTIMEOUT 29 +#define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT) +#define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U) + +#define S_TRGT1BARTYPEERR 28 +#define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR) +#define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U) + +#define S_MAEXTRARSPERR 27 +#define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR) +#define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U) + +#define S_MARSPTIMEOUT 26 +#define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT) +#define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U) + +#define S_INTVFALLMSIDISERR 25 +#define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR) +#define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U) + +#define S_INTVFRANGEERR 24 +#define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR) +#define F_INTVFRANGEERR V_INTVFRANGEERR(1U) + +#define S_INTPLIRSPERR 23 +#define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR) +#define F_INTPLIRSPERR V_INTPLIRSPERR(1U) + +#define S_MEMREQRDTAGERR 22 +#define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR) +#define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U) + +#define S_CFGINITDONEERR 21 +#define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR) +#define F_CFGINITDONEERR V_CFGINITDONEERR(1U) + +#define S_BAR2TIMEOUT 20 +#define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT) +#define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U) + +#define S_VPDTIMEOUT 19 +#define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT) +#define F_VPDTIMEOUT V_VPDTIMEOUT(1U) + +#define S_MEMRSPRDTAGERR 18 +#define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR) +#define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U) + +#define S_MEMRSPWRTAGERR 17 +#define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR) +#define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U) + +#define S_PIORSPRDTAGERR 16 +#define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR) +#define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U) + +#define S_PIORSPWRTAGERR 15 +#define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR) +#define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U) + +#define S_DBITIMEOUT 14 +#define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT) +#define F_DBITIMEOUT V_DBITIMEOUT(1U) + +#define S_PIOUNALINDWR 13 +#define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR) +#define F_PIOUNALINDWR V_PIOUNALINDWR(1U) + +#define S_BAR2RDERR 12 +#define V_BAR2RDERR(x) ((x) << S_BAR2RDERR) +#define F_BAR2RDERR V_BAR2RDERR(1U) + +#define S_MAWREOPERR 11 +#define V_MAWREOPERR(x) ((x) << S_MAWREOPERR) +#define F_MAWREOPERR V_MAWREOPERR(1U) + +#define S_MARDEOPERR 10 +#define V_MARDEOPERR(x) ((x) << S_MARDEOPERR) +#define F_MARDEOPERR V_MARDEOPERR(1U) + +#define S_BAR2REQ 2 +#define V_BAR2REQ(x) ((x) << S_BAR2REQ) +#define F_BAR2REQ V_BAR2REQ(1U) + #define A_PCIE_CFG 0x3014 #define S_CFGDMAXPYLDSZRX 26 @@ -1861,12 +3625,80 @@ #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN) #define F_LINKDNRSTEN V_LINKDNRSTEN(1U) +#define S_DIAGCTRLBUS 28 +#define M_DIAGCTRLBUS 0x7U +#define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS) +#define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS) + +#define S_IPPERREN 27 +#define V_IPPERREN(x) ((x) << S_IPPERREN) +#define F_IPPERREN V_IPPERREN(1U) + +#define S_CFGDEXTTAGEN 26 +#define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN) +#define F_CFGDEXTTAGEN V_CFGDEXTTAGEN(1U) + +#define S_CFGDMAXPYLDSZ 23 +#define M_CFGDMAXPYLDSZ 0x7U +#define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ) +#define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ) + +#define S_DCAEN 17 +#define V_DCAEN(x) ((x) << S_DCAEN) +#define F_DCAEN V_DCAEN(1U) + +#define S_T5CMDREQPRIORITY 16 +#define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY) +#define F_T5CMDREQPRIORITY V_T5CMDREQPRIORITY(1U) + +#define S_T5VPDREQPROTECT 14 +#define M_T5VPDREQPROTECT 0x3U +#define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT) +#define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT) + +#define S_DROPPEDRDRSPDATA 12 +#define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA) +#define F_DROPPEDRDRSPDATA V_DROPPEDRDRSPDATA(1U) + +#define S_AI_INTX_REASSERTEN 11 +#define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN) +#define F_AI_INTX_REASSERTEN V_AI_INTX_REASSERTEN(1U) + +#define S_AUTOTXNDISABLE 10 +#define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE) +#define F_AUTOTXNDISABLE V_AUTOTXNDISABLE(1U) + +#define S_LINKREQRSTPCIECRSTMODE 3 +#define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE) +#define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U) + #define A_PCIE_DMA_CTRL 0x3018 #define S_LITTLEENDIAN 7 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN) #define F_LITTLEENDIAN V_LITTLEENDIAN(1U) +#define A_PCIE_CFG2 0x3018 + +#define S_VPDTIMER 16 +#define M_VPDTIMER 0xffffU +#define V_VPDTIMER(x) ((x) << S_VPDTIMER) +#define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER) + +#define S_BAR2TIMER 4 +#define M_BAR2TIMER 0xfffU +#define V_BAR2TIMER(x) ((x) << S_BAR2TIMER) +#define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER) + +#define S_MSTREQRDRRASIMPLE 3 +#define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE) +#define F_MSTREQRDRRASIMPLE V_MSTREQRDRRASIMPLE(1U) + +#define S_TOTMAXTAG 0 +#define M_TOTMAXTAG 0x3U +#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG) +#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG) + #define A_PCIE_DMA_CFG 0x301c #define S_MAXPYLDSIZE 28 @@ -1894,6 +3726,29 @@ #define V_MAXTAG(x) ((x) << S_MAXTAG) #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG) +#define A_PCIE_CFG3 0x301c + +#define S_AUTOPIOCOOKIEMATCH 6 +#define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH) +#define F_AUTOPIOCOOKIEMATCH V_AUTOPIOCOOKIEMATCH(1U) + +#define S_FLRPNDCPLMODE 4 +#define M_FLRPNDCPLMODE 0x3U +#define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE) +#define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE) + +#define S_HMADCASTFIRSTONLY 2 +#define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY) +#define F_HMADCASTFIRSTONLY V_HMADCASTFIRSTONLY(1U) + +#define S_CMDDCASTFIRSTONLY 1 +#define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY) +#define F_CMDDCASTFIRSTONLY V_CMDDCASTFIRSTONLY(1U) + +#define S_DMADCASTFIRSTONLY 0 +#define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY) +#define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U) + #define A_PCIE_DMA_STAT 0x3020 #define S_STATEREQ 28 @@ -1920,6 +3775,59 @@ #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT) #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT) +#define A_PCIE_CFG4 0x3020 + +#define S_L1CLKREMOVALEN 17 +#define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN) +#define F_L1CLKREMOVALEN V_L1CLKREMOVALEN(1U) + +#define S_READYENTERL23 16 +#define V_READYENTERL23(x) ((x) << S_READYENTERL23) +#define F_READYENTERL23 V_READYENTERL23(1U) + +#define S_EXITL1 12 +#define V_EXITL1(x) ((x) << S_EXITL1) +#define F_EXITL1 V_EXITL1(1U) + +#define S_ENTERL1 8 +#define V_ENTERL1(x) ((x) << S_ENTERL1) +#define F_ENTERL1 V_ENTERL1(1U) + +#define S_GENPME 0 +#define M_GENPME 0xffU +#define V_GENPME(x) ((x) << S_GENPME) +#define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME) + +#define A_PCIE_CFG5 0x3024 + +#define S_ENABLESKPPARITYFIX 2 +#define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX) +#define F_ENABLESKPPARITYFIX V_ENABLESKPPARITYFIX(1U) + +#define S_ENABLEL2ENTRYINL1 1 +#define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1) +#define F_ENABLEL2ENTRYINL1 V_ENABLEL2ENTRYINL1(1U) + +#define S_HOLDCPLENTERINGL1 0 +#define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1) +#define F_HOLDCPLENTERINGL1 V_HOLDCPLENTERINGL1(1U) + +#define A_PCIE_CFG6 0x3028 + +#define S_PERSTTIMERCOUNT 12 +#define M_PERSTTIMERCOUNT 0x3fffU +#define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT) +#define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT) + +#define S_PERSTTIMEOUT 8 +#define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT) +#define F_PERSTTIMEOUT V_PERSTTIMEOUT(1U) + +#define S_PERSTTIMER 0 +#define M_PERSTTIMER 0xfU +#define V_PERSTTIMER(x) ((x) << S_PERSTTIMER) +#define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER) + #define A_PCIE_CMD_CTRL 0x303c #define A_PCIE_CMD_CFG 0x3040 @@ -2034,6 +3942,29 @@ #define V_REGISTER(x) ((x) << S_REGISTER) #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER) +#define S_CS2 28 +#define V_CS2(x) ((x) << S_CS2) +#define F_CS2 V_CS2(1U) + +#define S_WRBE 24 +#define M_WRBE 0xfU +#define V_WRBE(x) ((x) << S_WRBE) +#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE) + +#define S_CFG_SPACE_VFVLD 23 +#define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD) +#define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U) + +#define S_CFG_SPACE_RVF 16 +#define M_CFG_SPACE_RVF 0x7fU +#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF) +#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF) + +#define S_CFG_SPACE_PF 12 +#define M_CFG_SPACE_PF 0x7U +#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF) +#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF) + #define A_PCIE_CFG_SPACE_DATA 0x3064 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068 @@ -2053,6 +3984,12 @@ #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW) #define A_PCIE_MEM_ACCESS_OFFSET 0x306c + +#define S_MEMOFST 7 +#define M_MEMOFST 0x1ffffffU +#define V_MEMOFST(x) ((x) << S_MEMOFST) +#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST) + #define A_PCIE_MAILBOX_BASE_WIN 0x30a8 #define S_MBOXPCIEOFST 6 @@ -2106,6 +4043,16 @@ #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG) #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG) +#define S_T5_MA_MAXREQCNT 16 +#define M_T5_MA_MAXREQCNT 0x7fU +#define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT) +#define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT) + +#define S_MA_MAXREQSIZE 8 +#define M_MA_MAXREQSIZE 0x7U +#define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE) +#define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE) + #define A_PCIE_MA_SYNC 0x30b4 #define A_PCIE_FW 0x30b8 #define A_PCIE_FW_PF 0x30bc @@ -2124,7 +4071,16 @@ #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE) #define F_PIOPAUSE V_PIOPAUSE(1U) +#define S_MSTPAUSEDONE 30 +#define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE) +#define F_MSTPAUSEDONE V_MSTPAUSEDONE(1U) + +#define S_MSTPAUSE 1 +#define V_MSTPAUSE(x) ((x) << S_MSTPAUSE) +#define F_MSTPAUSE V_MSTPAUSE(1U) + #define A_PCIE_SYS_CFG_READY 0x30e0 +#define A_PCIE_MA_STAT 0x30e0 #define A_PCIE_STATIC_CFG1 0x30e4 #define S_LINKDOWN_RESET_EN 26 @@ -2180,6 +4136,22 @@ #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE) #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE) +#define S_AUXPOWER_DETECTED 27 +#define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED) +#define F_AUXPOWER_DETECTED V_AUXPOWER_DETECTED(1U) + +#define A_PCIE_STATIC_CFG2 0x30e8 + +#define S_PL_CONTROL 16 +#define M_PL_CONTROL 0xffffU +#define V_PL_CONTROL(x) ((x) << S_PL_CONTROL) +#define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL) + +#define S_STATIC_SPARE3 0 +#define M_STATIC_SPARE3 0x3fffU +#define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3) +#define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3) + #define A_PCIE_DBG_INDIR_REQ 0x30ec #define S_DBGENABLE 31 @@ -2254,6 +4226,74 @@ #define V_PFNUM(x) ((x) << S_PFNUM) #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) +#define A_PCIE_PF_INT_CFG 0x3140 +#define A_PCIE_PF_INT_CFG2 0x3144 +#define A_PCIE_VF_INT_CFG 0x3180 +#define A_PCIE_VF_INT_CFG2 0x3184 +#define A_PCIE_PF_MSI_EN 0x35a8 + +#define S_PFMSIEN_7_0 0 +#define M_PFMSIEN_7_0 0xffU +#define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0) +#define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0) + +#define A_PCIE_VF_MSI_EN_0 0x35ac +#define A_PCIE_VF_MSI_EN_1 0x35b0 +#define A_PCIE_VF_MSI_EN_2 0x35b4 +#define A_PCIE_VF_MSI_EN_3 0x35b8 +#define A_PCIE_PF_MSIX_EN 0x35bc + +#define S_PFMSIXEN_7_0 0 +#define M_PFMSIXEN_7_0 0xffU +#define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0) +#define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0) + +#define A_PCIE_VF_MSIX_EN_0 0x35c0 +#define A_PCIE_VF_MSIX_EN_1 0x35c4 +#define A_PCIE_VF_MSIX_EN_2 0x35c8 +#define A_PCIE_VF_MSIX_EN_3 0x35cc +#define A_PCIE_FID_VFID_SEL 0x35ec + +#define S_FID_VFID_SEL_SELECT 0 +#define M_FID_VFID_SEL_SELECT 0x3U +#define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT) +#define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT) + +#define A_PCIE_FID_VFID 0x3600 + +#define S_FID_VFID_SELECT 30 +#define M_FID_VFID_SELECT 0x3U +#define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT) +#define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT) + +#define S_IDO 24 +#define V_IDO(x) ((x) << S_IDO) +#define F_IDO V_IDO(1U) + +#define S_FID_VFID_VFID 16 +#define M_FID_VFID_VFID 0xffU +#define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID) +#define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID) + +#define S_FID_VFID_TC 11 +#define M_FID_VFID_TC 0x7U +#define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC) +#define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC) + +#define S_FID_VFID_VFVLD 10 +#define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD) +#define F_FID_VFID_VFVLD V_FID_VFID_VFVLD(1U) + +#define S_FID_VFID_PF 7 +#define M_FID_VFID_PF 0x7U +#define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF) +#define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF) + +#define S_FID_VFID_RVF 0 +#define M_FID_VFID_RVF 0x7fU +#define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF) +#define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF) + #define A_PCIE_FID 0x3900 #define S_PAD 11 @@ -2270,6 +4310,695 @@ #define V_FUNC(x) ((x) << S_FUNC) #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC) +#define A_PCIE_COOKIE_STAT 0x5600 + +#define S_COOKIEB 16 +#define M_COOKIEB 0x3ffU +#define V_COOKIEB(x) ((x) << S_COOKIEB) +#define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB) + +#define S_COOKIEA 0 +#define M_COOKIEA 0x3ffU +#define V_COOKIEA(x) ((x) << S_COOKIEA) +#define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA) + +#define A_PCIE_FLR_PIO 0x5620 + +#define S_RCVDBAR2COOKIE 24 +#define M_RCVDBAR2COOKIE 0xffU +#define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE) +#define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE) + +#define S_RCVDMARSPCOOKIE 16 +#define M_RCVDMARSPCOOKIE 0xffU +#define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE) +#define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE) + +#define S_RCVDPIORSPCOOKIE 8 +#define M_RCVDPIORSPCOOKIE 0xffU +#define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE) +#define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE) + +#define S_EXPDCOOKIE 0 +#define M_EXPDCOOKIE 0xffU +#define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE) +#define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE) + +#define A_PCIE_FLR_PIO2 0x5624 + +#define S_RCVDMAREQCOOKIE 16 +#define M_RCVDMAREQCOOKIE 0xffU +#define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE) +#define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE) + +#define S_RCVDPIOREQCOOKIE 8 +#define M_RCVDPIOREQCOOKIE 0xffU +#define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE) +#define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE) + +#define A_PCIE_VC0_CDTS0 0x56cc + +#define S_CPLD0 20 +#define M_CPLD0 0xfffU +#define V_CPLD0(x) ((x) << S_CPLD0) +#define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0) + +#define S_PH0 12 +#define M_PH0 0xffU +#define V_PH0(x) ((x) << S_PH0) +#define G_PH0(x) (((x) >> S_PH0) & M_PH0) + +#define S_PD0 0 +#define M_PD0 0xfffU +#define V_PD0(x) ((x) << S_PD0) +#define G_PD0(x) (((x) >> S_PD0) & M_PD0) + +#define A_PCIE_VC0_CDTS1 0x56d0 + +#define S_CPLH0 20 +#define M_CPLH0 0xffU +#define V_CPLH0(x) ((x) << S_CPLH0) +#define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0) + +#define S_NPH0 12 +#define M_NPH0 0xffU +#define V_NPH0(x) ((x) << S_NPH0) +#define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0) + +#define S_NPD0 0 +#define M_NPD0 0xfffU +#define V_NPD0(x) ((x) << S_NPD0) +#define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0) + +#define A_PCIE_VC1_CDTS0 0x56d4 + +#define S_CPLD1 20 +#define M_CPLD1 0xfffU +#define V_CPLD1(x) ((x) << S_CPLD1) +#define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1) + +#define S_PH1 12 +#define M_PH1 0xffU +#define V_PH1(x) ((x) << S_PH1) +#define G_PH1(x) (((x) >> S_PH1) & M_PH1) + +#define S_PD1 0 +#define M_PD1 0xfffU +#define V_PD1(x) ((x) << S_PD1) +#define G_PD1(x) (((x) >> S_PD1) & M_PD1) + +#define A_PCIE_VC1_CDTS1 0x56d8 + +#define S_CPLH1 20 +#define M_CPLH1 0xffU +#define V_CPLH1(x) ((x) << S_CPLH1) +#define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1) + +#define S_NPH1 12 +#define M_NPH1 0xffU +#define V_NPH1(x) ((x) << S_NPH1) +#define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1) + +#define S_NPD1 0 +#define M_NPD1 0xfffU +#define V_NPD1(x) ((x) << S_NPD1) +#define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1) + +#define A_PCIE_FLR_PF_STATUS 0x56dc +#define A_PCIE_FLR_VF0_STATUS 0x56e0 +#define A_PCIE_FLR_VF1_STATUS 0x56e4 +#define A_PCIE_FLR_VF2_STATUS 0x56e8 +#define A_PCIE_FLR_VF3_STATUS 0x56ec +#define A_PCIE_STAT 0x56f4 + +#define S_PM_STATUS 24 +#define M_PM_STATUS 0xffU +#define V_PM_STATUS(x) ((x) << S_PM_STATUS) +#define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS) + +#define S_PM_CURRENTSTATE 20 +#define M_PM_CURRENTSTATE 0x7U +#define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE) +#define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE) + +#define S_LTSSMENABLE 12 +#define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE) +#define F_LTSSMENABLE V_LTSSMENABLE(1U) + +#define S_STATECFGINITF 4 +#define M_STATECFGINITF 0x7fU +#define V_STATECFGINITF(x) ((x) << S_STATECFGINITF) +#define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF) + +#define S_STATECFGINIT 0 +#define M_STATECFGINIT 0xfU +#define V_STATECFGINIT(x) ((x) << S_STATECFGINIT) +#define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT) + +#define A_PCIE_CRS 0x56f8 + +#define S_CRS_ENABLE 0 +#define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE) +#define F_CRS_ENABLE V_CRS_ENABLE(1U) + +#define A_PCIE_LTSSM 0x56fc + +#define S_LTSSM_ENABLE 0 +#define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE) +#define F_LTSSM_ENABLE V_LTSSM_ENABLE(1U) + +#define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700 + +#define S_REPLAY_TIME_LIMIT 16 +#define M_REPLAY_TIME_LIMIT 0xffffU +#define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT) +#define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT) + +#define S_ACK_LATENCY_TIMER_LIMIT 0 +#define M_ACK_LATENCY_TIMER_LIMIT 0xffffU +#define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT) +#define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT) + +#define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704 +#define A_PCIE_CORE_PORT_FORCE_LINK 0x5708 + +#define S_LOW_POWER_ENTRANCE_COUNT 24 +#define M_LOW_POWER_ENTRANCE_COUNT 0xffU +#define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT) +#define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT) + +#define S_LINK_STATE 16 +#define M_LINK_STATE 0x3fU +#define V_LINK_STATE(x) ((x) << S_LINK_STATE) +#define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE) + +#define S_FORCE_LINK 15 +#define V_FORCE_LINK(x) ((x) << S_FORCE_LINK) +#define F_FORCE_LINK V_FORCE_LINK(1U) + +#define S_LINK_NUMBER 0 +#define M_LINK_NUMBER 0xffU +#define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER) +#define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER) + +#define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c + +#define S_ENTER_ASPM_L1_WO_L0S 30 +#define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S) +#define F_ENTER_ASPM_L1_WO_L0S V_ENTER_ASPM_L1_WO_L0S(1U) + +#define S_L1_ENTRANCE_LATENCY 27 +#define M_L1_ENTRANCE_LATENCY 0x7U +#define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY) +#define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY) + +#define S_L0S_ENTRANCE_LATENCY 24 +#define M_L0S_ENTRANCE_LATENCY 0x7U +#define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY) +#define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY) + +#define S_COMMON_CLOCK_N_FTS 16 +#define M_COMMON_CLOCK_N_FTS 0xffU +#define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS) +#define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS) + +#define S_N_FTS 8 +#define M_N_FTS 0xffU +#define V_N_FTS(x) ((x) << S_N_FTS) +#define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS) + +#define S_ACK_FREQUENCY 0 +#define M_ACK_FREQUENCY 0xffU +#define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY) +#define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY) + +#define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710 + +#define S_CROSSLINK_ACTIVE 23 +#define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE) +#define F_CROSSLINK_ACTIVE V_CROSSLINK_ACTIVE(1U) + +#define S_CROSSLINK_ENABLE 22 +#define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE) +#define F_CROSSLINK_ENABLE V_CROSSLINK_ENABLE(1U) + +#define S_LINK_MODE_ENABLE 16 +#define M_LINK_MODE_ENABLE 0x3fU +#define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE) +#define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE) + +#define S_FAST_LINK_MODE 7 +#define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE) +#define F_FAST_LINK_MODE V_FAST_LINK_MODE(1U) + +#define S_DLL_LINK_ENABLE 5 +#define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE) +#define F_DLL_LINK_ENABLE V_DLL_LINK_ENABLE(1U) + +#define S_RESET_ASSERT 3 +#define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT) +#define F_RESET_ASSERT V_RESET_ASSERT(1U) + +#define S_LOOPBACK_ENABLE 2 +#define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE) +#define F_LOOPBACK_ENABLE V_LOOPBACK_ENABLE(1U) + +#define S_SCRAMBLE_DISABLE 1 +#define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE) +#define F_SCRAMBLE_DISABLE V_SCRAMBLE_DISABLE(1U) + +#define S_VENDOR_SPECIFIC_DLLP_REQUEST 0 +#define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST) +#define F_VENDOR_SPECIFIC_DLLP_REQUEST V_VENDOR_SPECIFIC_DLLP_REQUEST(1U) + +#define A_PCIE_CORE_LANE_SKEW 0x5714 + +#define S_DISABLE_DESKEW 31 +#define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW) +#define F_DISABLE_DESKEW V_DISABLE_DESKEW(1U) + +#define S_ACK_NAK_DISABLE 25 +#define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE) +#define F_ACK_NAK_DISABLE V_ACK_NAK_DISABLE(1U) + +#define S_FLOW_CONTROL_DISABLE 24 +#define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE) +#define F_FLOW_CONTROL_DISABLE V_FLOW_CONTROL_DISABLE(1U) + +#define S_INSERT_TXSKEW 0 +#define M_INSERT_TXSKEW 0xffffffU +#define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW) +#define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW) + +#define A_PCIE_CORE_SYMBOL_NUMBER 0x5718 + +#define S_FLOW_CONTROL_TIMER_MODIFIER 24 +#define M_FLOW_CONTROL_TIMER_MODIFIER 0x1fU +#define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER) +#define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER) + +#define S_ACK_NAK_TIMER_MODIFIER 19 +#define M_ACK_NAK_TIMER_MODIFIER 0x1fU +#define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER) +#define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER) + +#define S_REPLAY_TIMER_MODIFIER 14 +#define M_REPLAY_TIMER_MODIFIER 0x1fU +#define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER) +#define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER) + +#define S_MAXFUNC 0 +#define M_MAXFUNC 0x7U +#define V_MAXFUNC(x) ((x) << S_MAXFUNC) +#define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC) + +#define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c + +#define S_MASK_RADM_FILTER 16 +#define M_MASK_RADM_FILTER 0xffffU +#define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER) +#define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER) + +#define S_DISABLE_FC_WATCHDOG 15 +#define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG) +#define F_DISABLE_FC_WATCHDOG V_DISABLE_FC_WATCHDOG(1U) + +#define S_SKP_INTERVAL 0 +#define M_SKP_INTERVAL 0x7ffU +#define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL) +#define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL) + +#define A_PCIE_CORE_FILTER_MASK2 0x5720 +#define A_PCIE_CORE_DEBUG_0 0x5728 +#define A_PCIE_CORE_DEBUG_1 0x572c +#define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730 + +#define S_TXPH_FC 12 +#define M_TXPH_FC 0xffU +#define V_TXPH_FC(x) ((x) << S_TXPH_FC) +#define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC) + +#define S_TXPD_FC 0 +#define M_TXPD_FC 0xfffU +#define V_TXPD_FC(x) ((x) << S_TXPD_FC) +#define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC) + +#define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734 + +#define S_TXNPH_FC 12 +#define M_TXNPH_FC 0xffU +#define V_TXNPH_FC(x) ((x) << S_TXNPH_FC) +#define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC) + +#define S_TXNPD_FC 0 +#define M_TXNPD_FC 0xfffU +#define V_TXNPD_FC(x) ((x) << S_TXNPD_FC) +#define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC) + +#define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738 + +#define S_TXCPLH_FC 12 +#define M_TXCPLH_FC 0xffU +#define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC) +#define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC) + +#define S_TXCPLD_FC 0 +#define M_TXCPLD_FC 0xfffU +#define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC) +#define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC) + +#define A_PCIE_CORE_QUEUE_STATUS 0x573c + +#define S_RXQUEUE_NOT_EMPTY 2 +#define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY) +#define F_RXQUEUE_NOT_EMPTY V_RXQUEUE_NOT_EMPTY(1U) + +#define S_TXRETRYBUF_NOT_EMPTY 1 +#define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY) +#define F_TXRETRYBUF_NOT_EMPTY V_TXRETRYBUF_NOT_EMPTY(1U) + +#define S_RXTLP_FC_NOT_RETURNED 0 +#define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED) +#define F_RXTLP_FC_NOT_RETURNED V_RXTLP_FC_NOT_RETURNED(1U) + +#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740 + +#define S_VC3_WRR 24 +#define M_VC3_WRR 0xffU +#define V_VC3_WRR(x) ((x) << S_VC3_WRR) +#define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR) + +#define S_VC2_WRR 16 +#define M_VC2_WRR 0xffU +#define V_VC2_WRR(x) ((x) << S_VC2_WRR) +#define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR) + +#define S_VC1_WRR 8 +#define M_VC1_WRR 0xffU +#define V_VC1_WRR(x) ((x) << S_VC1_WRR) +#define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR) + +#define S_VC0_WRR 0 +#define M_VC0_WRR 0xffU +#define V_VC0_WRR(x) ((x) << S_VC0_WRR) +#define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR) + +#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744 + +#define S_VC7_WRR 24 +#define M_VC7_WRR 0xffU +#define V_VC7_WRR(x) ((x) << S_VC7_WRR) +#define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR) + +#define S_VC6_WRR 16 +#define M_VC6_WRR 0xffU +#define V_VC6_WRR(x) ((x) << S_VC6_WRR) +#define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR) + +#define S_VC5_WRR 8 +#define M_VC5_WRR 0xffU +#define V_VC5_WRR(x) ((x) << S_VC5_WRR) +#define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR) + +#define S_VC4_WRR 0 +#define M_VC4_WRR 0xffU +#define V_VC4_WRR(x) ((x) << S_VC4_WRR) +#define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR) + +#define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748 + +#define S_VC0_RX_ORDERING 31 +#define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING) +#define F_VC0_RX_ORDERING V_VC0_RX_ORDERING(1U) + +#define S_VC0_TLP_ORDERING 30 +#define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING) +#define F_VC0_TLP_ORDERING V_VC0_TLP_ORDERING(1U) + +#define S_VC0_PTLP_QUEUE_MODE 21 +#define M_VC0_PTLP_QUEUE_MODE 0x7U +#define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE) +#define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE) + +#define S_VC0_PH_CREDITS 12 +#define M_VC0_PH_CREDITS 0xffU +#define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS) +#define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS) + +#define S_VC0_PD_CREDITS 0 +#define M_VC0_PD_CREDITS 0xfffU +#define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS) +#define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS) + +#define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c + +#define S_VC0_NPTLP_QUEUE_MODE 21 +#define M_VC0_NPTLP_QUEUE_MODE 0x7U +#define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE) +#define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE) + +#define S_VC0_NPH_CREDITS 12 +#define M_VC0_NPH_CREDITS 0xffU +#define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS) +#define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS) + +#define S_VC0_NPD_CREDITS 0 +#define M_VC0_NPD_CREDITS 0xfffU +#define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS) +#define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS) + +#define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750 + +#define S_VC0_CPLTLP_QUEUE_MODE 21 +#define M_VC0_CPLTLP_QUEUE_MODE 0x7U +#define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE) +#define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE) + +#define S_VC0_CPLH_CREDITS 12 +#define M_VC0_CPLH_CREDITS 0xffU +#define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS) +#define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS) + +#define S_VC0_CPLD_CREDITS 0 +#define M_VC0_CPLD_CREDITS 0xfffU +#define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS) +#define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS) + +#define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754 + +#define S_VC1_TLP_ORDERING 30 +#define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING) +#define F_VC1_TLP_ORDERING V_VC1_TLP_ORDERING(1U) + +#define S_VC1_PTLP_QUEUE_MODE 21 +#define M_VC1_PTLP_QUEUE_MODE 0x7U +#define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE) +#define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE) + +#define S_VC1_PH_CREDITS 12 +#define M_VC1_PH_CREDITS 0xffU +#define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS) +#define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS) + +#define S_VC1_PD_CREDITS 0 +#define M_VC1_PD_CREDITS 0xfffU +#define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS) +#define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS) + +#define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758 + +#define S_VC1_NPTLP_QUEUE_MODE 21 +#define M_VC1_NPTLP_QUEUE_MODE 0x7U +#define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE) +#define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE) + +#define S_VC1_NPH_CREDITS 12 +#define M_VC1_NPH_CREDITS 0xffU +#define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS) +#define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS) + +#define S_VC1_NPD_CREDITS 0 +#define M_VC1_NPD_CREDITS 0xfffU +#define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS) +#define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS) + +#define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c + +#define S_VC1_CPLTLP_QUEUE_MODE 21 +#define M_VC1_CPLTLP_QUEUE_MODE 0x7U +#define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE) +#define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE) + +#define S_VC1_CPLH_CREDITS 12 +#define M_VC1_CPLH_CREDITS 0xffU +#define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS) +#define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS) + +#define S_VC1_CPLD_CREDITS 0 +#define M_VC1_CPLD_CREDITS 0xfffU +#define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS) +#define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS) + +#define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c + +#define S_SEL_DEEMPHASIS 20 +#define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS) +#define F_SEL_DEEMPHASIS V_SEL_DEEMPHASIS(1U) + +#define S_TXCMPLRCV 19 +#define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV) +#define F_TXCMPLRCV V_TXCMPLRCV(1U) + +#define S_PHYTXSWING 18 +#define V_PHYTXSWING(x) ((x) << S_PHYTXSWING) +#define F_PHYTXSWING V_PHYTXSWING(1U) + +#define S_DIRSPDCHANGE 17 +#define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE) +#define F_DIRSPDCHANGE V_DIRSPDCHANGE(1U) + +#define S_NUM_LANES 8 +#define M_NUM_LANES 0x1ffU +#define V_NUM_LANES(x) ((x) << S_NUM_LANES) +#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES) + +#define S_NFTS_GEN2_3 0 +#define M_NFTS_GEN2_3 0xffU +#define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3) +#define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3) + +#define A_PCIE_CORE_PHY_STATUS 0x5810 +#define A_PCIE_CORE_PHY_CONTROL 0x5814 +#define A_PCIE_CORE_GEN3_CONTROL 0x5890 + +#define S_DC_BALANCE_DISABLE 18 +#define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE) +#define F_DC_BALANCE_DISABLE V_DC_BALANCE_DISABLE(1U) + +#define S_DLLP_DELAY_DISABLE 17 +#define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE) +#define F_DLLP_DELAY_DISABLE V_DLLP_DELAY_DISABLE(1U) + +#define S_EQL_DISABLE 16 +#define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE) +#define F_EQL_DISABLE V_EQL_DISABLE(1U) + +#define S_EQL_REDO_DISABLE 11 +#define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE) +#define F_EQL_REDO_DISABLE V_EQL_REDO_DISABLE(1U) + +#define S_EQL_EIEOS_CNTRST_DISABLE 10 +#define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE) +#define F_EQL_EIEOS_CNTRST_DISABLE V_EQL_EIEOS_CNTRST_DISABLE(1U) + +#define S_EQL_PH2_PH3_DISABLE 9 +#define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE) +#define F_EQL_PH2_PH3_DISABLE V_EQL_PH2_PH3_DISABLE(1U) + +#define S_DISABLE_SCRAMBLER 8 +#define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER) +#define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U) + +#define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894 + +#define S_FULL_SWING 6 +#define M_FULL_SWING 0x3fU +#define V_FULL_SWING(x) ((x) << S_FULL_SWING) +#define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING) + +#define S_LOW_FREQUENCY 0 +#define M_LOW_FREQUENCY 0x3fU +#define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY) +#define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY) + +#define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898 + +#define S_POSTCURSOR 12 +#define M_POSTCURSOR 0x3fU +#define V_POSTCURSOR(x) ((x) << S_POSTCURSOR) +#define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR) + +#define S_CURSOR 6 +#define M_CURSOR 0x3fU +#define V_CURSOR(x) ((x) << S_CURSOR) +#define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR) + +#define S_PRECURSOR 0 +#define M_PRECURSOR 0x3fU +#define V_PRECURSOR(x) ((x) << S_PRECURSOR) +#define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR) + +#define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c + +#define S_INDEX 0 +#define M_INDEX 0xfU +#define V_INDEX(x) ((x) << S_INDEX) +#define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX) + +#define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4 + +#define S_LEGALITY_STATUS 0 +#define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS) +#define F_LEGALITY_STATUS V_LEGALITY_STATUS(1U) + +#define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8 + +#define S_INCLUDE_INITIAL_FOM 24 +#define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM) +#define F_INCLUDE_INITIAL_FOM V_INCLUDE_INITIAL_FOM(1U) + +#define S_PRESET_REQUEST_VECTOR 8 +#define M_PRESET_REQUEST_VECTOR 0xffffU +#define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR) +#define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR) + +#define S_PHASE23_2MS_TIMEOUT_DISABLE 5 +#define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE) +#define F_PHASE23_2MS_TIMEOUT_DISABLE V_PHASE23_2MS_TIMEOUT_DISABLE(1U) + +#define S_AFTER24MS 4 +#define V_AFTER24MS(x) ((x) << S_AFTER24MS) +#define F_AFTER24MS V_AFTER24MS(1U) + +#define S_FEEDBACK_MODE 0 +#define M_FEEDBACK_MODE 0xfU +#define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE) +#define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE) + +#define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac + +#define S_WINAPERTURE_CPLUS1 14 +#define M_WINAPERTURE_CPLUS1 0xfU +#define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1) +#define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1) + +#define S_WINAPERTURE_CMINS1 10 +#define M_WINAPERTURE_CMINS1 0xfU +#define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1) +#define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1) + +#define S_CONVERGENCE_WINDEPTH 5 +#define M_CONVERGENCE_WINDEPTH 0x1fU +#define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH) +#define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH) + +#define S_EQMASTERPHASE_MINTIME 0 +#define M_EQMASTERPHASE_MINTIME 0x1fU +#define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME) +#define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME) + +#define A_PCIE_CORE_PIPE_CONTROL 0x58b8 + +#define S_PIPE_LOOPBACK_EN 0 +#define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN) +#define F_PIPE_LOOPBACK_EN V_PIPE_LOOPBACK_EN(1U) + +#define A_PCIE_CORE_DBI_RO_WE 0x58bc + +#define S_READONLY_WRITEEN 0 +#define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN) +#define F_READONLY_WRITEEN V_READONLY_WRITEEN(1U) + #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900 #define S_SMTD 27 @@ -2489,6 +5218,105 @@ #define V_BRVN(x) ((x) << S_BRVN) #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN) +#define A_PCIE_T5_DMA_CFG 0x5940 + +#define S_T5_DMA_MAXREQCNT 20 +#define M_T5_DMA_MAXREQCNT 0xffU +#define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT) +#define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT) + +#define S_T5_DMA_MAXRDREQSIZE 17 +#define M_T5_DMA_MAXRDREQSIZE 0x7U +#define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE) +#define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE) + +#define S_T5_DMA_MAXRSPCNT 8 +#define M_T5_DMA_MAXRSPCNT 0x1ffU +#define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT) +#define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT) + +#define S_SEQCHKDIS 7 +#define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS) +#define F_SEQCHKDIS V_SEQCHKDIS(1U) + +#define S_MINTAG 0 +#define M_MINTAG 0x7fU +#define V_MINTAG(x) ((x) << S_MINTAG) +#define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG) + +#define A_PCIE_T5_DMA_STAT 0x5944 + +#define S_DMA_RESPCNT 20 +#define M_DMA_RESPCNT 0xfffU +#define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT) +#define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT) + +#define S_DMA_RDREQCNT 12 +#define M_DMA_RDREQCNT 0xffU +#define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT) +#define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT) + +#define S_DMA_WRREQCNT 0 +#define M_DMA_WRREQCNT 0x7ffU +#define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT) +#define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT) + +#define A_PCIE_T5_DMA_STAT2 0x5948 + +#define S_COOKIECNT 24 +#define M_COOKIECNT 0xfU +#define V_COOKIECNT(x) ((x) << S_COOKIECNT) +#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT) + +#define S_RDSEQNUMUPDCNT 20 +#define M_RDSEQNUMUPDCNT 0xfU +#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT) +#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT) + +#define S_SIREQCNT 16 +#define M_SIREQCNT 0xfU +#define V_SIREQCNT(x) ((x) << S_SIREQCNT) +#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT) + +#define S_WREOPMATCHSOP 12 +#define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP) +#define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U) + +#define S_WRSOPCNT 8 +#define M_WRSOPCNT 0xfU +#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT) +#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT) + +#define S_RDSOPCNT 0 +#define M_RDSOPCNT 0xffU +#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT) +#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT) + +#define A_PCIE_T5_DMA_STAT3 0x594c + +#define S_ATMREQSOPCNT 24 +#define M_ATMREQSOPCNT 0xffU +#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT) +#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT) + +#define S_ATMEOPMATCHSOP 17 +#define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP) +#define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U) + +#define S_RSPEOPMATCHSOP 16 +#define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP) +#define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U) + +#define S_RSPERRCNT 8 +#define M_RSPERRCNT 0xffU +#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT) +#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT) + +#define S_RSPSOPCNT 0 +#define M_RSPSOPCNT 0xffU +#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT) +#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT) + #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960 #define S_OP0H 24 @@ -2599,6 +5427,34 @@ #define V_ON3H(x) ((x) << S_ON3H) #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H) +#define A_PCIE_T5_CMD_CFG 0x5980 + +#define S_T5_CMD_MAXRDREQSIZE 17 +#define M_T5_CMD_MAXRDREQSIZE 0x7U +#define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE) +#define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE) + +#define S_T5_CMD_MAXRSPCNT 8 +#define M_T5_CMD_MAXRSPCNT 0xffU +#define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT) +#define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT) + +#define S_USECMDPOOL 7 +#define V_USECMDPOOL(x) ((x) << S_USECMDPOOL) +#define F_USECMDPOOL V_USECMDPOOL(1U) + +#define A_PCIE_T5_CMD_STAT 0x5984 + +#define S_T5_STAT_RSPCNT 20 +#define M_T5_STAT_RSPCNT 0x7ffU +#define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT) +#define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT) + +#define S_RDREQCNT 12 +#define M_RDREQCNT 0x1fU +#define V_RDREQCNT(x) ((x) << S_RDREQCNT) +#define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT) + #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988 #define S_IN0H 24 @@ -2621,6 +5477,8 @@ #define V_IN3H(x) ((x) << S_IN3H) #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H) +#define A_PCIE_T5_CMD_STAT2 0x5988 +#define A_PCIE_T5_CMD_STAT3 0x598c #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990 #define S_OC0T 24 @@ -2904,6 +5762,23 @@ #define V_CRSE(x) ((x) << S_CRSE) #define F_CRSE V_CRSE(1U) +#define A_PCIE_T5_HMA_CFG 0x59b0 + +#define S_HMA_MAXREQCNT 20 +#define M_HMA_MAXREQCNT 0x1fU +#define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT) +#define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT) + +#define S_T5_HMA_MAXRDREQSIZE 17 +#define M_T5_HMA_MAXRDREQSIZE 0x7U +#define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE) +#define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE) + +#define S_T5_HMA_MAXRSPCNT 8 +#define M_T5_HMA_MAXRSPCNT 0x1fU +#define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT) +#define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT) + #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4 #define S_RLCS 31 @@ -2950,6 +5825,23 @@ #define V_CRSS(x) ((x) << S_CRSS) #define F_CRSS V_CRSS(1U) +#define A_PCIE_T5_HMA_STAT 0x59b4 + +#define S_HMA_RESPCNT 20 +#define M_HMA_RESPCNT 0x1ffU +#define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT) +#define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT) + +#define S_HMA_RDREQCNT 12 +#define M_HMA_RDREQCNT 0x3fU +#define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT) +#define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT) + +#define S_HMA_WRREQCNT 0 +#define M_HMA_WRREQCNT 0x1ffU +#define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT) +#define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT) + #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8 #define S_RLCI 31 @@ -2996,6 +5888,7 @@ #define V_CRSI(x) ((x) << S_CRSI) #define F_CRSI V_CRSI(1U) +#define A_PCIE_T5_HMA_STAT2 0x59b8 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc #define S_PTOM 31 @@ -3038,6 +5931,7 @@ #define V_PMC7(x) ((x) << S_PMC7) #define F_PMC7 V_PMC7(1U) +#define A_PCIE_T5_HMA_STAT3 0x59bc #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0 #define S_PTOS 31 @@ -3112,6 +6006,84 @@ #define V_PME7(x) ((x) << S_PME7) #define F_PME7 V_PME7(1U) +#define A_PCIE_CGEN 0x59c0 + +#define S_VPD_DYNAMIC_CGEN 26 +#define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN) +#define F_VPD_DYNAMIC_CGEN V_VPD_DYNAMIC_CGEN(1U) + +#define S_MA_DYNAMIC_CGEN 25 +#define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN) +#define F_MA_DYNAMIC_CGEN V_MA_DYNAMIC_CGEN(1U) + +#define S_TAGQ_DYNAMIC_CGEN 24 +#define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN) +#define F_TAGQ_DYNAMIC_CGEN V_TAGQ_DYNAMIC_CGEN(1U) + +#define S_REQCTL_DYNAMIC_CGEN 23 +#define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN) +#define F_REQCTL_DYNAMIC_CGEN V_REQCTL_DYNAMIC_CGEN(1U) + +#define S_RSPDATAPROC_DYNAMIC_CGEN 22 +#define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN) +#define F_RSPDATAPROC_DYNAMIC_CGEN V_RSPDATAPROC_DYNAMIC_CGEN(1U) + +#define S_RSPRDQ_DYNAMIC_CGEN 21 +#define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN) +#define F_RSPRDQ_DYNAMIC_CGEN V_RSPRDQ_DYNAMIC_CGEN(1U) + +#define S_RSPIPIF_DYNAMIC_CGEN 20 +#define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN) +#define F_RSPIPIF_DYNAMIC_CGEN V_RSPIPIF_DYNAMIC_CGEN(1U) + +#define S_HMA_STATIC_CGEN 19 +#define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN) +#define F_HMA_STATIC_CGEN V_HMA_STATIC_CGEN(1U) + +#define S_HMA_DYNAMIC_CGEN 18 +#define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN) +#define F_HMA_DYNAMIC_CGEN V_HMA_DYNAMIC_CGEN(1U) + +#define S_CMD_STATIC_CGEN 16 +#define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN) +#define F_CMD_STATIC_CGEN V_CMD_STATIC_CGEN(1U) + +#define S_CMD_DYNAMIC_CGEN 15 +#define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN) +#define F_CMD_DYNAMIC_CGEN V_CMD_DYNAMIC_CGEN(1U) + +#define S_DMA_STATIC_CGEN 13 +#define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN) +#define F_DMA_STATIC_CGEN V_DMA_STATIC_CGEN(1U) + +#define S_DMA_DYNAMIC_CGEN 12 +#define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN) +#define F_DMA_DYNAMIC_CGEN V_DMA_DYNAMIC_CGEN(1U) + +#define S_VFID_SLEEPSTATUS 10 +#define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS) +#define F_VFID_SLEEPSTATUS V_VFID_SLEEPSTATUS(1U) + +#define S_VC1_SLEEPSTATUS 9 +#define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS) +#define F_VC1_SLEEPSTATUS V_VC1_SLEEPSTATUS(1U) + +#define S_STI_SLEEPSTATUS 8 +#define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS) +#define F_STI_SLEEPSTATUS V_STI_SLEEPSTATUS(1U) + +#define S_VFID_SLEEPREQ 2 +#define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ) +#define F_VFID_SLEEPREQ V_VFID_SLEEPREQ(1U) + +#define S_VC1_SLEEPREQ 1 +#define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ) +#define F_VC1_SLEEPREQ V_VC1_SLEEPREQ(1U) + +#define S_STI_SLEEPREQ 0 +#define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ) +#define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U) + #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4 #define S_PTOI 31 @@ -3154,6 +6126,21 @@ #define V_PC7I(x) ((x) << S_PC7I) #define F_PC7I V_PC7I(1U) +#define A_PCIE_MA_RSP 0x59c4 + +#define S_TIMERVALUE 8 +#define M_TIMERVALUE 0xffffffU +#define V_TIMERVALUE(x) ((x) << S_TIMERVALUE) +#define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE) + +#define S_MAREQTIMEREN 1 +#define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN) +#define F_MAREQTIMEREN V_MAREQTIMEREN(1U) + +#define S_MARSPTIMEREN 0 +#define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN) +#define F_MARSPTIMEREN V_MARSPTIMEREN(1U) + #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8 #define S_TOAK 31 @@ -3176,6 +6163,52 @@ #define V_ALET(x) ((x) << S_ALET) #define F_ALET V_ALET(1U) +#define A_PCIE_HPRD 0x59c8 + +#define S_NPH_CREDITSAVAILVC0 19 +#define M_NPH_CREDITSAVAILVC0 0x3U +#define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0) +#define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0) + +#define S_NPD_CREDITSAVAILVC0 17 +#define M_NPD_CREDITSAVAILVC0 0x3U +#define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0) +#define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0) + +#define S_NPH_CREDITSAVAILVC1 15 +#define M_NPH_CREDITSAVAILVC1 0x3U +#define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1) +#define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1) + +#define S_NPD_CREDITSAVAILVC1 13 +#define M_NPD_CREDITSAVAILVC1 0x3U +#define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1) +#define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1) + +#define S_NPH_CREDITSREQUIRED 11 +#define M_NPH_CREDITSREQUIRED 0x3U +#define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED) +#define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED) + +#define S_NPD_CREDITSREQUIRED 9 +#define M_NPD_CREDITSREQUIRED 0x3U +#define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED) +#define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED) + +#define S_REQBURSTCOUNT 5 +#define M_REQBURSTCOUNT 0xfU +#define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT) +#define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT) + +#define S_REQBURSTFREQUENCY 1 +#define M_REQBURSTFREQUENCY 0xfU +#define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY) +#define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY) + +#define S_ENABLEVC1 0 +#define V_ENABLEVC1(x) ((x) << S_ENABLEVC1) +#define F_ENABLEVC1 V_ENABLEVC1(1U) + #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc #define S_CPM0 30 @@ -3259,7 +6292,204 @@ #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7) #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0 +#define A_PCIE_PERR_GROUP 0x59d0 + +#define S_MST_DATAPATHPERR 25 +#define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR) +#define F_MST_DATAPATHPERR V_MST_DATAPATHPERR(1U) + +#define S_MST_RSPRDQPERR 24 +#define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR) +#define F_MST_RSPRDQPERR V_MST_RSPRDQPERR(1U) + +#define S_IP_RXPERR 23 +#define V_IP_RXPERR(x) ((x) << S_IP_RXPERR) +#define F_IP_RXPERR V_IP_RXPERR(1U) + +#define S_IP_BACKTXPERR 22 +#define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR) +#define F_IP_BACKTXPERR V_IP_BACKTXPERR(1U) + +#define S_IP_FRONTTXPERR 21 +#define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR) +#define F_IP_FRONTTXPERR V_IP_FRONTTXPERR(1U) + +#define S_TRGT1_FIDLKUPHDRPERR 20 +#define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR) +#define F_TRGT1_FIDLKUPHDRPERR V_TRGT1_FIDLKUPHDRPERR(1U) + +#define S_TRGT1_ALINDDATAPERR 19 +#define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR) +#define F_TRGT1_ALINDDATAPERR V_TRGT1_ALINDDATAPERR(1U) + +#define S_TRGT1_UNALINDATAPERR 18 +#define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR) +#define F_TRGT1_UNALINDATAPERR V_TRGT1_UNALINDATAPERR(1U) + +#define S_TRGT1_REQDATAPERR 17 +#define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR) +#define F_TRGT1_REQDATAPERR V_TRGT1_REQDATAPERR(1U) + +#define S_TRGT1_REQHDRPERR 16 +#define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR) +#define F_TRGT1_REQHDRPERR V_TRGT1_REQHDRPERR(1U) + +#define S_IPRXDATA_VC1PERR 15 +#define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR) +#define F_IPRXDATA_VC1PERR V_IPRXDATA_VC1PERR(1U) + +#define S_IPRXDATA_VC0PERR 14 +#define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR) +#define F_IPRXDATA_VC0PERR V_IPRXDATA_VC0PERR(1U) + +#define S_IPRXHDR_VC1PERR 13 +#define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR) +#define F_IPRXHDR_VC1PERR V_IPRXHDR_VC1PERR(1U) + +#define S_IPRXHDR_VC0PERR 12 +#define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR) +#define F_IPRXHDR_VC0PERR V_IPRXHDR_VC0PERR(1U) + +#define S_MA_RSPDATAPERR 11 +#define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR) +#define F_MA_RSPDATAPERR V_MA_RSPDATAPERR(1U) + +#define S_MA_CPLTAGQPERR 10 +#define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR) +#define F_MA_CPLTAGQPERR V_MA_CPLTAGQPERR(1U) + +#define S_MA_REQTAGQPERR 9 +#define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR) +#define F_MA_REQTAGQPERR V_MA_REQTAGQPERR(1U) + +#define S_PIOREQ_BAR2CTLPERR 8 +#define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR) +#define F_PIOREQ_BAR2CTLPERR V_PIOREQ_BAR2CTLPERR(1U) + +#define S_PIOREQ_MEMCTLPERR 7 +#define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR) +#define F_PIOREQ_MEMCTLPERR V_PIOREQ_MEMCTLPERR(1U) + +#define S_PIOREQ_PLMCTLPERR 6 +#define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR) +#define F_PIOREQ_PLMCTLPERR V_PIOREQ_PLMCTLPERR(1U) + +#define S_PIOREQ_BAR2DATAPERR 5 +#define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR) +#define F_PIOREQ_BAR2DATAPERR V_PIOREQ_BAR2DATAPERR(1U) + +#define S_PIOREQ_MEMDATAPERR 4 +#define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR) +#define F_PIOREQ_MEMDATAPERR V_PIOREQ_MEMDATAPERR(1U) + +#define S_PIOREQ_PLMDATAPERR 3 +#define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR) +#define F_PIOREQ_PLMDATAPERR V_PIOREQ_PLMDATAPERR(1U) + +#define S_PIOCPL_CTLPERR 2 +#define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR) +#define F_PIOCPL_CTLPERR V_PIOCPL_CTLPERR(1U) + +#define S_PIOCPL_DATAPERR 1 +#define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR) +#define F_PIOCPL_DATAPERR V_PIOCPL_DATAPERR(1U) + +#define S_PIOCPL_PLMRSPPERR 0 +#define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR) +#define F_PIOCPL_PLMRSPPERR V_PIOCPL_PLMRSPPERR(1U) + #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4 +#define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4 + +#define S_CPLSTATUSINTEN 12 +#define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN) +#define F_CPLSTATUSINTEN V_CPLSTATUSINTEN(1U) + +#define S_REQTIMEOUTINTEN 11 +#define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN) +#define F_REQTIMEOUTINTEN V_REQTIMEOUTINTEN(1U) + +#define S_DISABLEDINTEN 10 +#define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN) +#define F_DISABLEDINTEN V_DISABLEDINTEN(1U) + +#define S_RSPDROPFLRINTEN 9 +#define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN) +#define F_RSPDROPFLRINTEN V_RSPDROPFLRINTEN(1U) + +#define S_REQUNDERFLRINTEN 8 +#define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN) +#define F_REQUNDERFLRINTEN V_REQUNDERFLRINTEN(1U) + +#define S_CPLSTATUSLOGEN 4 +#define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN) +#define F_CPLSTATUSLOGEN V_CPLSTATUSLOGEN(1U) + +#define S_TIMEOUTLOGEN 3 +#define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN) +#define F_TIMEOUTLOGEN V_TIMEOUTLOGEN(1U) + +#define S_DISABLEDLOGEN 2 +#define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN) +#define F_DISABLEDLOGEN V_DISABLEDLOGEN(1U) + +#define S_RSPDROPFLRLOGEN 1 +#define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN) +#define F_RSPDROPFLRLOGEN V_RSPDROPFLRLOGEN(1U) + +#define S_REQUNDERFLRLOGEN 0 +#define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN) +#define F_REQUNDERFLRLOGEN V_REQUNDERFLRLOGEN(1U) + +#define A_PCIE_RSP_ERR_LOG1 0x59d8 + +#define S_REQTAG 25 +#define M_REQTAG 0x7fU +#define V_REQTAG(x) ((x) << S_REQTAG) +#define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG) + +#define S_CID 22 +#define M_CID 0x7U +#define V_CID(x) ((x) << S_CID) +#define G_CID(x) (((x) >> S_CID) & M_CID) + +#define S_CHNUM 19 +#define M_CHNUM 0x7U +#define V_CHNUM(x) ((x) << S_CHNUM) +#define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM) + +#define S_BYTELEN 6 +#define M_BYTELEN 0x1fffU +#define V_BYTELEN(x) ((x) << S_BYTELEN) +#define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN) + +#define S_REASON 3 +#define M_REASON 0x7U +#define V_REASON(x) ((x) << S_REASON) +#define G_REASON(x) (((x) >> S_REASON) & M_REASON) + +#define S_CPLSTATUS 0 +#define M_CPLSTATUS 0x7U +#define V_CPLSTATUS(x) ((x) << S_CPLSTATUS) +#define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS) + +#define A_PCIE_RSP_ERR_LOG2 0x59dc + +#define S_LOGVALID 31 +#define V_LOGVALID(x) ((x) << S_LOGVALID) +#define F_LOGVALID V_LOGVALID(1U) + +#define S_ADDR10B 8 +#define M_ADDR10B 0x3ffU +#define V_ADDR10B(x) ((x) << S_ADDR10B) +#define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B) + +#define S_REQVFID 0 +#define M_REQVFID 0xffU +#define V_REQVFID(x) ((x) << S_REQVFID) +#define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID) + +#define A_PCIE_CHANGESET 0x59fc #define A_PCIE_REVISION 0x5a00 #define A_PCIE_PDEBUG_INDEX 0x5a04 @@ -3402,6 +6632,12 @@ #define A_PCIE_BUS_MST_STAT_2 0x5a68 #define A_PCIE_BUS_MST_STAT_3 0x5a6c #define A_PCIE_BUS_MST_STAT_4 0x5a70 + +#define S_BUSMST_135_128 0 +#define M_BUSMST_135_128 0xffU +#define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128) +#define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128) + #define A_PCIE_BUS_MST_STAT_5 0x5a74 #define A_PCIE_BUS_MST_STAT_6 0x5a78 #define A_PCIE_BUS_MST_STAT_7 0x5a7c @@ -3410,9 +6646,53 @@ #define A_PCIE_RSP_ERR_STAT_2 0x5a88 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c #define A_PCIE_RSP_ERR_STAT_4 0x5a90 + +#define S_RSPERR_135_128 0 +#define M_RSPERR_135_128 0xffU +#define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128) +#define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128) + #define A_PCIE_RSP_ERR_STAT_5 0x5a94 +#define A_PCIE_DBI_TIMEOUT_CTL 0x5a94 + +#define S_DBI_TIMER 0 +#define M_DBI_TIMER 0xffffU +#define V_DBI_TIMER(x) ((x) << S_DBI_TIMER) +#define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER) + #define A_PCIE_RSP_ERR_STAT_6 0x5a98 +#define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c +#define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c + +#define S_SOURCE 16 +#define M_SOURCE 0x3U +#define V_SOURCE(x) ((x) << S_SOURCE) +#define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE) + +#define S_DBI_WRITE 12 +#define M_DBI_WRITE 0xfU +#define V_DBI_WRITE(x) ((x) << S_DBI_WRITE) +#define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE) + +#define S_DBI_CS2 11 +#define V_DBI_CS2(x) ((x) << S_DBI_CS2) +#define F_DBI_CS2 V_DBI_CS2(1U) + +#define S_DBI_PF 8 +#define M_DBI_PF 0x7U +#define V_DBI_PF(x) ((x) << S_DBI_PF) +#define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF) + +#define S_PL_TOVFVLD 7 +#define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD) +#define F_PL_TOVFVLD V_PL_TOVFVLD(1U) + +#define S_PL_TOVF 0 +#define M_PL_TOVF 0x7fU +#define V_PL_TOVF(x) ((x) << S_PL_TOVF) +#define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF) + #define A_PCIE_MSI_EN_0 0x5aa0 #define A_PCIE_MSI_EN_1 0x5aa4 #define A_PCIE_MSI_EN_2 0x5aa8 @@ -3446,6 +6726,388 @@ #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ) #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ) +#define A_PCIE_PB_CTL 0x5b94 + +#define S_PB_SEL 16 +#define M_PB_SEL 0xffU +#define V_PB_SEL(x) ((x) << S_PB_SEL) +#define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL) + +#define S_PB_SELREG 8 +#define M_PB_SELREG 0xffU +#define V_PB_SELREG(x) ((x) << S_PB_SELREG) +#define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG) + +#define S_PB_FUNC 0 +#define M_PB_FUNC 0x7U +#define V_PB_FUNC(x) ((x) << S_PB_FUNC) +#define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC) + +#define A_PCIE_PB_DATA 0x5b98 +#define A_PCIE_CUR_LINK 0x5b9c + +#define S_CFGINITCOEFFDONESEEN 22 +#define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN) +#define F_CFGINITCOEFFDONESEEN V_CFGINITCOEFFDONESEEN(1U) + +#define S_CFGINITCOEFFDONE 21 +#define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE) +#define F_CFGINITCOEFFDONE V_CFGINITCOEFFDONE(1U) + +#define S_XMLH_LINK_UP 20 +#define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP) +#define F_XMLH_LINK_UP V_XMLH_LINK_UP(1U) + +#define S_PM_LINKST_IN_L0S 19 +#define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S) +#define F_PM_LINKST_IN_L0S V_PM_LINKST_IN_L0S(1U) + +#define S_PM_LINKST_IN_L1 18 +#define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1) +#define F_PM_LINKST_IN_L1 V_PM_LINKST_IN_L1(1U) + +#define S_PM_LINKST_IN_L2 17 +#define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2) +#define F_PM_LINKST_IN_L2 V_PM_LINKST_IN_L2(1U) + +#define S_PM_LINKST_L2_EXIT 16 +#define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT) +#define F_PM_LINKST_L2_EXIT V_PM_LINKST_L2_EXIT(1U) + +#define S_XMLH_IN_RL0S 15 +#define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S) +#define F_XMLH_IN_RL0S V_XMLH_IN_RL0S(1U) + +#define S_XMLH_LTSSM_STATE_RCVRY_EQ 14 +#define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ) +#define F_XMLH_LTSSM_STATE_RCVRY_EQ V_XMLH_LTSSM_STATE_RCVRY_EQ(1U) + +#define S_NEGOTIATEDWIDTH 8 +#define M_NEGOTIATEDWIDTH 0x3fU +#define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH) +#define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH) + +#define S_ACTIVELANES 0 +#define M_ACTIVELANES 0xffU +#define V_ACTIVELANES(x) ((x) << S_ACTIVELANES) +#define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES) + +#define A_PCIE_PHY_REQRXPWR 0x5ba0 + +#define S_LNH_RXSTATEDONE 31 +#define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE) +#define F_LNH_RXSTATEDONE V_LNH_RXSTATEDONE(1U) + +#define S_LNH_RXSTATEREQ 30 +#define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ) +#define F_LNH_RXSTATEREQ V_LNH_RXSTATEREQ(1U) + +#define S_LNH_RXPWRSTATE 28 +#define M_LNH_RXPWRSTATE 0x3U +#define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE) +#define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE) + +#define S_LNG_RXSTATEDONE 27 +#define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE) +#define F_LNG_RXSTATEDONE V_LNG_RXSTATEDONE(1U) + +#define S_LNG_RXSTATEREQ 26 +#define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ) +#define F_LNG_RXSTATEREQ V_LNG_RXSTATEREQ(1U) + +#define S_LNG_RXPWRSTATE 24 +#define M_LNG_RXPWRSTATE 0x3U +#define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE) +#define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE) + +#define S_LNF_RXSTATEDONE 23 +#define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE) +#define F_LNF_RXSTATEDONE V_LNF_RXSTATEDONE(1U) + +#define S_LNF_RXSTATEREQ 22 +#define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ) +#define F_LNF_RXSTATEREQ V_LNF_RXSTATEREQ(1U) + +#define S_LNF_RXPWRSTATE 20 +#define M_LNF_RXPWRSTATE 0x3U +#define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE) +#define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE) + +#define S_LNE_RXSTATEDONE 19 +#define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE) +#define F_LNE_RXSTATEDONE V_LNE_RXSTATEDONE(1U) + +#define S_LNE_RXSTATEREQ 18 +#define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ) +#define F_LNE_RXSTATEREQ V_LNE_RXSTATEREQ(1U) + +#define S_LNE_RXPWRSTATE 16 +#define M_LNE_RXPWRSTATE 0x3U +#define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE) +#define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE) + +#define S_LND_RXSTATEDONE 15 +#define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE) +#define F_LND_RXSTATEDONE V_LND_RXSTATEDONE(1U) + +#define S_LND_RXSTATEREQ 14 +#define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ) +#define F_LND_RXSTATEREQ V_LND_RXSTATEREQ(1U) + +#define S_LND_RXPWRSTATE 12 +#define M_LND_RXPWRSTATE 0x3U +#define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE) +#define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE) + +#define S_LNC_RXSTATEDONE 11 +#define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE) +#define F_LNC_RXSTATEDONE V_LNC_RXSTATEDONE(1U) + +#define S_LNC_RXSTATEREQ 10 +#define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ) +#define F_LNC_RXSTATEREQ V_LNC_RXSTATEREQ(1U) + +#define S_LNC_RXPWRSTATE 8 +#define M_LNC_RXPWRSTATE 0x3U +#define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE) +#define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE) + +#define S_LNB_RXSTATEDONE 7 +#define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE) +#define F_LNB_RXSTATEDONE V_LNB_RXSTATEDONE(1U) + +#define S_LNB_RXSTATEREQ 6 +#define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ) +#define F_LNB_RXSTATEREQ V_LNB_RXSTATEREQ(1U) + +#define S_LNB_RXPWRSTATE 4 +#define M_LNB_RXPWRSTATE 0x3U +#define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE) +#define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE) + +#define S_LNA_RXSTATEDONE 3 +#define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE) +#define F_LNA_RXSTATEDONE V_LNA_RXSTATEDONE(1U) + +#define S_LNA_RXSTATEREQ 2 +#define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ) +#define F_LNA_RXSTATEREQ V_LNA_RXSTATEREQ(1U) + +#define S_LNA_RXPWRSTATE 0 +#define M_LNA_RXPWRSTATE 0x3U +#define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE) +#define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE) + +#define A_PCIE_PHY_CURRXPWR 0x5ba4 +#define A_PCIE_PHY_GEN3_AE0 0x5ba8 + +#define S_LND_STAT 28 +#define M_LND_STAT 0x7U +#define V_LND_STAT(x) ((x) << S_LND_STAT) +#define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT) + +#define S_LND_CMD 24 +#define M_LND_CMD 0x7U +#define V_LND_CMD(x) ((x) << S_LND_CMD) +#define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD) + +#define S_LNC_STAT 20 +#define M_LNC_STAT 0x7U +#define V_LNC_STAT(x) ((x) << S_LNC_STAT) +#define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT) + +#define S_LNC_CMD 16 +#define M_LNC_CMD 0x7U +#define V_LNC_CMD(x) ((x) << S_LNC_CMD) +#define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD) + +#define S_LNB_STAT 12 +#define M_LNB_STAT 0x7U +#define V_LNB_STAT(x) ((x) << S_LNB_STAT) +#define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT) + +#define S_LNB_CMD 8 +#define M_LNB_CMD 0x7U +#define V_LNB_CMD(x) ((x) << S_LNB_CMD) +#define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD) + +#define S_LNA_STAT 4 +#define M_LNA_STAT 0x7U +#define V_LNA_STAT(x) ((x) << S_LNA_STAT) +#define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT) + +#define S_LNA_CMD 0 +#define M_LNA_CMD 0x7U +#define V_LNA_CMD(x) ((x) << S_LNA_CMD) +#define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD) + +#define A_PCIE_PHY_GEN3_AE1 0x5bac + +#define S_LNH_STAT 28 +#define M_LNH_STAT 0x7U +#define V_LNH_STAT(x) ((x) << S_LNH_STAT) +#define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT) + +#define S_LNH_CMD 24 +#define M_LNH_CMD 0x7U +#define V_LNH_CMD(x) ((x) << S_LNH_CMD) +#define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD) + +#define S_LNG_STAT 20 +#define M_LNG_STAT 0x7U +#define V_LNG_STAT(x) ((x) << S_LNG_STAT) +#define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT) + +#define S_LNG_CMD 16 +#define M_LNG_CMD 0x7U +#define V_LNG_CMD(x) ((x) << S_LNG_CMD) +#define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD) + +#define S_LNF_STAT 12 +#define M_LNF_STAT 0x7U +#define V_LNF_STAT(x) ((x) << S_LNF_STAT) +#define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT) + +#define S_LNF_CMD 8 +#define M_LNF_CMD 0x7U +#define V_LNF_CMD(x) ((x) << S_LNF_CMD) +#define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD) + +#define S_LNE_STAT 4 +#define M_LNE_STAT 0x7U +#define V_LNE_STAT(x) ((x) << S_LNE_STAT) +#define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT) + +#define S_LNE_CMD 0 +#define M_LNE_CMD 0x7U +#define V_LNE_CMD(x) ((x) << S_LNE_CMD) +#define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD) + +#define A_PCIE_PHY_FS_LF0 0x5bb0 + +#define S_LANE1LF 24 +#define M_LANE1LF 0x3fU +#define V_LANE1LF(x) ((x) << S_LANE1LF) +#define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF) + +#define S_LANE1FS 16 +#define M_LANE1FS 0x3fU +#define V_LANE1FS(x) ((x) << S_LANE1FS) +#define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS) + +#define S_LANE0LF 8 +#define M_LANE0LF 0x3fU +#define V_LANE0LF(x) ((x) << S_LANE0LF) +#define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF) + +#define S_LANE0FS 0 +#define M_LANE0FS 0x3fU +#define V_LANE0FS(x) ((x) << S_LANE0FS) +#define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS) + +#define A_PCIE_PHY_FS_LF1 0x5bb4 + +#define S_LANE3LF 24 +#define M_LANE3LF 0x3fU +#define V_LANE3LF(x) ((x) << S_LANE3LF) +#define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF) + +#define S_LANE3FS 16 +#define M_LANE3FS 0x3fU +#define V_LANE3FS(x) ((x) << S_LANE3FS) +#define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS) + +#define S_LANE2LF 8 +#define M_LANE2LF 0x3fU +#define V_LANE2LF(x) ((x) << S_LANE2LF) +#define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF) + +#define S_LANE2FS 0 +#define M_LANE2FS 0x3fU +#define V_LANE2FS(x) ((x) << S_LANE2FS) +#define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS) + +#define A_PCIE_PHY_FS_LF2 0x5bb8 + +#define S_LANE5LF 24 +#define M_LANE5LF 0x3fU +#define V_LANE5LF(x) ((x) << S_LANE5LF) +#define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF) + +#define S_LANE5FS 16 +#define M_LANE5FS 0x3fU +#define V_LANE5FS(x) ((x) << S_LANE5FS) +#define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS) + +#define S_LANE4LF 8 +#define M_LANE4LF 0x3fU +#define V_LANE4LF(x) ((x) << S_LANE4LF) +#define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF) + +#define S_LANE4FS 0 +#define M_LANE4FS 0x3fU +#define V_LANE4FS(x) ((x) << S_LANE4FS) +#define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS) + +#define A_PCIE_PHY_FS_LF3 0x5bbc + +#define S_LANE7LF 24 +#define M_LANE7LF 0x3fU +#define V_LANE7LF(x) ((x) << S_LANE7LF) +#define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF) + +#define S_LANE7FS 16 +#define M_LANE7FS 0x3fU +#define V_LANE7FS(x) ((x) << S_LANE7FS) +#define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS) + +#define S_LANE6LF 8 +#define M_LANE6LF 0x3fU +#define V_LANE6LF(x) ((x) << S_LANE6LF) +#define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF) + +#define S_LANE6FS 0 +#define M_LANE6FS 0x3fU +#define V_LANE6FS(x) ((x) << S_LANE6FS) +#define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS) + +#define A_PCIE_PHY_PRESET_REQ 0x5bc0 + +#define S_COEFFDONE 16 +#define V_COEFFDONE(x) ((x) << S_COEFFDONE) +#define F_COEFFDONE V_COEFFDONE(1U) + +#define S_COEFFLANE 8 +#define M_COEFFLANE 0x7U +#define V_COEFFLANE(x) ((x) << S_COEFFLANE) +#define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE) + +#define S_COEFFSTART 0 +#define V_COEFFSTART(x) ((x) << S_COEFFSTART) +#define F_COEFFSTART V_COEFFSTART(1U) + +#define A_PCIE_PHY_PRESET_COEFF 0x5bc4 + +#define S_COEFF 0 +#define M_COEFF 0x3ffffU +#define V_COEFF(x) ((x) << S_COEFF) +#define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF) + +#define A_PCIE_PHY_INDIR_REQ 0x5bf0 + +#define S_PHYENABLE 31 +#define V_PHYENABLE(x) ((x) << S_PHYENABLE) +#define F_PHYENABLE V_PHYENABLE(1U) + +#define S_PCIE_PHY_REGADDR 0 +#define M_PCIE_PHY_REGADDR 0xffffU +#define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR) +#define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR) + +#define A_PCIE_PHY_INDIR_DATA 0x5bf4 +#define A_PCIE_STATIC_SPARE1 0x5bf8 +#define A_PCIE_STATIC_SPARE2 0x5bfc + /* registers for module DBG */ #define DBG_BASE_ADDR 0x6000 @@ -3490,6 +7152,11 @@ #define A_DBG_DBG1_CFG 0x6008 #define A_DBG_DBG1_EN 0x600c + +#define S_CLK_EN_ON_DBG1 20 +#define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1) +#define F_CLK_EN_ON_DBG1 V_CLK_EN_ON_DBG1(1U) + #define A_DBG_GPIO_EN 0x6010 #define S_GPIO15_OEN 31 @@ -3856,6 +7523,22 @@ #define V_GPIO0(x) ((x) << S_GPIO0) #define F_GPIO0 V_GPIO0(1U) +#define S_GPIO19 29 +#define V_GPIO19(x) ((x) << S_GPIO19) +#define F_GPIO19 V_GPIO19(1U) + +#define S_GPIO18 28 +#define V_GPIO18(x) ((x) << S_GPIO18) +#define F_GPIO18 V_GPIO18(1U) + +#define S_GPIO17 27 +#define V_GPIO17(x) ((x) << S_GPIO17) +#define F_GPIO17 V_GPIO17(1U) + +#define S_GPIO16 26 +#define V_GPIO16(x) ((x) << S_GPIO16) +#define F_GPIO16 V_GPIO16(1U) + #define A_DBG_INT_CAUSE 0x601c #define S_IBM_FDL_FAIL_INT_CAUSE 25 @@ -4029,6 +7712,22 @@ #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) +#define S_GPIO19_ACT_LOW 25 +#define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW) +#define F_GPIO19_ACT_LOW V_GPIO19_ACT_LOW(1U) + +#define S_GPIO18_ACT_LOW 24 +#define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW) +#define F_GPIO18_ACT_LOW V_GPIO18_ACT_LOW(1U) + +#define S_GPIO17_ACT_LOW 23 +#define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW) +#define F_GPIO17_ACT_LOW V_GPIO17_ACT_LOW(1U) + +#define S_GPIO16_ACT_LOW 22 +#define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW) +#define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U) + #define A_DBG_EFUSE_BYTE0_3 0x6034 #define A_DBG_EFUSE_BYTE4_7 0x6038 #define A_DBG_EFUSE_BYTE8_11 0x603c @@ -4294,6 +7993,11 @@ #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL) #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL) +#define S_T5_P_OCLK_MUXSEL 13 +#define M_T5_P_OCLK_MUXSEL 0xfU +#define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL) +#define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL) + #define A_DBG_TRACE0_CONF_COMPREG0 0x6060 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068 @@ -4381,6 +8085,513 @@ #define A_DBG_TRACE0_DATA_OUT 0x6094 #define A_DBG_TRACE1_DATA_OUT 0x6098 +#define A_DBG_FUSE_SENSE_DONE 0x609c + +#define S_STATIC_JTAG_VERSIONNR 5 +#define M_STATIC_JTAG_VERSIONNR 0xfU +#define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR) +#define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR) + +#define S_UNQ0 1 +#define M_UNQ0 0xfU +#define V_UNQ0(x) ((x) << S_UNQ0) +#define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0) + +#define S_FUSE_DONE_SENSE 0 +#define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE) +#define F_FUSE_DONE_SENSE V_FUSE_DONE_SENSE(1U) + +#define A_DBG_TVSENSE_EN 0x60a8 + +#define S_MCIMPED1_OUT 29 +#define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT) +#define F_MCIMPED1_OUT V_MCIMPED1_OUT(1U) + +#define S_MCIMPED2_OUT 28 +#define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT) +#define F_MCIMPED2_OUT V_MCIMPED2_OUT(1U) + +#define S_TVSENSE_SNSOUT 17 +#define M_TVSENSE_SNSOUT 0x1ffU +#define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT) +#define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT) + +#define S_TVSENSE_OUTPUTVALID 16 +#define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID) +#define F_TVSENSE_OUTPUTVALID V_TVSENSE_OUTPUTVALID(1U) + +#define S_TVSENSE_SLEEP 10 +#define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP) +#define F_TVSENSE_SLEEP V_TVSENSE_SLEEP(1U) + +#define S_TVSENSE_SENSV 9 +#define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV) +#define F_TVSENSE_SENSV V_TVSENSE_SENSV(1U) + +#define S_TVSENSE_RST 8 +#define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST) +#define F_TVSENSE_RST V_TVSENSE_RST(1U) + +#define S_TVSENSE_RATIO 0 +#define M_TVSENSE_RATIO 0xffU +#define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO) +#define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO) + +#define A_DBG_CUST_EFUSE_OUT_EN 0x60ac +#define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0 +#define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4 + +#define S_DBG_FEENABLE 29 +#define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE) +#define F_DBG_FEENABLE V_DBG_FEENABLE(1U) + +#define S_DBG_FEF 23 +#define M_DBG_FEF 0x3fU +#define V_DBG_FEF(x) ((x) << S_DBG_FEF) +#define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF) + +#define S_DBG_FEMIMICN 22 +#define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN) +#define F_DBG_FEMIMICN V_DBG_FEMIMICN(1U) + +#define S_DBG_FEGATEC 21 +#define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC) +#define F_DBG_FEGATEC V_DBG_FEGATEC(1U) + +#define S_DBG_FEPROGP 20 +#define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP) +#define F_DBG_FEPROGP V_DBG_FEPROGP(1U) + +#define S_DBG_FEREADCLK 19 +#define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK) +#define F_DBG_FEREADCLK V_DBG_FEREADCLK(1U) + +#define S_DBG_FERSEL 3 +#define M_DBG_FERSEL 0xffffU +#define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL) +#define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL) + +#define S_DBG_FETIME 0 +#define M_DBG_FETIME 0x7U +#define V_DBG_FETIME(x) ((x) << S_DBG_FETIME) +#define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME) + +#define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8 + +#define S_T5_STATIC_M_PLL_MULTFRAC 8 +#define M_T5_STATIC_M_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC) +#define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC) + +#define S_T5_STATIC_M_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_M_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE) +#define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc + +#define S_T5_STATIC_M_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS) +#define F_T5_STATIC_M_PLL_DCO_BYPASS V_T5_STATIC_M_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_M_PLL_SDORDER 21 +#define M_T5_STATIC_M_PLL_SDORDER 0x3U +#define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER) +#define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER) + +#define S_T5_STATIC_M_PLL_FFENABLE 20 +#define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE) +#define F_T5_STATIC_M_PLL_FFENABLE V_T5_STATIC_M_PLL_FFENABLE(1U) + +#define S_T5_STATIC_M_PLL_STOPCLKB 19 +#define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB) +#define F_T5_STATIC_M_PLL_STOPCLKB V_T5_STATIC_M_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_M_PLL_STOPCLKA 18 +#define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA) +#define F_T5_STATIC_M_PLL_STOPCLKA V_T5_STATIC_M_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_M_PLL_SLEEP 17 +#define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP) +#define F_T5_STATIC_M_PLL_SLEEP V_T5_STATIC_M_PLL_SLEEP(1U) + +#define S_T5_STATIC_M_PLL_BYPASS 16 +#define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS) +#define F_T5_STATIC_M_PLL_BYPASS V_T5_STATIC_M_PLL_BYPASS(1U) + +#define S_T5_STATIC_M_PLL_LOCKTUNE 0 +#define M_T5_STATIC_M_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE) +#define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0 + +#define S_T5_STATIC_M_PLL_MULTPRE 30 +#define M_T5_STATIC_M_PLL_MULTPRE 0x3U +#define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE) +#define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE) + +#define S_T5_STATIC_M_PLL_LOCKSEL 28 +#define M_T5_STATIC_M_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL) +#define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL) + +#define S_T5_STATIC_M_PLL_FFTUNE 12 +#define M_T5_STATIC_M_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE) +#define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE) + +#define S_T5_STATIC_M_PLL_RANGEPRE 10 +#define M_T5_STATIC_M_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE) +#define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE) + +#define S_T5_STATIC_M_PLL_RANGEB 5 +#define M_T5_STATIC_M_PLL_RANGEB 0x1fU +#define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB) +#define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB) + +#define S_T5_STATIC_M_PLL_RANGEA 0 +#define M_T5_STATIC_M_PLL_RANGEA 0x1fU +#define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA) +#define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA) + +#define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4 +#define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8 + +#define S_T5_STATIC_M_PLL_VCVTUNE 24 +#define M_T5_STATIC_M_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE) +#define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE) + +#define S_T5_STATIC_M_PLL_RESET 23 +#define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET) +#define F_T5_STATIC_M_PLL_RESET V_T5_STATIC_M_PLL_RESET(1U) + +#define S_T5_STATIC_MPLL_REFCLK_SEL 22 +#define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL) +#define F_T5_STATIC_MPLL_REFCLK_SEL V_T5_STATIC_MPLL_REFCLK_SEL(1U) + +#define S_T5_STATIC_M_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_M_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40) +#define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_M_PLL_PREDIV 8 +#define M_T5_STATIC_M_PLL_PREDIV 0x1fU +#define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV) +#define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV) + +#define S_T5_STATIC_M_PLL_MULT 0 +#define M_T5_STATIC_M_PLL_MULT 0xffU +#define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT) +#define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT) + +#define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc + +#define S_T5_STATIC_PHY0RECRST_ 5 +#define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_) +#define F_T5_STATIC_PHY0RECRST_ V_T5_STATIC_PHY0RECRST_(1U) + +#define S_T5_STATIC_PHY1RECRST_ 4 +#define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_) +#define F_T5_STATIC_PHY1RECRST_ V_T5_STATIC_PHY1RECRST_(1U) + +#define S_T5_STATIC_SWMC0RST_ 3 +#define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_) +#define F_T5_STATIC_SWMC0RST_ V_T5_STATIC_SWMC0RST_(1U) + +#define S_T5_STATIC_SWMC0CFGRST_ 2 +#define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_) +#define F_T5_STATIC_SWMC0CFGRST_ V_T5_STATIC_SWMC0CFGRST_(1U) + +#define S_T5_STATIC_SWMC1RST_ 1 +#define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_) +#define F_T5_STATIC_SWMC1RST_ V_T5_STATIC_SWMC1RST_(1U) + +#define S_T5_STATIC_SWMC1CFGRST_ 0 +#define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_) +#define F_T5_STATIC_SWMC1CFGRST_ V_T5_STATIC_SWMC1CFGRST_(1U) + +#define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0 + +#define S_T5_STATIC_C_PLL_MULTFRAC 8 +#define M_T5_STATIC_C_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC) +#define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC) + +#define S_T5_STATIC_C_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_C_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE) +#define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4 + +#define S_T5_STATIC_C_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS) +#define F_T5_STATIC_C_PLL_DCO_BYPASS V_T5_STATIC_C_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_C_PLL_SDORDER 21 +#define M_T5_STATIC_C_PLL_SDORDER 0x3U +#define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER) +#define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER) + +#define S_T5_STATIC_C_PLL_FFENABLE 20 +#define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE) +#define F_T5_STATIC_C_PLL_FFENABLE V_T5_STATIC_C_PLL_FFENABLE(1U) + +#define S_T5_STATIC_C_PLL_STOPCLKB 19 +#define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB) +#define F_T5_STATIC_C_PLL_STOPCLKB V_T5_STATIC_C_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_C_PLL_STOPCLKA 18 +#define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA) +#define F_T5_STATIC_C_PLL_STOPCLKA V_T5_STATIC_C_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_C_PLL_SLEEP 17 +#define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP) +#define F_T5_STATIC_C_PLL_SLEEP V_T5_STATIC_C_PLL_SLEEP(1U) + +#define S_T5_STATIC_C_PLL_BYPASS 16 +#define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS) +#define F_T5_STATIC_C_PLL_BYPASS V_T5_STATIC_C_PLL_BYPASS(1U) + +#define S_T5_STATIC_C_PLL_LOCKTUNE 0 +#define M_T5_STATIC_C_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE) +#define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8 + +#define S_T5_STATIC_C_PLL_MULTPRE 30 +#define M_T5_STATIC_C_PLL_MULTPRE 0x3U +#define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE) +#define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE) + +#define S_T5_STATIC_C_PLL_LOCKSEL 28 +#define M_T5_STATIC_C_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL) +#define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL) + +#define S_T5_STATIC_C_PLL_FFTUNE 12 +#define M_T5_STATIC_C_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE) +#define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE) + +#define S_T5_STATIC_C_PLL_RANGEPRE 10 +#define M_T5_STATIC_C_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE) +#define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE) + +#define S_T5_STATIC_C_PLL_RANGEB 5 +#define M_T5_STATIC_C_PLL_RANGEB 0x1fU +#define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB) +#define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB) + +#define S_T5_STATIC_C_PLL_RANGEA 0 +#define M_T5_STATIC_C_PLL_RANGEA 0x1fU +#define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA) +#define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA) + +#define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc +#define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0 + +#define S_T5_STATIC_C_PLL_VCVTUNE 22 +#define M_T5_STATIC_C_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE) +#define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE) + +#define S_T5_STATIC_C_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_C_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40) +#define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_C_PLL_PREDIV 8 +#define M_T5_STATIC_C_PLL_PREDIV 0x1fU +#define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV) +#define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV) + +#define S_T5_STATIC_C_PLL_MULT 0 +#define M_T5_STATIC_C_PLL_MULT 0xffU +#define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT) +#define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT) + +#define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4 + +#define S_T5_STATIC_U_PLL_MULTFRAC 8 +#define M_T5_STATIC_U_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC) +#define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC) + +#define S_T5_STATIC_U_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_U_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE) +#define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8 + +#define S_T5_STATIC_U_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS) +#define F_T5_STATIC_U_PLL_DCO_BYPASS V_T5_STATIC_U_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_U_PLL_SDORDER 21 +#define M_T5_STATIC_U_PLL_SDORDER 0x3U +#define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER) +#define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER) + +#define S_T5_STATIC_U_PLL_FFENABLE 20 +#define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE) +#define F_T5_STATIC_U_PLL_FFENABLE V_T5_STATIC_U_PLL_FFENABLE(1U) + +#define S_T5_STATIC_U_PLL_STOPCLKB 19 +#define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB) +#define F_T5_STATIC_U_PLL_STOPCLKB V_T5_STATIC_U_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_U_PLL_STOPCLKA 18 +#define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA) +#define F_T5_STATIC_U_PLL_STOPCLKA V_T5_STATIC_U_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_U_PLL_SLEEP 17 +#define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP) +#define F_T5_STATIC_U_PLL_SLEEP V_T5_STATIC_U_PLL_SLEEP(1U) + +#define S_T5_STATIC_U_PLL_BYPASS 16 +#define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS) +#define F_T5_STATIC_U_PLL_BYPASS V_T5_STATIC_U_PLL_BYPASS(1U) + +#define S_T5_STATIC_U_PLL_LOCKTUNE 0 +#define M_T5_STATIC_U_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE) +#define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec + +#define S_T5_STATIC_U_PLL_MULTPRE 30 +#define M_T5_STATIC_U_PLL_MULTPRE 0x3U +#define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE) +#define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE) + +#define S_T5_STATIC_U_PLL_LOCKSEL 28 +#define M_T5_STATIC_U_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL) +#define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL) + +#define S_T5_STATIC_U_PLL_FFTUNE 12 +#define M_T5_STATIC_U_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE) +#define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE) + +#define S_T5_STATIC_U_PLL_RANGEPRE 10 +#define M_T5_STATIC_U_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE) +#define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE) + +#define S_T5_STATIC_U_PLL_RANGEB 5 +#define M_T5_STATIC_U_PLL_RANGEB 0x1fU +#define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB) +#define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB) + +#define S_T5_STATIC_U_PLL_RANGEA 0 +#define M_T5_STATIC_U_PLL_RANGEA 0x1fU +#define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA) +#define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA) + +#define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0 +#define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4 + +#define S_T5_STATIC_U_PLL_VCVTUNE 22 +#define M_T5_STATIC_U_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE) +#define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE) + +#define S_T5_STATIC_U_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_U_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40) +#define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_U_PLL_PREDIV 8 +#define M_T5_STATIC_U_PLL_PREDIV 0x1fU +#define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV) +#define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV) + +#define S_T5_STATIC_U_PLL_MULT 0 +#define M_T5_STATIC_U_PLL_MULT 0xffU +#define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT) +#define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT) + +#define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8 + +#define S_T5_STATIC_KR_PLL_BYPASS 30 +#define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS) +#define F_T5_STATIC_KR_PLL_BYPASS V_T5_STATIC_KR_PLL_BYPASS(1U) + +#define S_T5_STATIC_KR_PLL_VBOOSTDIV 27 +#define M_T5_STATIC_KR_PLL_VBOOSTDIV 0x7U +#define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV) +#define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV) + +#define S_T5_STATIC_KR_PLL_CPISEL 24 +#define M_T5_STATIC_KR_PLL_CPISEL 0x7U +#define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL) +#define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL) + +#define S_T5_STATIC_KR_PLL_CCALMETHOD 23 +#define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD) +#define F_T5_STATIC_KR_PLL_CCALMETHOD V_T5_STATIC_KR_PLL_CCALMETHOD(1U) + +#define S_T5_STATIC_KR_PLL_CCALLOAD 22 +#define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD) +#define F_T5_STATIC_KR_PLL_CCALLOAD V_T5_STATIC_KR_PLL_CCALLOAD(1U) + +#define S_T5_STATIC_KR_PLL_CCALFMIN 21 +#define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN) +#define F_T5_STATIC_KR_PLL_CCALFMIN V_T5_STATIC_KR_PLL_CCALFMIN(1U) + +#define S_T5_STATIC_KR_PLL_CCALFMAX 20 +#define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX) +#define F_T5_STATIC_KR_PLL_CCALFMAX V_T5_STATIC_KR_PLL_CCALFMAX(1U) + +#define S_T5_STATIC_KR_PLL_CCALCVHOLD 19 +#define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD) +#define F_T5_STATIC_KR_PLL_CCALCVHOLD V_T5_STATIC_KR_PLL_CCALCVHOLD(1U) + +#define S_T5_STATIC_KR_PLL_CCALBANDSEL 15 +#define M_T5_STATIC_KR_PLL_CCALBANDSEL 0xfU +#define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL) +#define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL) + +#define S_T5_STATIC_KR_PLL_BGOFFSET 11 +#define M_T5_STATIC_KR_PLL_BGOFFSET 0xfU +#define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET) +#define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET) + +#define S_T5_STATIC_KR_PLL_P 8 +#define M_T5_STATIC_KR_PLL_P 0x7U +#define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P) +#define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P) + +#define S_T5_STATIC_KR_PLL_N2 4 +#define M_T5_STATIC_KR_PLL_N2 0xfU +#define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2) +#define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2) + +#define S_T5_STATIC_KR_PLL_N1 0 +#define M_T5_STATIC_KR_PLL_N1 0xfU +#define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1) +#define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1) + +#define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc + +#define S_T5_STATIC_KR_PLL_M 11 +#define M_T5_STATIC_KR_PLL_M 0x1ffU +#define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M) +#define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M) + +#define S_T5_STATIC_KR_PLL_ANALOGTUNE 0 +#define M_T5_STATIC_KR_PLL_ANALOGTUNE 0x7ffU +#define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE) +#define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE) + #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100 #define S_HALT_CALIBRATE 1 @@ -4391,6 +8602,40 @@ #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE) #define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U) +#define A_DBG_GPIO_EN_NEW 0x6100 + +#define S_GPIO16_OEN 7 +#define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN) +#define F_GPIO16_OEN V_GPIO16_OEN(1U) + +#define S_GPIO17_OEN 6 +#define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN) +#define F_GPIO17_OEN V_GPIO17_OEN(1U) + +#define S_GPIO18_OEN 5 +#define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN) +#define F_GPIO18_OEN V_GPIO18_OEN(1U) + +#define S_GPIO19_OEN 4 +#define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN) +#define F_GPIO19_OEN V_GPIO19_OEN(1U) + +#define S_GPIO16_OUT_VAL 3 +#define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL) +#define F_GPIO16_OUT_VAL V_GPIO16_OUT_VAL(1U) + +#define S_GPIO17_OUT_VAL 2 +#define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL) +#define F_GPIO17_OUT_VAL V_GPIO17_OUT_VAL(1U) + +#define S_GPIO18_OUT_VAL 1 +#define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL) +#define F_GPIO18_OUT_VAL V_GPIO18_OUT_VAL(1U) + +#define S_GPIO19_OUT_VAL 0 +#define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL) +#define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U) + #define A_DBG_PVT_REG_UPDATE_CTL 0x6104 #define S_FAST_UPDATE 8 @@ -4405,6 +8650,40 @@ #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE) #define F_HALT_UPDATE V_HALT_UPDATE(1U) +#define A_DBG_GPIO_IN_NEW 0x6104 + +#define S_GPIO16_CHG_DET 7 +#define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET) +#define F_GPIO16_CHG_DET V_GPIO16_CHG_DET(1U) + +#define S_GPIO17_CHG_DET 6 +#define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET) +#define F_GPIO17_CHG_DET V_GPIO17_CHG_DET(1U) + +#define S_GPIO18_CHG_DET 5 +#define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET) +#define F_GPIO18_CHG_DET V_GPIO18_CHG_DET(1U) + +#define S_GPIO19_CHG_DET 4 +#define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET) +#define F_GPIO19_CHG_DET V_GPIO19_CHG_DET(1U) + +#define S_GPIO16_IN 3 +#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN) +#define F_GPIO16_IN V_GPIO16_IN(1U) + +#define S_GPIO17_IN 2 +#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN) +#define F_GPIO17_IN V_GPIO17_IN(1U) + +#define S_GPIO18_IN 1 +#define V_GPIO18_IN(x) ((x) << S_GPIO18_IN) +#define F_GPIO18_IN V_GPIO18_IN(1U) + +#define S_GPIO19_IN 0 +#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN) +#define F_GPIO19_IN V_GPIO19_IN(1U) + #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108 #define S_LAST_MEASUREMENT_SELECT 8 @@ -4422,6 +8701,67 @@ #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A) #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A) +#define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108 + +#define S_T5_STATIC_KX_PLL_BYPASS 30 +#define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS) +#define F_T5_STATIC_KX_PLL_BYPASS V_T5_STATIC_KX_PLL_BYPASS(1U) + +#define S_T5_STATIC_KX_PLL_VBOOSTDIV 27 +#define M_T5_STATIC_KX_PLL_VBOOSTDIV 0x7U +#define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV) +#define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV) + +#define S_T5_STATIC_KX_PLL_CPISEL 24 +#define M_T5_STATIC_KX_PLL_CPISEL 0x7U +#define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL) +#define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL) + +#define S_T5_STATIC_KX_PLL_CCALMETHOD 23 +#define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD) +#define F_T5_STATIC_KX_PLL_CCALMETHOD V_T5_STATIC_KX_PLL_CCALMETHOD(1U) + +#define S_T5_STATIC_KX_PLL_CCALLOAD 22 +#define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD) +#define F_T5_STATIC_KX_PLL_CCALLOAD V_T5_STATIC_KX_PLL_CCALLOAD(1U) + +#define S_T5_STATIC_KX_PLL_CCALFMIN 21 +#define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN) +#define F_T5_STATIC_KX_PLL_CCALFMIN V_T5_STATIC_KX_PLL_CCALFMIN(1U) + +#define S_T5_STATIC_KX_PLL_CCALFMAX 20 +#define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX) +#define F_T5_STATIC_KX_PLL_CCALFMAX V_T5_STATIC_KX_PLL_CCALFMAX(1U) + +#define S_T5_STATIC_KX_PLL_CCALCVHOLD 19 +#define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD) +#define F_T5_STATIC_KX_PLL_CCALCVHOLD V_T5_STATIC_KX_PLL_CCALCVHOLD(1U) + +#define S_T5_STATIC_KX_PLL_CCALBANDSEL 15 +#define M_T5_STATIC_KX_PLL_CCALBANDSEL 0xfU +#define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL) +#define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL) + +#define S_T5_STATIC_KX_PLL_BGOFFSET 11 +#define M_T5_STATIC_KX_PLL_BGOFFSET 0xfU +#define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET) +#define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET) + +#define S_T5_STATIC_KX_PLL_P 8 +#define M_T5_STATIC_KX_PLL_P 0x7U +#define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P) +#define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P) + +#define S_T5_STATIC_KX_PLL_N2 4 +#define M_T5_STATIC_KX_PLL_N2 0xfU +#define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2) +#define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2) + +#define S_T5_STATIC_KX_PLL_N1 0 +#define M_T5_STATIC_KX_PLL_N1 0xfU +#define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1) +#define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1) + #define A_DBG_PVT_REG_DRVN 0x610c #define S_PVT_REG_DRVN_EN 8 @@ -4438,6 +8778,18 @@ #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A) #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A) +#define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c + +#define S_T5_STATIC_KX_PLL_M 11 +#define M_T5_STATIC_KX_PLL_M 0x1ffU +#define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M) +#define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M) + +#define S_T5_STATIC_KX_PLL_ANALOGTUNE 0 +#define M_T5_STATIC_KX_PLL_ANALOGTUNE 0x7ffU +#define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE) +#define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE) + #define A_DBG_PVT_REG_DRVP 0x6110 #define S_PVT_REG_DRVP_EN 8 @@ -4454,6 +8806,30 @@ #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A) #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A) +#define A_DBG_T5_STATIC_C_DFS_CONF 0x6110 + +#define S_STATIC_C_DFS_RANGEA 8 +#define M_STATIC_C_DFS_RANGEA 0x1fU +#define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA) +#define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA) + +#define S_STATIC_C_DFS_RANGEB 3 +#define M_STATIC_C_DFS_RANGEB 0x1fU +#define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB) +#define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB) + +#define S_STATIC_C_DFS_FFTUNE4 2 +#define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4) +#define F_STATIC_C_DFS_FFTUNE4 V_STATIC_C_DFS_FFTUNE4(1U) + +#define S_STATIC_C_DFS_FFTUNE5 1 +#define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5) +#define F_STATIC_C_DFS_FFTUNE5 V_STATIC_C_DFS_FFTUNE5(1U) + +#define S_STATIC_C_DFS_ENABLE 0 +#define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE) +#define F_STATIC_C_DFS_ENABLE V_STATIC_C_DFS_ENABLE(1U) + #define A_DBG_PVT_REG_TERMN 0x6114 #define S_PVT_REG_TERMN_EN 8 @@ -4470,6 +8846,30 @@ #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A) #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A) +#define A_DBG_T5_STATIC_U_DFS_CONF 0x6114 + +#define S_STATIC_U_DFS_RANGEA 8 +#define M_STATIC_U_DFS_RANGEA 0x1fU +#define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA) +#define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA) + +#define S_STATIC_U_DFS_RANGEB 3 +#define M_STATIC_U_DFS_RANGEB 0x1fU +#define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB) +#define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB) + +#define S_STATIC_U_DFS_FFTUNE4 2 +#define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4) +#define F_STATIC_U_DFS_FFTUNE4 V_STATIC_U_DFS_FFTUNE4(1U) + +#define S_STATIC_U_DFS_FFTUNE5 1 +#define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5) +#define F_STATIC_U_DFS_FFTUNE5 V_STATIC_U_DFS_FFTUNE5(1U) + +#define S_STATIC_U_DFS_ENABLE 0 +#define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE) +#define F_STATIC_U_DFS_ENABLE V_STATIC_U_DFS_ENABLE(1U) + #define A_DBG_PVT_REG_TERMP 0x6118 #define S_PVT_REG_TERMP_EN 8 @@ -4486,6 +8886,88 @@ #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A) #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A) +#define A_DBG_GPIO_PE_EN 0x6118 + +#define S_GPIO19_PE_EN 19 +#define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN) +#define F_GPIO19_PE_EN V_GPIO19_PE_EN(1U) + +#define S_GPIO18_PE_EN 18 +#define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN) +#define F_GPIO18_PE_EN V_GPIO18_PE_EN(1U) + +#define S_GPIO17_PE_EN 17 +#define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN) +#define F_GPIO17_PE_EN V_GPIO17_PE_EN(1U) + +#define S_GPIO16_PE_EN 16 +#define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN) +#define F_GPIO16_PE_EN V_GPIO16_PE_EN(1U) + +#define S_GPIO15_PE_EN 15 +#define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN) +#define F_GPIO15_PE_EN V_GPIO15_PE_EN(1U) + +#define S_GPIO14_PE_EN 14 +#define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN) +#define F_GPIO14_PE_EN V_GPIO14_PE_EN(1U) + +#define S_GPIO13_PE_EN 13 +#define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN) +#define F_GPIO13_PE_EN V_GPIO13_PE_EN(1U) + +#define S_GPIO12_PE_EN 12 +#define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN) +#define F_GPIO12_PE_EN V_GPIO12_PE_EN(1U) + +#define S_GPIO11_PE_EN 11 +#define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN) +#define F_GPIO11_PE_EN V_GPIO11_PE_EN(1U) + +#define S_GPIO10_PE_EN 10 +#define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN) +#define F_GPIO10_PE_EN V_GPIO10_PE_EN(1U) + +#define S_GPIO9_PE_EN 9 +#define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN) +#define F_GPIO9_PE_EN V_GPIO9_PE_EN(1U) + +#define S_GPIO8_PE_EN 8 +#define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN) +#define F_GPIO8_PE_EN V_GPIO8_PE_EN(1U) + +#define S_GPIO7_PE_EN 7 +#define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN) +#define F_GPIO7_PE_EN V_GPIO7_PE_EN(1U) + +#define S_GPIO6_PE_EN 6 +#define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN) +#define F_GPIO6_PE_EN V_GPIO6_PE_EN(1U) + +#define S_GPIO5_PE_EN 5 +#define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN) +#define F_GPIO5_PE_EN V_GPIO5_PE_EN(1U) + +#define S_GPIO4_PE_EN 4 +#define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN) +#define F_GPIO4_PE_EN V_GPIO4_PE_EN(1U) + +#define S_GPIO3_PE_EN 3 +#define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN) +#define F_GPIO3_PE_EN V_GPIO3_PE_EN(1U) + +#define S_GPIO2_PE_EN 2 +#define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN) +#define F_GPIO2_PE_EN V_GPIO2_PE_EN(1U) + +#define S_GPIO1_PE_EN 1 +#define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN) +#define F_GPIO1_PE_EN V_GPIO1_PE_EN(1U) + +#define S_GPIO0_PE_EN 0 +#define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN) +#define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U) + #define A_DBG_PVT_REG_THRESHOLD 0x611c #define S_PVT_CALIBRATION_DONE 8 @@ -4524,6 +9006,88 @@ #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC) #define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U) +#define A_DBG_GPIO_PS_EN 0x611c + +#define S_GPIO19_PS_EN 19 +#define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN) +#define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U) + +#define S_GPIO18_PS_EN 18 +#define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN) +#define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U) + +#define S_GPIO17_PS_EN 17 +#define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN) +#define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U) + +#define S_GPIO16_PS_EN 16 +#define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN) +#define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U) + +#define S_GPIO15_PS_EN 15 +#define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN) +#define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U) + +#define S_GPIO14_PS_EN 14 +#define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN) +#define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U) + +#define S_GPIO13_PS_EN 13 +#define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN) +#define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U) + +#define S_GPIO12_PS_EN 12 +#define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN) +#define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U) + +#define S_GPIO11_PS_EN 11 +#define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN) +#define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U) + +#define S_GPIO10_PS_EN 10 +#define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN) +#define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U) + +#define S_GPIO9_PS_EN 9 +#define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN) +#define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U) + +#define S_GPIO8_PS_EN 8 +#define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN) +#define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U) + +#define S_GPIO7_PS_EN 7 +#define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN) +#define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U) + +#define S_GPIO6_PS_EN 6 +#define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN) +#define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U) + +#define S_GPIO5_PS_EN 5 +#define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN) +#define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U) + +#define S_GPIO4_PS_EN 4 +#define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN) +#define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U) + +#define S_GPIO3_PS_EN 3 +#define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN) +#define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U) + +#define S_GPIO2_PS_EN 2 +#define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN) +#define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U) + +#define S_GPIO1_PS_EN 1 +#define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN) +#define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U) + +#define S_GPIO0_PS_EN 0 +#define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN) +#define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U) + #define A_DBG_PVT_REG_IN_TERMP 0x6120 #define S_REG_IN_TERMP_B 4 @@ -4536,6 +9100,7 @@ #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A) #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A) +#define A_DBG_EFUSE_BYTE16_19 0x6120 #define A_DBG_PVT_REG_IN_TERMN 0x6124 #define S_REG_IN_TERMN_B 4 @@ -4548,6 +9113,7 @@ #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A) #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A) +#define A_DBG_EFUSE_BYTE20_23 0x6124 #define A_DBG_PVT_REG_IN_DRVP 0x6128 #define S_REG_IN_DRVP_B 4 @@ -4560,6 +9126,7 @@ #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A) #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A) +#define A_DBG_EFUSE_BYTE24_27 0x6128 #define A_DBG_PVT_REG_IN_DRVN 0x612c #define S_REG_IN_DRVN_B 4 @@ -4572,6 +9139,7 @@ #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A) #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A) +#define A_DBG_EFUSE_BYTE28_31 0x612c #define A_DBG_PVT_REG_OUT_TERMP 0x6130 #define S_REG_OUT_TERMP_B 4 @@ -4584,6 +9152,7 @@ #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A) #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A) +#define A_DBG_EFUSE_BYTE32_35 0x6130 #define A_DBG_PVT_REG_OUT_TERMN 0x6134 #define S_REG_OUT_TERMN_B 4 @@ -4596,6 +9165,7 @@ #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A) #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A) +#define A_DBG_EFUSE_BYTE36_39 0x6134 #define A_DBG_PVT_REG_OUT_DRVP 0x6138 #define S_REG_OUT_DRVP_B 4 @@ -4608,6 +9178,7 @@ #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A) #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A) +#define A_DBG_EFUSE_BYTE40_43 0x6138 #define A_DBG_PVT_REG_OUT_DRVN 0x613c #define S_REG_OUT_DRVN_B 4 @@ -4620,6 +9191,7 @@ #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A) #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A) +#define A_DBG_EFUSE_BYTE44_47 0x613c #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140 #define S_TERMP_B_HISTORY 4 @@ -4632,6 +9204,7 @@ #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY) #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY) +#define A_DBG_EFUSE_BYTE48_51 0x6140 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144 #define S_TERMN_B_HISTORY 4 @@ -4644,6 +9217,7 @@ #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY) #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY) +#define A_DBG_EFUSE_BYTE52_55 0x6144 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148 #define S_DRVP_B_HISTORY 4 @@ -4656,6 +9230,7 @@ #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY) #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY) +#define A_DBG_EFUSE_BYTE56_59 0x6148 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c #define S_DRVN_B_HISTORY 4 @@ -4668,6 +9243,7 @@ #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY) #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY) +#define A_DBG_EFUSE_BYTE60_63 0x614c #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150 #define S_SAMPLE_WAIT_CLKS 0 @@ -6507,6 +11083,18 @@ #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE) #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE) +#define A_MA_EXT_MEMORY0_BAR 0x77c8 + +#define S_EXT_MEM0_BASE 16 +#define M_EXT_MEM0_BASE 0xfffU +#define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE) +#define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE) + +#define S_EXT_MEM0_SIZE 0 +#define M_EXT_MEM0_SIZE 0xfffU +#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE) +#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE) + #define A_MA_HOST_MEMORY_BAR 0x77cc #define S_HMA_BASE 16 @@ -6530,6 +11118,15 @@ #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE) #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE) +#define S_BRC_MODE1 6 +#define V_BRC_MODE1(x) ((x) << S_BRC_MODE1) +#define F_BRC_MODE1 V_BRC_MODE1(1U) + +#define S_EXT_MEM_PAGE_SIZE1 4 +#define M_EXT_MEM_PAGE_SIZE1 0x3U +#define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1) +#define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1) + #define A_MA_ARB_CTRL 0x77d4 #define S_DIS_PAGE_HINT 1 @@ -6540,6 +11137,10 @@ #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB) #define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U) +#define S_DIS_BANK_FAIR 2 +#define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR) +#define F_DIS_BANK_FAIR V_DIS_BANK_FAIR(1U) + #define A_MA_TARGET_MEM_ENABLE 0x77d8 #define S_HMA_ENABLE 3 @@ -6558,6 +11159,18 @@ #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE) #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U) +#define S_HMA_MUX 5 +#define V_HMA_MUX(x) ((x) << S_HMA_MUX) +#define F_HMA_MUX V_HMA_MUX(1U) + +#define S_EXT_MEM1_ENABLE 4 +#define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE) +#define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U) + +#define S_EXT_MEM0_ENABLE 2 +#define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE) +#define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U) + #define A_MA_INT_ENABLE 0x77dc #define S_MEM_PERR_INT_ENABLE 1 @@ -6568,6 +11181,10 @@ #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE) #define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U) +#define S_MEM_TO_INT_ENABLE 2 +#define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE) +#define F_MEM_TO_INT_ENABLE V_MEM_TO_INT_ENABLE(1U) + #define A_MA_INT_CAUSE 0x77e0 #define S_MEM_PERR_INT_CAUSE 1 @@ -6578,6 +11195,10 @@ #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE) #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U) +#define S_MEM_TO_INT_CAUSE 2 +#define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE) +#define F_MEM_TO_INT_CAUSE V_MEM_TO_INT_CAUSE(1U) + #define A_MA_INT_WRAP_STATUS 0x77e4 #define S_MEM_WRAP_ADDRESS 4 @@ -6734,6 +11355,7 @@ #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN) #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U) +#define A_MA_PARITY_ERROR_ENABLE1 0x77f0 #define A_MA_PARITY_ERROR_STATUS 0x77f4 #define S_TP_DMARBT_PAR_ERROR 31 @@ -6864,6 +11486,7 @@ #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR) #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U) +#define A_MA_PARITY_ERROR_STATUS1 0x77f4 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8 #define S_BONUS_REG 6 @@ -6891,6 +11514,737 @@ #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE) #define F_UE_ENABLE V_UE_ENABLE(1U) +#define S_FUTURE_EXPANSION 1 +#define M_FUTURE_EXPANSION 0x7fffffffU +#define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION) +#define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION) + +#define A_MA_PARITY_ERROR_ENABLE2 0x7800 + +#define S_ARB4_PAR_WRQUEUE_ERROR_EN 1 +#define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN) +#define F_ARB4_PAR_WRQUEUE_ERROR_EN V_ARB4_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB4_PAR_RDQUEUE_ERROR_EN 0 +#define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN) +#define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U) + +#define A_MA_PARITY_ERROR_STATUS2 0x7804 + +#define S_ARB4_PAR_WRQUEUE_ERROR 1 +#define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR) +#define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U) + +#define S_ARB4_PAR_RDQUEUE_ERROR 0 +#define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR) +#define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U) + +#define A_MA_EXT_MEMORY1_BAR 0x7808 + +#define S_EXT_MEM1_BASE 16 +#define M_EXT_MEM1_BASE 0xfffU +#define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE) +#define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE) + +#define S_EXT_MEM1_SIZE 0 +#define M_EXT_MEM1_SIZE 0xfffU +#define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE) +#define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE) + +#define A_MA_PMTX_THROTTLE 0x780c + +#define S_FL_ENABLE 31 +#define V_FL_ENABLE(x) ((x) << S_FL_ENABLE) +#define F_FL_ENABLE V_FL_ENABLE(1U) + +#define S_FL_LIMIT 0 +#define M_FL_LIMIT 0xffU +#define V_FL_LIMIT(x) ((x) << S_FL_LIMIT) +#define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT) + +#define A_MA_PMRX_THROTTLE 0x7810 +#define A_MA_SGE_TH0_WRDATA_CNT 0x7814 +#define A_MA_SGE_TH1_WRDATA_CNT 0x7818 +#define A_MA_ULPTX_WRDATA_CNT 0x781c +#define A_MA_ULPRX_WRDATA_CNT 0x7820 +#define A_MA_ULPTXRX_WRDATA_CNT 0x7824 +#define A_MA_TP_TH0_WRDATA_CNT 0x7828 +#define A_MA_TP_TH1_WRDATA_CNT 0x782c +#define A_MA_LE_WRDATA_CNT 0x7830 +#define A_MA_CIM_WRDATA_CNT 0x7834 +#define A_MA_PCIE_WRDATA_CNT 0x7838 +#define A_MA_PMTX_WRDATA_CNT 0x783c +#define A_MA_PMRX_WRDATA_CNT 0x7840 +#define A_MA_HMA_WRDATA_CNT 0x7844 +#define A_MA_SGE_TH0_RDDATA_CNT 0x7848 +#define A_MA_SGE_TH1_RDDATA_CNT 0x784c +#define A_MA_ULPTX_RDDATA_CNT 0x7850 +#define A_MA_ULPRX_RDDATA_CNT 0x7854 +#define A_MA_ULPTXRX_RDDATA_CNT 0x7858 +#define A_MA_TP_TH0_RDDATA_CNT 0x785c +#define A_MA_TP_TH1_RDDATA_CNT 0x7860 +#define A_MA_LE_RDDATA_CNT 0x7864 +#define A_MA_CIM_RDDATA_CNT 0x7868 +#define A_MA_PCIE_RDDATA_CNT 0x786c +#define A_MA_PMTX_RDDATA_CNT 0x7870 +#define A_MA_PMRX_RDDATA_CNT 0x7874 +#define A_MA_HMA_RDDATA_CNT 0x7878 +#define A_MA_EDRAM0_WRDATA_CNT1 0x787c +#define A_MA_EDRAM0_WRDATA_CNT0 0x7880 +#define A_MA_EDRAM1_WRDATA_CNT1 0x7884 +#define A_MA_EDRAM1_WRDATA_CNT0 0x7888 +#define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c +#define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890 +#define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894 +#define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898 +#define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c +#define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0 +#define A_MA_EDRAM0_RDDATA_CNT1 0x78a4 +#define A_MA_EDRAM0_RDDATA_CNT0 0x78a8 +#define A_MA_EDRAM1_RDDATA_CNT1 0x78ac +#define A_MA_EDRAM1_RDDATA_CNT0 0x78b0 +#define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4 +#define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8 +#define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc +#define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0 +#define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4 +#define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8 +#define A_MA_TIMEOUT_CFG 0x78cc + +#define S_CLR 31 +#define V_CLR(x) ((x) << S_CLR) +#define F_CLR V_CLR(1U) + +#define S_CNT_LOCK 30 +#define V_CNT_LOCK(x) ((x) << S_CNT_LOCK) +#define F_CNT_LOCK V_CNT_LOCK(1U) + +#define S_WRN 24 +#define V_WRN(x) ((x) << S_WRN) +#define F_WRN V_WRN(1U) + +#define S_DIR 23 +#define V_DIR(x) ((x) << S_DIR) +#define F_DIR V_DIR(1U) + +#define S_TO_BUS 22 +#define V_TO_BUS(x) ((x) << S_TO_BUS) +#define F_TO_BUS V_TO_BUS(1U) + +#define S_CLIENT 16 +#define M_CLIENT 0xfU +#define V_CLIENT(x) ((x) << S_CLIENT) +#define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT) + +#define S_DELAY 0 +#define M_DELAY 0xffffU +#define V_DELAY(x) ((x) << S_DELAY) +#define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY) + +#define A_MA_TIMEOUT_CNT 0x78d0 + +#define S_CNT_VAL 0 +#define M_CNT_VAL 0xffffU +#define V_CNT_VAL(x) ((x) << S_CNT_VAL) +#define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL) + +#define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4 + +#define S_FUTURE_CEXPANSION 29 +#define M_FUTURE_CEXPANSION 0x7U +#define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION) +#define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION) + +#define S_CL12_WR_CMD_TO_EN 28 +#define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN) +#define F_CL12_WR_CMD_TO_EN V_CL12_WR_CMD_TO_EN(1U) + +#define S_CL11_WR_CMD_TO_EN 27 +#define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN) +#define F_CL11_WR_CMD_TO_EN V_CL11_WR_CMD_TO_EN(1U) + +#define S_CL10_WR_CMD_TO_EN 26 +#define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN) +#define F_CL10_WR_CMD_TO_EN V_CL10_WR_CMD_TO_EN(1U) + +#define S_CL9_WR_CMD_TO_EN 25 +#define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN) +#define F_CL9_WR_CMD_TO_EN V_CL9_WR_CMD_TO_EN(1U) + +#define S_CL8_WR_CMD_TO_EN 24 +#define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN) +#define F_CL8_WR_CMD_TO_EN V_CL8_WR_CMD_TO_EN(1U) + +#define S_CL7_WR_CMD_TO_EN 23 +#define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN) +#define F_CL7_WR_CMD_TO_EN V_CL7_WR_CMD_TO_EN(1U) + +#define S_CL6_WR_CMD_TO_EN 22 +#define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN) +#define F_CL6_WR_CMD_TO_EN V_CL6_WR_CMD_TO_EN(1U) + +#define S_CL5_WR_CMD_TO_EN 21 +#define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN) +#define F_CL5_WR_CMD_TO_EN V_CL5_WR_CMD_TO_EN(1U) + +#define S_CL4_WR_CMD_TO_EN 20 +#define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN) +#define F_CL4_WR_CMD_TO_EN V_CL4_WR_CMD_TO_EN(1U) + +#define S_CL3_WR_CMD_TO_EN 19 +#define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN) +#define F_CL3_WR_CMD_TO_EN V_CL3_WR_CMD_TO_EN(1U) + +#define S_CL2_WR_CMD_TO_EN 18 +#define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN) +#define F_CL2_WR_CMD_TO_EN V_CL2_WR_CMD_TO_EN(1U) + +#define S_CL1_WR_CMD_TO_EN 17 +#define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN) +#define F_CL1_WR_CMD_TO_EN V_CL1_WR_CMD_TO_EN(1U) + +#define S_CL0_WR_CMD_TO_EN 16 +#define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN) +#define F_CL0_WR_CMD_TO_EN V_CL0_WR_CMD_TO_EN(1U) + +#define S_FUTURE_DEXPANSION 13 +#define M_FUTURE_DEXPANSION 0x7U +#define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION) +#define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION) + +#define S_CL12_WR_DATA_TO_EN 12 +#define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN) +#define F_CL12_WR_DATA_TO_EN V_CL12_WR_DATA_TO_EN(1U) + +#define S_CL11_WR_DATA_TO_EN 11 +#define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN) +#define F_CL11_WR_DATA_TO_EN V_CL11_WR_DATA_TO_EN(1U) + +#define S_CL10_WR_DATA_TO_EN 10 +#define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN) +#define F_CL10_WR_DATA_TO_EN V_CL10_WR_DATA_TO_EN(1U) + +#define S_CL9_WR_DATA_TO_EN 9 +#define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN) +#define F_CL9_WR_DATA_TO_EN V_CL9_WR_DATA_TO_EN(1U) + +#define S_CL8_WR_DATA_TO_EN 8 +#define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN) +#define F_CL8_WR_DATA_TO_EN V_CL8_WR_DATA_TO_EN(1U) + +#define S_CL7_WR_DATA_TO_EN 7 +#define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN) +#define F_CL7_WR_DATA_TO_EN V_CL7_WR_DATA_TO_EN(1U) + +#define S_CL6_WR_DATA_TO_EN 6 +#define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN) +#define F_CL6_WR_DATA_TO_EN V_CL6_WR_DATA_TO_EN(1U) + +#define S_CL5_WR_DATA_TO_EN 5 +#define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN) +#define F_CL5_WR_DATA_TO_EN V_CL5_WR_DATA_TO_EN(1U) + +#define S_CL4_WR_DATA_TO_EN 4 +#define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN) +#define F_CL4_WR_DATA_TO_EN V_CL4_WR_DATA_TO_EN(1U) + +#define S_CL3_WR_DATA_TO_EN 3 +#define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN) +#define F_CL3_WR_DATA_TO_EN V_CL3_WR_DATA_TO_EN(1U) + +#define S_CL2_WR_DATA_TO_EN 2 +#define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN) +#define F_CL2_WR_DATA_TO_EN V_CL2_WR_DATA_TO_EN(1U) + +#define S_CL1_WR_DATA_TO_EN 1 +#define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN) +#define F_CL1_WR_DATA_TO_EN V_CL1_WR_DATA_TO_EN(1U) + +#define S_CL0_WR_DATA_TO_EN 0 +#define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN) +#define F_CL0_WR_DATA_TO_EN V_CL0_WR_DATA_TO_EN(1U) + +#define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8 + +#define S_CL12_WR_CMD_TO_ERROR 28 +#define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR) +#define F_CL12_WR_CMD_TO_ERROR V_CL12_WR_CMD_TO_ERROR(1U) + +#define S_CL11_WR_CMD_TO_ERROR 27 +#define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR) +#define F_CL11_WR_CMD_TO_ERROR V_CL11_WR_CMD_TO_ERROR(1U) + +#define S_CL10_WR_CMD_TO_ERROR 26 +#define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR) +#define F_CL10_WR_CMD_TO_ERROR V_CL10_WR_CMD_TO_ERROR(1U) + +#define S_CL9_WR_CMD_TO_ERROR 25 +#define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR) +#define F_CL9_WR_CMD_TO_ERROR V_CL9_WR_CMD_TO_ERROR(1U) + +#define S_CL8_WR_CMD_TO_ERROR 24 +#define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR) +#define F_CL8_WR_CMD_TO_ERROR V_CL8_WR_CMD_TO_ERROR(1U) + +#define S_CL7_WR_CMD_TO_ERROR 23 +#define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR) +#define F_CL7_WR_CMD_TO_ERROR V_CL7_WR_CMD_TO_ERROR(1U) + +#define S_CL6_WR_CMD_TO_ERROR 22 +#define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR) +#define F_CL6_WR_CMD_TO_ERROR V_CL6_WR_CMD_TO_ERROR(1U) + +#define S_CL5_WR_CMD_TO_ERROR 21 +#define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR) +#define F_CL5_WR_CMD_TO_ERROR V_CL5_WR_CMD_TO_ERROR(1U) + +#define S_CL4_WR_CMD_TO_ERROR 20 +#define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR) +#define F_CL4_WR_CMD_TO_ERROR V_CL4_WR_CMD_TO_ERROR(1U) + +#define S_CL3_WR_CMD_TO_ERROR 19 +#define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR) +#define F_CL3_WR_CMD_TO_ERROR V_CL3_WR_CMD_TO_ERROR(1U) + +#define S_CL2_WR_CMD_TO_ERROR 18 +#define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR) +#define F_CL2_WR_CMD_TO_ERROR V_CL2_WR_CMD_TO_ERROR(1U) + +#define S_CL1_WR_CMD_TO_ERROR 17 +#define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR) +#define F_CL1_WR_CMD_TO_ERROR V_CL1_WR_CMD_TO_ERROR(1U) + +#define S_CL0_WR_CMD_TO_ERROR 16 +#define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR) +#define F_CL0_WR_CMD_TO_ERROR V_CL0_WR_CMD_TO_ERROR(1U) + +#define S_CL12_WR_DATA_TO_ERROR 12 +#define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR) +#define F_CL12_WR_DATA_TO_ERROR V_CL12_WR_DATA_TO_ERROR(1U) + +#define S_CL11_WR_DATA_TO_ERROR 11 +#define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR) +#define F_CL11_WR_DATA_TO_ERROR V_CL11_WR_DATA_TO_ERROR(1U) + +#define S_CL10_WR_DATA_TO_ERROR 10 +#define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR) +#define F_CL10_WR_DATA_TO_ERROR V_CL10_WR_DATA_TO_ERROR(1U) + +#define S_CL9_WR_DATA_TO_ERROR 9 +#define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR) +#define F_CL9_WR_DATA_TO_ERROR V_CL9_WR_DATA_TO_ERROR(1U) + +#define S_CL8_WR_DATA_TO_ERROR 8 +#define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR) +#define F_CL8_WR_DATA_TO_ERROR V_CL8_WR_DATA_TO_ERROR(1U) + +#define S_CL7_WR_DATA_TO_ERROR 7 +#define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR) +#define F_CL7_WR_DATA_TO_ERROR V_CL7_WR_DATA_TO_ERROR(1U) + +#define S_CL6_WR_DATA_TO_ERROR 6 +#define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR) +#define F_CL6_WR_DATA_TO_ERROR V_CL6_WR_DATA_TO_ERROR(1U) + +#define S_CL5_WR_DATA_TO_ERROR 5 +#define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR) +#define F_CL5_WR_DATA_TO_ERROR V_CL5_WR_DATA_TO_ERROR(1U) + +#define S_CL4_WR_DATA_TO_ERROR 4 +#define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR) +#define F_CL4_WR_DATA_TO_ERROR V_CL4_WR_DATA_TO_ERROR(1U) + +#define S_CL3_WR_DATA_TO_ERROR 3 +#define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR) +#define F_CL3_WR_DATA_TO_ERROR V_CL3_WR_DATA_TO_ERROR(1U) + +#define S_CL2_WR_DATA_TO_ERROR 2 +#define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR) +#define F_CL2_WR_DATA_TO_ERROR V_CL2_WR_DATA_TO_ERROR(1U) + +#define S_CL1_WR_DATA_TO_ERROR 1 +#define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR) +#define F_CL1_WR_DATA_TO_ERROR V_CL1_WR_DATA_TO_ERROR(1U) + +#define S_CL0_WR_DATA_TO_ERROR 0 +#define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR) +#define F_CL0_WR_DATA_TO_ERROR V_CL0_WR_DATA_TO_ERROR(1U) + +#define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc + +#define S_CL12_RD_CMD_TO_EN 28 +#define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN) +#define F_CL12_RD_CMD_TO_EN V_CL12_RD_CMD_TO_EN(1U) + +#define S_CL11_RD_CMD_TO_EN 27 +#define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN) +#define F_CL11_RD_CMD_TO_EN V_CL11_RD_CMD_TO_EN(1U) + +#define S_CL10_RD_CMD_TO_EN 26 +#define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN) +#define F_CL10_RD_CMD_TO_EN V_CL10_RD_CMD_TO_EN(1U) + +#define S_CL9_RD_CMD_TO_EN 25 +#define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN) +#define F_CL9_RD_CMD_TO_EN V_CL9_RD_CMD_TO_EN(1U) + +#define S_CL8_RD_CMD_TO_EN 24 +#define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN) +#define F_CL8_RD_CMD_TO_EN V_CL8_RD_CMD_TO_EN(1U) + +#define S_CL7_RD_CMD_TO_EN 23 +#define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN) +#define F_CL7_RD_CMD_TO_EN V_CL7_RD_CMD_TO_EN(1U) + +#define S_CL6_RD_CMD_TO_EN 22 +#define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN) +#define F_CL6_RD_CMD_TO_EN V_CL6_RD_CMD_TO_EN(1U) + +#define S_CL5_RD_CMD_TO_EN 21 +#define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN) +#define F_CL5_RD_CMD_TO_EN V_CL5_RD_CMD_TO_EN(1U) + +#define S_CL4_RD_CMD_TO_EN 20 +#define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN) +#define F_CL4_RD_CMD_TO_EN V_CL4_RD_CMD_TO_EN(1U) + +#define S_CL3_RD_CMD_TO_EN 19 +#define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN) +#define F_CL3_RD_CMD_TO_EN V_CL3_RD_CMD_TO_EN(1U) + +#define S_CL2_RD_CMD_TO_EN 18 +#define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN) +#define F_CL2_RD_CMD_TO_EN V_CL2_RD_CMD_TO_EN(1U) + +#define S_CL1_RD_CMD_TO_EN 17 +#define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN) +#define F_CL1_RD_CMD_TO_EN V_CL1_RD_CMD_TO_EN(1U) + +#define S_CL0_RD_CMD_TO_EN 16 +#define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN) +#define F_CL0_RD_CMD_TO_EN V_CL0_RD_CMD_TO_EN(1U) + +#define S_CL12_RD_DATA_TO_EN 12 +#define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN) +#define F_CL12_RD_DATA_TO_EN V_CL12_RD_DATA_TO_EN(1U) + +#define S_CL11_RD_DATA_TO_EN 11 +#define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN) +#define F_CL11_RD_DATA_TO_EN V_CL11_RD_DATA_TO_EN(1U) + +#define S_CL10_RD_DATA_TO_EN 10 +#define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN) +#define F_CL10_RD_DATA_TO_EN V_CL10_RD_DATA_TO_EN(1U) + +#define S_CL9_RD_DATA_TO_EN 9 +#define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN) +#define F_CL9_RD_DATA_TO_EN V_CL9_RD_DATA_TO_EN(1U) + +#define S_CL8_RD_DATA_TO_EN 8 +#define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN) +#define F_CL8_RD_DATA_TO_EN V_CL8_RD_DATA_TO_EN(1U) + +#define S_CL7_RD_DATA_TO_EN 7 +#define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN) +#define F_CL7_RD_DATA_TO_EN V_CL7_RD_DATA_TO_EN(1U) + +#define S_CL6_RD_DATA_TO_EN 6 +#define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN) +#define F_CL6_RD_DATA_TO_EN V_CL6_RD_DATA_TO_EN(1U) + +#define S_CL5_RD_DATA_TO_EN 5 +#define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN) +#define F_CL5_RD_DATA_TO_EN V_CL5_RD_DATA_TO_EN(1U) + +#define S_CL4_RD_DATA_TO_EN 4 +#define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN) +#define F_CL4_RD_DATA_TO_EN V_CL4_RD_DATA_TO_EN(1U) + +#define S_CL3_RD_DATA_TO_EN 3 +#define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN) +#define F_CL3_RD_DATA_TO_EN V_CL3_RD_DATA_TO_EN(1U) + +#define S_CL2_RD_DATA_TO_EN 2 +#define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN) +#define F_CL2_RD_DATA_TO_EN V_CL2_RD_DATA_TO_EN(1U) + +#define S_CL1_RD_DATA_TO_EN 1 +#define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN) +#define F_CL1_RD_DATA_TO_EN V_CL1_RD_DATA_TO_EN(1U) + +#define S_CL0_RD_DATA_TO_EN 0 +#define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN) +#define F_CL0_RD_DATA_TO_EN V_CL0_RD_DATA_TO_EN(1U) + +#define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0 + +#define S_CL12_RD_CMD_TO_ERROR 28 +#define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR) +#define F_CL12_RD_CMD_TO_ERROR V_CL12_RD_CMD_TO_ERROR(1U) + +#define S_CL11_RD_CMD_TO_ERROR 27 +#define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR) +#define F_CL11_RD_CMD_TO_ERROR V_CL11_RD_CMD_TO_ERROR(1U) + +#define S_CL10_RD_CMD_TO_ERROR 26 +#define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR) +#define F_CL10_RD_CMD_TO_ERROR V_CL10_RD_CMD_TO_ERROR(1U) + +#define S_CL9_RD_CMD_TO_ERROR 25 +#define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR) +#define F_CL9_RD_CMD_TO_ERROR V_CL9_RD_CMD_TO_ERROR(1U) + +#define S_CL8_RD_CMD_TO_ERROR 24 +#define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR) +#define F_CL8_RD_CMD_TO_ERROR V_CL8_RD_CMD_TO_ERROR(1U) + +#define S_CL7_RD_CMD_TO_ERROR 23 +#define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR) +#define F_CL7_RD_CMD_TO_ERROR V_CL7_RD_CMD_TO_ERROR(1U) + +#define S_CL6_RD_CMD_TO_ERROR 22 +#define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR) +#define F_CL6_RD_CMD_TO_ERROR V_CL6_RD_CMD_TO_ERROR(1U) + +#define S_CL5_RD_CMD_TO_ERROR 21 +#define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR) +#define F_CL5_RD_CMD_TO_ERROR V_CL5_RD_CMD_TO_ERROR(1U) + +#define S_CL4_RD_CMD_TO_ERROR 20 +#define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR) +#define F_CL4_RD_CMD_TO_ERROR V_CL4_RD_CMD_TO_ERROR(1U) + +#define S_CL3_RD_CMD_TO_ERROR 19 +#define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR) +#define F_CL3_RD_CMD_TO_ERROR V_CL3_RD_CMD_TO_ERROR(1U) + +#define S_CL2_RD_CMD_TO_ERROR 18 +#define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR) +#define F_CL2_RD_CMD_TO_ERROR V_CL2_RD_CMD_TO_ERROR(1U) + +#define S_CL1_RD_CMD_TO_ERROR 17 +#define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR) +#define F_CL1_RD_CMD_TO_ERROR V_CL1_RD_CMD_TO_ERROR(1U) + +#define S_CL0_RD_CMD_TO_ERROR 16 +#define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR) +#define F_CL0_RD_CMD_TO_ERROR V_CL0_RD_CMD_TO_ERROR(1U) + +#define S_CL12_RD_DATA_TO_ERROR 12 +#define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR) +#define F_CL12_RD_DATA_TO_ERROR V_CL12_RD_DATA_TO_ERROR(1U) + +#define S_CL11_RD_DATA_TO_ERROR 11 +#define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR) +#define F_CL11_RD_DATA_TO_ERROR V_CL11_RD_DATA_TO_ERROR(1U) + +#define S_CL10_RD_DATA_TO_ERROR 10 +#define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR) +#define F_CL10_RD_DATA_TO_ERROR V_CL10_RD_DATA_TO_ERROR(1U) + +#define S_CL9_RD_DATA_TO_ERROR 9 +#define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR) +#define F_CL9_RD_DATA_TO_ERROR V_CL9_RD_DATA_TO_ERROR(1U) + +#define S_CL8_RD_DATA_TO_ERROR 8 +#define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR) +#define F_CL8_RD_DATA_TO_ERROR V_CL8_RD_DATA_TO_ERROR(1U) + +#define S_CL7_RD_DATA_TO_ERROR 7 +#define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR) +#define F_CL7_RD_DATA_TO_ERROR V_CL7_RD_DATA_TO_ERROR(1U) + +#define S_CL6_RD_DATA_TO_ERROR 6 +#define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR) +#define F_CL6_RD_DATA_TO_ERROR V_CL6_RD_DATA_TO_ERROR(1U) + +#define S_CL5_RD_DATA_TO_ERROR 5 +#define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR) +#define F_CL5_RD_DATA_TO_ERROR V_CL5_RD_DATA_TO_ERROR(1U) + +#define S_CL4_RD_DATA_TO_ERROR 4 +#define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR) +#define F_CL4_RD_DATA_TO_ERROR V_CL4_RD_DATA_TO_ERROR(1U) + +#define S_CL3_RD_DATA_TO_ERROR 3 +#define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR) +#define F_CL3_RD_DATA_TO_ERROR V_CL3_RD_DATA_TO_ERROR(1U) + +#define S_CL2_RD_DATA_TO_ERROR 2 +#define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR) +#define F_CL2_RD_DATA_TO_ERROR V_CL2_RD_DATA_TO_ERROR(1U) + +#define S_CL1_RD_DATA_TO_ERROR 1 +#define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR) +#define F_CL1_RD_DATA_TO_ERROR V_CL1_RD_DATA_TO_ERROR(1U) + +#define S_CL0_RD_DATA_TO_ERROR 0 +#define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR) +#define F_CL0_RD_DATA_TO_ERROR V_CL0_RD_DATA_TO_ERROR(1U) + +#define A_MA_BKP_CNT_SEL 0x78e4 + +#define S_BKP_CNT_TYPE 30 +#define M_BKP_CNT_TYPE 0x3U +#define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE) +#define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE) + +#define S_BKP_CLIENT 24 +#define M_BKP_CLIENT 0xfU +#define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT) +#define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT) + +#define A_MA_BKP_CNT 0x78e8 +#define A_MA_WRT_ARB 0x78ec + +#define S_WRT_EN 31 +#define V_WRT_EN(x) ((x) << S_WRT_EN) +#define F_WRT_EN V_WRT_EN(1U) + +#define S_WR_TIM 16 +#define M_WR_TIM 0xffU +#define V_WR_TIM(x) ((x) << S_WR_TIM) +#define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM) + +#define S_RD_WIN 8 +#define M_RD_WIN 0xffU +#define V_RD_WIN(x) ((x) << S_RD_WIN) +#define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN) + +#define S_WR_WIN 0 +#define M_WR_WIN 0xffU +#define V_WR_WIN(x) ((x) << S_WR_WIN) +#define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN) + +#define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0 + +#define S_CL12_IF_PAR_EN 12 +#define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN) +#define F_CL12_IF_PAR_EN V_CL12_IF_PAR_EN(1U) + +#define S_CL11_IF_PAR_EN 11 +#define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN) +#define F_CL11_IF_PAR_EN V_CL11_IF_PAR_EN(1U) + +#define S_CL10_IF_PAR_EN 10 +#define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN) +#define F_CL10_IF_PAR_EN V_CL10_IF_PAR_EN(1U) + +#define S_CL9_IF_PAR_EN 9 +#define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN) +#define F_CL9_IF_PAR_EN V_CL9_IF_PAR_EN(1U) + +#define S_CL8_IF_PAR_EN 8 +#define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN) +#define F_CL8_IF_PAR_EN V_CL8_IF_PAR_EN(1U) + +#define S_CL7_IF_PAR_EN 7 +#define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN) +#define F_CL7_IF_PAR_EN V_CL7_IF_PAR_EN(1U) + +#define S_CL6_IF_PAR_EN 6 +#define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN) +#define F_CL6_IF_PAR_EN V_CL6_IF_PAR_EN(1U) + +#define S_CL5_IF_PAR_EN 5 +#define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN) +#define F_CL5_IF_PAR_EN V_CL5_IF_PAR_EN(1U) + +#define S_CL4_IF_PAR_EN 4 +#define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN) +#define F_CL4_IF_PAR_EN V_CL4_IF_PAR_EN(1U) + +#define S_CL3_IF_PAR_EN 3 +#define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN) +#define F_CL3_IF_PAR_EN V_CL3_IF_PAR_EN(1U) + +#define S_CL2_IF_PAR_EN 2 +#define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN) +#define F_CL2_IF_PAR_EN V_CL2_IF_PAR_EN(1U) + +#define S_CL1_IF_PAR_EN 1 +#define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN) +#define F_CL1_IF_PAR_EN V_CL1_IF_PAR_EN(1U) + +#define S_CL0_IF_PAR_EN 0 +#define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN) +#define F_CL0_IF_PAR_EN V_CL0_IF_PAR_EN(1U) + +#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4 + +#define S_CL12_IF_PAR_ERROR 12 +#define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR) +#define F_CL12_IF_PAR_ERROR V_CL12_IF_PAR_ERROR(1U) + +#define S_CL11_IF_PAR_ERROR 11 +#define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR) +#define F_CL11_IF_PAR_ERROR V_CL11_IF_PAR_ERROR(1U) + +#define S_CL10_IF_PAR_ERROR 10 +#define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR) +#define F_CL10_IF_PAR_ERROR V_CL10_IF_PAR_ERROR(1U) + +#define S_CL9_IF_PAR_ERROR 9 +#define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR) +#define F_CL9_IF_PAR_ERROR V_CL9_IF_PAR_ERROR(1U) + +#define S_CL8_IF_PAR_ERROR 8 +#define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR) +#define F_CL8_IF_PAR_ERROR V_CL8_IF_PAR_ERROR(1U) + +#define S_CL7_IF_PAR_ERROR 7 +#define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR) +#define F_CL7_IF_PAR_ERROR V_CL7_IF_PAR_ERROR(1U) + +#define S_CL6_IF_PAR_ERROR 6 +#define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR) +#define F_CL6_IF_PAR_ERROR V_CL6_IF_PAR_ERROR(1U) + +#define S_CL5_IF_PAR_ERROR 5 +#define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR) +#define F_CL5_IF_PAR_ERROR V_CL5_IF_PAR_ERROR(1U) + +#define S_CL4_IF_PAR_ERROR 4 +#define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR) +#define F_CL4_IF_PAR_ERROR V_CL4_IF_PAR_ERROR(1U) + +#define S_CL3_IF_PAR_ERROR 3 +#define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR) +#define F_CL3_IF_PAR_ERROR V_CL3_IF_PAR_ERROR(1U) + +#define S_CL2_IF_PAR_ERROR 2 +#define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR) +#define F_CL2_IF_PAR_ERROR V_CL2_IF_PAR_ERROR(1U) + +#define S_CL1_IF_PAR_ERROR 1 +#define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR) +#define F_CL1_IF_PAR_ERROR V_CL1_IF_PAR_ERROR(1U) + +#define S_CL0_IF_PAR_ERROR 0 +#define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR) +#define F_CL0_IF_PAR_ERROR V_CL0_IF_PAR_ERROR(1U) + +#define A_MA_LOCAL_DEBUG_CFG 0x78f8 + +#define S_DEBUG_OR 15 +#define V_DEBUG_OR(x) ((x) << S_DEBUG_OR) +#define F_DEBUG_OR V_DEBUG_OR(1U) + +#define S_DEBUG_HI 14 +#define V_DEBUG_HI(x) ((x) << S_DEBUG_HI) +#define F_DEBUG_HI V_DEBUG_HI(1U) + +#define S_DEBUG_RPT 13 +#define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT) +#define F_DEBUG_RPT V_DEBUG_RPT(1U) + +#define S_DEBUGPAGE 10 +#define M_DEBUGPAGE 0x7U +#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE) +#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE) + +#define A_MA_LOCAL_DEBUG_RPT 0x78fc + /* registers for module EDC_0 */ #define EDC_0_BASE_ADDR 0x7900 @@ -7011,6 +12365,7 @@ #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT) #define F_MBMSGRDYINT V_MBMSGRDYINT(1U) +#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290 #define A_CIM_BOOT_CFG 0x7b00 #define S_BOOTADDR 8 @@ -7180,6 +12535,38 @@ #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN) #define F_PREFDROPINTEN V_PREFDROPINTEN(1U) +#define S_MA_CIM_INTFPERR 28 +#define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR) +#define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U) + +#define S_PLCIM_MSTRSPDATAPARERR 27 +#define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR) +#define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U) + +#define S_NCSI2CIMINTFPARERR 26 +#define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR) +#define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U) + +#define S_SGE2CIMINTFPARERR 25 +#define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR) +#define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U) + +#define S_ULP2CIMINTFPARERR 24 +#define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR) +#define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U) + +#define S_TP2CIMINTFPARERR 23 +#define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR) +#define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U) + +#define S_OBQSGERX1PARERR 22 +#define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR) +#define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U) + +#define S_OBQSGERX0PARERR 21 +#define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR) +#define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U) + #define A_CIM_HOST_INT_CAUSE 0x7b2c #define S_TIEQOUTPARERRINT 20 @@ -7738,6 +13125,11 @@ #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK) #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK) +#define S_T5_DPIFHOSTMASK 0 +#define M_T5_DPIFHOSTMASK 0x1fffffffU +#define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK) +#define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK) + #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14 #define S_DPIFHUPAMASK 0 @@ -7752,6 +13144,11 @@ #define V_DUPMASK(x) ((x) << S_DUPMASK) #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK) +#define S_T5_DUPMASK 0 +#define M_T5_DUPMASK 0x1fffffffU +#define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK) +#define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK) + #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c #define S_DUPUACCMASK 0 @@ -7767,6 +13164,11 @@ #define V_PERREN(x) ((x) << S_PERREN) #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN) +#define S_T5_PERREN 0 +#define M_T5_PERREN 0x1fffffffU +#define V_T5_PERREN(x) ((x) << S_T5_PERREN) +#define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN) + #define A_CIM_EEPROM_BUSY_BIT 0x7c28 #define S_EEPROMBUSY 0 @@ -7787,6 +13189,69 @@ #define A_CIM_CIM_DEBUG_SPARE 0x7c34 #define A_CIM_UP_OPERATION_FREQ 0x7c38 +#define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c + +#define S_CIM_ULP_TX_PKT_ERR_CODE 16 +#define M_CIM_ULP_TX_PKT_ERR_CODE 0xffU +#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE) +#define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE) + +#define S_CIM_SGE1_PKT_ERR_CODE 8 +#define M_CIM_SGE1_PKT_ERR_CODE 0xffU +#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE) +#define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE) + +#define S_CIM_SGE0_PKT_ERR_CODE 0 +#define M_CIM_SGE0_PKT_ERR_CODE 0xffU +#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE) +#define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE) + +#define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40 +#define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44 + +#define S_PIO_UP_MST_CFG_SEL 0 +#define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL) +#define F_PIO_UP_MST_CFG_SEL V_PIO_UP_MST_CFG_SEL(1U) + +#define A_CIM_CGEN 0x7c48 + +#define S_TSCH_CGEN 0 +#define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN) +#define F_TSCH_CGEN V_TSCH_CGEN(1U) + +#define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c + +#define S_OBQ_THROUTTLE_ON_EOP 4 +#define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP) +#define F_OBQ_THROUTTLE_ON_EOP V_OBQ_THROUTTLE_ON_EOP(1U) + +#define S_OBQ_READ_CTL_PERF_MODE_DISABLE 3 +#define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE) +#define F_OBQ_READ_CTL_PERF_MODE_DISABLE V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U) + +#define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE 2 +#define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE) +#define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U) + +#define S_IBQ_RRA_DSBL 1 +#define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL) +#define F_IBQ_RRA_DSBL V_IBQ_RRA_DSBL(1U) + +#define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL 0 +#define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL) +#define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U) + +#define A_CIM_CGEN_GLOBAL 0x7c50 + +#define S_CGEN_GLOBAL 0 +#define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL) +#define F_CGEN_GLOBAL V_CGEN_GLOBAL(1U) + +#define A_CIM_DPSLP_EN 0x7c54 + +#define S_PIFDBGLA_DPSLP_EN 0 +#define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN) +#define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U) /* registers for module TP */ #define TP_BASE_ADDR 0x7d00 @@ -7897,6 +13362,58 @@ #define V_CTUNNEL(x) ((x) << S_CTUNNEL) #define F_CTUNNEL V_CTUNNEL(1U) +#define S_VLANEXTENPORT3 31 +#define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3) +#define F_VLANEXTENPORT3 V_VLANEXTENPORT3(1U) + +#define S_VLANEXTENPORT2 30 +#define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2) +#define F_VLANEXTENPORT2 V_VLANEXTENPORT2(1U) + +#define S_VLANEXTENPORT1 29 +#define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1) +#define F_VLANEXTENPORT1 V_VLANEXTENPORT1(1U) + +#define S_VLANEXTENPORT0 28 +#define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0) +#define F_VLANEXTENPORT0 V_VLANEXTENPORT0(1U) + +#define S_VNTAGDEFAULTVAL 13 +#define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL) +#define F_VNTAGDEFAULTVAL V_VNTAGDEFAULTVAL(1U) + +#define S_ECHECKUDPLEN 12 +#define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN) +#define F_ECHECKUDPLEN V_ECHECKUDPLEN(1U) + +#define S_FCOEFPMA 10 +#define V_FCOEFPMA(x) ((x) << S_FCOEFPMA) +#define F_FCOEFPMA V_FCOEFPMA(1U) + +#define S_VNTAGETHENABLE 8 +#define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE) +#define F_VNTAGETHENABLE V_VNTAGETHENABLE(1U) + +#define S_IP_CCSM 7 +#define V_IP_CCSM(x) ((x) << S_IP_CCSM) +#define F_IP_CCSM V_IP_CCSM(1U) + +#define S_CCHECKSUMCHECKUDP 6 +#define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP) +#define F_CCHECKSUMCHECKUDP V_CCHECKSUMCHECKUDP(1U) + +#define S_TCP_CCSM 5 +#define V_TCP_CCSM(x) ((x) << S_TCP_CCSM) +#define F_TCP_CCSM V_TCP_CCSM(1U) + +#define S_CDEMUX 3 +#define V_CDEMUX(x) ((x) << S_CDEMUX) +#define F_CDEMUX V_CDEMUX(1U) + +#define S_ETHUPEN 2 +#define V_ETHUPEN(x) ((x) << S_ETHUPEN) +#define F_ETHUPEN V_ETHUPEN(1U) + #define A_TP_OUT_CONFIG 0x7d04 #define S_PORTQFCEN 28 @@ -7988,6 +13505,10 @@ #define V_CETHERNET(x) ((x) << S_CETHERNET) #define F_CETHERNET V_CETHERNET(1U) +#define S_EVNTAGEN 9 +#define V_EVNTAGEN(x) ((x) << S_EVNTAGEN) +#define F_EVNTAGEN V_EVNTAGEN(1U) + #define A_TP_GLOBAL_CONFIG 0x7d08 #define S_SYNCOOKIEPARAMS 26 @@ -8066,6 +13587,14 @@ #define V_IPTTL(x) ((x) << S_IPTTL) #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) +#define S_RSSSYNSTEERENABLE 12 +#define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE) +#define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U) + +#define S_ISSFROMCPLENABLE 11 +#define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE) +#define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U) + #define A_TP_DB_CONFIG 0x7d0c #define S_DBMAXOPCNT 24 @@ -8346,6 +13875,10 @@ #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE) #define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U) +#define S_ENABLEFILTERNAT 5 +#define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT) +#define F_ENABLEFILTERNAT V_ENABLEFILTERNAT(1U) + #define A_TP_PC_CONFIG2 0x7d4c #define S_ENABLEMTUVFMODE 31 @@ -8476,6 +14009,10 @@ #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED) #define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U) +#define S_ENABLEFINDDPOFF 14 +#define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF) +#define F_ENABLEFINDDPOFF V_ENABLEFINDDPOFF(1U) + #define A_TP_TCP_BACKOFF_REG0 0x7d50 #define S_TIMERBACKOFFINDEX3 24 @@ -8626,6 +14163,19 @@ #define V_SWSTIMER(x) ((x) << S_SWSTIMER) #define F_SWSTIMER V_SWSTIMER(1U) +#define S_LIMTXTHRESH 28 +#define M_LIMTXTHRESH 0xfU +#define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH) +#define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH) + +#define S_CHNERRENABLE 14 +#define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE) +#define F_CHNERRENABLE V_CHNERRENABLE(1U) + +#define S_SETTIMEENABLE 13 +#define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE) +#define F_SETTIMEENABLE V_SETTIMEENABLE(1U) + #define A_TP_PARA_REG1 0x7d64 #define S_INITRWND 16 @@ -8777,6 +14327,74 @@ #define V_RENOCFG(x) ((x) << S_RENOCFG) #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG) +#define S_IDLECWNDHIGHSPEED 28 +#define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED) +#define F_IDLECWNDHIGHSPEED V_IDLECWNDHIGHSPEED(1U) + +#define S_RXMTCWNDHIGHSPEED 27 +#define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED) +#define F_RXMTCWNDHIGHSPEED V_RXMTCWNDHIGHSPEED(1U) + +#define S_OVERDRIVEHIGHSPEED 25 +#define M_OVERDRIVEHIGHSPEED 0x3U +#define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED) +#define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED) + +#define S_BYTECOUNTHIGHSPEED 24 +#define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED) +#define F_BYTECOUNTHIGHSPEED V_BYTECOUNTHIGHSPEED(1U) + +#define S_IDLECWNDNEWRENO 20 +#define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO) +#define F_IDLECWNDNEWRENO V_IDLECWNDNEWRENO(1U) + +#define S_RXMTCWNDNEWRENO 19 +#define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO) +#define F_RXMTCWNDNEWRENO V_RXMTCWNDNEWRENO(1U) + +#define S_OVERDRIVENEWRENO 17 +#define M_OVERDRIVENEWRENO 0x3U +#define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO) +#define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO) + +#define S_BYTECOUNTNEWRENO 16 +#define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO) +#define F_BYTECOUNTNEWRENO V_BYTECOUNTNEWRENO(1U) + +#define S_IDLECWNDTAHOE 12 +#define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE) +#define F_IDLECWNDTAHOE V_IDLECWNDTAHOE(1U) + +#define S_RXMTCWNDTAHOE 11 +#define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE) +#define F_RXMTCWNDTAHOE V_RXMTCWNDTAHOE(1U) + +#define S_OVERDRIVETAHOE 9 +#define M_OVERDRIVETAHOE 0x3U +#define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE) +#define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE) + +#define S_BYTECOUNTTAHOE 8 +#define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE) +#define F_BYTECOUNTTAHOE V_BYTECOUNTTAHOE(1U) + +#define S_IDLECWNDRENO 4 +#define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO) +#define F_IDLECWNDRENO V_IDLECWNDRENO(1U) + +#define S_RXMTCWNDRENO 3 +#define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO) +#define F_RXMTCWNDRENO V_RXMTCWNDRENO(1U) + +#define S_OVERDRIVERENO 1 +#define M_OVERDRIVERENO 0x3U +#define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO) +#define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO) + +#define S_BYTECOUNTRENO 0 +#define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO) +#define F_BYTECOUNTRENO V_BYTECOUNTRENO(1U) + #define A_TP_PARA_REG5 0x7d74 #define S_INDICATESIZE 16 @@ -8825,6 +14443,18 @@ #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) +#define S_ENABLEXOFFPDU 7 +#define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU) +#define F_ENABLEXOFFPDU V_ENABLEXOFFPDU(1U) + +#define S_ENABLENEWFAR 6 +#define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR) +#define F_ENABLENEWFAR V_ENABLENEWFAR(1U) + +#define S_ENABLEFRAGCHECK 5 +#define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK) +#define F_ENABLEFRAGCHECK V_ENABLEFRAGCHECK(1U) + #define A_TP_PARA_REG6 0x7d78 #define S_TXPDUSIZEADJ 24 @@ -8917,6 +14547,10 @@ #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) +#define S_DISABLEPDUACK 20 +#define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK) +#define F_DISABLEPDUACK V_DISABLEPDUACK(1U) + #define A_TP_PARA_REG7 0x7d7c #define S_PMMAXXFERLEN1 16 @@ -9072,6 +14706,14 @@ #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY) #define F_DROPERRORANY V_DROPERRORANY(1U) +#define S_TNLERRORFPMA 31 +#define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA) +#define F_TNLERRORFPMA V_TNLERRORFPMA(1U) + +#define S_DROPERRORFPMA 15 +#define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA) +#define F_DROPERRORFPMA V_DROPERRORFPMA(1U) + #define A_TP_TIMER_RESOLUTION 0x7d90 #define S_TIMERRESOLUTION 16 @@ -9448,6 +15090,18 @@ #define V_DISABLE(x) ((x) << S_DISABLE) #define F_DISABLE V_DISABLE(1U) +#define S_TNLFCOEMODE 23 +#define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE) +#define F_TNLFCOEMODE V_TNLFCOEMODE(1U) + +#define S_TNLFCOEEN 21 +#define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN) +#define F_TNLFCOEEN V_TNLFCOEEN(1U) + +#define S_HASHXOR 20 +#define V_HASHXOR(x) ((x) << S_HASHXOR) +#define F_HASHXOR V_HASHXOR(1U) + #define A_TP_RSS_CONFIG_TNL 0x7df4 #define S_MASKSIZE 28 @@ -9475,6 +15129,11 @@ #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH) #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH) +#define S_FRMWRQUEMASK 12 +#define M_FRMWRQUEMASK 0xfU +#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK) +#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK) + #define A_TP_RSS_CONFIG_SYN 0x7dfc #define A_TP_RSS_CONFIG_VRT 0x7e00 @@ -9530,6 +15189,14 @@ #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR) #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR) +#define S_VFVLANEN 21 +#define V_VFVLANEN(x) ((x) << S_VFVLANEN) +#define F_VFVLANEN V_VFVLANEN(1U) + +#define S_VFFWEN 20 +#define V_VFFWEN(x) ((x) << S_VFFWEN) +#define F_VFFWEN V_VFFWEN(1U) + #define A_TP_RSS_CONFIG_CNG 0x7e04 #define S_CHNCOUNT3 31 @@ -9909,6 +15576,10 @@ #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR) #define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U) +#define S_CTPOUTPLDFIFOPERR 7 +#define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR) +#define F_CTPOUTPLDFIFOPERR V_CTPOUTPLDFIFOPERR(1U) + #define A_TP_INT_CAUSE 0x7e74 #define A_TP_PER_ENABLE 0x7e78 #define A_TP_FLM_FREE_PS_CNT 0x7e80 @@ -9958,6 +15629,7 @@ #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE) #define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U) +#define A_TP_STAMP_TIME 0x7ea8 #define A_TP_DEBUG_FLAGS 0x7eac #define S_RXTIMERDACKFIRST 26 @@ -10052,6 +15724,18 @@ #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) +#define S_RXTIMERCOMPBUFFER 27 +#define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER) +#define F_RXTIMERCOMPBUFFER V_RXTIMERCOMPBUFFER(1U) + +#define S_TXDFRFAST 13 +#define V_TXDFRFAST(x) ((x) << S_TXDFRFAST) +#define F_TXDFRFAST V_TXDFRFAST(1U) + +#define S_TXRXMMISC 12 +#define V_TXRXMMISC(x) ((x) << S_TXRXMMISC) +#define F_TXRXMMISC V_TXRXMMISC(1U) + #define A_TP_RX_SCHED 0x7eb0 #define S_RXCOMMITRESET1 31 @@ -10852,6 +16536,28 @@ #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0) #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0) +#define A_TP_RX_SCHED_FIFO 0x2b + +#define S_COMMITLIMIT1H 24 +#define M_COMMITLIMIT1H 0xffU +#define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H) +#define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H) + +#define S_COMMITLIMIT1L 16 +#define M_COMMITLIMIT1L 0xffU +#define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L) +#define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L) + +#define S_COMMITLIMIT0H 8 +#define M_COMMITLIMIT0H 0xffU +#define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H) +#define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H) + +#define S_COMMITLIMIT0L 0 +#define M_COMMITLIMIT0L 0xffU +#define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L) +#define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L) + #define A_TP_IPMI_CFG1 0x2e #define S_VLANENABLE 31 @@ -11120,6 +16826,90 @@ #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE) #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE) +#define A_TP_ETHER_TYPE_FW 0x52 + +#define S_ETHTYPE1 16 +#define M_ETHTYPE1 0xffffU +#define V_ETHTYPE1(x) ((x) << S_ETHTYPE1) +#define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1) + +#define S_ETHTYPE0 0 +#define M_ETHTYPE0 0xffffU +#define V_ETHTYPE0(x) ((x) << S_ETHTYPE0) +#define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0) + +#define A_TP_CORE_POWER 0x54 + +#define S_SLEEPRDYVNT 12 +#define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT) +#define F_SLEEPRDYVNT V_SLEEPRDYVNT(1U) + +#define S_SLEEPRDYTBL 11 +#define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL) +#define F_SLEEPRDYTBL V_SLEEPRDYTBL(1U) + +#define S_SLEEPRDYMIB 10 +#define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB) +#define F_SLEEPRDYMIB V_SLEEPRDYMIB(1U) + +#define S_SLEEPRDYARP 9 +#define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP) +#define F_SLEEPRDYARP V_SLEEPRDYARP(1U) + +#define S_SLEEPRDYRSS 8 +#define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS) +#define F_SLEEPRDYRSS V_SLEEPRDYRSS(1U) + +#define S_SLEEPREQVNT 4 +#define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT) +#define F_SLEEPREQVNT V_SLEEPREQVNT(1U) + +#define S_SLEEPREQTBL 3 +#define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL) +#define F_SLEEPREQTBL V_SLEEPREQTBL(1U) + +#define S_SLEEPREQMIB 2 +#define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB) +#define F_SLEEPREQMIB V_SLEEPREQMIB(1U) + +#define S_SLEEPREQARP 1 +#define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP) +#define F_SLEEPREQARP V_SLEEPREQARP(1U) + +#define S_SLEEPREQRSS 0 +#define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS) +#define F_SLEEPREQRSS V_SLEEPREQRSS(1U) + +#define A_TP_CORE_RDMA 0x55 + +#define S_IMMEDIATEOP 20 +#define M_IMMEDIATEOP 0xfU +#define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP) +#define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP) + +#define S_IMMEDIATESE 16 +#define M_IMMEDIATESE 0xfU +#define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE) +#define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE) + +#define S_ATOMICREQOP 12 +#define M_ATOMICREQOP 0xfU +#define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP) +#define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP) + +#define S_ATOMICRSPOP 8 +#define M_ATOMICRSPOP 0xfU +#define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP) +#define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP) + +#define S_IMMEDIASEEN 1 +#define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN) +#define F_IMMEDIASEEN V_IMMEDIASEEN(1U) + +#define S_IMMEDIATEEN 0 +#define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN) +#define F_IMMEDIATEEN V_IMMEDIATEEN(1U) + #define A_TP_DBG_CLEAR 0x60 #define A_TP_DBG_CORE_HDR0 0x61 @@ -11239,16 +17029,16 @@ #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL) #define F_SRAMFATAL V_SRAMFATAL(1U) -#define S_EPCMDCONG 24 -#define M_EPCMDCONG 0xfU -#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG) -#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG) - -#define S_CPCMDCONG 22 -#define M_CPCMDCONG 0x3U +#define S_CPCMDCONG 24 +#define M_CPCMDCONG 0xfU #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG) #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG) +#define S_EPCMDCONG 22 +#define M_EPCMDCONG 0x3U +#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG) +#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG) + #define S_CPCMDLENFATAL 21 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL) #define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U) @@ -11295,6 +17085,14 @@ #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT) #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT) +#define S_CPCMDTTLFATAL 6 +#define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL) +#define F_CPCMDTTLFATAL V_CPCMDTTLFATAL(1U) + +#define S_CDATACHNFATAL 5 +#define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL) +#define F_CDATACHNFATAL V_CDATACHNFATAL(1U) + #define A_TP_DBG_CORE_OUT 0x64 #define S_CCPLENC 26 @@ -11385,6 +17183,46 @@ #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY) #define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U) +#define S_CRXBUSYOUT 31 +#define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT) +#define F_CRXBUSYOUT V_CRXBUSYOUT(1U) + +#define S_CTXBUSYOUT 30 +#define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT) +#define F_CTXBUSYOUT V_CTXBUSYOUT(1U) + +#define S_CRDCPLPKT 29 +#define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT) +#define F_CRDCPLPKT V_CRDCPLPKT(1U) + +#define S_CRDTCPPKT 28 +#define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT) +#define F_CRDTCPPKT V_CRDTCPPKT(1U) + +#define S_CNEWMSG 27 +#define V_CNEWMSG(x) ((x) << S_CNEWMSG) +#define F_CNEWMSG V_CNEWMSG(1U) + +#define S_ERXBUSYOUT 15 +#define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT) +#define F_ERXBUSYOUT V_ERXBUSYOUT(1U) + +#define S_ETXBUSYOUT 14 +#define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT) +#define F_ETXBUSYOUT V_ETXBUSYOUT(1U) + +#define S_ERDCPLPKT 13 +#define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT) +#define F_ERDCPLPKT V_ERDCPLPKT(1U) + +#define S_ERDTCPPKT 12 +#define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT) +#define F_ERDTCPPKT V_ERDTCPPKT(1U) + +#define S_ENEWMSG 11 +#define V_ENEWMSG(x) ((x) << S_ENEWMSG) +#define F_ENEWMSG V_ENEWMSG(1U) + #define A_TP_DBG_CORE_TID 0x65 #define S_LINENUMBER 24 @@ -11405,6 +17243,11 @@ #define V_TIDVALUE(x) ((x) << S_TIDVALUE) #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE) +#define S_SRC 21 +#define M_SRC 0x3U +#define V_SRC(x) ((x) << S_SRC) +#define G_SRC(x) (((x) >> S_SRC) & M_SRC) + #define A_TP_DBG_ENG_RES0 0x66 #define S_RESOURCESREADY 31 @@ -11502,13 +17345,22 @@ #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY) #define F_CPCMDBUSY V_CPCMDBUSY(1U) -#define S_ETXBUSY 1 +#define S_EPCMDBUSY 1 +#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY) +#define F_EPCMDBUSY V_EPCMDBUSY(1U) + +#define S_ETXBUSY 0 #define V_ETXBUSY(x) ((x) << S_ETXBUSY) #define F_ETXBUSY V_ETXBUSY(1U) -#define S_EPCMDBUSY 0 -#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY) -#define F_EPCMDBUSY V_EPCMDBUSY(1U) +#define S_EFFOPCODEOUT 16 +#define M_EFFOPCODEOUT 0xfU +#define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT) +#define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT) + +#define S_DELDRDY 14 +#define V_DELDRDY(x) ((x) << S_DELDRDY) +#define F_DELDRDY V_DELDRDY(1U) #define A_TP_DBG_ENG_RES1 0x67 @@ -11759,6 +17611,49 @@ #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF) #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF) +#define A_TP_DBG_ERROR_CNT 0x6c +#define A_TP_MIB_DEBUG 0x6f + +#define S_SRC3 31 +#define V_SRC3(x) ((x) << S_SRC3) +#define F_SRC3 V_SRC3(1U) + +#define S_LINENUM3 24 +#define M_LINENUM3 0x7fU +#define V_LINENUM3(x) ((x) << S_LINENUM3) +#define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3) + +#define S_SRC2 23 +#define V_SRC2(x) ((x) << S_SRC2) +#define F_SRC2 V_SRC2(1U) + +#define S_LINENUM2 16 +#define M_LINENUM2 0x7fU +#define V_LINENUM2(x) ((x) << S_LINENUM2) +#define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2) + +#define S_SRC1 15 +#define V_SRC1(x) ((x) << S_SRC1) +#define F_SRC1 V_SRC1(1U) + +#define S_LINENUM1 8 +#define M_LINENUM1 0x7fU +#define V_LINENUM1(x) ((x) << S_LINENUM1) +#define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1) + +#define S_SRC0 7 +#define V_SRC0(x) ((x) << S_SRC0) +#define F_SRC0 V_SRC0(1U) + +#define S_LINENUM0 0 +#define M_LINENUM0 0x7fU +#define V_LINENUM0(x) ((x) << S_LINENUM0) +#define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0) + +#define A_TP_T5_TX_DROP_CNT_CH0 0x120 +#define A_TP_T5_TX_DROP_CNT_CH1 0x121 +#define A_TP_TX_DROP_CNT_CH2 0x122 +#define A_TP_TX_DROP_CNT_CH3 0x123 #define A_TP_TX_DROP_CFG_CH0 0x12b #define S_TIMERENABLED 31 @@ -12341,6 +18236,18 @@ #define V_FCOE(x) ((x) << S_FCOE) #define F_FCOE V_FCOE(1U) +#define S_FILTERMODE 15 +#define V_FILTERMODE(x) ((x) << S_FILTERMODE) +#define F_FILTERMODE V_FILTERMODE(1U) + +#define S_FCOEMASK 14 +#define V_FCOEMASK(x) ((x) << S_FCOEMASK) +#define F_FCOEMASK V_FCOEMASK(1U) + +#define S_SRVRSRAM 13 +#define V_SRVRSRAM(x) ((x) << S_SRVRSRAM) +#define F_SRVRSRAM V_SRVRSRAM(1U) + #define A_TP_INGRESS_CONFIG 0x141 #define S_OPAQUE_TYPE 16 @@ -12385,6 +18292,10 @@ #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP) #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP) +#define S_FRAG_LEN_MOD8_COMPAT 12 +#define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT) +#define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U) + #define A_TP_TX_DROP_CFG_CH2 0x142 #define A_TP_TX_DROP_CFG_CH3 0x143 #define A_TP_EGRESS_CONFIG 0x145 @@ -12393,6 +18304,31 @@ #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) +#define A_TP_INGRESS_CONFIG2 0x145 + +#define S_IPV6_UDP_CSUM_COMPAT 31 +#define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT) +#define F_IPV6_UDP_CSUM_COMPAT V_IPV6_UDP_CSUM_COMPAT(1U) + +#define S_VNTAGPLDENABLE 30 +#define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE) +#define F_VNTAGPLDENABLE V_VNTAGPLDENABLE(1U) + +#define S_TCP_PLD_FILTER_OFFSET 20 +#define M_TCP_PLD_FILTER_OFFSET 0x3ffU +#define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET) +#define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET) + +#define S_UDP_PLD_FILTER_OFFSET 10 +#define M_UDP_PLD_FILTER_OFFSET 0x3ffU +#define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET) +#define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET) + +#define S_TNL_PLD_FILTER_OFFSET 0 +#define M_TNL_PLD_FILTER_OFFSET 0x3ffU +#define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET) +#define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET) + #define A_TP_EHDR_CONFIG_LO 0x146 #define S_CPLLIMIT 24 @@ -12652,6 +18588,22 @@ #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY) #define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U) +#define S_RXRUNT 25 +#define V_RXRUNT(x) ((x) << S_RXRUNT) +#define F_RXRUNT V_RXRUNT(1U) + +#define S_RXRUNTPARSER 24 +#define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER) +#define F_RXRUNTPARSER V_RXRUNTPARSER(1U) + +#define S_ERROR_SRDY 5 +#define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY) +#define F_ERROR_SRDY V_ERROR_SRDY(1U) + +#define S_ERROR_DRDY 4 +#define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY) +#define F_ERROR_DRDY V_ERROR_DRDY(1U) + #define A_TP_DBG_ESIDE_IN1 0x14b #define A_TP_DBG_ESIDE_IN2 0x14c #define A_TP_DBG_ESIDE_IN3 0x14d @@ -12754,6 +18706,162 @@ #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET) #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET) +#define A_TP_DBG_ESIDE_OP 0x154 + +#define S_OPT_PARSER_FATAL_CHANNEL0 29 +#define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0) +#define F_OPT_PARSER_FATAL_CHANNEL0 V_OPT_PARSER_FATAL_CHANNEL0(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL0 28 +#define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0) +#define F_OPT_PARSER_BUSY_CHANNEL0 V_OPT_PARSER_BUSY_CHANNEL0(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL0 26 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL0 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL0 24 +#define M_OPT_PARSER_OTK_STATE_CHANNEL0 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0) +#define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0) + +#define S_OPT_PARSER_FATAL_CHANNEL1 21 +#define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1) +#define F_OPT_PARSER_FATAL_CHANNEL1 V_OPT_PARSER_FATAL_CHANNEL1(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL1 20 +#define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1) +#define F_OPT_PARSER_BUSY_CHANNEL1 V_OPT_PARSER_BUSY_CHANNEL1(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL1 18 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL1 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL1 16 +#define M_OPT_PARSER_OTK_STATE_CHANNEL1 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1) +#define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1) + +#define S_OPT_PARSER_FATAL_CHANNEL2 13 +#define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2) +#define F_OPT_PARSER_FATAL_CHANNEL2 V_OPT_PARSER_FATAL_CHANNEL2(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL2 12 +#define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2) +#define F_OPT_PARSER_BUSY_CHANNEL2 V_OPT_PARSER_BUSY_CHANNEL2(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL2 10 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL2 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL2 8 +#define M_OPT_PARSER_OTK_STATE_CHANNEL2 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2) +#define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2) + +#define S_OPT_PARSER_FATAL_CHANNEL3 5 +#define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3) +#define F_OPT_PARSER_FATAL_CHANNEL3 V_OPT_PARSER_FATAL_CHANNEL3(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL3 4 +#define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3) +#define F_OPT_PARSER_BUSY_CHANNEL3 V_OPT_PARSER_BUSY_CHANNEL3(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL3 2 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL3 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL3 0 +#define M_OPT_PARSER_OTK_STATE_CHANNEL3 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3) +#define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3) + +#define A_TP_DBG_ESIDE_OP_ALT 0x155 + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0 29 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0 V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 24 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1 21 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1 V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 16 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2 13 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2 V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 8 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3 5 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3 V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) + +#define A_TP_DBG_ESIDE_OP_BUSY 0x156 + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL3 24 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL3 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL2 16 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL2 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL1 8 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL1 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL0 0 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL0 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0) + +#define A_TP_DBG_ESIDE_OP_COOKIE 0x157 + +#define S_OPT_PARSER_COOKIE_CHANNEL3 24 +#define M_OPT_PARSER_COOKIE_CHANNEL3 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3) +#define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3) + +#define S_OPT_PARSER_COOKIE_CHANNEL2 16 +#define M_OPT_PARSER_COOKIE_CHANNEL2 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2) +#define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2) + +#define S_OPT_PARSER_COOKIE_CHANNEL1 8 +#define M_OPT_PARSER_COOKIE_CHANNEL1 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1) +#define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1) + +#define S_OPT_PARSER_COOKIE_CHANNEL0 0 +#define M_OPT_PARSER_COOKIE_CHANNEL0 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0) +#define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0) + #define A_TP_DBG_CSIDE_RX0 0x230 #define S_CRXSOPCNT 28 @@ -13166,6 +19274,50 @@ #define V_CMD_SEL(x) ((x) << S_CMD_SEL) #define F_CMD_SEL V_CMD_SEL(1U) +#define S_CPL5RXFULL 26 +#define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL) +#define F_CPL5RXFULL V_CPL5RXFULL(1U) + +#define S_PLD2XRXVALID 23 +#define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID) +#define F_PLD2XRXVALID V_PLD2XRXVALID(1U) + +#define S_DDPSTATE 16 +#define M_DDPSTATE 0x1fU +#define V_DDPSTATE(x) ((x) << S_DDPSTATE) +#define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE) + +#define S_DDPMSGCODE 12 +#define M_DDPMSGCODE 0xfU +#define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE) +#define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE) + +#define S_CPL5SOCPCNT 8 +#define M_CPL5SOCPCNT 0xfU +#define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT) +#define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT) + +#define S_PLDRXZEROPCNT 4 +#define M_PLDRXZEROPCNT 0xfU +#define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT) +#define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT) + +#define S_TXFRMERR2 3 +#define V_TXFRMERR2(x) ((x) << S_TXFRMERR2) +#define F_TXFRMERR2 V_TXFRMERR2(1U) + +#define S_TXFRMERR1 2 +#define V_TXFRMERR1(x) ((x) << S_TXFRMERR1) +#define F_TXFRMERR1 V_TXFRMERR1(1U) + +#define S_TXVALID2X 1 +#define V_TXVALID2X(x) ((x) << S_TXVALID2X) +#define F_TXVALID2X V_TXVALID2X(1U) + +#define S_TXFULL2X 0 +#define V_TXFULL2X(x) ((x) << S_TXFULL2X) +#define F_TXFULL2X V_TXFULL2X(1U) + #define A_TP_DBG_CSIDE_DISP1 0x23b #define A_TP_DBG_CSIDE_DDP0 0x23c @@ -13365,6 +19517,48 @@ #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP) #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP) +#define S_STARTSKIPPLD 7 +#define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD) +#define F_STARTSKIPPLD V_STARTSKIPPLD(1U) + +#define S_ATOMICCMDEN 5 +#define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN) +#define F_ATOMICCMDEN V_ATOMICCMDEN(1U) + +#define A_TP_CSPI_POWER 0x243 + +#define S_GATECHNTX3 11 +#define V_GATECHNTX3(x) ((x) << S_GATECHNTX3) +#define F_GATECHNTX3 V_GATECHNTX3(1U) + +#define S_GATECHNTX2 10 +#define V_GATECHNTX2(x) ((x) << S_GATECHNTX2) +#define F_GATECHNTX2 V_GATECHNTX2(1U) + +#define S_GATECHNTX1 9 +#define V_GATECHNTX1(x) ((x) << S_GATECHNTX1) +#define F_GATECHNTX1 V_GATECHNTX1(1U) + +#define S_GATECHNTX0 8 +#define V_GATECHNTX0(x) ((x) << S_GATECHNTX0) +#define F_GATECHNTX0 V_GATECHNTX0(1U) + +#define S_GATECHNRX1 7 +#define V_GATECHNRX1(x) ((x) << S_GATECHNRX1) +#define F_GATECHNRX1 V_GATECHNRX1(1U) + +#define S_GATECHNRX0 6 +#define V_GATECHNRX0(x) ((x) << S_GATECHNRX0) +#define F_GATECHNRX0 V_GATECHNRX0(1U) + +#define S_SLEEPRDYUTRN 4 +#define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN) +#define F_SLEEPRDYUTRN V_SLEEPRDYUTRN(1U) + +#define S_SLEEPREQUTRN 0 +#define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN) +#define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U) + #define A_TP_TRC_CONFIG 0x244 #define S_TRCRR 1 @@ -13404,6 +19598,70 @@ #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0) #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0) +#define S_C4TUPBUSY3 31 +#define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3) +#define F_C4TUPBUSY3 V_C4TUPBUSY3(1U) + +#define S_CDBVALID3 30 +#define V_CDBVALID3(x) ((x) << S_CDBVALID3) +#define F_CDBVALID3 V_CDBVALID3(1U) + +#define S_CRXVALID3 29 +#define V_CRXVALID3(x) ((x) << S_CRXVALID3) +#define F_CRXVALID3 V_CRXVALID3(1U) + +#define S_CRXFULL3 28 +#define V_CRXFULL3(x) ((x) << S_CRXFULL3) +#define F_CRXFULL3 V_CRXFULL3(1U) + +#define S_C4TUPBUSY2 23 +#define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2) +#define F_C4TUPBUSY2 V_C4TUPBUSY2(1U) + +#define S_CDBVALID2 22 +#define V_CDBVALID2(x) ((x) << S_CDBVALID2) +#define F_CDBVALID2 V_CDBVALID2(1U) + +#define S_CRXVALID2 21 +#define V_CRXVALID2(x) ((x) << S_CRXVALID2) +#define F_CRXVALID2 V_CRXVALID2(1U) + +#define S_CRXFULL2 20 +#define V_CRXFULL2(x) ((x) << S_CRXFULL2) +#define F_CRXFULL2 V_CRXFULL2(1U) + +#define S_C4TUPBUSY1 15 +#define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1) +#define F_C4TUPBUSY1 V_C4TUPBUSY1(1U) + +#define S_CDBVALID1 14 +#define V_CDBVALID1(x) ((x) << S_CDBVALID1) +#define F_CDBVALID1 V_CDBVALID1(1U) + +#define S_CRXVALID1 13 +#define V_CRXVALID1(x) ((x) << S_CRXVALID1) +#define F_CRXVALID1 V_CRXVALID1(1U) + +#define S_CRXFULL1 12 +#define V_CRXFULL1(x) ((x) << S_CRXFULL1) +#define F_CRXFULL1 V_CRXFULL1(1U) + +#define S_C4TUPBUSY0 7 +#define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0) +#define F_C4TUPBUSY0 V_C4TUPBUSY0(1U) + +#define S_CDBVALID0 6 +#define V_CDBVALID0(x) ((x) << S_CDBVALID0) +#define F_CDBVALID0 V_CDBVALID0(1U) + +#define S_CRXVALID0 5 +#define V_CRXVALID0(x) ((x) << S_CRXVALID0) +#define F_CRXVALID0 V_CRXVALID0(1U) + +#define S_CRXFULL0 4 +#define V_CRXFULL0(x) ((x) << S_CRXFULL0) +#define F_CRXFULL0 V_CRXFULL0(1U) + #define A_TP_DBG_CSIDE_DEMUX 0x247 #define S_CALLDONE 28 @@ -13446,6 +19704,151 @@ #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE) #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE) +#define S_CARBVALID 28 +#define M_CARBVALID 0xfU +#define V_CARBVALID(x) ((x) << S_CARBVALID) +#define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID) + +#define S_CCPL5DONE 24 +#define M_CCPL5DONE 0xfU +#define V_CCPL5DONE(x) ((x) << S_CCPL5DONE) +#define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE) + +#define S_CTCPOPDONE 12 +#define M_CTCPOPDONE 0xfU +#define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE) +#define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE) + +#define A_TP_DBG_CSIDE_ARBIT 0x248 + +#define S_CPLVALID3 31 +#define V_CPLVALID3(x) ((x) << S_CPLVALID3) +#define F_CPLVALID3 V_CPLVALID3(1U) + +#define S_PLDVALID3 30 +#define V_PLDVALID3(x) ((x) << S_PLDVALID3) +#define F_PLDVALID3 V_PLDVALID3(1U) + +#define S_CRCVALID3 29 +#define V_CRCVALID3(x) ((x) << S_CRCVALID3) +#define F_CRCVALID3 V_CRCVALID3(1U) + +#define S_ISSVALID3 28 +#define V_ISSVALID3(x) ((x) << S_ISSVALID3) +#define F_ISSVALID3 V_ISSVALID3(1U) + +#define S_DBVALID3 27 +#define V_DBVALID3(x) ((x) << S_DBVALID3) +#define F_DBVALID3 V_DBVALID3(1U) + +#define S_CHKVALID3 26 +#define V_CHKVALID3(x) ((x) << S_CHKVALID3) +#define F_CHKVALID3 V_CHKVALID3(1U) + +#define S_ZRPVALID3 25 +#define V_ZRPVALID3(x) ((x) << S_ZRPVALID3) +#define F_ZRPVALID3 V_ZRPVALID3(1U) + +#define S_ERRVALID3 24 +#define V_ERRVALID3(x) ((x) << S_ERRVALID3) +#define F_ERRVALID3 V_ERRVALID3(1U) + +#define S_CPLVALID2 23 +#define V_CPLVALID2(x) ((x) << S_CPLVALID2) +#define F_CPLVALID2 V_CPLVALID2(1U) + +#define S_PLDVALID2 22 +#define V_PLDVALID2(x) ((x) << S_PLDVALID2) +#define F_PLDVALID2 V_PLDVALID2(1U) + +#define S_CRCVALID2 21 +#define V_CRCVALID2(x) ((x) << S_CRCVALID2) +#define F_CRCVALID2 V_CRCVALID2(1U) + +#define S_ISSVALID2 20 +#define V_ISSVALID2(x) ((x) << S_ISSVALID2) +#define F_ISSVALID2 V_ISSVALID2(1U) + +#define S_DBVALID2 19 +#define V_DBVALID2(x) ((x) << S_DBVALID2) +#define F_DBVALID2 V_DBVALID2(1U) + +#define S_CHKVALID2 18 +#define V_CHKVALID2(x) ((x) << S_CHKVALID2) +#define F_CHKVALID2 V_CHKVALID2(1U) + +#define S_ZRPVALID2 17 +#define V_ZRPVALID2(x) ((x) << S_ZRPVALID2) +#define F_ZRPVALID2 V_ZRPVALID2(1U) + +#define S_ERRVALID2 16 +#define V_ERRVALID2(x) ((x) << S_ERRVALID2) +#define F_ERRVALID2 V_ERRVALID2(1U) + +#define S_CPLVALID1 15 +#define V_CPLVALID1(x) ((x) << S_CPLVALID1) +#define F_CPLVALID1 V_CPLVALID1(1U) + +#define S_PLDVALID1 14 +#define V_PLDVALID1(x) ((x) << S_PLDVALID1) +#define F_PLDVALID1 V_PLDVALID1(1U) + +#define S_CRCVALID1 13 +#define V_CRCVALID1(x) ((x) << S_CRCVALID1) +#define F_CRCVALID1 V_CRCVALID1(1U) + +#define S_ISSVALID1 12 +#define V_ISSVALID1(x) ((x) << S_ISSVALID1) +#define F_ISSVALID1 V_ISSVALID1(1U) + +#define S_DBVALID1 11 +#define V_DBVALID1(x) ((x) << S_DBVALID1) +#define F_DBVALID1 V_DBVALID1(1U) + +#define S_CHKVALID1 10 +#define V_CHKVALID1(x) ((x) << S_CHKVALID1) +#define F_CHKVALID1 V_CHKVALID1(1U) + +#define S_ZRPVALID1 9 +#define V_ZRPVALID1(x) ((x) << S_ZRPVALID1) +#define F_ZRPVALID1 V_ZRPVALID1(1U) + +#define S_ERRVALID1 8 +#define V_ERRVALID1(x) ((x) << S_ERRVALID1) +#define F_ERRVALID1 V_ERRVALID1(1U) + +#define S_CPLVALID0 7 +#define V_CPLVALID0(x) ((x) << S_CPLVALID0) +#define F_CPLVALID0 V_CPLVALID0(1U) + +#define S_PLDVALID0 6 +#define V_PLDVALID0(x) ((x) << S_PLDVALID0) +#define F_PLDVALID0 V_PLDVALID0(1U) + +#define S_CRCVALID0 5 +#define V_CRCVALID0(x) ((x) << S_CRCVALID0) +#define F_CRCVALID0 V_CRCVALID0(1U) + +#define S_ISSVALID0 4 +#define V_ISSVALID0(x) ((x) << S_ISSVALID0) +#define F_ISSVALID0 V_ISSVALID0(1U) + +#define S_DBVALID0 3 +#define V_DBVALID0(x) ((x) << S_DBVALID0) +#define F_DBVALID0 V_DBVALID0(1U) + +#define S_CHKVALID0 2 +#define V_CHKVALID0(x) ((x) << S_CHKVALID0) +#define F_CHKVALID0 V_CHKVALID0(1U) + +#define S_ZRPVALID0 1 +#define V_ZRPVALID0(x) ((x) << S_ZRPVALID0) +#define F_ZRPVALID0 V_ZRPVALID0(1U) + +#define S_ERRVALID0 0 +#define V_ERRVALID0(x) ((x) << S_ERRVALID0) +#define F_ERRVALID0 V_ERRVALID0(1U) + #define A_TP_FIFO_CONFIG 0x8c0 #define S_CH1_OUTPUT 27 @@ -13573,12 +19976,16 @@ #define A_TP_MIB_TID_INV 0x61 #define A_TP_MIB_TID_ACT 0x62 #define A_TP_MIB_TID_PAS 0x63 -#define A_TP_MIB_RQE_DFR_MOD 0x64 -#define A_TP_MIB_RQE_DFR_PKT 0x65 +#define A_TP_MIB_RQE_DFR_PKT 0x64 +#define A_TP_MIB_RQE_DFR_MOD 0x65 #define A_TP_MIB_CPL_OUT_ERR_0 0x68 #define A_TP_MIB_CPL_OUT_ERR_1 0x69 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a #define A_TP_MIB_CPL_OUT_ERR_3 0x6b +#define A_TP_MIB_ENG_LINE_0 0x6c +#define A_TP_MIB_ENG_LINE_1 0x6d +#define A_TP_MIB_ENG_LINE_2 0x6e +#define A_TP_MIB_ENG_LINE_3 0x6f /* registers for module ULP_TX */ #define ULP_TX_BASE_ADDR 0x8dc0 @@ -13597,6 +20004,30 @@ #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE) #define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U) +#define S_PHYS_ADDR_RESP_EN 6 +#define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN) +#define F_PHYS_ADDR_RESP_EN V_PHYS_ADDR_RESP_EN(1U) + +#define S_ENDIANESS_CHANGE 5 +#define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE) +#define F_ENDIANESS_CHANGE V_ENDIANESS_CHANGE(1U) + +#define S_ERR_RTAG_EN 4 +#define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN) +#define F_ERR_RTAG_EN V_ERR_RTAG_EN(1U) + +#define S_TSO_ETHLEN_EN 3 +#define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN) +#define F_TSO_ETHLEN_EN V_TSO_ETHLEN_EN(1U) + +#define S_EMSG_MORE_INFO 2 +#define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO) +#define F_EMSG_MORE_INFO V_EMSG_MORE_INFO(1U) + +#define S_LOSDR 1 +#define V_LOSDR(x) ((x) << S_LOSDR) +#define F_LOSDR V_LOSDR(1U) + #define A_ULP_TX_PERR_INJECT 0x8dc4 #define A_ULP_TX_INT_ENABLE 0x8dc8 @@ -13813,25 +20244,193 @@ #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3) #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3) +#define A_ULP_TX_FC_SOF 0x8e20 + +#define S_SOF_FS3 24 +#define M_SOF_FS3 0xffU +#define V_SOF_FS3(x) ((x) << S_SOF_FS3) +#define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3) + +#define S_SOF_FS2 16 +#define M_SOF_FS2 0xffU +#define V_SOF_FS2(x) ((x) << S_SOF_FS2) +#define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2) + +#define S_SOF_3 8 +#define M_SOF_3 0xffU +#define V_SOF_3(x) ((x) << S_SOF_3) +#define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3) + +#define S_SOF_2 0 +#define M_SOF_2 0xffU +#define V_SOF_2(x) ((x) << S_SOF_2) +#define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2) + +#define A_ULP_TX_FC_EOF 0x8e24 + +#define S_EOF_LS3 24 +#define M_EOF_LS3 0xffU +#define V_EOF_LS3(x) ((x) << S_EOF_LS3) +#define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3) + +#define S_EOF_LS2 16 +#define M_EOF_LS2 0xffU +#define V_EOF_LS2(x) ((x) << S_EOF_LS2) +#define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2) + +#define S_EOF_3 8 +#define M_EOF_3 0xffU +#define V_EOF_3(x) ((x) << S_EOF_3) +#define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3) + +#define S_EOF_2 0 +#define M_EOF_2 0xffU +#define V_EOF_2(x) ((x) << S_EOF_2) +#define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2) + +#define A_ULP_TX_CGEN_GLOBAL 0x8e28 + +#define S_ULP_TX_GLOBAL_CGEN 0 +#define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN) +#define F_ULP_TX_GLOBAL_CGEN V_ULP_TX_GLOBAL_CGEN(1U) + +#define A_ULP_TX_CGEN 0x8e2c + +#define S_ULP_TX_CGEN_STORAGE 8 +#define M_ULP_TX_CGEN_STORAGE 0xfU +#define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE) +#define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE) + +#define S_ULP_TX_CGEN_RDMA 4 +#define M_ULP_TX_CGEN_RDMA 0xfU +#define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA) +#define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA) + +#define S_ULP_TX_CGEN_CHANNEL 0 +#define M_ULP_TX_CGEN_CHANNEL 0xfU +#define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL) +#define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL) + #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30 +#define A_ULP_TX_MEM_CFG 0x8e30 + +#define S_WRREQ_SZ 0 +#define M_WRREQ_SZ 0x7U +#define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ) +#define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ) + #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34 +#define A_ULP_TX_PERR_INJECT_2 0x8e34 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38 +#define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38 + +#define S_CHANNEL_SEL 12 +#define M_CHANNEL_SEL 0x3U +#define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL) +#define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL) + +#define S_INTF_SEL 4 +#define M_INTF_SEL 0xfU +#define V_INTF_SEL(x) ((x) << S_INTF_SEL) +#define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL) + +#define S_NUM_FLITS 1 +#define M_NUM_FLITS 0x7U +#define V_NUM_FLITS(x) ((x) << S_NUM_FLITS) +#define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS) + +#define S_CMD_GEN_EN 0 +#define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN) +#define F_CMD_GEN_EN V_CMD_GEN_EN(1U) + #define A_ULP_TX_FPGA_CMD_0 0x8e3c +#define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c #define A_ULP_TX_FPGA_CMD_1 0x8e40 +#define A_ULP_TX_T5_FPGA_CMD_1 0x8e40 #define A_ULP_TX_FPGA_CMD_2 0x8e44 +#define A_ULP_TX_T5_FPGA_CMD_2 0x8e44 #define A_ULP_TX_FPGA_CMD_3 0x8e48 +#define A_ULP_TX_T5_FPGA_CMD_3 0x8e48 #define A_ULP_TX_FPGA_CMD_4 0x8e4c +#define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c #define A_ULP_TX_FPGA_CMD_5 0x8e50 +#define A_ULP_TX_T5_FPGA_CMD_5 0x8e50 #define A_ULP_TX_FPGA_CMD_6 0x8e54 +#define A_ULP_TX_T5_FPGA_CMD_6 0x8e54 #define A_ULP_TX_FPGA_CMD_7 0x8e58 +#define A_ULP_TX_T5_FPGA_CMD_7 0x8e58 #define A_ULP_TX_FPGA_CMD_8 0x8e5c +#define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c #define A_ULP_TX_FPGA_CMD_9 0x8e60 +#define A_ULP_TX_T5_FPGA_CMD_9 0x8e60 #define A_ULP_TX_FPGA_CMD_10 0x8e64 +#define A_ULP_TX_T5_FPGA_CMD_10 0x8e64 #define A_ULP_TX_FPGA_CMD_11 0x8e68 +#define A_ULP_TX_T5_FPGA_CMD_11 0x8e68 #define A_ULP_TX_FPGA_CMD_12 0x8e6c +#define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c #define A_ULP_TX_FPGA_CMD_13 0x8e70 +#define A_ULP_TX_T5_FPGA_CMD_13 0x8e70 #define A_ULP_TX_FPGA_CMD_14 0x8e74 +#define A_ULP_TX_T5_FPGA_CMD_14 0x8e74 #define A_ULP_TX_FPGA_CMD_15 0x8e78 +#define A_ULP_TX_T5_FPGA_CMD_15 0x8e78 +#define A_ULP_TX_INT_ENABLE_2 0x8e7c + +#define S_SMARBT2ULP_DATA_PERR_SET 12 +#define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET) +#define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U) + +#define S_ULP2TP_DATA_PERR_SET 11 +#define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET) +#define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U) + +#define S_MA2ULP_DATA_PERR_SET 10 +#define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET) +#define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U) + +#define S_SGE2ULP_DATA_PERR_SET 9 +#define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET) +#define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U) + +#define S_CIM2ULP_DATA_PERR_SET 8 +#define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET) +#define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U) + +#define S_FSO_HDR_SRAM_PERR_SET3 7 +#define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3) +#define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U) + +#define S_FSO_HDR_SRAM_PERR_SET2 6 +#define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2) +#define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U) + +#define S_FSO_HDR_SRAM_PERR_SET1 5 +#define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1) +#define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U) + +#define S_FSO_HDR_SRAM_PERR_SET0 4 +#define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0) +#define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U) + +#define S_T10_PI_SRAM_PERR_SET3 3 +#define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3) +#define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U) + +#define S_T10_PI_SRAM_PERR_SET2 2 +#define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2) +#define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U) + +#define S_T10_PI_SRAM_PERR_SET1 1 +#define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1) +#define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U) + +#define S_T10_PI_SRAM_PERR_SET0 0 +#define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0) +#define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U) + +#define A_ULP_TX_INT_CAUSE_2 0x8e80 +#define A_ULP_TX_PERR_ENABLE_2 0x8e84 #define A_ULP_TX_SE_CNT_ERR 0x8ea0 #define S_ERR_CH3 12 @@ -13854,6 +20453,7 @@ #define V_ERR_CH0(x) ((x) << S_ERR_CH0) #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0) +#define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0 #define A_ULP_TX_SE_CNT_CLR 0x8ea4 #define S_CLR_DROP 16 @@ -13881,6 +20481,7 @@ #define V_CLR_CH0(x) ((x) << S_CLR_CH0) #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0) +#define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4 #define A_ULP_TX_SE_CNT_CH0 0x8ea8 #define S_SOP_CNT_ULP2TP 28 @@ -13923,9 +20524,13 @@ #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP) #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP) +#define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8 #define A_ULP_TX_SE_CNT_CH1 0x8eac +#define A_ULP_TX_T5_SE_CNT_CH1 0x8eac #define A_ULP_TX_SE_CNT_CH2 0x8eb0 +#define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0 #define A_ULP_TX_SE_CNT_CH3 0x8eb4 +#define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4 #define A_ULP_TX_DROP_CNT 0x8eb8 #define S_DROP_CH3 12 @@ -13948,6 +20553,8 @@ #define V_DROP_CH0(x) ((x) << S_DROP_CH0) #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0) +#define A_ULP_TX_T5_DROP_CNT 0x8eb8 +#define A_ULP_TX_CSU_REVISION 0x8ebc #define A_ULP_TX_LA_RDPTR_0 0x8ec0 #define A_ULP_TX_LA_RDDATA_0 0x8ec4 #define A_ULP_TX_LA_WRPTR_0 0x8ec8 @@ -13992,6 +20599,17 @@ #define A_ULP_TX_LA_RDDATA_10 0x8f64 #define A_ULP_TX_LA_WRPTR_10 0x8f68 #define A_ULP_TX_LA_RESERVED_10 0x8f6c +#define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70 + +#define S_LA_WR0 0 +#define V_LA_WR0(x) ((x) << S_LA_WR0) +#define F_LA_WR0 V_LA_WR0(1U) + +#define A_ULP_TX_ASIC_DEBUG_0 0x8f74 +#define A_ULP_TX_ASIC_DEBUG_1 0x8f78 +#define A_ULP_TX_ASIC_DEBUG_2 0x8f7c +#define A_ULP_TX_ASIC_DEBUG_3 0x8f80 +#define A_ULP_TX_ASIC_DEBUG_4 0x8f84 /* registers for module PM_RX */ #define PM_RX_BASE_ADDR 0x8fc0 @@ -14019,7 +20637,25 @@ #define A_PM_RX_STAT_CONFIG 0x8fc8 #define A_PM_RX_STAT_COUNT 0x8fcc #define A_PM_RX_STAT_LSB 0x8fd0 +#define A_PM_RX_DBG_CTRL 0x8fd0 + +#define S_OSPIWRBUSY_T5 21 +#define M_OSPIWRBUSY_T5 0x3U +#define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5) +#define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5) + +#define S_ISPIWRBUSY 17 +#define M_ISPIWRBUSY 0xfU +#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY) +#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY) + +#define S_PMDBGADDR 0 +#define M_PMDBGADDR 0x1ffffU +#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR) +#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR) + #define A_PM_RX_STAT_MSB 0x8fd4 +#define A_PM_RX_DBG_DATA 0x8fd4 #define A_PM_RX_INT_ENABLE 0x8fd8 #define S_ZERO_E_CMD_ERROR 22 @@ -14114,7 +20750,573 @@ #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR) #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U) +#define S_OSPI_OVERFLOW1 28 +#define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1) +#define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U) + +#define S_OSPI_OVERFLOW0 27 +#define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0) +#define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U) + +#define S_MA_INTF_SDC_ERR 26 +#define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR) +#define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U) + +#define S_BUNDLE_LEN_PARERR 25 +#define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR) +#define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U) + +#define S_BUNDLE_LEN_OVFL 24 +#define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL) +#define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U) + +#define S_SDC_ERR 23 +#define V_SDC_ERR(x) ((x) << S_SDC_ERR) +#define F_SDC_ERR V_SDC_ERR(1U) + #define A_PM_RX_INT_CAUSE 0x8fdc +#define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000 +#define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001 +#define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002 +#define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003 +#define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004 +#define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005 +#define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006 +#define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007 +#define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008 +#define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009 +#define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a +#define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b +#define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c +#define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d +#define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e +#define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f +#define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010 +#define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011 +#define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012 +#define A_PM_RX_DBG_STAT_MSB 0x10013 +#define A_PM_RX_DBG_STAT_LSB 0x10014 +#define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015 + +#define S_I_TO_O_PATH_RSVD_FLIT_BACKUP 12 +#define M_I_TO_O_PATH_RSVD_FLIT_BACKUP 0xfU +#define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP) +#define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP) + +#define S_I_TO_O_PATH_RSVD_FLIT 8 +#define M_I_TO_O_PATH_RSVD_FLIT 0xfU +#define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT) +#define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT) + +#define S_PRFCH_RSVD_FLIT 4 +#define M_PRFCH_RSVD_FLIT 0xfU +#define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT) +#define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT) + +#define S_OSPI_RSVD_FLIT 0 +#define M_OSPI_RSVD_FLIT 0xfU +#define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT) +#define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT) + +#define A_PM_RX_SDC_EN 0x10016 + +#define S_SDC_EN 0 +#define V_SDC_EN(x) ((x) << S_SDC_EN) +#define F_SDC_EN V_SDC_EN(1U) + +#define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017 + +#define S_CHNL_3_SEL 3 +#define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL) +#define F_CHNL_3_SEL V_CHNL_3_SEL(1U) + +#define S_CHNL_2_SEL 2 +#define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL) +#define F_CHNL_2_SEL V_CHNL_2_SEL(1U) + +#define S_CHNL_1_SEL 1 +#define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL) +#define F_CHNL_1_SEL V_CHNL_1_SEL(1U) + +#define S_CHNL_0_SEL 0 +#define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL) +#define F_CHNL_0_SEL V_CHNL_0_SEL(1U) + +#define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018 + +#define S_O_FIFO_WRITE 3 +#define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE) +#define F_O_FIFO_WRITE V_O_FIFO_WRITE(1U) + +#define S_I_FIFO_WRITE 2 +#define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE) +#define F_I_FIFO_WRITE V_I_FIFO_WRITE(1U) + +#define S_O_FIFO_READ 1 +#define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ) +#define F_O_FIFO_READ V_O_FIFO_READ(1U) + +#define S_I_FIFO_READ 0 +#define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ) +#define F_I_FIFO_READ V_I_FIFO_READ(1U) + +#define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019 + +#define S_ISPI_STR_FWD_EN 0 +#define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN) +#define F_ISPI_STR_FWD_EN V_ISPI_STR_FWD_EN(1U) + +#define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a + +#define S_PRFTCH_ACROSS_BNDLE_EN 0 +#define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN) +#define F_PRFTCH_ACROSS_BNDLE_EN V_PRFTCH_ACROSS_BNDLE_EN(1U) + +#define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b + +#define S_PRFTCH_WRR_ENABLE 0 +#define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE) +#define F_PRFTCH_WRR_ENABLE V_PRFTCH_WRR_ENABLE(1U) + +#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c + +#define S_CHNL1_MAX_DEFICIT_CNT 16 +#define M_CHNL1_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT) +#define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT) + +#define S_CHNL0_MAX_DEFICIT_CNT 0 +#define M_CHNL0_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT) +#define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT) + +#define A_PM_RX_FEATURE_EN 0x1001d + +#define S_PIO_CH_DEFICIT_CTL_EN_RX 0 +#define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX) +#define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U) + +#define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e + +#define S_CH0_OSPI_DEFICIT_THRSHLD 0 +#define M_CH0_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD) +#define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD) + +#define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f + +#define S_CH1_OSPI_DEFICIT_THRSHLD 0 +#define M_CH1_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD) +#define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD) + +#define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020 +#define A_PM_RX_DBG_STAT0 0x10021 + +#define S_RX_RD_I_BUSY 29 +#define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY) +#define F_RX_RD_I_BUSY V_RX_RD_I_BUSY(1U) + +#define S_RX_WR_TO_O_BUSY 28 +#define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY) +#define F_RX_WR_TO_O_BUSY V_RX_WR_TO_O_BUSY(1U) + +#define S_RX_M_TO_O_BUSY 27 +#define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY) +#define F_RX_M_TO_O_BUSY V_RX_M_TO_O_BUSY(1U) + +#define S_RX_I_TO_M_BUSY 26 +#define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY) +#define F_RX_I_TO_M_BUSY V_RX_I_TO_M_BUSY(1U) + +#define S_RX_PCMD_FB_ONLY 25 +#define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY) +#define F_RX_PCMD_FB_ONLY V_RX_PCMD_FB_ONLY(1U) + +#define S_RX_PCMD_MEM 24 +#define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM) +#define F_RX_PCMD_MEM V_RX_PCMD_MEM(1U) + +#define S_RX_PCMD_BYPASS 23 +#define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS) +#define F_RX_PCMD_BYPASS V_RX_PCMD_BYPASS(1U) + +#define S_RX_PCMD_EOP 22 +#define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP) +#define F_RX_PCMD_EOP V_RX_PCMD_EOP(1U) + +#define S_RX_DUMPLICATE_PCMD_EOP 21 +#define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP) +#define F_RX_DUMPLICATE_PCMD_EOP V_RX_DUMPLICATE_PCMD_EOP(1U) + +#define S_RX_PCMD_EOB 20 +#define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB) +#define F_RX_PCMD_EOB V_RX_PCMD_EOB(1U) + +#define S_RX_PCMD_FB 16 +#define M_RX_PCMD_FB 0xfU +#define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB) +#define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB) + +#define S_RX_PCMD_LEN 0 +#define M_RX_PCMD_LEN 0xffffU +#define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN) +#define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN) + +#define A_PM_RX_DBG_STAT1 0x10022 + +#define S_RX_PCMD0_MEM 30 +#define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM) +#define F_RX_PCMD0_MEM V_RX_PCMD0_MEM(1U) + +#define S_RX_FREE_OSPI_CNT0 18 +#define M_RX_FREE_OSPI_CNT0 0xfffU +#define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0) +#define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0) + +#define S_RX_PCMD0_FLIT_LEN 6 +#define M_RX_PCMD0_FLIT_LEN 0xfffU +#define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN) +#define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN) + +#define S_RX_PCMD0_CMD 2 +#define M_RX_PCMD0_CMD 0xfU +#define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD) +#define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD) + +#define S_RX_OFIFO_FULL0 1 +#define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0) +#define F_RX_OFIFO_FULL0 V_RX_OFIFO_FULL0(1U) + +#define S_RX_PCMD0_BYPASS 0 +#define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS) +#define F_RX_PCMD0_BYPASS V_RX_PCMD0_BYPASS(1U) + +#define A_PM_RX_DBG_STAT2 0x10023 + +#define S_RX_PCMD1_MEM 30 +#define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM) +#define F_RX_PCMD1_MEM V_RX_PCMD1_MEM(1U) + +#define S_RX_FREE_OSPI_CNT1 18 +#define M_RX_FREE_OSPI_CNT1 0xfffU +#define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1) +#define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1) + +#define S_RX_PCMD1_FLIT_LEN 6 +#define M_RX_PCMD1_FLIT_LEN 0xfffU +#define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN) +#define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN) + +#define S_RX_PCMD1_CMD 2 +#define M_RX_PCMD1_CMD 0xfU +#define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD) +#define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD) + +#define S_RX_OFIFO_FULL1 1 +#define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1) +#define F_RX_OFIFO_FULL1 V_RX_OFIFO_FULL1(1U) + +#define S_RX_PCMD1_BYPASS 0 +#define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS) +#define F_RX_PCMD1_BYPASS V_RX_PCMD1_BYPASS(1U) + +#define A_PM_RX_DBG_STAT3 0x10024 + +#define S_RX_SET_PCMD_RES_RDY_RD 10 +#define M_RX_SET_PCMD_RES_RDY_RD 0x3U +#define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD) +#define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD) + +#define S_RX_ISSUED_PREFETCH_RD_E_CLR 8 +#define M_RX_ISSUED_PREFETCH_RD_E_CLR 0x3U +#define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR) +#define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR) + +#define S_RX_ISSUED_PREFETCH_RD 6 +#define M_RX_ISSUED_PREFETCH_RD 0x3U +#define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD) +#define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD) + +#define S_RX_PCMD_RES_RDY 4 +#define M_RX_PCMD_RES_RDY 0x3U +#define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY) +#define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY) + +#define S_RX_DB_VLD 3 +#define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD) +#define F_RX_DB_VLD V_RX_DB_VLD(1U) + +#define S_RX_FIRST_BUNDLE 1 +#define M_RX_FIRST_BUNDLE 0x3U +#define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE) +#define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE) + +#define S_RX_SDC_DRDY 0 +#define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY) +#define F_RX_SDC_DRDY V_RX_SDC_DRDY(1U) + +#define A_PM_RX_DBG_STAT4 0x10025 + +#define S_RX_PCMD_VLD 26 +#define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD) +#define F_RX_PCMD_VLD V_RX_PCMD_VLD(1U) + +#define S_RX_PCMD_TO_CH 25 +#define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH) +#define F_RX_PCMD_TO_CH V_RX_PCMD_TO_CH(1U) + +#define S_RX_PCMD_FROM_CH 23 +#define M_RX_PCMD_FROM_CH 0x3U +#define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH) +#define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH) + +#define S_RX_LINE 18 +#define M_RX_LINE 0x1fU +#define V_RX_LINE(x) ((x) << S_RX_LINE) +#define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE) + +#define S_RX_IESPI_TXVALID 14 +#define M_RX_IESPI_TXVALID 0xfU +#define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID) +#define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID) + +#define S_RX_IESPI_TXFULL 10 +#define M_RX_IESPI_TXFULL 0xfU +#define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL) +#define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL) + +#define S_RX_PCMD_SRDY 8 +#define M_RX_PCMD_SRDY 0x3U +#define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY) +#define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY) + +#define S_RX_PCMD_DRDY 6 +#define M_RX_PCMD_DRDY 0x3U +#define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY) +#define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY) + +#define S_RX_PCMD_CMD 2 +#define M_RX_PCMD_CMD 0xfU +#define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD) +#define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD) + +#define S_DUPLICATE 0 +#define M_DUPLICATE 0x3U +#define V_DUPLICATE(x) ((x) << S_DUPLICATE) +#define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE) + +#define A_PM_RX_DBG_STAT5 0x10026 + +#define S_RX_ATLST_1_PCMD_CH1 29 +#define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1) +#define F_RX_ATLST_1_PCMD_CH1 V_RX_ATLST_1_PCMD_CH1(1U) + +#define S_RX_ATLST_1_PCMD_CH0 28 +#define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0) +#define F_RX_ATLST_1_PCMD_CH0 V_RX_ATLST_1_PCMD_CH0(1U) + +#define S_RX_ISPI_TXVALID 20 +#define M_RX_ISPI_TXVALID 0xfU +#define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID) +#define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID) + +#define S_RX_ISPI_FULL 16 +#define M_RX_ISPI_FULL 0xfU +#define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL) +#define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL) + +#define S_RX_OSPI_TXVALID 14 +#define M_RX_OSPI_TXVALID 0x3U +#define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID) +#define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID) + +#define S_RX_OSPI_FULL 12 +#define M_RX_OSPI_FULL 0x3U +#define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL) +#define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL) + +#define S_RX_E_RXVALID 8 +#define M_RX_E_RXVALID 0xfU +#define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID) +#define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID) + +#define S_RX_E_RXAFULL 4 +#define M_RX_E_RXAFULL 0xfU +#define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL) +#define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL) + +#define S_RX_C_TXVALID 2 +#define M_RX_C_TXVALID 0x3U +#define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID) +#define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID) + +#define S_RX_C_TXAFULL 0 +#define M_RX_C_TXAFULL 0x3U +#define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL) +#define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL) + +#define A_PM_RX_DBG_STAT6 0x10027 + +#define S_RX_M_INTRNL_FIFO_CNT 4 +#define M_RX_M_INTRNL_FIFO_CNT 0x3U +#define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT) +#define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT) + +#define S_RX_M_REQADDRRDY 3 +#define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY) +#define F_RX_M_REQADDRRDY V_RX_M_REQADDRRDY(1U) + +#define S_RX_M_REQWRITE 2 +#define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE) +#define F_RX_M_REQWRITE V_RX_M_REQWRITE(1U) + +#define S_RX_M_REQDATAVLD 1 +#define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD) +#define F_RX_M_REQDATAVLD V_RX_M_REQDATAVLD(1U) + +#define S_RX_M_REQDATARDY 0 +#define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY) +#define F_RX_M_REQDATARDY V_RX_M_REQDATARDY(1U) + +#define A_PM_RX_DBG_STAT7 0x10028 + +#define S_RX_PCMD1_FREE_CNT 7 +#define M_RX_PCMD1_FREE_CNT 0x7fU +#define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT) +#define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT) + +#define S_RX_PCMD0_FREE_CNT 0 +#define M_RX_PCMD0_FREE_CNT 0x7fU +#define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT) +#define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT) + +#define A_PM_RX_DBG_STAT8 0x10029 + +#define S_RX_IN_EOP_CNT3 28 +#define M_RX_IN_EOP_CNT3 0xfU +#define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3) +#define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3) + +#define S_RX_IN_EOP_CNT2 24 +#define M_RX_IN_EOP_CNT2 0xfU +#define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2) +#define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2) + +#define S_RX_IN_EOP_CNT1 20 +#define M_RX_IN_EOP_CNT1 0xfU +#define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1) +#define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1) + +#define S_RX_IN_EOP_CNT0 16 +#define M_RX_IN_EOP_CNT0 0xfU +#define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0) +#define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0) + +#define S_RX_IN_SOP_CNT3 12 +#define M_RX_IN_SOP_CNT3 0xfU +#define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3) +#define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3) + +#define S_RX_IN_SOP_CNT2 8 +#define M_RX_IN_SOP_CNT2 0xfU +#define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2) +#define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2) + +#define S_RX_IN_SOP_CNT1 4 +#define M_RX_IN_SOP_CNT1 0xfU +#define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1) +#define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1) + +#define S_RX_IN_SOP_CNT0 0 +#define M_RX_IN_SOP_CNT0 0xfU +#define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0) +#define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0) + +#define A_PM_RX_DBG_STAT9 0x1002a + +#define S_RX_RSVD0 28 +#define M_RX_RSVD0 0xfU +#define V_RX_RSVD0(x) ((x) << S_RX_RSVD0) +#define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0) + +#define S_RX_RSVD1 24 +#define M_RX_RSVD1 0xfU +#define V_RX_RSVD1(x) ((x) << S_RX_RSVD1) +#define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1) + +#define S_RX_OUT_EOP_CNT1 20 +#define M_RX_OUT_EOP_CNT1 0xfU +#define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1) +#define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1) + +#define S_RX_OUT_EOP_CNT0 16 +#define M_RX_OUT_EOP_CNT0 0xfU +#define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0) +#define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0) + +#define S_RX_RSVD2 12 +#define M_RX_RSVD2 0xfU +#define V_RX_RSVD2(x) ((x) << S_RX_RSVD2) +#define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2) + +#define S_RX_RSVD3 8 +#define M_RX_RSVD3 0xfU +#define V_RX_RSVD3(x) ((x) << S_RX_RSVD3) +#define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3) + +#define S_RX_OUT_SOP_CNT1 4 +#define M_RX_OUT_SOP_CNT1 0xfU +#define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1) +#define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1) + +#define S_RX_OUT_SOP_CNT0 0 +#define M_RX_OUT_SOP_CNT0 0xfU +#define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0) +#define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0) + +#define A_PM_RX_DBG_STAT10 0x1002b + +#define S_RX_CH_DEFICIT_BLOWED 24 +#define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED) +#define F_RX_CH_DEFICIT_BLOWED V_RX_CH_DEFICIT_BLOWED(1U) + +#define S_RX_CH1_DEFICIT 12 +#define M_RX_CH1_DEFICIT 0xfffU +#define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT) +#define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT) + +#define S_RX_CH0_DEFICIT 0 +#define M_RX_CH0_DEFICIT 0xfffU +#define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT) +#define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT) + +#define A_PM_RX_DBG_STAT11 0x1002c + +#define S_RX_BUNDLE_LEN_SRDY 30 +#define M_RX_BUNDLE_LEN_SRDY 0x3U +#define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY) +#define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY) + +#define S_RX_RSVD11_1 28 +#define M_RX_RSVD11_1 0x3U +#define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1) +#define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1) + +#define S_RX_BUNDLE_LEN1 16 +#define M_RX_BUNDLE_LEN1 0xfffU +#define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1) +#define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1) + +#define S_RX_RSVD11 12 +#define M_RX_RSVD11 0xfU +#define V_RX_RSVD11(x) ((x) << S_RX_RSVD11) +#define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11) + +#define S_RX_BUNDLE_LEN0 0 +#define M_RX_BUNDLE_LEN0 0xfffU +#define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0) +#define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0) /* registers for module PM_TX */ #define PM_TX_BASE_ADDR 0x8fe0 @@ -14160,7 +21362,15 @@ #define A_PM_TX_STAT_CONFIG 0x8fe8 #define A_PM_TX_STAT_COUNT 0x8fec #define A_PM_TX_STAT_LSB 0x8ff0 +#define A_PM_TX_DBG_CTRL 0x8ff0 + +#define S_OSPIWRBUSY 21 +#define M_OSPIWRBUSY 0xfU +#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY) +#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY) + #define A_PM_TX_STAT_MSB 0x8ff4 +#define A_PM_TX_DBG_DATA 0x8ff4 #define A_PM_TX_INT_ENABLE 0x8ff8 #define S_PCMD_LEN_OVFL0 31 @@ -14293,6 +21503,636 @@ #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) +#define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3 +#define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR) +#define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U) + +#define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000 +#define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001 +#define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002 +#define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003 +#define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004 +#define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005 +#define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006 +#define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007 +#define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008 +#define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009 +#define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a +#define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b +#define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c +#define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d +#define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e +#define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f +#define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010 +#define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011 +#define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012 +#define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013 +#define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014 +#define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015 +#define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016 +#define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017 +#define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018 +#define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019 +#define A_PM_TX_DBG_STAT_MSB 0x1001a +#define A_PM_TX_DBG_STAT_LSB 0x1001b +#define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c +#define A_PM_TX_SDC_EN 0x1001d +#define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e +#define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f +#define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020 +#define A_PM_TX_FEATURE_EN 0x10021 + +#define S_PIO_CH_DEFICIT_CTL_EN 2 +#define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN) +#define F_PIO_CH_DEFICIT_CTL_EN V_PIO_CH_DEFICIT_CTL_EN(1U) + +#define S_PIO_WRR_BASED_PRFTCH_EN 1 +#define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN) +#define F_PIO_WRR_BASED_PRFTCH_EN V_PIO_WRR_BASED_PRFTCH_EN(1U) + +#define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022 + +#define S_OSPI_OVERFLOW3 7 +#define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3) +#define F_OSPI_OVERFLOW3 V_OSPI_OVERFLOW3(1U) + +#define S_OSPI_OVERFLOW2 6 +#define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2) +#define F_OSPI_OVERFLOW2 V_OSPI_OVERFLOW2(1U) + +#define S_M_INTFPERREN 3 +#define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN) +#define F_M_INTFPERREN V_M_INTFPERREN(1U) + +#define S_BUNDLE_LEN_PARERR_EN 2 +#define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN) +#define F_BUNDLE_LEN_PARERR_EN V_BUNDLE_LEN_PARERR_EN(1U) + +#define S_BUNDLE_LEN_OVFL_EN 1 +#define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN) +#define F_BUNDLE_LEN_OVFL_EN V_BUNDLE_LEN_OVFL_EN(1U) + +#define S_SDC_ERR_EN 0 +#define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN) +#define F_SDC_ERR_EN V_SDC_ERR_EN(1U) + +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026 +#define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027 +#define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028 +#define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029 + +#define S_CH2_OSPI_DEFICIT_THRSHLD 0 +#define M_CH2_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD) +#define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD) + +#define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a + +#define S_CH3_OSPI_DEFICIT_THRSHLD 0 +#define M_CH3_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD) +#define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD) + +#define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b +#define A_PM_TX_DBG_STAT0 0x1002c + +#define S_RD_I_BUSY 28 +#define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY) +#define F_RD_I_BUSY V_RD_I_BUSY(1U) + +#define S_WR_O_ONLY 27 +#define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY) +#define F_WR_O_ONLY V_WR_O_ONLY(1U) + +#define S_M_TO_BUSY 26 +#define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY) +#define F_M_TO_BUSY V_M_TO_BUSY(1U) + +#define S_I_TO_M_BUSY 25 +#define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY) +#define F_I_TO_M_BUSY V_I_TO_M_BUSY(1U) + +#define S_PCMD_FB_ONLY 24 +#define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY) +#define F_PCMD_FB_ONLY V_PCMD_FB_ONLY(1U) + +#define S_PCMD_MEM 23 +#define V_PCMD_MEM(x) ((x) << S_PCMD_MEM) +#define F_PCMD_MEM V_PCMD_MEM(1U) + +#define S_PCMD_BYPASS 22 +#define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS) +#define F_PCMD_BYPASS V_PCMD_BYPASS(1U) + +#define S_PCMD_EOP 21 +#define V_PCMD_EOP(x) ((x) << S_PCMD_EOP) +#define F_PCMD_EOP V_PCMD_EOP(1U) + +#define S_PCMD_END_BUNDLE 20 +#define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE) +#define F_PCMD_END_BUNDLE V_PCMD_END_BUNDLE(1U) + +#define S_PCMD_FB_CMD 16 +#define M_PCMD_FB_CMD 0xfU +#define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD) +#define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD) + +#define S_CUR_PCMD_LEN 0 +#define M_CUR_PCMD_LEN 0xffffU +#define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN) +#define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN) + +#define A_PM_TX_DBG_STAT1 0x1002d + +#define S_PCMD_MEM0 31 +#define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0) +#define F_PCMD_MEM0 V_PCMD_MEM0(1U) + +#define S_FREE_OESPI_CNT0 19 +#define M_FREE_OESPI_CNT0 0xfffU +#define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0) +#define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0) + +#define S_PCMD_FLIT_LEN0 7 +#define M_PCMD_FLIT_LEN0 0xfffU +#define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0) +#define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0) + +#define S_PCMD_CMD0 3 +#define M_PCMD_CMD0 0xfU +#define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0) +#define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0) + +#define S_OFIFO_FULL0 2 +#define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0) +#define F_OFIFO_FULL0 V_OFIFO_FULL0(1U) + +#define S_GCSUM_DRDY0 1 +#define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0) +#define F_GCSUM_DRDY0 V_GCSUM_DRDY0(1U) + +#define S_BYPASS0 0 +#define V_BYPASS0(x) ((x) << S_BYPASS0) +#define F_BYPASS0 V_BYPASS0(1U) + +#define A_PM_TX_DBG_STAT2 0x1002e + +#define S_PCMD_MEM1 31 +#define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1) +#define F_PCMD_MEM1 V_PCMD_MEM1(1U) + +#define S_FREE_OESPI_CNT1 19 +#define M_FREE_OESPI_CNT1 0xfffU +#define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1) +#define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1) + +#define S_PCMD_FLIT_LEN1 7 +#define M_PCMD_FLIT_LEN1 0xfffU +#define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1) +#define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1) + +#define S_PCMD_CMD1 3 +#define M_PCMD_CMD1 0xfU +#define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1) +#define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1) + +#define S_OFIFO_FULL1 2 +#define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1) +#define F_OFIFO_FULL1 V_OFIFO_FULL1(1U) + +#define S_GCSUM_DRDY1 1 +#define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1) +#define F_GCSUM_DRDY1 V_GCSUM_DRDY1(1U) + +#define S_BYPASS1 0 +#define V_BYPASS1(x) ((x) << S_BYPASS1) +#define F_BYPASS1 V_BYPASS1(1U) + +#define A_PM_TX_DBG_STAT3 0x1002f + +#define S_PCMD_MEM2 31 +#define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2) +#define F_PCMD_MEM2 V_PCMD_MEM2(1U) + +#define S_FREE_OESPI_CNT2 19 +#define M_FREE_OESPI_CNT2 0xfffU +#define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2) +#define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2) + +#define S_PCMD_FLIT_LEN2 7 +#define M_PCMD_FLIT_LEN2 0xfffU +#define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2) +#define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2) + +#define S_PCMD_CMD2 3 +#define M_PCMD_CMD2 0xfU +#define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2) +#define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2) + +#define S_OFIFO_FULL2 2 +#define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2) +#define F_OFIFO_FULL2 V_OFIFO_FULL2(1U) + +#define S_GCSUM_DRDY2 1 +#define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2) +#define F_GCSUM_DRDY2 V_GCSUM_DRDY2(1U) + +#define S_BYPASS2 0 +#define V_BYPASS2(x) ((x) << S_BYPASS2) +#define F_BYPASS2 V_BYPASS2(1U) + +#define A_PM_TX_DBG_STAT4 0x10030 + +#define S_PCMD_MEM3 31 +#define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3) +#define F_PCMD_MEM3 V_PCMD_MEM3(1U) + +#define S_FREE_OESPI_CNT3 19 +#define M_FREE_OESPI_CNT3 0xfffU +#define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3) +#define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3) + +#define S_PCMD_FLIT_LEN3 7 +#define M_PCMD_FLIT_LEN3 0xfffU +#define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3) +#define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3) + +#define S_PCMD_CMD3 3 +#define M_PCMD_CMD3 0xfU +#define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3) +#define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3) + +#define S_OFIFO_FULL3 2 +#define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3) +#define F_OFIFO_FULL3 V_OFIFO_FULL3(1U) + +#define S_GCSUM_DRDY3 1 +#define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3) +#define F_GCSUM_DRDY3 V_GCSUM_DRDY3(1U) + +#define S_BYPASS3 0 +#define V_BYPASS3(x) ((x) << S_BYPASS3) +#define F_BYPASS3 V_BYPASS3(1U) + +#define A_PM_TX_DBG_STAT5 0x10031 + +#define S_SET_PCMD_RES_RDY_RD 24 +#define M_SET_PCMD_RES_RDY_RD 0xfU +#define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD) +#define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD) + +#define S_ISSUED_PREF_RD_ER_CLR 20 +#define M_ISSUED_PREF_RD_ER_CLR 0xfU +#define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR) +#define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR) + +#define S_ISSUED_PREF_RD 16 +#define M_ISSUED_PREF_RD 0xfU +#define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD) +#define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD) + +#define S_PCMD_RES_RDY 12 +#define M_PCMD_RES_RDY 0xfU +#define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY) +#define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY) + +#define S_DB_VLD 11 +#define V_DB_VLD(x) ((x) << S_DB_VLD) +#define F_DB_VLD V_DB_VLD(1U) + +#define S_INJECT0_DRDY 10 +#define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY) +#define F_INJECT0_DRDY V_INJECT0_DRDY(1U) + +#define S_INJECT1_DRDY 9 +#define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY) +#define F_INJECT1_DRDY V_INJECT1_DRDY(1U) + +#define S_FIRST_BUNDLE 5 +#define M_FIRST_BUNDLE 0xfU +#define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE) +#define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE) + +#define S_GCSUM_MORE_THAN_2_LEFT 1 +#define M_GCSUM_MORE_THAN_2_LEFT 0xfU +#define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT) +#define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT) + +#define S_SDC_DRDY 0 +#define V_SDC_DRDY(x) ((x) << S_SDC_DRDY) +#define F_SDC_DRDY V_SDC_DRDY(1U) + +#define A_PM_TX_DBG_STAT6 0x10032 + +#define S_PCMD_VLD 31 +#define V_PCMD_VLD(x) ((x) << S_PCMD_VLD) +#define F_PCMD_VLD V_PCMD_VLD(1U) + +#define S_PCMD_CH 29 +#define M_PCMD_CH 0x3U +#define V_PCMD_CH(x) ((x) << S_PCMD_CH) +#define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH) + +#define S_STATE_MACHINE_LOC 24 +#define M_STATE_MACHINE_LOC 0x1fU +#define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC) +#define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC) + +#define S_ICSPI_TXVALID 20 +#define M_ICSPI_TXVALID 0xfU +#define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID) +#define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID) + +#define S_ICSPI_TXFULL 16 +#define M_ICSPI_TXFULL 0xfU +#define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL) +#define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL) + +#define S_PCMD_SRDY 12 +#define M_PCMD_SRDY 0xfU +#define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY) +#define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY) + +#define S_PCMD_DRDY 8 +#define M_PCMD_DRDY 0xfU +#define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY) +#define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY) + +#define S_PCMD_CMD 4 +#define M_PCMD_CMD 0xfU +#define V_PCMD_CMD(x) ((x) << S_PCMD_CMD) +#define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD) + +#define S_OEFIFO_FULL3 3 +#define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3) +#define F_OEFIFO_FULL3 V_OEFIFO_FULL3(1U) + +#define S_OEFIFO_FULL2 2 +#define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2) +#define F_OEFIFO_FULL2 V_OEFIFO_FULL2(1U) + +#define S_OEFIFO_FULL1 1 +#define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1) +#define F_OEFIFO_FULL1 V_OEFIFO_FULL1(1U) + +#define S_OEFIFO_FULL0 0 +#define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0) +#define F_OEFIFO_FULL0 V_OEFIFO_FULL0(1U) + +#define A_PM_TX_DBG_STAT7 0x10033 + +#define S_ICSPI_RXVALID 28 +#define M_ICSPI_RXVALID 0xfU +#define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID) +#define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID) + +#define S_ICSPI_RXFULL 24 +#define M_ICSPI_RXFULL 0xfU +#define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL) +#define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL) + +#define S_OESPI_VALID 20 +#define M_OESPI_VALID 0xfU +#define V_OESPI_VALID(x) ((x) << S_OESPI_VALID) +#define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID) + +#define S_OESPI_FULL 16 +#define M_OESPI_FULL 0xfU +#define V_OESPI_FULL(x) ((x) << S_OESPI_FULL) +#define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL) + +#define S_C_RXVALID 12 +#define M_C_RXVALID 0xfU +#define V_C_RXVALID(x) ((x) << S_C_RXVALID) +#define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID) + +#define S_C_RXAFULL 8 +#define M_C_RXAFULL 0xfU +#define V_C_RXAFULL(x) ((x) << S_C_RXAFULL) +#define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL) + +#define S_E_TXVALID3 7 +#define V_E_TXVALID3(x) ((x) << S_E_TXVALID3) +#define F_E_TXVALID3 V_E_TXVALID3(1U) + +#define S_E_TXVALID2 6 +#define V_E_TXVALID2(x) ((x) << S_E_TXVALID2) +#define F_E_TXVALID2 V_E_TXVALID2(1U) + +#define S_E_TXVALID1 5 +#define V_E_TXVALID1(x) ((x) << S_E_TXVALID1) +#define F_E_TXVALID1 V_E_TXVALID1(1U) + +#define S_E_TXVALID0 4 +#define V_E_TXVALID0(x) ((x) << S_E_TXVALID0) +#define F_E_TXVALID0 V_E_TXVALID0(1U) + +#define S_E_TXFULL3 3 +#define V_E_TXFULL3(x) ((x) << S_E_TXFULL3) +#define F_E_TXFULL3 V_E_TXFULL3(1U) + +#define S_E_TXFULL2 2 +#define V_E_TXFULL2(x) ((x) << S_E_TXFULL2) +#define F_E_TXFULL2 V_E_TXFULL2(1U) + +#define S_E_TXFULL1 1 +#define V_E_TXFULL1(x) ((x) << S_E_TXFULL1) +#define F_E_TXFULL1 V_E_TXFULL1(1U) + +#define S_E_TXFULL0 0 +#define V_E_TXFULL0(x) ((x) << S_E_TXFULL0) +#define F_E_TXFULL0 V_E_TXFULL0(1U) + +#define A_PM_TX_DBG_STAT8 0x10034 + +#define S_MC_RSP_FIFO_CNT 24 +#define M_MC_RSP_FIFO_CNT 0x3U +#define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT) +#define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT) + +#define S_PCMD_FREE_CNT0 14 +#define M_PCMD_FREE_CNT0 0x3ffU +#define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0) +#define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0) + +#define S_PCMD_FREE_CNT1 4 +#define M_PCMD_FREE_CNT1 0x3ffU +#define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1) +#define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1) + +#define S_M_REQADDRRDY 3 +#define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY) +#define F_M_REQADDRRDY V_M_REQADDRRDY(1U) + +#define S_M_REQWRITE 2 +#define V_M_REQWRITE(x) ((x) << S_M_REQWRITE) +#define F_M_REQWRITE V_M_REQWRITE(1U) + +#define S_M_REQDATAVLD 1 +#define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD) +#define F_M_REQDATAVLD V_M_REQDATAVLD(1U) + +#define S_M_REQDATARDY 0 +#define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY) +#define F_M_REQDATARDY V_M_REQDATARDY(1U) + +#define A_PM_TX_DBG_STAT9 0x10035 + +#define S_PCMD_FREE_CNT2 10 +#define M_PCMD_FREE_CNT2 0x3ffU +#define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2) +#define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2) + +#define S_PCMD_FREE_CNT3 0 +#define M_PCMD_FREE_CNT3 0x3ffU +#define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3) +#define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3) + +#define A_PM_TX_DBG_STAT10 0x10036 + +#define S_IN_EOP_CNT3 28 +#define M_IN_EOP_CNT3 0xfU +#define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3) +#define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3) + +#define S_IN_EOP_CNT2 24 +#define M_IN_EOP_CNT2 0xfU +#define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2) +#define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2) + +#define S_IN_EOP_CNT1 20 +#define M_IN_EOP_CNT1 0xfU +#define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1) +#define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1) + +#define S_IN_EOP_CNT0 16 +#define M_IN_EOP_CNT0 0xfU +#define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0) +#define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0) + +#define S_IN_SOP_CNT3 12 +#define M_IN_SOP_CNT3 0xfU +#define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3) +#define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3) + +#define S_IN_SOP_CNT2 8 +#define M_IN_SOP_CNT2 0xfU +#define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2) +#define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2) + +#define S_IN_SOP_CNT1 4 +#define M_IN_SOP_CNT1 0xfU +#define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1) +#define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1) + +#define S_IN_SOP_CNT0 0 +#define M_IN_SOP_CNT0 0xfU +#define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0) +#define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0) + +#define A_PM_TX_DBG_STAT11 0x10037 + +#define S_OUT_EOP_CNT3 28 +#define M_OUT_EOP_CNT3 0xfU +#define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3) +#define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3) + +#define S_OUT_EOP_CNT2 24 +#define M_OUT_EOP_CNT2 0xfU +#define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2) +#define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2) + +#define S_OUT_EOP_CNT1 20 +#define M_OUT_EOP_CNT1 0xfU +#define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1) +#define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1) + +#define S_OUT_EOP_CNT0 16 +#define M_OUT_EOP_CNT0 0xfU +#define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0) +#define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0) + +#define S_OUT_SOP_CNT3 12 +#define M_OUT_SOP_CNT3 0xfU +#define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3) +#define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3) + +#define S_OUT_SOP_CNT2 8 +#define M_OUT_SOP_CNT2 0xfU +#define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2) +#define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2) + +#define S_OUT_SOP_CNT1 4 +#define M_OUT_SOP_CNT1 0xfU +#define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1) +#define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1) + +#define S_OUT_SOP_CNT0 0 +#define M_OUT_SOP_CNT0 0xfU +#define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0) +#define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0) + +#define A_PM_TX_DBG_STAT12 0x10038 +#define A_PM_TX_DBG_STAT13 0x10039 + +#define S_CH_DEFICIT_BLOWED 31 +#define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED) +#define F_CH_DEFICIT_BLOWED V_CH_DEFICIT_BLOWED(1U) + +#define S_CH1_DEFICIT 16 +#define M_CH1_DEFICIT 0xfffU +#define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT) +#define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT) + +#define S_CH0_DEFICIT 0 +#define M_CH0_DEFICIT 0xfffU +#define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT) +#define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT) + +#define A_PM_TX_DBG_STAT14 0x1003a + +#define S_CH3_DEFICIT 16 +#define M_CH3_DEFICIT 0xfffU +#define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT) +#define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT) + +#define S_CH2_DEFICIT 0 +#define M_CH2_DEFICIT 0xfffU +#define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT) +#define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT) + +#define A_PM_TX_DBG_STAT15 0x1003b + +#define S_BUNDLE_LEN_SRDY 28 +#define M_BUNDLE_LEN_SRDY 0xfU +#define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY) +#define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY) + +#define S_BUNDLE_LEN1 16 +#define M_BUNDLE_LEN1 0xfffU +#define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1) +#define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1) + +#define S_BUNDLE_LEN0 0 +#define M_BUNDLE_LEN0 0xfffU +#define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0) +#define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0) + +#define A_PM_TX_DBG_STAT16 0x1003c + +#define S_BUNDLE_LEN3 16 +#define M_BUNDLE_LEN3 0xfffU +#define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3) +#define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3) + +#define S_BUNDLE_LEN2 0 +#define M_BUNDLE_LEN2 0xfffU +#define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2) +#define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2) + /* registers for module MPS */ #define MPS_BASE_ADDR 0x9000 @@ -14456,6 +22296,48 @@ #define V_PRTY0(x) ((x) << S_PRTY0) #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0) +#define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30 + +#define S_TXPRTY7 28 +#define M_TXPRTY7 0xfU +#define V_TXPRTY7(x) ((x) << S_TXPRTY7) +#define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7) + +#define S_TXPRTY6 24 +#define M_TXPRTY6 0xfU +#define V_TXPRTY6(x) ((x) << S_TXPRTY6) +#define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6) + +#define S_TXPRTY5 20 +#define M_TXPRTY5 0xfU +#define V_TXPRTY5(x) ((x) << S_TXPRTY5) +#define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5) + +#define S_TXPRTY4 16 +#define M_TXPRTY4 0xfU +#define V_TXPRTY4(x) ((x) << S_TXPRTY4) +#define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4) + +#define S_TXPRTY3 12 +#define M_TXPRTY3 0xfU +#define V_TXPRTY3(x) ((x) << S_TXPRTY3) +#define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3) + +#define S_TXPRTY2 8 +#define M_TXPRTY2 0xfU +#define V_TXPRTY2(x) ((x) << S_TXPRTY2) +#define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2) + +#define S_TXPRTY1 4 +#define M_TXPRTY1 0xfU +#define V_TXPRTY1(x) ((x) << S_TXPRTY1) +#define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1) + +#define S_TXPRTY0 0 +#define M_TXPRTY0 0xfU +#define V_TXPRTY0(x) ((x) << S_TXPRTY0) +#define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0) + #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88 @@ -14571,6 +22453,10 @@ #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0) #define F_OVLAN_EN0 V_OVLAN_EN0(1U) +#define S_PTP_FWD_UP 21 +#define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP) +#define F_PTP_FWD_UP V_PTP_FWD_UP(1U) + #define A_MPS_PORT_RX_MTU 0x104 #define A_MPS_PORT_RX_PF_MAP 0x108 #define A_MPS_PORT_RX_VF_MAP0 0x10c @@ -14641,6 +22527,8 @@ #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF) #define A_MPS_PORT_RX_SPARE 0x13c +#define A_MPS_PORT_RX_PTP_RSS_HASH 0x140 +#define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190 #define S_CREDIT 0 @@ -14674,6 +22562,23 @@ #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT) #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8 + +#define S_FPGAPAUSEEN 0 +#define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN) +#define F_FPGAPAUSEEN V_FPGAPAUSEEN(1U) + +#define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0 + +#define S_OFF_PENDING 8 +#define M_OFF_PENDING 0xffU +#define V_OFF_PENDING(x) ((x) << S_OFF_PENDING) +#define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING) + +#define S_ON_PENDING 0 +#define M_ON_PENDING 0xffU +#define V_ON_PENDING(x) ((x) << S_ON_PENDING) +#define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING) + #define A_MPS_PORT_CLS_HASH_SRAM 0x200 #define S_VALID 20 @@ -14789,6 +22694,50 @@ #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL) #define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U) +#define S_LPBK_TCAM1_HIT_PRIORITY 14 +#define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY) +#define F_LPBK_TCAM1_HIT_PRIORITY V_LPBK_TCAM1_HIT_PRIORITY(1U) + +#define S_LPBK_TCAM0_HIT_PRIORITY 13 +#define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY) +#define F_LPBK_TCAM0_HIT_PRIORITY V_LPBK_TCAM0_HIT_PRIORITY(1U) + +#define S_LPBK_TCAM_PRIORITY 12 +#define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY) +#define F_LPBK_TCAM_PRIORITY V_LPBK_TCAM_PRIORITY(1U) + +#define S_LPBK_SMAC_TCAM_SEL 10 +#define M_LPBK_SMAC_TCAM_SEL 0x3U +#define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL) +#define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL) + +#define S_LPBK_DMAC_TCAM_SEL 8 +#define M_LPBK_DMAC_TCAM_SEL 0x3U +#define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL) +#define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL) + +#define S_TCAM1_HIT_PRIORITY 7 +#define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY) +#define F_TCAM1_HIT_PRIORITY V_TCAM1_HIT_PRIORITY(1U) + +#define S_TCAM0_HIT_PRIORITY 6 +#define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY) +#define F_TCAM0_HIT_PRIORITY V_TCAM0_HIT_PRIORITY(1U) + +#define S_TCAM_PRIORITY 5 +#define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY) +#define F_TCAM_PRIORITY V_TCAM_PRIORITY(1U) + +#define S_SMAC_TCAM_SEL 3 +#define M_SMAC_TCAM_SEL 0x3U +#define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL) +#define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL) + +#define S_DMAC_TCAM_SEL 1 +#define M_DMAC_TCAM_SEL 0x3U +#define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL) +#define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL) + #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324 @@ -14889,6 +22838,8 @@ #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 +#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 +#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 @@ -14943,6 +22894,8 @@ #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 +#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618 +#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c #define A_MPS_CMN_CTL 0x9000 #define S_DETECT8023 3 @@ -14958,6 +22911,10 @@ #define V_NUMPORTS(x) ((x) << S_NUMPORTS) #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS) +#define S_LPBKCRDTCTRL 4 +#define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL) +#define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U) + #define A_MPS_INT_ENABLE 0x9004 #define S_STATINTENB 5 @@ -15010,6 +22967,12 @@ #define V_PLINT(x) ((x) << S_PLINT) #define F_PLINT V_PLINT(1U) +#define A_MPS_CGEN_GLOBAL 0x900c + +#define S_MPS_GLOBAL_CGEN 0 +#define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN) +#define F_MPS_GLOBAL_CGEN V_MPS_GLOBAL_CGEN(1U) + #define A_MPS_VF_TX_CTL_31_0 0x9010 #define A_MPS_VF_TX_CTL_63_32 0x9014 #define A_MPS_VF_TX_CTL_95_64 0x9018 @@ -15072,6 +23035,11 @@ #define V_CH_MAP0(x) ((x) << S_CH_MAP0) #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0) +#define S_FPGA_PTP_PORT 9 +#define M_FPGA_PTP_PORT 0x3U +#define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT) +#define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT) + #define A_MPS_DEBUG_CTL 0x9068 #define S_DBGMODECTL_H 11 @@ -15096,16 +23064,11 @@ #define A_MPS_DEBUG_DATA_REG_H 0x9070 #define A_MPS_TOP_SPARE 0x9074 -#define S_TOPSPARE 12 -#define M_TOPSPARE 0xfffffU +#define S_TOPSPARE 8 +#define M_TOPSPARE 0xffffffU #define V_TOPSPARE(x) ((x) << S_TOPSPARE) #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE) -#define S_CHIKN_14463 8 -#define M_CHIKN_14463 0xfU -#define V_CHIKN_14463(x) ((x) << S_CHIKN_14463) -#define G_CHIKN_14463(x) (((x) >> S_CHIKN_14463) & M_CHIKN_14463) - #define S_OVLANSELLPBK3 7 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3) #define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U) @@ -15138,6 +23101,44 @@ #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0) #define F_OVLANSELMAC0 V_OVLANSELMAC0(1U) +#define S_T5_TOPSPARE 8 +#define M_T5_TOPSPARE 0xffffffU +#define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE) +#define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE) + +#define A_MPS_T5_BUILD_REVISION 0x9078 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8 #define A_MPS_BUILD_REVISION 0x90fc #define A_MPS_TX_PRTY_SEL 0x9400 @@ -15250,6 +23251,15 @@ #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR) #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR) +#define S_NCSISECNT 20 +#define V_NCSISECNT(x) ((x) << S_NCSISECNT) +#define F_NCSISECNT V_NCSISECNT(1U) + +#define S_LPBKSECNT 16 +#define M_LPBKSECNT 0xfU +#define V_LPBKSECNT(x) ((x) << S_LPBKSECNT) +#define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT) + #define A_MPS_TX_PORT_ERR 0x9430 #define S_LPBKPT3 7 @@ -15552,6 +23562,13 @@ #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR) #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR) +#define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454 + +#define S_T5SGEPAUSEIGNR 0 +#define M_T5SGEPAUSEIGNR 0xffffU +#define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR) +#define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR) + #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458 #define S_SUBPRTH 11 @@ -15574,6 +23591,182 @@ #define V_PORTL(x) ((x) << S_PORTL) #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL) +#define A_MPS_TX_PAD_CTL 0x945c + +#define S_LPBKPADENPT3 7 +#define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3) +#define F_LPBKPADENPT3 V_LPBKPADENPT3(1U) + +#define S_LPBKPADENPT2 6 +#define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2) +#define F_LPBKPADENPT2 V_LPBKPADENPT2(1U) + +#define S_LPBKPADENPT1 5 +#define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1) +#define F_LPBKPADENPT1 V_LPBKPADENPT1(1U) + +#define S_LPBKPADENPT0 4 +#define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0) +#define F_LPBKPADENPT0 V_LPBKPADENPT0(1U) + +#define S_MACPADENPT3 3 +#define V_MACPADENPT3(x) ((x) << S_MACPADENPT3) +#define F_MACPADENPT3 V_MACPADENPT3(1U) + +#define S_MACPADENPT2 2 +#define V_MACPADENPT2(x) ((x) << S_MACPADENPT2) +#define F_MACPADENPT2 V_MACPADENPT2(1U) + +#define S_MACPADENPT1 1 +#define V_MACPADENPT1(x) ((x) << S_MACPADENPT1) +#define F_MACPADENPT1 V_MACPADENPT1(1U) + +#define S_MACPADENPT0 0 +#define V_MACPADENPT0(x) ((x) << S_MACPADENPT0) +#define F_MACPADENPT0 V_MACPADENPT0(1U) + +#define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460 + +#define S_TP2MPS_CH3 24 +#define M_TP2MPS_CH3 0xffU +#define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3) +#define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3) + +#define S_TP2MPS_CH2 16 +#define M_TP2MPS_CH2 0xffU +#define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2) +#define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2) + +#define S_TP2MPS_CH1 8 +#define M_TP2MPS_CH1 0xffU +#define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1) +#define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1) + +#define S_TP2MPS_CH0 0 +#define M_TP2MPS_CH0 0xffU +#define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0) +#define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0) + +#define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464 + +#define S_NCSI_CH4 0 +#define M_NCSI_CH4 0xffU +#define V_NCSI_CH4(x) ((x) << S_NCSI_CH4) +#define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4) + +#define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468 + +#define S_PFNOVFDROP 5 +#define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP) +#define F_PFNOVFDROP V_PFNOVFDROP(1U) + +#define S_NCSI_CH4_CLR 4 +#define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR) +#define F_NCSI_CH4_CLR V_NCSI_CH4_CLR(1U) + +#define S_TP2MPS_CH3_CLR 3 +#define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR) +#define F_TP2MPS_CH3_CLR V_TP2MPS_CH3_CLR(1U) + +#define S_TP2MPS_CH2_CLR 2 +#define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR) +#define F_TP2MPS_CH2_CLR V_TP2MPS_CH2_CLR(1U) + +#define S_TP2MPS_CH1_CLR 1 +#define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR) +#define F_TP2MPS_CH1_CLR V_TP2MPS_CH1_CLR(1U) + +#define S_TP2MPS_CH0_CLR 0 +#define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR) +#define F_TP2MPS_CH0_CLR V_TP2MPS_CH0_CLR(1U) + +#define A_MPS_TX_CGEN 0x946c + +#define S_TXOUTLPBK3_CGEN 31 +#define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN) +#define F_TXOUTLPBK3_CGEN V_TXOUTLPBK3_CGEN(1U) + +#define S_TXOUTLPBK2_CGEN 30 +#define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN) +#define F_TXOUTLPBK2_CGEN V_TXOUTLPBK2_CGEN(1U) + +#define S_TXOUTLPBK1_CGEN 29 +#define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN) +#define F_TXOUTLPBK1_CGEN V_TXOUTLPBK1_CGEN(1U) + +#define S_TXOUTLPBK0_CGEN 28 +#define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN) +#define F_TXOUTLPBK0_CGEN V_TXOUTLPBK0_CGEN(1U) + +#define S_TXOUTMAC3_CGEN 27 +#define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN) +#define F_TXOUTMAC3_CGEN V_TXOUTMAC3_CGEN(1U) + +#define S_TXOUTMAC2_CGEN 26 +#define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN) +#define F_TXOUTMAC2_CGEN V_TXOUTMAC2_CGEN(1U) + +#define S_TXOUTMAC1_CGEN 25 +#define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN) +#define F_TXOUTMAC1_CGEN V_TXOUTMAC1_CGEN(1U) + +#define S_TXOUTMAC0_CGEN 24 +#define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN) +#define F_TXOUTMAC0_CGEN V_TXOUTMAC0_CGEN(1U) + +#define S_TXSCHLPBK3_CGEN 23 +#define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN) +#define F_TXSCHLPBK3_CGEN V_TXSCHLPBK3_CGEN(1U) + +#define S_TXSCHLPBK2_CGEN 22 +#define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN) +#define F_TXSCHLPBK2_CGEN V_TXSCHLPBK2_CGEN(1U) + +#define S_TXSCHLPBK1_CGEN 21 +#define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN) +#define F_TXSCHLPBK1_CGEN V_TXSCHLPBK1_CGEN(1U) + +#define S_TXSCHLPBK0_CGEN 20 +#define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN) +#define F_TXSCHLPBK0_CGEN V_TXSCHLPBK0_CGEN(1U) + +#define S_TXSCHMAC3_CGEN 19 +#define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN) +#define F_TXSCHMAC3_CGEN V_TXSCHMAC3_CGEN(1U) + +#define S_TXSCHMAC2_CGEN 18 +#define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN) +#define F_TXSCHMAC2_CGEN V_TXSCHMAC2_CGEN(1U) + +#define S_TXSCHMAC1_CGEN 17 +#define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN) +#define F_TXSCHMAC1_CGEN V_TXSCHMAC1_CGEN(1U) + +#define S_TXSCHMAC0_CGEN 16 +#define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN) +#define F_TXSCHMAC0_CGEN V_TXSCHMAC0_CGEN(1U) + +#define S_TXINCH4_CGEN 15 +#define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN) +#define F_TXINCH4_CGEN V_TXINCH4_CGEN(1U) + +#define S_TXINCH3_CGEN 14 +#define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN) +#define F_TXINCH3_CGEN V_TXINCH3_CGEN(1U) + +#define S_TXINCH2_CGEN 13 +#define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN) +#define F_TXINCH2_CGEN V_TXINCH2_CGEN(1U) + +#define S_TXINCH1_CGEN 12 +#define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN) +#define F_TXINCH1_CGEN V_TXINCH1_CGEN(1U) + +#define S_TXINCH0_CGEN 11 +#define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN) +#define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U) + +#define A_MPS_TX_CGEN_DYNAMIC 0x9470 #define A_MPS_STAT_CTL 0x9600 #define S_COUNTVFINPF 1 @@ -15584,6 +23777,42 @@ #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT) #define F_LPBKERRSTAT V_LPBKERRSTAT(1U) +#define S_STATSTOPCTRL 10 +#define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL) +#define F_STATSTOPCTRL V_STATSTOPCTRL(1U) + +#define S_STOPSTAT 9 +#define V_STOPSTAT(x) ((x) << S_STOPSTAT) +#define F_STOPSTAT V_STOPSTAT(1U) + +#define S_STATWRITECTRL 8 +#define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL) +#define F_STATWRITECTRL V_STATWRITECTRL(1U) + +#define S_COUNTLBPF 7 +#define V_COUNTLBPF(x) ((x) << S_COUNTLBPF) +#define F_COUNTLBPF V_COUNTLBPF(1U) + +#define S_COUNTLBVF 6 +#define V_COUNTLBVF(x) ((x) << S_COUNTLBVF) +#define F_COUNTLBVF V_COUNTLBVF(1U) + +#define S_COUNTPAUSEMCRX 5 +#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX) +#define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U) + +#define S_COUNTPAUSESTATRX 4 +#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX) +#define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U) + +#define S_COUNTPAUSEMCTX 3 +#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX) +#define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U) + +#define S_COUNTPAUSESTATTX 2 +#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX) +#define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U) + #define A_MPS_STAT_INT_ENABLE 0x9608 #define S_PLREADSYNCERR 0 @@ -15632,6 +23861,36 @@ #define V_TXPORT(x) ((x) << S_TXPORT) #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT) +#define S_T5_RXBG 27 +#define M_T5_RXBG 0x3U +#define V_T5_RXBG(x) ((x) << S_T5_RXBG) +#define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG) + +#define S_T5_RXPF 22 +#define M_T5_RXPF 0x1fU +#define V_T5_RXPF(x) ((x) << S_T5_RXPF) +#define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF) + +#define S_T5_TXPF 18 +#define M_T5_TXPF 0xfU +#define V_T5_TXPF(x) ((x) << S_T5_TXPF) +#define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF) + +#define S_T5_RXPORT 11 +#define M_T5_RXPORT 0x7fU +#define V_T5_RXPORT(x) ((x) << S_T5_RXPORT) +#define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT) + +#define S_T5_LBPORT 6 +#define M_T5_LBPORT 0x1fU +#define V_T5_LBPORT(x) ((x) << S_T5_LBPORT) +#define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT) + +#define S_T5_TXPORT 0 +#define M_T5_TXPORT 0x3fU +#define V_T5_TXPORT(x) ((x) << S_T5_TXPORT) +#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT) + #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c @@ -15651,6 +23910,11 @@ #define V_DROP(x) ((x) << S_DROP) #define G_DROP(x) (((x) >> S_DROP) & M_DROP) +#define S_TXCH 20 +#define M_TXCH 0xfU +#define V_TXCH(x) ((x) << S_TXCH) +#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH) + #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628 @@ -15690,6 +23954,22 @@ #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL) #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638 + +#define S_STATSSUBPRTH 5 +#define M_STATSSUBPRTH 0x1fU +#define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH) +#define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH) + +#define S_STATSSUBPRTL 0 +#define M_STATSSUBPRTL 0x1fU +#define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL) +#define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL) + +#define S_STATSUBPRTH 5 +#define M_STATSUBPRTH 0x1fU +#define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH) +#define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH) + #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 @@ -15722,6 +24002,64 @@ #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc +#define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0 + +#define S_T5_RXVF 5 +#define M_T5_RXVF 0x7U +#define V_T5_RXVF(x) ((x) << S_T5_RXVF) +#define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF) + +#define S_T5_TXVF 0 +#define M_T5_TXVF 0x1fU +#define V_T5_TXVF(x) ((x) << S_T5_TXVF) +#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF) + +#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4 +#define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8 +#define A_MPS_STAT_STOP_UPD_BG 0x96cc + +#define S_BGRX 0 +#define M_BGRX 0xfU +#define V_BGRX(x) ((x) << S_BGRX) +#define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX) + +#define A_MPS_STAT_STOP_UPD_PORT 0x96d0 + +#define S_PTLPBK 8 +#define M_PTLPBK 0xfU +#define V_PTLPBK(x) ((x) << S_PTLPBK) +#define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK) + +#define S_PTTX 4 +#define M_PTTX 0xfU +#define V_PTTX(x) ((x) << S_PTTX) +#define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX) + +#define S_PTRX 0 +#define M_PTRX 0xfU +#define V_PTRX(x) ((x) << S_PTRX) +#define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX) + +#define A_MPS_STAT_STOP_UPD_PF 0x96d4 + +#define S_PFTX 8 +#define M_PFTX 0xffU +#define V_PFTX(x) ((x) << S_PFTX) +#define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX) + +#define S_PFRX 0 +#define M_PFRX 0xffU +#define V_PFRX(x) ((x) << S_PFRX) +#define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX) + +#define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8 +#define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc +#define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0 +#define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4 +#define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8 +#define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec +#define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0 +#define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4 #define A_MPS_TRC_CFG 0x9800 #define S_TRCFIFOEMPTY 4 @@ -15744,7 +24082,12 @@ #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER) #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U) +#define S_TRCMULTIRSSFILTER 5 +#define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER) +#define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U) + #define A_MPS_TRC_RSS_HASH 0x9804 +#define A_MPS_TRC_FILTER0_RSS_HASH 0x9804 #define A_MPS_TRC_RSS_CONTROL 0x9808 #define S_RSSCONTROL 16 @@ -15757,6 +24100,7 @@ #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER) #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER) +#define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810 #define S_TFINVERTMATCH 24 @@ -15794,6 +24138,31 @@ #define V_TFOFFSET(x) ((x) << S_TFOFFSET) #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET) +#define S_TFINSERTACTLEN 27 +#define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN) +#define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U) + +#define S_TFINSERTTIMER 26 +#define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER) +#define F_TFINSERTTIMER V_TFINSERTTIMER(1U) + +#define S_T5_TFINVERTMATCH 25 +#define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH) +#define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U) + +#define S_T5_TFPKTTOOLARGE 24 +#define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE) +#define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U) + +#define S_T5_TFEN 23 +#define V_T5_TFEN(x) ((x) << S_T5_TFEN) +#define F_T5_TFEN V_T5_TFEN(1U) + +#define S_T5_TFPORT 18 +#define M_T5_TFPORT 0x1fU +#define V_T5_TFPORT(x) ((x) << S_T5_TFPORT) +#define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT) + #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820 #define S_TFMINPKTSIZE 16 @@ -15865,6 +24234,64 @@ #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80 #define A_MPS_TRC_FILTER3_MATCH 0x9f00 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80 +#define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0 +#define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4 +#define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8 +#define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc +#define A_MPS_TRC_FILTER3_RSS_HASH 0xa000 +#define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004 +#define A_MPS_T5_TRC_RSS_HASH 0xa008 +#define A_MPS_T5_TRC_RSS_CONTROL 0xa00c +#define A_MPS_TRC_VF_OFF_FILTER_0 0xa010 + +#define S_TRCMPS2TP_MACONLY 20 +#define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY) +#define F_TRCMPS2TP_MACONLY V_TRCMPS2TP_MACONLY(1U) + +#define S_TRCALLMPS2TP 19 +#define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP) +#define F_TRCALLMPS2TP V_TRCALLMPS2TP(1U) + +#define S_TRCALLTP2MPS 18 +#define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS) +#define F_TRCALLTP2MPS V_TRCALLTP2MPS(1U) + +#define S_TRCALLVF 17 +#define V_TRCALLVF(x) ((x) << S_TRCALLVF) +#define F_TRCALLVF V_TRCALLVF(1U) + +#define S_TRC_OFLD_EN 16 +#define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN) +#define F_TRC_OFLD_EN V_TRC_OFLD_EN(1U) + +#define S_VFFILTEN 15 +#define V_VFFILTEN(x) ((x) << S_VFFILTEN) +#define F_VFFILTEN V_VFFILTEN(1U) + +#define S_VFFILTMASK 8 +#define M_VFFILTMASK 0x7fU +#define V_VFFILTMASK(x) ((x) << S_VFFILTMASK) +#define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK) + +#define S_VFFILTVALID 7 +#define V_VFFILTVALID(x) ((x) << S_VFFILTVALID) +#define F_VFFILTVALID V_VFFILTVALID(1U) + +#define S_VFFILTDATA 0 +#define M_VFFILTDATA 0x7fU +#define V_VFFILTDATA(x) ((x) << S_VFFILTDATA) +#define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA) + +#define A_MPS_TRC_VF_OFF_FILTER_1 0xa014 +#define A_MPS_TRC_VF_OFF_FILTER_2 0xa018 +#define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c +#define A_MPS_TRC_CGEN 0xa020 + +#define S_MPSTRCCGEN 0 +#define M_MPSTRCCGEN 0xfU +#define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN) +#define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN) + #define A_MPS_CLS_CTL 0xd000 #define S_MEMWRITEFAULT 4 @@ -16042,6 +24469,7 @@ #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD) #define F_SRAM_VLD V_SRAM_VLD(1U) +#define A_MPS_T5_CLS_SRAM_L 0xe000 #define A_MPS_CLS_SRAM_H 0xe004 #define S_MACPARITY1 9 @@ -16062,6 +24490,7 @@ #define V_PORTMAP(x) ((x) << S_PORTMAP) #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP) +#define A_MPS_T5_CLS_SRAM_H 0xe004 #define A_MPS_CLS_TCAM_Y_L 0xf000 #define A_MPS_CLS_TCAM_Y_H 0xf004 @@ -16157,6 +24586,16 @@ #define V_ALLOC(x) ((x) << S_ALLOC) #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC) +#define S_T5_USED 16 +#define M_T5_USED 0xfffU +#define V_T5_USED(x) ((x) << S_T5_USED) +#define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED) + +#define S_T5_ALLOC 0 +#define M_T5_ALLOC 0xfffU +#define V_T5_ALLOC(x) ((x) << S_T5_ALLOC) +#define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC) + #define A_MPS_RX_PG_RSV1 0x11014 #define A_MPS_RX_PG_RSV2 0x11018 #define A_MPS_RX_PG_RSV3 0x1101c @@ -16184,6 +24623,16 @@ #define V_BORW(x) ((x) << S_BORW) #define G_BORW(x) (((x) >> S_BORW) & M_BORW) +#define S_T5_MAX 16 +#define M_T5_MAX 0xfffU +#define V_T5_MAX(x) ((x) << S_T5_MAX) +#define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX) + +#define S_T5_BORW 0 +#define M_T5_BORW 0xfffU +#define V_T5_BORW(x) ((x) << S_T5_BORW) +#define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW) + #define A_MPS_RX_PG_SHR_BG1 0x11034 #define A_MPS_RX_PG_SHR_BG2 0x11038 #define A_MPS_RX_PG_SHR_BG3 0x1103c @@ -16199,6 +24648,16 @@ #define V_SHR_USED(x) ((x) << S_SHR_USED) #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED) +#define S_T5_QUOTA 16 +#define M_T5_QUOTA 0xfffU +#define V_T5_QUOTA(x) ((x) << S_T5_QUOTA) +#define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA) + +#define S_T5_SHR_USED 0 +#define M_T5_SHR_USED 0xfffU +#define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED) +#define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED) + #define A_MPS_RX_PG_SHR1 0x11044 #define A_MPS_RX_PG_HYST_BG0 0x11048 @@ -16207,6 +24666,11 @@ #define V_TH(x) ((x) << S_TH) #define G_TH(x) (((x) >> S_TH) & M_TH) +#define S_T5_TH 0 +#define M_T5_TH 0xfffU +#define V_T5_TH(x) ((x) << S_T5_TH) +#define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH) + #define A_MPS_RX_PG_HYST_BG1 0x1104c #define A_MPS_RX_PG_HYST_BG2 0x11050 #define A_MPS_RX_PG_HYST_BG3 0x11054 @@ -16395,6 +24859,34 @@ #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0) #define F_PG_TH_INT0 V_PG_TH_INT0(1U) +#define S_MTU_ERR_INT3 19 +#define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3) +#define F_MTU_ERR_INT3 V_MTU_ERR_INT3(1U) + +#define S_MTU_ERR_INT2 18 +#define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2) +#define F_MTU_ERR_INT2 V_MTU_ERR_INT2(1U) + +#define S_MTU_ERR_INT1 17 +#define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1) +#define F_MTU_ERR_INT1 V_MTU_ERR_INT1(1U) + +#define S_MTU_ERR_INT0 16 +#define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0) +#define F_MTU_ERR_INT0 V_MTU_ERR_INT0(1U) + +#define S_SE_CNT_ERR_INT 15 +#define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT) +#define F_SE_CNT_ERR_INT V_SE_CNT_ERR_INT(1U) + +#define S_FRM_ERR_INT 14 +#define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT) +#define F_FRM_ERR_INT V_FRM_ERR_INT(1U) + +#define S_LEN_ERR_INT 13 +#define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT) +#define F_LEN_ERR_INT V_LEN_ERR_INT(1U) + #define A_MPS_RX_FUNC_INT_ENABLE 0x11088 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c @@ -16752,6 +25244,123 @@ #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3) #define A_MPS_RX_SPARE 0x11190 +#define A_MPS_RX_PTP_ETYPE 0x11194 + +#define S_PETYPE2 16 +#define M_PETYPE2 0xffffU +#define V_PETYPE2(x) ((x) << S_PETYPE2) +#define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2) + +#define S_PETYPE1 0 +#define M_PETYPE1 0xffffU +#define V_PETYPE1(x) ((x) << S_PETYPE1) +#define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1) + +#define A_MPS_RX_PTP_TCP 0x11198 + +#define S_PTCPORT2 16 +#define M_PTCPORT2 0xffffU +#define V_PTCPORT2(x) ((x) << S_PTCPORT2) +#define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2) + +#define S_PTCPORT1 0 +#define M_PTCPORT1 0xffffU +#define V_PTCPORT1(x) ((x) << S_PTCPORT1) +#define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1) + +#define A_MPS_RX_PTP_UDP 0x1119c + +#define S_PUDPORT2 16 +#define M_PUDPORT2 0xffffU +#define V_PUDPORT2(x) ((x) << S_PUDPORT2) +#define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2) + +#define S_PUDPORT1 0 +#define M_PUDPORT1 0xffffU +#define V_PUDPORT1(x) ((x) << S_PUDPORT1) +#define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1) + +#define A_MPS_RX_PTP_CTL 0x111a0 + +#define S_MIN_PTP_SPACE 24 +#define M_MIN_PTP_SPACE 0x7fU +#define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE) +#define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE) + +#define S_PUDP2EN 20 +#define M_PUDP2EN 0xfU +#define V_PUDP2EN(x) ((x) << S_PUDP2EN) +#define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN) + +#define S_PUDP1EN 16 +#define M_PUDP1EN 0xfU +#define V_PUDP1EN(x) ((x) << S_PUDP1EN) +#define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN) + +#define S_PTCP2EN 12 +#define M_PTCP2EN 0xfU +#define V_PTCP2EN(x) ((x) << S_PTCP2EN) +#define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN) + +#define S_PTCP1EN 8 +#define M_PTCP1EN 0xfU +#define V_PTCP1EN(x) ((x) << S_PTCP1EN) +#define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN) + +#define S_PETYPE2EN 4 +#define M_PETYPE2EN 0xfU +#define V_PETYPE2EN(x) ((x) << S_PETYPE2EN) +#define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN) + +#define S_PETYPE1EN 0 +#define M_PETYPE1EN 0xfU +#define V_PETYPE1EN(x) ((x) << S_PETYPE1EN) +#define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN) + +#define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4 +#define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8 +#define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac +#define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0 +#define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4 +#define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8 +#define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc +#define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0 +#define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4 +#define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8 +#define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc +#define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0 +#define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4 +#define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8 +#define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc +#define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0 +#define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4 +#define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8 +#define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec +#define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0 +#define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4 +#define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8 +#define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc +#define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200 +#define A_MPS_RX_CGEN 0x11204 + +#define S_MPS_RX_CGEN_NCSI 12 +#define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI) +#define F_MPS_RX_CGEN_NCSI V_MPS_RX_CGEN_NCSI(1U) + +#define S_MPS_RX_CGEN_OUT 8 +#define M_MPS_RX_CGEN_OUT 0xfU +#define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT) +#define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT) + +#define S_MPS_RX_CGEN_LPBK_IN 4 +#define M_MPS_RX_CGEN_LPBK_IN 0xfU +#define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN) +#define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN) + +#define S_MPS_RX_CGEN_MAC_IN 0 +#define M_MPS_RX_CGEN_MAC_IN 0xfU +#define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN) +#define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN) /* registers for module CPL_SWITCH */ #define CPL_SWITCH_BASE_ADDR 0x19040 @@ -16787,6 +25396,10 @@ #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE) #define F_CIM_ENABLE V_CIM_ENABLE(1U) +#define S_CIM_SPLIT_ENABLE 6 +#define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE) +#define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U) + #define A_CPL_SWITCH_TBL_IDX 0x19044 #define S_SWITCH_TBL_IDX 0 @@ -16833,6 +25446,14 @@ #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) +#define S_PERR_CPL_128TO128_1 7 +#define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1) +#define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U) + +#define S_PERR_CPL_128TO128_0 6 +#define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0) +#define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U) + #define A_CPL_INTR_CAUSE 0x19054 #define A_CPL_MAP_TBL_IDX 0x19058 @@ -16841,6 +25462,10 @@ #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX) #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX) +#define S_CIM_SPLIT_OPCODE_PROGRAM 8 +#define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM) +#define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U) + #define A_CPL_MAP_TBL_DATA 0x1905c #define S_MAP_TBL_DATA 0 @@ -17194,6 +25819,18 @@ #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN) #define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U) +#define S_MSTTXFIFO 21 +#define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO) +#define F_MSTTXFIFO V_MSTTXFIFO(1U) + +#define S_MSTRXFIFO 19 +#define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO) +#define F_MSTRXFIFO V_MSTRXFIFO(1U) + +#define S_SLVFIFO 18 +#define V_SLVFIFO(x) ((x) << S_SLVFIFO) +#define F_SLVFIFO V_SLVFIFO(1U) + #define A_SMB_PERR_INJ 0x1909c #define S_MSTTXINJDATAERR 3 @@ -17381,6 +26018,20 @@ #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG) #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG) +#define A_SMB_CTL_STATUS 0x190e8 + +#define S_MSTBUSBUSY 2 +#define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY) +#define F_MSTBUSBUSY V_MSTBUSBUSY(1U) + +#define S_SLVBUSBUSY 1 +#define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY) +#define F_SLVBUSBUSY V_SLVBUSBUSY(1U) + +#define S_BUSBUSY 0 +#define V_BUSBUSY(x) ((x) << S_BUSBUSY) +#define F_BUSBUSY V_BUSBUSY(1U) + /* registers for module I2CM */ #define I2CM_BASE_ADDR 0x190f0 @@ -17391,6 +26042,11 @@ #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV) +#define S_I2C_CLKDIV16B 0 +#define M_I2C_CLKDIV16B 0xffffU +#define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B) +#define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B) + #define A_I2CM_DATA 0x190f4 #define S_I2C_DATA 0 @@ -17536,6 +26192,46 @@ #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE) #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE) +#define S_SGE_PART_CGEN 19 +#define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN) +#define F_SGE_PART_CGEN V_SGE_PART_CGEN(1U) + +#define S_PDP_PART_CGEN 18 +#define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN) +#define F_PDP_PART_CGEN V_PDP_PART_CGEN(1U) + +#define S_TP_PART_CGEN 17 +#define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN) +#define F_TP_PART_CGEN V_TP_PART_CGEN(1U) + +#define S_EDC0_PART_CGEN 16 +#define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN) +#define F_EDC0_PART_CGEN V_EDC0_PART_CGEN(1U) + +#define S_EDC1_PART_CGEN 15 +#define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN) +#define F_EDC1_PART_CGEN V_EDC1_PART_CGEN(1U) + +#define S_LE_PART_CGEN 14 +#define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN) +#define F_LE_PART_CGEN V_LE_PART_CGEN(1U) + +#define S_MA_PART_CGEN 13 +#define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN) +#define F_MA_PART_CGEN V_MA_PART_CGEN(1U) + +#define S_MC0_PART_CGEN 12 +#define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN) +#define F_MC0_PART_CGEN V_MC0_PART_CGEN(1U) + +#define S_MC1_PART_CGEN 11 +#define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN) +#define F_MC1_PART_CGEN V_MC1_PART_CGEN(1U) + +#define S_PCIE_PART_CGEN 10 +#define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN) +#define F_PCIE_PART_CGEN V_PCIE_PART_CGEN(1U) + #define A_PMU_SLEEPMODE_WAKEUP 0x19124 #define S_HWWAKEUPEN 5 @@ -17562,6 +26258,10 @@ #define V_WAKEUP(x) ((x) << S_WAKEUP) #define F_WAKEUP V_WAKEUP(1U) +#define S_GLOBALDEEPSLEEPEN 6 +#define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN) +#define F_GLOBALDEEPSLEEPEN V_GLOBALDEEPSLEEPEN(1U) + /* registers for module ULP_RX */ #define ULP_RX_BASE_ADDR 0x19150 @@ -17656,78 +26356,86 @@ #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0) #define F_ENABLE_AF_0 V_ENABLE_AF_0(1U) -#define S_ENABLE_PCMDF_1 17 -#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1) -#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U) - -#define S_ENABLE_MPARC_1 16 -#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1) -#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U) - -#define S_ENABLE_MPARF_1 15 -#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1) -#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U) - -#define S_ENABLE_DDPCF_1 14 -#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1) -#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U) - -#define S_ENABLE_TPTCF_1 13 -#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1) -#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U) - -#define S_ENABLE_PCMDF_0 12 -#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0) -#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U) - -#define S_ENABLE_MPARC_0 11 -#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0) -#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U) - -#define S_ENABLE_MPARF_0 10 -#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0) -#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U) - -#define S_ENABLE_DDPCF_0 9 -#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0) -#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U) - -#define S_ENABLE_TPTCF_0 8 -#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0) -#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U) - -#define S_ENABLE_DDPDF_1 7 +#define S_ENABLE_DDPDF_1 17 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1) #define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U) -#define S_ENABLE_DDPMF_1 6 +#define S_ENABLE_DDPMF_1 16 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1) #define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U) -#define S_ENABLE_MEMRF_1 5 +#define S_ENABLE_MEMRF_1 15 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1) #define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U) -#define S_ENABLE_PRSDF_1 4 +#define S_ENABLE_PRSDF_1 14 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1) #define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U) -#define S_ENABLE_DDPDF_0 3 +#define S_ENABLE_DDPDF_0 13 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0) #define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U) -#define S_ENABLE_DDPMF_0 2 +#define S_ENABLE_DDPMF_0 12 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0) #define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U) -#define S_ENABLE_MEMRF_0 1 +#define S_ENABLE_MEMRF_0 11 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0) #define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U) -#define S_ENABLE_PRSDF_0 0 +#define S_ENABLE_PRSDF_0 10 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0) #define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U) +#define S_ENABLE_PCMDF_1 9 +#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1) +#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U) + +#define S_ENABLE_TPTCF_1 8 +#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1) +#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U) + +#define S_ENABLE_DDPCF_1 7 +#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1) +#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U) + +#define S_ENABLE_MPARF_1 6 +#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1) +#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U) + +#define S_ENABLE_MPARC_1 5 +#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1) +#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U) + +#define S_ENABLE_PCMDF_0 4 +#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0) +#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U) + +#define S_ENABLE_TPTCF_0 3 +#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0) +#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U) + +#define S_ENABLE_DDPCF_0 2 +#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0) +#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U) + +#define S_ENABLE_MPARF_0 1 +#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0) +#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U) + +#define S_ENABLE_MPARC_0 0 +#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0) +#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U) + +#define S_SE_CNT_MISMATCH_1 26 +#define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1) +#define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U) + +#define S_SE_CNT_MISMATCH_0 25 +#define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0) +#define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U) + #define A_ULP_RX_INT_CAUSE 0x19158 #define S_CAUSE_CTX_1 24 @@ -17758,78 +26466,78 @@ #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0) #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U) -#define S_CAUSE_PCMDF_1 17 -#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1) -#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U) - -#define S_CAUSE_MPARC_1 16 -#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1) -#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U) - -#define S_CAUSE_MPARF_1 15 -#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1) -#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U) - -#define S_CAUSE_DDPCF_1 14 -#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1) -#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U) - -#define S_CAUSE_TPTCF_1 13 -#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1) -#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U) - -#define S_CAUSE_PCMDF_0 12 -#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0) -#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U) - -#define S_CAUSE_MPARC_0 11 -#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0) -#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U) - -#define S_CAUSE_MPARF_0 10 -#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0) -#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U) - -#define S_CAUSE_DDPCF_0 9 -#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0) -#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U) - -#define S_CAUSE_TPTCF_0 8 -#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0) -#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U) - -#define S_CAUSE_DDPDF_1 7 +#define S_CAUSE_DDPDF_1 17 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1) #define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U) -#define S_CAUSE_DDPMF_1 6 +#define S_CAUSE_DDPMF_1 16 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1) #define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U) -#define S_CAUSE_MEMRF_1 5 +#define S_CAUSE_MEMRF_1 15 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1) #define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U) -#define S_CAUSE_PRSDF_1 4 +#define S_CAUSE_PRSDF_1 14 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1) #define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U) -#define S_CAUSE_DDPDF_0 3 +#define S_CAUSE_DDPDF_0 13 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0) #define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U) -#define S_CAUSE_DDPMF_0 2 +#define S_CAUSE_DDPMF_0 12 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0) #define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U) -#define S_CAUSE_MEMRF_0 1 +#define S_CAUSE_MEMRF_0 11 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0) #define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U) -#define S_CAUSE_PRSDF_0 0 +#define S_CAUSE_PRSDF_0 10 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0) #define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U) +#define S_CAUSE_PCMDF_1 9 +#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1) +#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U) + +#define S_CAUSE_TPTCF_1 8 +#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1) +#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U) + +#define S_CAUSE_DDPCF_1 7 +#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1) +#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U) + +#define S_CAUSE_MPARF_1 6 +#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1) +#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U) + +#define S_CAUSE_MPARC_1 5 +#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1) +#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U) + +#define S_CAUSE_PCMDF_0 4 +#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0) +#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U) + +#define S_CAUSE_TPTCF_0 3 +#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0) +#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U) + +#define S_CAUSE_DDPCF_0 2 +#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0) +#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U) + +#define S_CAUSE_MPARF_0 1 +#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0) +#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U) + +#define S_CAUSE_MPARC_0 0 +#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0) +#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U) + #define A_ULP_RX_ISCSI_LLIMIT 0x1915c #define S_ISCSILLIMIT 6 @@ -17903,6 +26611,115 @@ #define A_ULP_RX_PBL_ULIMIT 0x19190 #define A_ULP_RX_CTX_BASE 0x19194 #define A_ULP_RX_PERR_ENABLE 0x1919c + +#define S_PERR_ENABLE_FF 22 +#define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF) +#define F_PERR_ENABLE_FF V_PERR_ENABLE_FF(1U) + +#define S_PERR_ENABLE_APF_1 21 +#define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1) +#define F_PERR_ENABLE_APF_1 V_PERR_ENABLE_APF_1(1U) + +#define S_PERR_ENABLE_APF_0 20 +#define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0) +#define F_PERR_ENABLE_APF_0 V_PERR_ENABLE_APF_0(1U) + +#define S_PERR_ENABLE_AF_1 19 +#define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1) +#define F_PERR_ENABLE_AF_1 V_PERR_ENABLE_AF_1(1U) + +#define S_PERR_ENABLE_AF_0 18 +#define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0) +#define F_PERR_ENABLE_AF_0 V_PERR_ENABLE_AF_0(1U) + +#define S_PERR_ENABLE_DDPDF_1 17 +#define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1) +#define F_PERR_ENABLE_DDPDF_1 V_PERR_ENABLE_DDPDF_1(1U) + +#define S_PERR_ENABLE_DDPMF_1 16 +#define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1) +#define F_PERR_ENABLE_DDPMF_1 V_PERR_ENABLE_DDPMF_1(1U) + +#define S_PERR_ENABLE_MEMRF_1 15 +#define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1) +#define F_PERR_ENABLE_MEMRF_1 V_PERR_ENABLE_MEMRF_1(1U) + +#define S_PERR_ENABLE_PRSDF_1 14 +#define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1) +#define F_PERR_ENABLE_PRSDF_1 V_PERR_ENABLE_PRSDF_1(1U) + +#define S_PERR_ENABLE_DDPDF_0 13 +#define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0) +#define F_PERR_ENABLE_DDPDF_0 V_PERR_ENABLE_DDPDF_0(1U) + +#define S_PERR_ENABLE_DDPMF_0 12 +#define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0) +#define F_PERR_ENABLE_DDPMF_0 V_PERR_ENABLE_DDPMF_0(1U) + +#define S_PERR_ENABLE_MEMRF_0 11 +#define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0) +#define F_PERR_ENABLE_MEMRF_0 V_PERR_ENABLE_MEMRF_0(1U) + +#define S_PERR_ENABLE_PRSDF_0 10 +#define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0) +#define F_PERR_ENABLE_PRSDF_0 V_PERR_ENABLE_PRSDF_0(1U) + +#define S_PERR_ENABLE_PCMDF_1 9 +#define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1) +#define F_PERR_ENABLE_PCMDF_1 V_PERR_ENABLE_PCMDF_1(1U) + +#define S_PERR_ENABLE_TPTCF_1 8 +#define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1) +#define F_PERR_ENABLE_TPTCF_1 V_PERR_ENABLE_TPTCF_1(1U) + +#define S_PERR_ENABLE_DDPCF_1 7 +#define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1) +#define F_PERR_ENABLE_DDPCF_1 V_PERR_ENABLE_DDPCF_1(1U) + +#define S_PERR_ENABLE_MPARF_1 6 +#define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1) +#define F_PERR_ENABLE_MPARF_1 V_PERR_ENABLE_MPARF_1(1U) + +#define S_PERR_ENABLE_MPARC_1 5 +#define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1) +#define F_PERR_ENABLE_MPARC_1 V_PERR_ENABLE_MPARC_1(1U) + +#define S_PERR_ENABLE_PCMDF_0 4 +#define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0) +#define F_PERR_ENABLE_PCMDF_0 V_PERR_ENABLE_PCMDF_0(1U) + +#define S_PERR_ENABLE_TPTCF_0 3 +#define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0) +#define F_PERR_ENABLE_TPTCF_0 V_PERR_ENABLE_TPTCF_0(1U) + +#define S_PERR_ENABLE_DDPCF_0 2 +#define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0) +#define F_PERR_ENABLE_DDPCF_0 V_PERR_ENABLE_DDPCF_0(1U) + +#define S_PERR_ENABLE_MPARF_0 1 +#define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0) +#define F_PERR_ENABLE_MPARF_0 V_PERR_ENABLE_MPARF_0(1U) + +#define S_PERR_ENABLE_MPARC_0 0 +#define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0) +#define F_PERR_ENABLE_MPARC_0 V_PERR_ENABLE_MPARC_0(1U) + +#define S_PERR_SE_CNT_MISMATCH_1 26 +#define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1) +#define F_PERR_SE_CNT_MISMATCH_1 V_PERR_SE_CNT_MISMATCH_1(1U) + +#define S_PERR_SE_CNT_MISMATCH_0 25 +#define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0) +#define F_PERR_SE_CNT_MISMATCH_0 V_PERR_SE_CNT_MISMATCH_0(1U) + +#define S_PERR_RSVD0 24 +#define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0) +#define F_PERR_RSVD0 V_PERR_RSVD0(1U) + +#define S_PERR_RSVD1 23 +#define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1) +#define F_PERR_RSVD1 V_PERR_RSVD1(1U) + #define A_ULP_RX_PERR_INJECT 0x191a0 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8 @@ -18069,6 +26886,262 @@ #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR) #define A_ULP_RX_LA_RESERVED 0x1924c +#define A_ULP_RX_CQE_GEN_EN 0x19250 + +#define S_TERMIMATE_MSG 1 +#define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG) +#define F_TERMIMATE_MSG V_TERMIMATE_MSG(1U) + +#define S_TERMINATE_WITH_ERR 0 +#define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR) +#define F_TERMINATE_WITH_ERR V_TERMINATE_WITH_ERR(1U) + +#define A_ULP_RX_ATOMIC_OPCODES 0x19254 + +#define S_ATOMIC_REQ_QNO 22 +#define M_ATOMIC_REQ_QNO 0x3U +#define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO) +#define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO) + +#define S_ATOMIC_RSP_QNO 20 +#define M_ATOMIC_RSP_QNO 0x3U +#define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO) +#define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO) + +#define S_IMMEDIATE_QNO 18 +#define M_IMMEDIATE_QNO 0x3U +#define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO) +#define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO) + +#define S_IMMEDIATE_WITH_SE_QNO 16 +#define M_IMMEDIATE_WITH_SE_QNO 0x3U +#define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO) +#define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO) + +#define S_ATOMIC_WR_OPCODE 12 +#define M_ATOMIC_WR_OPCODE 0xfU +#define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE) +#define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE) + +#define S_ATOMIC_RD_OPCODE 8 +#define M_ATOMIC_RD_OPCODE 0xfU +#define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE) +#define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE) + +#define S_IMMEDIATE_OPCODE 4 +#define M_IMMEDIATE_OPCODE 0xfU +#define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE) +#define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE) + +#define S_IMMEDIATE_WITH_SE_OPCODE 0 +#define M_IMMEDIATE_WITH_SE_OPCODE 0xfU +#define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE) +#define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE) + +#define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258 + +#define S_EN_ORIG_DATA 0 +#define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA) +#define F_EN_ORIG_DATA V_EN_ORIG_DATA(1U) + +#define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c + +#define S_TERMINATE_STATUS_EN 4 +#define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN) +#define F_TERMINATE_STATUS_EN V_TERMINATE_STATUS_EN(1U) + +#define S_MULTIPLE_PREF_ENABLE 3 +#define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE) +#define F_MULTIPLE_PREF_ENABLE V_MULTIPLE_PREF_ENABLE(1U) + +#define S_UMUDP_PBL_PREF_ENABLE 2 +#define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE) +#define F_UMUDP_PBL_PREF_ENABLE V_UMUDP_PBL_PREF_ENABLE(1U) + +#define S_RDMA_PBL_PREF_EN 1 +#define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN) +#define F_RDMA_PBL_PREF_EN V_RDMA_PBL_PREF_EN(1U) + +#define S_SDC_CRC_PROT_EN 0 +#define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN) +#define F_SDC_CRC_PROT_EN V_SDC_CRC_PROT_EN(1U) + +#define A_ULP_RX_CH0_CGEN 0x19260 + +#define S_BYPASS_CGEN 7 +#define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN) +#define F_BYPASS_CGEN V_BYPASS_CGEN(1U) + +#define S_TDDP_CGEN 6 +#define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN) +#define F_TDDP_CGEN V_TDDP_CGEN(1U) + +#define S_ISCSI_CGEN 5 +#define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN) +#define F_ISCSI_CGEN V_ISCSI_CGEN(1U) + +#define S_RDMA_CGEN 4 +#define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN) +#define F_RDMA_CGEN V_RDMA_CGEN(1U) + +#define S_CHANNEL_CGEN 3 +#define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN) +#define F_CHANNEL_CGEN V_CHANNEL_CGEN(1U) + +#define S_ALL_DATAPATH_CGEN 2 +#define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN) +#define F_ALL_DATAPATH_CGEN V_ALL_DATAPATH_CGEN(1U) + +#define S_T10DIFF_DATAPATH_CGEN 1 +#define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN) +#define F_T10DIFF_DATAPATH_CGEN V_T10DIFF_DATAPATH_CGEN(1U) + +#define S_RDMA_DATAPATH_CGEN 0 +#define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN) +#define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U) + +#define A_ULP_RX_CH1_CGEN 0x19264 +#define A_ULP_RX_RFE_DISABLE 0x19268 + +#define S_RQE_LIM_CHECK_RFE_DISABLE 0 +#define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE) +#define F_RQE_LIM_CHECK_RFE_DISABLE V_RQE_LIM_CHECK_RFE_DISABLE(1U) + +#define A_ULP_RX_INT_ENABLE_2 0x1926c + +#define S_ULPRX2MA_INTFPERR 8 +#define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR) +#define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U) + +#define S_ALN_SDC_ERR_1 7 +#define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1) +#define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U) + +#define S_ALN_SDC_ERR_0 6 +#define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0) +#define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U) + +#define S_PF_UNTAGGED_TPT_1 5 +#define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1) +#define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U) + +#define S_PF_UNTAGGED_TPT_0 4 +#define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0) +#define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U) + +#define S_PF_PBL_1 3 +#define V_PF_PBL_1(x) ((x) << S_PF_PBL_1) +#define F_PF_PBL_1 V_PF_PBL_1(1U) + +#define S_PF_PBL_0 2 +#define V_PF_PBL_0(x) ((x) << S_PF_PBL_0) +#define F_PF_PBL_0 V_PF_PBL_0(1U) + +#define S_DDP_HINT_1 1 +#define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1) +#define F_DDP_HINT_1 V_DDP_HINT_1(1U) + +#define S_DDP_HINT_0 0 +#define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0) +#define F_DDP_HINT_0 V_DDP_HINT_0(1U) + +#define A_ULP_RX_INT_CAUSE_2 0x19270 +#define A_ULP_RX_PERR_ENABLE_2 0x19274 + +#define S_ENABLE_ULPRX2MA_INTFPERR 8 +#define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR) +#define F_ENABLE_ULPRX2MA_INTFPERR V_ENABLE_ULPRX2MA_INTFPERR(1U) + +#define S_ENABLE_ALN_SDC_ERR_1 7 +#define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1) +#define F_ENABLE_ALN_SDC_ERR_1 V_ENABLE_ALN_SDC_ERR_1(1U) + +#define S_ENABLE_ALN_SDC_ERR_0 6 +#define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0) +#define F_ENABLE_ALN_SDC_ERR_0 V_ENABLE_ALN_SDC_ERR_0(1U) + +#define S_ENABLE_PF_UNTAGGED_TPT_1 5 +#define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1) +#define F_ENABLE_PF_UNTAGGED_TPT_1 V_ENABLE_PF_UNTAGGED_TPT_1(1U) + +#define S_ENABLE_PF_UNTAGGED_TPT_0 4 +#define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0) +#define F_ENABLE_PF_UNTAGGED_TPT_0 V_ENABLE_PF_UNTAGGED_TPT_0(1U) + +#define S_ENABLE_PF_PBL_1 3 +#define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1) +#define F_ENABLE_PF_PBL_1 V_ENABLE_PF_PBL_1(1U) + +#define S_ENABLE_PF_PBL_0 2 +#define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0) +#define F_ENABLE_PF_PBL_0 V_ENABLE_PF_PBL_0(1U) + +#define S_ENABLE_DDP_HINT_1 1 +#define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1) +#define F_ENABLE_DDP_HINT_1 V_ENABLE_DDP_HINT_1(1U) + +#define S_ENABLE_DDP_HINT_0 0 +#define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0) +#define F_ENABLE_DDP_HINT_0 V_ENABLE_DDP_HINT_0(1U) + +#define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278 + +#define S_PIO_RQE_PBL_MULTIPLE_CNT 0 +#define M_PIO_RQE_PBL_MULTIPLE_CNT 0xfU +#define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT) +#define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT) + +#define A_ULP_RX_ATOMIC_LEN 0x1927c + +#define S_ATOMIC_RPL_LEN 16 +#define M_ATOMIC_RPL_LEN 0xffU +#define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN) +#define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN) + +#define S_ATOMIC_REQ_LEN 8 +#define M_ATOMIC_REQ_LEN 0xffU +#define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN) +#define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN) + +#define S_ATOMIC_IMMEDIATE_LEN 0 +#define M_ATOMIC_IMMEDIATE_LEN 0xffU +#define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN) +#define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN) + +#define A_ULP_RX_CGEN_GLOBAL 0x19280 +#define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284 + +#define S_CLEAR_CTX_ERR_CNT1 3 +#define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1) +#define F_CLEAR_CTX_ERR_CNT1 V_CLEAR_CTX_ERR_CNT1(1U) + +#define S_CLEAR_CTX_ERR_CNT0 2 +#define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0) +#define F_CLEAR_CTX_ERR_CNT0 V_CLEAR_CTX_ERR_CNT0(1U) + +#define S_SKIP_MA_REQ_EN1 1 +#define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1) +#define F_SKIP_MA_REQ_EN1 V_SKIP_MA_REQ_EN1(1U) + +#define S_SKIP_MA_REQ_EN0 0 +#define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0) +#define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U) + +#define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288 +#define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c +#define A_ULP_RX_MSN_CHECK_ENABLE 0x19290 + +#define S_RD_OR_TERM_MSN_CHECK_ENABLE 2 +#define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE) +#define F_RD_OR_TERM_MSN_CHECK_ENABLE V_RD_OR_TERM_MSN_CHECK_ENABLE(1U) + +#define S_ATOMIC_OP_MSN_CHECK_ENABLE 1 +#define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE) +#define F_ATOMIC_OP_MSN_CHECK_ENABLE V_ATOMIC_OP_MSN_CHECK_ENABLE(1U) + +#define S_SEND_MSN_CHECK_ENABLE 0 +#define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE) +#define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U) /* registers for module SF */ #define SF_BASE_ADDR 0x193f8 @@ -18118,6 +27191,14 @@ #define V_VFID(x) ((x) << S_VFID) #define G_VFID(x) (((x) >> S_VFID) & M_VFID) +#define A_PL_VF_REV 0x4 + +#define S_CHIPID 4 +#define M_CHIPID 0xfU +#define V_CHIPID(x) ((x) << S_CHIPID) +#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) + +#define A_PL_VF_REVISION 0x8 #define A_PL_PF_INT_CAUSE 0x3c0 #define S_PFSW 3 @@ -18262,6 +27343,18 @@ #define V_CIM(x) ((x) << S_CIM) #define F_CIM V_CIM(1U) +#define S_MC1 31 +#define V_MC1(x) ((x) << S_MC1) +#define F_MC1 V_MC1(1U) + +#define S_MC0 15 +#define V_MC0(x) ((x) << S_MC0) +#define F_MC0 V_MC0(1U) + +#define S_ANYMAC 9 +#define V_ANYMAC(x) ((x) << S_ANYMAC) +#define F_ANYMAC V_ANYMAC(1U) + #define A_PL_PERR_ENABLE 0x19408 #define A_PL_INT_CAUSE 0x1940c @@ -18273,6 +27366,22 @@ #define V_SW_CIM(x) ((x) << S_SW_CIM) #define F_SW_CIM V_SW_CIM(1U) +#define S_MAC3 12 +#define V_MAC3(x) ((x) << S_MAC3) +#define F_MAC3 V_MAC3(1U) + +#define S_MAC2 11 +#define V_MAC2(x) ((x) << S_MAC2) +#define F_MAC2 V_MAC2(1U) + +#define S_MAC1 10 +#define V_MAC1(x) ((x) << S_MAC1) +#define F_MAC1 V_MAC1(1U) + +#define S_MAC0 9 +#define V_MAC0(x) ((x) << S_MAC0) +#define F_MAC0 V_MAC0(1U) + #define A_PL_INT_ENABLE 0x19410 #define A_PL_INT_MAP0 0x19414 @@ -18298,6 +27407,16 @@ #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0) #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0) +#define S_MAPMAC1 16 +#define M_MAPMAC1 0x1ffU +#define V_MAPMAC1(x) ((x) << S_MAPMAC1) +#define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1) + +#define S_MAPMAC0 0 +#define M_MAPMAC0 0x1ffU +#define V_MAPMAC0(x) ((x) << S_MAPMAC0) +#define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0) + #define A_PL_INT_MAP2 0x1941c #define S_MAPXGMAC_KR1 16 @@ -18310,6 +27429,16 @@ #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0) #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0) +#define S_MAPMAC3 16 +#define M_MAPMAC3 0x1ffU +#define V_MAPMAC3(x) ((x) << S_MAPMAC3) +#define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3) + +#define S_MAPMAC2 0 +#define M_MAPMAC2 0x1ffU +#define V_MAPMAC2(x) ((x) << S_MAPMAC2) +#define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2) + #define A_PL_INT_MAP3 0x19420 #define S_MAPMI 16 @@ -18352,6 +27481,10 @@ #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE) #define F_PIORSTMODE V_PIORSTMODE(1U) +#define S_AUTOPCIEPAUSE 4 +#define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE) +#define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U) + #define A_PL_PL_PERR_INJECT 0x1942c #define S_PL_MEMSEL 1 @@ -18384,6 +27517,10 @@ #define V_PERRVFID(x) ((x) << S_PERRVFID) #define F_PERRVFID V_PERRVFID(1U) +#define S_PL_BUSPERR 6 +#define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR) +#define F_PL_BUSPERR V_PL_BUSPERR(1U) + #define A_PL_PL_INT_ENABLE 0x19434 #define A_PL_PL_PERR_ENABLE 0x19438 #define A_PL_REV 0x1943c @@ -18393,6 +27530,40 @@ #define V_REV(x) ((x) << S_REV) #define G_REV(x) (((x) >> S_REV) & M_REV) +#define A_PL_PCIE_LINK 0x19440 + +#define S_LN0_AESTAT 26 +#define M_LN0_AESTAT 0x7U +#define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT) +#define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT) + +#define S_LN0_AECMD 23 +#define M_LN0_AECMD 0x7U +#define V_LN0_AECMD(x) ((x) << S_LN0_AECMD) +#define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD) + +#define S_PCIE_SPEED 8 +#define M_PCIE_SPEED 0x3U +#define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED) +#define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED) + +#define S_LTSSM 0 +#define M_LTSSM 0x3fU +#define V_LTSSM(x) ((x) << S_LTSSM) +#define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM) + +#define A_PL_PCIE_CTL_STAT 0x19444 + +#define S_PCIE_STATUS 16 +#define M_PCIE_STATUS 0xffffU +#define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS) +#define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS) + +#define S_PCIE_CONTROL 0 +#define M_PCIE_CONTROL 0xffffU +#define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL) +#define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL) + #define A_PL_SEMAPHORE_CTL 0x1944c #define S_LOCKSTATUS 16 @@ -18513,6 +27684,10 @@ #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT) #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT) +#define S_PERRCAPTURE 16 +#define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE) +#define F_PERRCAPTURE V_PERRCAPTURE(1U) + #define A_PL_TIMEOUT_STATUS0 0x194f4 #define S_PL_TOADDR 2 @@ -18549,6 +27724,15 @@ #define V_PL_TORID(x) ((x) << S_PL_TORID) #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID) +#define S_VALIDPERR 30 +#define V_VALIDPERR(x) ((x) << S_VALIDPERR) +#define F_VALIDPERR V_VALIDPERR(1U) + +#define S_PL_TOVFID 0 +#define M_PL_TOVFID 0xffU +#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID) +#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID) + #define A_PL_VFID_MAP 0x19800 #define S_VFID_VLD 7 @@ -18614,6 +27798,58 @@ #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS) #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U) +#define S_MASKCMDOLAPDIS 26 +#define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS) +#define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U) + +#define S_IPV4HASHSIZEEN 25 +#define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN) +#define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U) + +#define S_PROTOCOLMASKEN 24 +#define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN) +#define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U) + +#define S_TUPLESIZEEN 23 +#define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN) +#define F_TUPLESIZEEN V_TUPLESIZEEN(1U) + +#define S_SRVRSRAMEN 22 +#define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN) +#define F_SRVRSRAMEN V_SRVRSRAMEN(1U) + +#define S_ASBOTHSRCHENPR 19 +#define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR) +#define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U) + +#define S_POCLIPTID0 15 +#define V_POCLIPTID0(x) ((x) << S_POCLIPTID0) +#define F_POCLIPTID0 V_POCLIPTID0(1U) + +#define S_TCAMARBOFF 14 +#define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF) +#define F_TCAMARBOFF V_TCAMARBOFF(1U) + +#define S_ACCNTFULLEN 13 +#define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN) +#define F_ACCNTFULLEN V_ACCNTFULLEN(1U) + +#define S_FILTERRWNOCLIP 12 +#define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP) +#define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U) + +#define S_CRCHASH 10 +#define V_CRCHASH(x) ((x) << S_CRCHASH) +#define F_CRCHASH V_CRCHASH(1U) + +#define S_COMPTID 9 +#define V_COMPTID(x) ((x) << S_COMPTID) +#define F_COMPTID V_COMPTID(1U) + +#define S_SINGLETHREAD 6 +#define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD) +#define F_SINGLETHREAD V_SINGLETHREAD(1U) + #define A_LE_MISC 0x19c08 #define S_CMPUNVAIL 0 @@ -18621,6 +27857,38 @@ #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL) #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL) +#define S_SRAMDEEPSLEEP_STAT 11 +#define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT) +#define F_SRAMDEEPSLEEP_STAT V_SRAMDEEPSLEEP_STAT(1U) + +#define S_TCAMDEEPSLEEP1_STAT 10 +#define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT) +#define F_TCAMDEEPSLEEP1_STAT V_TCAMDEEPSLEEP1_STAT(1U) + +#define S_TCAMDEEPSLEEP0_STAT 9 +#define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT) +#define F_TCAMDEEPSLEEP0_STAT V_TCAMDEEPSLEEP0_STAT(1U) + +#define S_SRAMDEEPSLEEP 8 +#define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP) +#define F_SRAMDEEPSLEEP V_SRAMDEEPSLEEP(1U) + +#define S_TCAMDEEPSLEEP1 7 +#define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1) +#define F_TCAMDEEPSLEEP1 V_TCAMDEEPSLEEP1(1U) + +#define S_TCAMDEEPSLEEP0 6 +#define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0) +#define F_TCAMDEEPSLEEP0 V_TCAMDEEPSLEEP0(1U) + +#define S_SRVRAMCLKOFF 5 +#define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF) +#define F_SRVRAMCLKOFF V_SRVRAMCLKOFF(1U) + +#define S_HASHCLKOFF 4 +#define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF) +#define F_HASHCLKOFF V_HASHCLKOFF(1U) + #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10 #define S_RTINDX 7 @@ -18749,6 +28017,30 @@ #define V_SERVERHIT(x) ((x) << S_SERVERHIT) #define F_SERVERHIT V_SERVERHIT(1U) +#define S_ACTCNTIPV6TZERO 21 +#define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO) +#define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U) + +#define S_ACTCNTIPV4TZERO 20 +#define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO) +#define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U) + +#define S_ACTCNTIPV6ZERO 19 +#define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO) +#define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U) + +#define S_ACTCNTIPV4ZERO 18 +#define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO) +#define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U) + +#define S_MARSPPARERR 17 +#define V_MARSPPARERR(x) ((x) << S_MARSPPARERR) +#define F_MARSPPARERR V_MARSPPARERR(1U) + +#define S_VFPARERR 14 +#define V_VFPARERR(x) ((x) << S_VFPARERR) +#define F_VFPARERR V_VFPARERR(1U) + #define A_LE_DB_INT_CAUSE 0x19c3c #define A_LE_DB_INT_TID 0x19c40 @@ -18779,8 +28071,29 @@ #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD) #define A_LE_DB_MASK_IPV4 0x19c50 +#define A_LE_T5_DB_MASK_IPV4 0x19c50 +#define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94 +#define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98 +#define A_LE_ACT_CNT_THRSH 0x19c9c + +#define S_ACT_CNT_THRSH 0 +#define M_ACT_CNT_THRSH 0x1fffffU +#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH) +#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH) + #define A_LE_DB_MASK_IPV6 0x19ca0 #define A_LE_DB_REQ_RSP_CNT 0x19ce4 + +#define S_RSPCNTLE 16 +#define M_RSPCNTLE 0xffffU +#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE) +#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE) + +#define S_REQCNTLE 0 +#define M_REQCNTLE 0xffffU +#define V_REQCNTLE(x) ((x) << S_REQCNTLE) +#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE) + #define A_LE_DB_DBGI_CONFIG 0x19cf0 #define S_DBGICMDPERR 31 @@ -18860,6 +28173,22 @@ #define V_TCAM(x) ((x) << S_TCAM) #define F_TCAM V_TCAM(1U) +#define S_MARSPPARERRLE 17 +#define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE) +#define F_MARSPPARERRLE V_MARSPPARERRLE(1U) + +#define S_REQQUEUELE 16 +#define V_REQQUEUELE(x) ((x) << S_REQQUEUELE) +#define F_REQQUEUELE V_REQQUEUELE(1U) + +#define S_VFPARERRLE 14 +#define V_VFPARERRLE(x) ((x) << S_VFPARERRLE) +#define F_VFPARERRLE V_VFPARERRLE(1U) + +#define S_TCAMLE 6 +#define V_TCAMLE(x) ((x) << S_TCAMLE) +#define F_TCAMLE V_TCAMLE(1U) + #define A_LE_SPARE 0x19cfc #define A_LE_DB_DBGI_REQ_DATA 0x19d00 #define A_LE_DB_DBGI_REQ_MASK 0x19d50 @@ -18952,16 +28281,76 @@ #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL) #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00 +#define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0 +#define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0 +#define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0 +#define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0 +#define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8 #define A_LE_DEBUG_LA_CONFIG 0x19f20 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30 +#define A_LE_DEBUG_LA_SELECTOR 0x19f34 +#define A_LE_SRVR_SRAM_INIT 0x19f34 + +#define S_SRVRSRAMBASE 2 +#define M_SRVRSRAMBASE 0xfffffU +#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE) +#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE) + +#define S_SRVRINITBUSY 1 +#define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY) +#define F_SRVRINITBUSY V_SRVRINITBUSY(1U) + +#define S_SRVRINIT 0 +#define V_SRVRINIT(x) ((x) << S_SRVRINIT) +#define F_SRVRINIT V_SRVRINIT(1U) + +#define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38 +#define A_LE_SRVR_VF_SRCH_TABLE 0x19f38 + +#define S_RDWR 21 +#define V_RDWR(x) ((x) << S_RDWR) +#define F_RDWR V_RDWR(1U) + +#define S_VFINDEX 14 +#define M_VFINDEX 0x7fU +#define V_VFINDEX(x) ((x) << S_VFINDEX) +#define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX) + +#define S_SRCHHADDR 7 +#define M_SRCHHADDR 0x7fU +#define V_SRCHHADDR(x) ((x) << S_SRCHHADDR) +#define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR) + +#define S_SRCHLADDR 0 +#define M_SRCHLADDR 0x7fU +#define V_SRCHLADDR(x) ((x) << S_SRCHLADDR) +#define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR) + +#define A_LE_MA_DEBUG_LA_DATA 0x19f3c +#define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40 +#define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40 +#define A_LE_HASH_DEBUG_LA_DATA 0x19f44 +#define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48 +#define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c +#define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90 +#define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4 +#define A_LE_HASH_COLLISION 0x19fc4 +#define A_LE_GLOBAL_COLLISION 0x19fc8 +#define A_LE_FULL_CNT_COLLISION 0x19fcc +#define A_LE_DEBUG_LA_CONFIGT5 0x19fd0 +#define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4 +#define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8 +#define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc +#define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0 +#define A_LE_DEBUG_LA_SEL_DATA 0x19fe4 /* registers for module NCSI */ #define NCSI_BASE_ADDR 0x1a000 @@ -19304,12 +28693,26 @@ #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL) #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL) +#define S_TXFIFO_EMPTY 4 +#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY) +#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U) + +#define S_TXFIFO_FULL 3 +#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL) +#define F_TXFIFO_FULL V_TXFIFO_FULL(1U) + +#define S_PKG_ID 0 +#define M_PKG_ID 0x7U +#define V_PKG_ID(x) ((x) << S_PKG_ID) +#define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID) + #define A_NCSI_PERR_INJECT 0x1a0f4 #define S_MCSIMELSEL 1 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL) #define F_MCSIMELSEL V_MCSIMELSEL(1U) +#define A_NCSI_PERR_ENABLE 0x1a0f8 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100 #define S_TXSNDZEROPAUSE 12 @@ -23323,6 +32726,16 @@ #define V_OBQFULL(x) ((x) << S_OBQFULL) #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL) +#define S_T5_OBQGEN 8 +#define M_T5_OBQGEN 0xffffffU +#define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN) +#define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN) + +#define S_T5_OBQFULL 0 +#define M_T5_OBQFULL 0xffU +#define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL) +#define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL) + #define A_UP_IBQ_0_RDADDR 0x10 #define S_QUEID 13 @@ -23541,6 +32954,10 @@ #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN) #define F_UPDBGLAEN V_UPDBGLAEN(1U) +#define S_UPDBGLABUSY 14 +#define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY) +#define F_UPDBGLABUSY V_UPDBGLABUSY(1U) + #define A_UP_UP_DBG_LA_DATA 0x144 #define A_UP_PIO_MST_CONFIG 0x148 @@ -23572,6 +32989,15 @@ #define V_UPRID(x) ((x) << S_UPRID) #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID) +#define S_REQVFVLD 27 +#define V_REQVFVLD(x) ((x) << S_REQVFVLD) +#define F_REQVFVLD V_REQVFVLD(1U) + +#define S_T5_UPRID 0 +#define M_T5_UPRID 0xffU +#define V_T5_UPRID(x) ((x) << S_T5_UPRID) +#define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID) + #define A_UP_UP_SELF_CONTROL 0x14c #define S_UPSELFRESET 0 @@ -23587,6 +33013,20 @@ #define A_UP_MAILBOX_PF6_CTL 0x1e0 #define A_UP_MAILBOX_PF7_CTL 0x1f0 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200 + +#define S_ECO_15444_SGE_DB_BUSY 31 +#define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY) +#define F_ECO_15444_SGE_DB_BUSY V_ECO_15444_SGE_DB_BUSY(1U) + +#define S_ECO_15444_PL_INTF_BUSY 30 +#define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY) +#define F_ECO_15444_PL_INTF_BUSY V_ECO_15444_PL_INTF_BUSY(1U) + +#define S_TSCHCHNLCRDY 0 +#define M_TSCHCHNLCRDY 0x3fffffffU +#define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY) +#define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY) + #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204 #define S_TSCHWRRLIMIT 16 @@ -23631,6 +33071,90 @@ #define A_UP_UPLADBGPCCHKMASK_2 0x264 #define A_UP_UPLADBGPCCHKDATA_3 0x270 #define A_UP_UPLADBGPCCHKMASK_3 0x274 +#define A_UP_IBQ_0_SHADOW_RDADDR 0x280 +#define A_UP_IBQ_0_SHADOW_WRADDR 0x284 +#define A_UP_IBQ_0_SHADOW_STATUS 0x288 +#define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c +#define A_UP_IBQ_1_SHADOW_RDADDR 0x290 +#define A_UP_IBQ_1_SHADOW_WRADDR 0x294 +#define A_UP_IBQ_1_SHADOW_STATUS 0x298 +#define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c +#define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0 +#define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4 +#define A_UP_IBQ_2_SHADOW_STATUS 0x2a8 +#define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac +#define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0 +#define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4 +#define A_UP_IBQ_3_SHADOW_STATUS 0x2b8 +#define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc +#define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0 +#define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4 +#define A_UP_IBQ_4_SHADOW_STATUS 0x2c8 +#define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc +#define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0 +#define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4 +#define A_UP_IBQ_5_SHADOW_STATUS 0x2d8 +#define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc +#define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0 +#define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4 +#define A_UP_OBQ_0_SHADOW_STATUS 0x2e8 +#define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec +#define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0 +#define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4 +#define A_UP_OBQ_1_SHADOW_STATUS 0x2f8 +#define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc +#define A_UP_OBQ_2_SHADOW_RDADDR 0x300 +#define A_UP_OBQ_2_SHADOW_WRADDR 0x304 +#define A_UP_OBQ_2_SHADOW_STATUS 0x308 +#define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c +#define A_UP_OBQ_3_SHADOW_RDADDR 0x310 +#define A_UP_OBQ_3_SHADOW_WRADDR 0x314 +#define A_UP_OBQ_3_SHADOW_STATUS 0x318 +#define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c +#define A_UP_OBQ_4_SHADOW_RDADDR 0x320 +#define A_UP_OBQ_4_SHADOW_WRADDR 0x324 +#define A_UP_OBQ_4_SHADOW_STATUS 0x328 +#define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c +#define A_UP_OBQ_5_SHADOW_RDADDR 0x330 +#define A_UP_OBQ_5_SHADOW_WRADDR 0x334 +#define A_UP_OBQ_5_SHADOW_STATUS 0x338 +#define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c +#define A_UP_OBQ_6_SHADOW_RDADDR 0x340 +#define A_UP_OBQ_6_SHADOW_WRADDR 0x344 +#define A_UP_OBQ_6_SHADOW_STATUS 0x348 +#define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c +#define A_UP_OBQ_7_SHADOW_RDADDR 0x350 +#define A_UP_OBQ_7_SHADOW_WRADDR 0x354 +#define A_UP_OBQ_7_SHADOW_STATUS 0x358 +#define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c +#define A_UP_IBQ_0_SHADOW_CONFIG 0x360 +#define A_UP_IBQ_0_SHADOW_REALADDR 0x364 +#define A_UP_IBQ_1_SHADOW_CONFIG 0x368 +#define A_UP_IBQ_1_SHADOW_REALADDR 0x36c +#define A_UP_IBQ_2_SHADOW_CONFIG 0x370 +#define A_UP_IBQ_2_SHADOW_REALADDR 0x374 +#define A_UP_IBQ_3_SHADOW_CONFIG 0x378 +#define A_UP_IBQ_3_SHADOW_REALADDR 0x37c +#define A_UP_IBQ_4_SHADOW_CONFIG 0x380 +#define A_UP_IBQ_4_SHADOW_REALADDR 0x384 +#define A_UP_IBQ_5_SHADOW_CONFIG 0x388 +#define A_UP_IBQ_5_SHADOW_REALADDR 0x38c +#define A_UP_OBQ_0_SHADOW_CONFIG 0x390 +#define A_UP_OBQ_0_SHADOW_REALADDR 0x394 +#define A_UP_OBQ_1_SHADOW_CONFIG 0x398 +#define A_UP_OBQ_1_SHADOW_REALADDR 0x39c +#define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0 +#define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4 +#define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8 +#define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac +#define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0 +#define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4 +#define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8 +#define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc +#define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0 +#define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4 +#define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8 +#define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc /* registers for module CIM_CTL */ #define CIM_CTL_BASE_ADDR 0x0 @@ -23941,6 +33465,17 @@ #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT) #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT) +#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920 + +#define S_TSCCLRATENEG 31 +#define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG) +#define F_TSCCLRATENEG V_TSCCLRATENEG(1U) + +#define S_TSCCLRATEL 0 +#define M_TSCCLRATEL 0xffffffU +#define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL) +#define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL) + #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924 #define S_TSCCLRMAX 16 @@ -23970,3 +33505,8876 @@ #define M_TSCCLWEIGHT 0xffffU #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT) #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT) + +#define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84 +#define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88 +#define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c +#define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90 +#define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94 +#define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98 +#define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c +#define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0 +#define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4 + +#define S_PF7_OWNER_PL 15 +#define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL) +#define F_PF7_OWNER_PL V_PF7_OWNER_PL(1U) + +#define S_PF6_OWNER_PL 14 +#define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL) +#define F_PF6_OWNER_PL V_PF6_OWNER_PL(1U) + +#define S_PF5_OWNER_PL 13 +#define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL) +#define F_PF5_OWNER_PL V_PF5_OWNER_PL(1U) + +#define S_PF4_OWNER_PL 12 +#define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL) +#define F_PF4_OWNER_PL V_PF4_OWNER_PL(1U) + +#define S_PF3_OWNER_PL 11 +#define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL) +#define F_PF3_OWNER_PL V_PF3_OWNER_PL(1U) + +#define S_PF2_OWNER_PL 10 +#define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL) +#define F_PF2_OWNER_PL V_PF2_OWNER_PL(1U) + +#define S_PF1_OWNER_PL 9 +#define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL) +#define F_PF1_OWNER_PL V_PF1_OWNER_PL(1U) + +#define S_PF0_OWNER_PL 8 +#define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL) +#define F_PF0_OWNER_PL V_PF0_OWNER_PL(1U) + +#define S_PF7_OWNER_UP 7 +#define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP) +#define F_PF7_OWNER_UP V_PF7_OWNER_UP(1U) + +#define S_PF6_OWNER_UP 6 +#define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP) +#define F_PF6_OWNER_UP V_PF6_OWNER_UP(1U) + +#define S_PF5_OWNER_UP 5 +#define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP) +#define F_PF5_OWNER_UP V_PF5_OWNER_UP(1U) + +#define S_PF4_OWNER_UP 4 +#define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP) +#define F_PF4_OWNER_UP V_PF4_OWNER_UP(1U) + +#define S_PF3_OWNER_UP 3 +#define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP) +#define F_PF3_OWNER_UP V_PF3_OWNER_UP(1U) + +#define S_PF2_OWNER_UP 2 +#define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP) +#define F_PF2_OWNER_UP V_PF2_OWNER_UP(1U) + +#define S_PF1_OWNER_UP 1 +#define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP) +#define F_PF1_OWNER_UP V_PF1_OWNER_UP(1U) + +#define S_PF0_OWNER_UP 0 +#define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP) +#define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U) + +#define A_CIM_CTL_PIO_MST_CONFIG 0xda8 + +#define S_T5_CTLRID 0 +#define M_T5_CTLRID 0xffU +#define V_T5_CTLRID(x) ((x) << S_T5_CTLRID) +#define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID) + +/* registers for module MAC */ +#define MAC_BASE_ADDR 0x0 + +#define A_MAC_PORT_CFG 0x800 + +#define S_MAC_CLK_SEL 29 +#define M_MAC_CLK_SEL 0x7U +#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL) +#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL) + +#define S_SMUXTXSEL 9 +#define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL) +#define F_SMUXTXSEL V_SMUXTXSEL(1U) + +#define S_SMUXRXSEL 8 +#define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL) +#define F_SMUXRXSEL V_SMUXRXSEL(1U) + +#define S_PORTSPEED 4 +#define M_PORTSPEED 0x3U +#define V_PORTSPEED(x) ((x) << S_PORTSPEED) +#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) + +#define A_MAC_PORT_RESET_CTRL 0x804 + +#define S_TWGDSK_HSSC16B 31 +#define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B) +#define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U) + +#define S_EEE_RESET 30 +#define V_EEE_RESET(x) ((x) << S_EEE_RESET) +#define F_EEE_RESET V_EEE_RESET(1U) + +#define S_PTP_TIMER 29 +#define V_PTP_TIMER(x) ((x) << S_PTP_TIMER) +#define F_PTP_TIMER V_PTP_TIMER(1U) + +#define S_MTIPREFRESET 28 +#define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET) +#define F_MTIPREFRESET V_MTIPREFRESET(1U) + +#define S_MTIPTXFFRESET 27 +#define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET) +#define F_MTIPTXFFRESET V_MTIPTXFFRESET(1U) + +#define S_MTIPRXFFRESET 26 +#define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET) +#define F_MTIPRXFFRESET V_MTIPRXFFRESET(1U) + +#define S_MTIPREGRESET 25 +#define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET) +#define F_MTIPREGRESET V_MTIPREGRESET(1U) + +#define S_AEC3RESET 23 +#define V_AEC3RESET(x) ((x) << S_AEC3RESET) +#define F_AEC3RESET V_AEC3RESET(1U) + +#define S_AEC2RESET 22 +#define V_AEC2RESET(x) ((x) << S_AEC2RESET) +#define F_AEC2RESET V_AEC2RESET(1U) + +#define S_AEC1RESET 21 +#define V_AEC1RESET(x) ((x) << S_AEC1RESET) +#define F_AEC1RESET V_AEC1RESET(1U) + +#define S_AEC0RESET 20 +#define V_AEC0RESET(x) ((x) << S_AEC0RESET) +#define F_AEC0RESET V_AEC0RESET(1U) + +#define S_AET3RESET 19 +#define V_AET3RESET(x) ((x) << S_AET3RESET) +#define F_AET3RESET V_AET3RESET(1U) + +#define S_AET2RESET 18 +#define V_AET2RESET(x) ((x) << S_AET2RESET) +#define F_AET2RESET V_AET2RESET(1U) + +#define S_AET1RESET 17 +#define V_AET1RESET(x) ((x) << S_AET1RESET) +#define F_AET1RESET V_AET1RESET(1U) + +#define S_AET0RESET 16 +#define V_AET0RESET(x) ((x) << S_AET0RESET) +#define F_AET0RESET V_AET0RESET(1U) + +#define S_TXIF_RESET 12 +#define V_TXIF_RESET(x) ((x) << S_TXIF_RESET) +#define F_TXIF_RESET V_TXIF_RESET(1U) + +#define S_RXIF_RESET 11 +#define V_RXIF_RESET(x) ((x) << S_RXIF_RESET) +#define F_RXIF_RESET V_RXIF_RESET(1U) + +#define S_MTIPSD3TXRST 9 +#define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST) +#define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U) + +#define S_MTIPSD2TXRST 8 +#define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST) +#define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U) + +#define S_MTIPSD1TXRST 7 +#define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST) +#define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U) + +#define S_MTIPSD0TXRST 6 +#define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST) +#define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U) + +#define S_MTIPSD3RXRST 5 +#define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST) +#define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U) + +#define S_MTIPSD2RXRST 4 +#define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST) +#define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U) + +#define S_MTIPSD1RXRST 3 +#define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST) +#define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U) + +#define S_MTIPSD0RXRST 1 +#define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST) +#define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U) + +#define A_MAC_PORT_LED_CFG 0x808 +#define A_MAC_PORT_LED_COUNTHI 0x80c +#define A_MAC_PORT_LED_COUNTLO 0x810 +#define A_MAC_PORT_CFG3 0x814 + +#define S_FCSDISCTRL 25 +#define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL) +#define F_FCSDISCTRL V_FCSDISCTRL(1U) + +#define S_SIGDETCTRL 24 +#define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL) +#define F_SIGDETCTRL V_SIGDETCTRL(1U) + +#define S_TX_LANE 23 +#define V_TX_LANE(x) ((x) << S_TX_LANE) +#define F_TX_LANE V_TX_LANE(1U) + +#define S_RX_LANE 22 +#define V_RX_LANE(x) ((x) << S_RX_LANE) +#define F_RX_LANE V_RX_LANE(1U) + +#define S_SE_CLR 21 +#define V_SE_CLR(x) ((x) << S_SE_CLR) +#define F_SE_CLR V_SE_CLR(1U) + +#define S_AN_ENA 17 +#define M_AN_ENA 0xfU +#define V_AN_ENA(x) ((x) << S_AN_ENA) +#define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA) + +#define S_SD_RX_CLK_ENA 13 +#define M_SD_RX_CLK_ENA 0xfU +#define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA) +#define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA) + +#define S_SD_TX_CLK_ENA 9 +#define M_SD_TX_CLK_ENA 0xfU +#define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA) +#define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA) + +#define S_SGMIISEL 8 +#define V_SGMIISEL(x) ((x) << S_SGMIISEL) +#define F_SGMIISEL V_SGMIISEL(1U) + +#define S_HSSPLLSEL 4 +#define M_HSSPLLSEL 0xfU +#define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL) +#define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL) + +#define S_HSSC16C20SEL 0 +#define M_HSSC16C20SEL 0xfU +#define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL) +#define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL) + +#define A_MAC_PORT_CFG2 0x818 + +#define S_T5_AEC_PMA_TX_READY 4 +#define M_T5_AEC_PMA_TX_READY 0xfU +#define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY) +#define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY) + +#define S_T5_AEC_PMA_RX_READY 0 +#define M_T5_AEC_PMA_RX_READY 0xfU +#define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY) +#define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY) + +#define A_MAC_PORT_PKT_COUNT 0x81c +#define A_MAC_PORT_CFG4 0x820 + +#define S_AEC3_RX_WIDTH 14 +#define M_AEC3_RX_WIDTH 0x3U +#define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH) +#define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH) + +#define S_AEC2_RX_WIDTH 12 +#define M_AEC2_RX_WIDTH 0x3U +#define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH) +#define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH) + +#define S_AEC1_RX_WIDTH 10 +#define M_AEC1_RX_WIDTH 0x3U +#define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH) +#define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH) + +#define S_AEC0_RX_WIDTH 8 +#define M_AEC0_RX_WIDTH 0x3U +#define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH) +#define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH) + +#define S_AEC3_TX_WIDTH 6 +#define M_AEC3_TX_WIDTH 0x3U +#define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH) +#define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH) + +#define S_AEC2_TX_WIDTH 4 +#define M_AEC2_TX_WIDTH 0x3U +#define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH) +#define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH) + +#define S_AEC1_TX_WIDTH 2 +#define M_AEC1_TX_WIDTH 0x3U +#define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH) +#define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH) + +#define S_AEC0_TX_WIDTH 0 +#define M_AEC0_TX_WIDTH 0x3U +#define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH) +#define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH) + +#define A_MAC_PORT_MAGIC_MACID_LO 0x824 +#define A_MAC_PORT_MAGIC_MACID_HI 0x828 +#define A_MAC_PORT_LINK_STATUS 0x834 + +#define S_AN_DONE 6 +#define V_AN_DONE(x) ((x) << S_AN_DONE) +#define F_AN_DONE V_AN_DONE(1U) + +#define S_ALIGN_DONE 5 +#define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE) +#define F_ALIGN_DONE V_ALIGN_DONE(1U) + +#define S_BLOCK_LOCK 4 +#define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK) +#define F_BLOCK_LOCK V_BLOCK_LOCK(1U) + +#define A_MAC_PORT_EPIO_DATA0 0x8c0 +#define A_MAC_PORT_EPIO_DATA1 0x8c4 +#define A_MAC_PORT_EPIO_DATA2 0x8c8 +#define A_MAC_PORT_EPIO_DATA3 0x8cc +#define A_MAC_PORT_EPIO_OP 0x8d0 +#define A_MAC_PORT_WOL_STATUS 0x8d4 +#define A_MAC_PORT_INT_EN 0x8d8 + +#define S_TX_TS_AVAIL 29 +#define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL) +#define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U) + +#define S_AN_PAGE_RCVD 2 +#define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD) +#define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U) + +#define A_MAC_PORT_INT_CAUSE 0x8dc +#define A_MAC_PORT_PERR_INT_EN 0x8e0 + +#define S_PERR_PKT_RAM 24 +#define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM) +#define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U) + +#define S_PERR_MASK_RAM 23 +#define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM) +#define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U) + +#define S_PERR_CRC_RAM 22 +#define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM) +#define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U) + +#define S_RX_DFF_SEG0 21 +#define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0) +#define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U) + +#define S_RX_SFF_SEG0 20 +#define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0) +#define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U) + +#define S_RX_DFF_MAC10 19 +#define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10) +#define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U) + +#define S_RX_SFF_MAC10 18 +#define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10) +#define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U) + +#define S_TX_DFF_SEG0 17 +#define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0) +#define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U) + +#define S_TX_SFF_SEG0 16 +#define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0) +#define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U) + +#define S_TX_DFF_MAC10 15 +#define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10) +#define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U) + +#define S_TX_SFF_MAC10 14 +#define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10) +#define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U) + +#define S_RX_STATS 13 +#define V_RX_STATS(x) ((x) << S_RX_STATS) +#define F_RX_STATS V_RX_STATS(1U) + +#define S_TX_STATS 12 +#define V_TX_STATS(x) ((x) << S_TX_STATS) +#define F_TX_STATS V_TX_STATS(1U) + +#define S_PERR3_RX_MIX 11 +#define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX) +#define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U) + +#define S_PERR3_RX_SD 10 +#define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD) +#define F_PERR3_RX_SD V_PERR3_RX_SD(1U) + +#define S_PERR3_TX 9 +#define V_PERR3_TX(x) ((x) << S_PERR3_TX) +#define F_PERR3_TX V_PERR3_TX(1U) + +#define S_PERR2_RX_MIX 8 +#define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX) +#define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U) + +#define S_PERR2_RX_SD 7 +#define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD) +#define F_PERR2_RX_SD V_PERR2_RX_SD(1U) + +#define S_PERR2_TX 6 +#define V_PERR2_TX(x) ((x) << S_PERR2_TX) +#define F_PERR2_TX V_PERR2_TX(1U) + +#define S_PERR1_RX_MIX 5 +#define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX) +#define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U) + +#define S_PERR1_RX_SD 4 +#define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD) +#define F_PERR1_RX_SD V_PERR1_RX_SD(1U) + +#define S_PERR1_TX 3 +#define V_PERR1_TX(x) ((x) << S_PERR1_TX) +#define F_PERR1_TX V_PERR1_TX(1U) + +#define S_PERR0_RX_MIX 2 +#define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX) +#define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U) + +#define S_PERR0_RX_SD 1 +#define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD) +#define F_PERR0_RX_SD V_PERR0_RX_SD(1U) + +#define S_PERR0_TX 0 +#define V_PERR0_TX(x) ((x) << S_PERR0_TX) +#define F_PERR0_TX V_PERR0_TX(1U) + +#define A_MAC_PORT_PERR_INT_CAUSE 0x8e4 +#define A_MAC_PORT_PERR_ENABLE 0x8e8 +#define A_MAC_PORT_PERR_INJECT 0x8ec +#define A_MAC_PORT_HSS_CFG0 0x8f0 + +#define S_HSSREFCLKVALIDA 20 +#define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA) +#define F_HSSREFCLKVALIDA V_HSSREFCLKVALIDA(1U) + +#define S_HSSREFCLKVALIDB 19 +#define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB) +#define F_HSSREFCLKVALIDB V_HSSREFCLKVALIDB(1U) + +#define S_HSSRESYNCA 18 +#define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA) +#define F_HSSRESYNCA V_HSSRESYNCA(1U) + +#define S_HSSRESYNCB 16 +#define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB) +#define F_HSSRESYNCB V_HSSRESYNCB(1U) + +#define S_HSSRECCALA 15 +#define V_HSSRECCALA(x) ((x) << S_HSSRECCALA) +#define F_HSSRECCALA V_HSSRECCALA(1U) + +#define S_HSSRECCALB 13 +#define V_HSSRECCALB(x) ((x) << S_HSSRECCALB) +#define F_HSSRECCALB V_HSSRECCALB(1U) + +#define S_HSSPLLBYPA 12 +#define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA) +#define F_HSSPLLBYPA V_HSSPLLBYPA(1U) + +#define S_HSSPLLBYPB 11 +#define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB) +#define F_HSSPLLBYPB V_HSSPLLBYPB(1U) + +#define S_HSSPDWNPLLA 10 +#define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA) +#define F_HSSPDWNPLLA V_HSSPDWNPLLA(1U) + +#define S_HSSPDWNPLLB 9 +#define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB) +#define F_HSSPDWNPLLB V_HSSPDWNPLLB(1U) + +#define S_HSSVCOSELA 8 +#define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA) +#define F_HSSVCOSELA V_HSSVCOSELA(1U) + +#define S_HSSVCOSELB 7 +#define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB) +#define F_HSSVCOSELB V_HSSVCOSELB(1U) + +#define S_HSSCALCOMP 6 +#define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP) +#define F_HSSCALCOMP V_HSSCALCOMP(1U) + +#define S_HSSCALENAB 5 +#define V_HSSCALENAB(x) ((x) << S_HSSCALENAB) +#define F_HSSCALENAB V_HSSCALENAB(1U) + +#define A_MAC_PORT_HSS_CFG1 0x8f4 + +#define S_RXACONFIGSEL 30 +#define M_RXACONFIGSEL 0x3U +#define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL) +#define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL) + +#define S_RXAQUIET 29 +#define V_RXAQUIET(x) ((x) << S_RXAQUIET) +#define F_RXAQUIET V_RXAQUIET(1U) + +#define S_RXAREFRESH 28 +#define V_RXAREFRESH(x) ((x) << S_RXAREFRESH) +#define F_RXAREFRESH V_RXAREFRESH(1U) + +#define S_RXBCONFIGSEL 26 +#define M_RXBCONFIGSEL 0x3U +#define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL) +#define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL) + +#define S_RXBQUIET 25 +#define V_RXBQUIET(x) ((x) << S_RXBQUIET) +#define F_RXBQUIET V_RXBQUIET(1U) + +#define S_RXBREFRESH 24 +#define V_RXBREFRESH(x) ((x) << S_RXBREFRESH) +#define F_RXBREFRESH V_RXBREFRESH(1U) + +#define S_RXCCONFIGSEL 22 +#define M_RXCCONFIGSEL 0x3U +#define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL) +#define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL) + +#define S_RXCQUIET 21 +#define V_RXCQUIET(x) ((x) << S_RXCQUIET) +#define F_RXCQUIET V_RXCQUIET(1U) + +#define S_RXCREFRESH 20 +#define V_RXCREFRESH(x) ((x) << S_RXCREFRESH) +#define F_RXCREFRESH V_RXCREFRESH(1U) + +#define S_RXDCONFIGSEL 18 +#define M_RXDCONFIGSEL 0x3U +#define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL) +#define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL) + +#define S_RXDQUIET 17 +#define V_RXDQUIET(x) ((x) << S_RXDQUIET) +#define F_RXDQUIET V_RXDQUIET(1U) + +#define S_RXDREFRESH 16 +#define V_RXDREFRESH(x) ((x) << S_RXDREFRESH) +#define F_RXDREFRESH V_RXDREFRESH(1U) + +#define S_TXACONFIGSEL 14 +#define M_TXACONFIGSEL 0x3U +#define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL) +#define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL) + +#define S_TXAQUIET 13 +#define V_TXAQUIET(x) ((x) << S_TXAQUIET) +#define F_TXAQUIET V_TXAQUIET(1U) + +#define S_TXAREFRESH 12 +#define V_TXAREFRESH(x) ((x) << S_TXAREFRESH) +#define F_TXAREFRESH V_TXAREFRESH(1U) + +#define S_TXBCONFIGSEL 10 +#define M_TXBCONFIGSEL 0x3U +#define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL) +#define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL) + +#define S_TXBQUIET 9 +#define V_TXBQUIET(x) ((x) << S_TXBQUIET) +#define F_TXBQUIET V_TXBQUIET(1U) + +#define S_TXBREFRESH 8 +#define V_TXBREFRESH(x) ((x) << S_TXBREFRESH) +#define F_TXBREFRESH V_TXBREFRESH(1U) + +#define S_TXCCONFIGSEL 6 +#define M_TXCCONFIGSEL 0x3U +#define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL) +#define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL) + +#define S_TXCQUIET 5 +#define V_TXCQUIET(x) ((x) << S_TXCQUIET) +#define F_TXCQUIET V_TXCQUIET(1U) + +#define S_TXCREFRESH 4 +#define V_TXCREFRESH(x) ((x) << S_TXCREFRESH) +#define F_TXCREFRESH V_TXCREFRESH(1U) + +#define S_TXDCONFIGSEL 2 +#define M_TXDCONFIGSEL 0x3U +#define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL) +#define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL) + +#define S_TXDQUIET 1 +#define V_TXDQUIET(x) ((x) << S_TXDQUIET) +#define F_TXDQUIET V_TXDQUIET(1U) + +#define S_TXDREFRESH 0 +#define V_TXDREFRESH(x) ((x) << S_TXDREFRESH) +#define F_TXDREFRESH V_TXDREFRESH(1U) + +#define A_MAC_PORT_HSS_CFG2 0x8f8 + +#define S_RXAASSTCLK 31 +#define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK) +#define F_RXAASSTCLK V_RXAASSTCLK(1U) + +#define S_T5RXAPRBSRST 30 +#define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST) +#define F_T5RXAPRBSRST V_T5RXAPRBSRST(1U) + +#define S_RXBASSTCLK 29 +#define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK) +#define F_RXBASSTCLK V_RXBASSTCLK(1U) + +#define S_T5RXBPRBSRST 28 +#define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST) +#define F_T5RXBPRBSRST V_T5RXBPRBSRST(1U) + +#define S_RXCASSTCLK 27 +#define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK) +#define F_RXCASSTCLK V_RXCASSTCLK(1U) + +#define S_T5RXCPRBSRST 26 +#define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST) +#define F_T5RXCPRBSRST V_T5RXCPRBSRST(1U) + +#define S_RXDASSTCLK 25 +#define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK) +#define F_RXDASSTCLK V_RXDASSTCLK(1U) + +#define S_T5RXDPRBSRST 24 +#define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST) +#define F_T5RXDPRBSRST V_T5RXDPRBSRST(1U) + +#define A_MAC_PORT_HSS_CFG3 0x8fc + +#define S_HSSCALSSTN 25 +#define M_HSSCALSSTN 0x7U +#define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN) +#define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN) + +#define S_HSSCALSSTP 22 +#define M_HSSCALSSTP 0x7U +#define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP) +#define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP) + +#define S_HSSVBOOSTDIVB 19 +#define M_HSSVBOOSTDIVB 0x7U +#define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB) +#define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB) + +#define S_HSSVBOOSTDIVA 16 +#define M_HSSVBOOSTDIVA 0x7U +#define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA) +#define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA) + +#define S_HSSPLLCONFIGB 8 +#define M_HSSPLLCONFIGB 0xffU +#define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB) +#define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB) + +#define S_HSSPLLCONFIGA 0 +#define M_HSSPLLCONFIGA 0xffU +#define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA) +#define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA) + +#define A_MAC_PORT_HSS_CFG4 0x900 + +#define S_HSSDIVSELA 9 +#define M_HSSDIVSELA 0x1ffU +#define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA) +#define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA) + +#define S_HSSDIVSELB 0 +#define M_HSSDIVSELB 0x1ffU +#define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB) +#define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB) + +#define A_MAC_PORT_HSS_STATUS 0x904 + +#define S_HSSPLLLOCKB 3 +#define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB) +#define F_HSSPLLLOCKB V_HSSPLLLOCKB(1U) + +#define S_HSSPLLLOCKA 2 +#define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA) +#define F_HSSPLLLOCKA V_HSSPLLLOCKA(1U) + +#define S_HSSPRTREADYB 1 +#define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB) +#define F_HSSPRTREADYB V_HSSPRTREADYB(1U) + +#define S_HSSPRTREADYA 0 +#define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA) +#define F_HSSPRTREADYA V_HSSPRTREADYA(1U) + +#define A_MAC_PORT_HSS_EEE_STATUS 0x908 + +#define S_RXAQUIET_STATUS 15 +#define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS) +#define F_RXAQUIET_STATUS V_RXAQUIET_STATUS(1U) + +#define S_RXAREFRESH_STATUS 14 +#define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS) +#define F_RXAREFRESH_STATUS V_RXAREFRESH_STATUS(1U) + +#define S_RXBQUIET_STATUS 13 +#define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS) +#define F_RXBQUIET_STATUS V_RXBQUIET_STATUS(1U) + +#define S_RXBREFRESH_STATUS 12 +#define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS) +#define F_RXBREFRESH_STATUS V_RXBREFRESH_STATUS(1U) + +#define S_RXCQUIET_STATUS 11 +#define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS) +#define F_RXCQUIET_STATUS V_RXCQUIET_STATUS(1U) + +#define S_RXCREFRESH_STATUS 10 +#define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS) +#define F_RXCREFRESH_STATUS V_RXCREFRESH_STATUS(1U) + +#define S_RXDQUIET_STATUS 9 +#define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS) +#define F_RXDQUIET_STATUS V_RXDQUIET_STATUS(1U) + +#define S_RXDREFRESH_STATUS 8 +#define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS) +#define F_RXDREFRESH_STATUS V_RXDREFRESH_STATUS(1U) + +#define S_TXAQUIET_STATUS 7 +#define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS) +#define F_TXAQUIET_STATUS V_TXAQUIET_STATUS(1U) + +#define S_TXAREFRESH_STATUS 6 +#define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS) +#define F_TXAREFRESH_STATUS V_TXAREFRESH_STATUS(1U) + +#define S_TXBQUIET_STATUS 5 +#define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS) +#define F_TXBQUIET_STATUS V_TXBQUIET_STATUS(1U) + +#define S_TXBREFRESH_STATUS 4 +#define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS) +#define F_TXBREFRESH_STATUS V_TXBREFRESH_STATUS(1U) + +#define S_TXCQUIET_STATUS 3 +#define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS) +#define F_TXCQUIET_STATUS V_TXCQUIET_STATUS(1U) + +#define S_TXCREFRESH_STATUS 2 +#define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS) +#define F_TXCREFRESH_STATUS V_TXCREFRESH_STATUS(1U) + +#define S_TXDQUIET_STATUS 1 +#define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS) +#define F_TXDQUIET_STATUS V_TXDQUIET_STATUS(1U) + +#define S_TXDREFRESH_STATUS 0 +#define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS) +#define F_TXDREFRESH_STATUS V_TXDREFRESH_STATUS(1U) + +#define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c +#define A_MAC_PORT_HSS_PL_CTL 0x910 + +#define S_TOV 16 +#define M_TOV 0xffU +#define V_TOV(x) ((x) << S_TOV) +#define G_TOV(x) (((x) >> S_TOV) & M_TOV) + +#define S_TSU 8 +#define M_TSU 0xffU +#define V_TSU(x) ((x) << S_TSU) +#define G_TSU(x) (((x) >> S_TSU) & M_TSU) + +#define S_IPW 0 +#define M_IPW 0xffU +#define V_IPW(x) ((x) << S_IPW) +#define G_IPW(x) (((x) >> S_IPW) & M_IPW) + +#define A_MAC_PORT_RUNT_FRAME 0x914 + +#define S_RUNTCLEAR 16 +#define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR) +#define F_RUNTCLEAR V_RUNTCLEAR(1U) + +#define S_RUNT 0 +#define M_RUNT 0xffffU +#define V_RUNT(x) ((x) << S_RUNT) +#define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT) + +#define A_MAC_PORT_EEE_STATUS 0x918 + +#define S_EEE_TX_10G_STATE 10 +#define M_EEE_TX_10G_STATE 0x3U +#define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE) +#define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE) + +#define S_EEE_RX_10G_STATE 8 +#define M_EEE_RX_10G_STATE 0x3U +#define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE) +#define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE) + +#define S_EEE_TX_1G_STATE 6 +#define M_EEE_TX_1G_STATE 0x3U +#define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE) +#define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE) + +#define S_EEE_RX_1G_STATE 4 +#define M_EEE_RX_1G_STATE 0x3U +#define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE) +#define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE) + +#define S_PMA_RX_REFRESH 3 +#define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH) +#define F_PMA_RX_REFRESH V_PMA_RX_REFRESH(1U) + +#define S_PMA_RX_QUIET 2 +#define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET) +#define F_PMA_RX_QUIET V_PMA_RX_QUIET(1U) + +#define S_PMA_TX_REFRESH 1 +#define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH) +#define F_PMA_TX_REFRESH V_PMA_TX_REFRESH(1U) + +#define S_PMA_TX_QUIET 0 +#define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET) +#define F_PMA_TX_QUIET V_PMA_TX_QUIET(1U) + +#define A_MAC_PORT_CGEN 0x91c + +#define S_CGEN 8 +#define V_CGEN(x) ((x) << S_CGEN) +#define F_CGEN V_CGEN(1U) + +#define S_SD7_CGEN 7 +#define V_SD7_CGEN(x) ((x) << S_SD7_CGEN) +#define F_SD7_CGEN V_SD7_CGEN(1U) + +#define S_SD6_CGEN 6 +#define V_SD6_CGEN(x) ((x) << S_SD6_CGEN) +#define F_SD6_CGEN V_SD6_CGEN(1U) + +#define S_SD5_CGEN 5 +#define V_SD5_CGEN(x) ((x) << S_SD5_CGEN) +#define F_SD5_CGEN V_SD5_CGEN(1U) + +#define S_SD4_CGEN 4 +#define V_SD4_CGEN(x) ((x) << S_SD4_CGEN) +#define F_SD4_CGEN V_SD4_CGEN(1U) + +#define S_SD3_CGEN 3 +#define V_SD3_CGEN(x) ((x) << S_SD3_CGEN) +#define F_SD3_CGEN V_SD3_CGEN(1U) + +#define S_SD2_CGEN 2 +#define V_SD2_CGEN(x) ((x) << S_SD2_CGEN) +#define F_SD2_CGEN V_SD2_CGEN(1U) + +#define S_SD1_CGEN 1 +#define V_SD1_CGEN(x) ((x) << S_SD1_CGEN) +#define F_SD1_CGEN V_SD1_CGEN(1U) + +#define S_SD0_CGEN 0 +#define V_SD0_CGEN(x) ((x) << S_SD0_CGEN) +#define F_SD0_CGEN V_SD0_CGEN(1U) + +#define A_MAC_PORT_CGEN_MTIP 0x920 + +#define S_MACSEG5_CGEN 11 +#define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN) +#define F_MACSEG5_CGEN V_MACSEG5_CGEN(1U) + +#define S_PCSSEG5_CGEN 10 +#define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN) +#define F_PCSSEG5_CGEN V_PCSSEG5_CGEN(1U) + +#define S_MACSEG4_CGEN 9 +#define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN) +#define F_MACSEG4_CGEN V_MACSEG4_CGEN(1U) + +#define S_PCSSEG4_CGEN 8 +#define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN) +#define F_PCSSEG4_CGEN V_PCSSEG4_CGEN(1U) + +#define S_MACSEG3_CGEN 7 +#define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN) +#define F_MACSEG3_CGEN V_MACSEG3_CGEN(1U) + +#define S_PCSSEG3_CGEN 6 +#define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN) +#define F_PCSSEG3_CGEN V_PCSSEG3_CGEN(1U) + +#define S_MACSEG2_CGEN 5 +#define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN) +#define F_MACSEG2_CGEN V_MACSEG2_CGEN(1U) + +#define S_PCSSEG2_CGEN 4 +#define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN) +#define F_PCSSEG2_CGEN V_PCSSEG2_CGEN(1U) + +#define S_MACSEG1_CGEN 3 +#define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN) +#define F_MACSEG1_CGEN V_MACSEG1_CGEN(1U) + +#define S_PCSSEG1_CGEN 2 +#define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN) +#define F_PCSSEG1_CGEN V_PCSSEG1_CGEN(1U) + +#define S_MACSEG0_CGEN 1 +#define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN) +#define F_MACSEG0_CGEN V_MACSEG0_CGEN(1U) + +#define S_PCSSEG0_CGEN 0 +#define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN) +#define F_PCSSEG0_CGEN V_PCSSEG0_CGEN(1U) + +#define A_MAC_PORT_TX_TS_ID 0x924 + +#define S_TS_ID 0 +#define M_TS_ID 0x7U +#define V_TS_ID(x) ((x) << S_TS_ID) +#define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID) + +#define A_MAC_PORT_TX_TS_VAL_LO 0x928 +#define A_MAC_PORT_TX_TS_VAL_HI 0x92c +#define A_MAC_PORT_EEE_CTL 0x930 + +#define S_EEE_CTRL 2 +#define M_EEE_CTRL 0x3fffffffU +#define V_EEE_CTRL(x) ((x) << S_EEE_CTRL) +#define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL) + +#define S_TICK_START 1 +#define V_TICK_START(x) ((x) << S_TICK_START) +#define F_TICK_START V_TICK_START(1U) + +#define S_EEE_ENABLE 0 +#define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE) +#define F_EEE_ENABLE V_EEE_ENABLE(1U) + +#define A_MAC_PORT_EEE_TX_CTL 0x934 + +#define S_WAKE_TIMER 16 +#define M_WAKE_TIMER 0xffffU +#define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER) +#define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER) + +#define S_HSS_TIMER 5 +#define M_HSS_TIMER 0xfU +#define V_HSS_TIMER(x) ((x) << S_HSS_TIMER) +#define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER) + +#define S_HSS_CTL 4 +#define V_HSS_CTL(x) ((x) << S_HSS_CTL) +#define F_HSS_CTL V_HSS_CTL(1U) + +#define S_LPI_ACTIVE 3 +#define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE) +#define F_LPI_ACTIVE V_LPI_ACTIVE(1U) + +#define S_LPI_TXHOLD 2 +#define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD) +#define F_LPI_TXHOLD V_LPI_TXHOLD(1U) + +#define S_LPI_REQ 1 +#define V_LPI_REQ(x) ((x) << S_LPI_REQ) +#define F_LPI_REQ V_LPI_REQ(1U) + +#define S_EEE_TX_RESET 0 +#define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET) +#define F_EEE_TX_RESET V_EEE_TX_RESET(1U) + +#define A_MAC_PORT_EEE_RX_CTL 0x938 + +#define S_LPI_IND 1 +#define V_LPI_IND(x) ((x) << S_LPI_IND) +#define F_LPI_IND V_LPI_IND(1U) + +#define S_EEE_RX_RESET 0 +#define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET) +#define F_EEE_RX_RESET V_EEE_RX_RESET(1U) + +#define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c +#define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940 +#define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944 +#define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948 +#define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c +#define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950 +#define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954 +#define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958 +#define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c +#define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960 +#define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964 +#define A_MAC_PORT_EEE_WF_COUNT 0x968 + +#define S_WAKE_CNT_CLR 16 +#define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR) +#define F_WAKE_CNT_CLR V_WAKE_CNT_CLR(1U) + +#define S_WAKE_CNT 0 +#define M_WAKE_CNT 0xffffU +#define V_WAKE_CNT(x) ((x) << S_WAKE_CNT) +#define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT) + +#define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c +#define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970 +#define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974 +#define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978 +#define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c +#define A_MAC_PORT_PTP_TIMER_WR_HI 0x980 +#define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984 +#define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988 +#define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c + +#define S_PTP_OFFSET 0 +#define M_PTP_OFFSET 0xffU +#define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET) +#define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET) + +#define A_MAC_PORT_PTP_SUM_LO 0x990 +#define A_MAC_PORT_PTP_SUM_HI 0x994 +#define A_MAC_PORT_PTP_TIMER_INCR0 0x998 + +#define S_Y 16 +#define M_Y 0xffffU +#define V_Y(x) ((x) << S_Y) +#define G_Y(x) (((x) >> S_Y) & M_Y) + +#define S_X 0 +#define M_X 0xffffU +#define V_X(x) ((x) << S_X) +#define G_X(x) (((x) >> S_X) & M_X) + +#define A_MAC_PORT_PTP_TIMER_INCR1 0x99c + +#define S_Y_TICK 16 +#define M_Y_TICK 0xffffU +#define V_Y_TICK(x) ((x) << S_Y_TICK) +#define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK) + +#define S_X_TICK 0 +#define M_X_TICK 0xffffU +#define V_X_TICK(x) ((x) << S_X_TICK) +#define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK) + +#define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0 +#define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4 + +#define S_B 16 +#define M_B 0xffffU +#define V_B(x) ((x) << S_B) +#define G_B(x) (((x) >> S_B) & M_B) + +#define S_A 0 +#define M_A 0xffffU +#define V_A(x) ((x) << S_A) +#define G_A(x) (((x) >> S_A) & M_A) + +#define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8 +#define A_MAC_PORT_PTP_CFG 0x9ac + +#define S_FRZ 18 +#define V_FRZ(x) ((x) << S_FRZ) +#define F_FRZ V_FRZ(1U) + +#define S_OFFSER_ADJUST_SIGN 17 +#define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN) +#define F_OFFSER_ADJUST_SIGN V_OFFSER_ADJUST_SIGN(1U) + +#define S_ADD_OFFSET 16 +#define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET) +#define F_ADD_OFFSET V_ADD_OFFSET(1U) + +#define S_CYCLE1 8 +#define M_CYCLE1 0xffU +#define V_CYCLE1(x) ((x) << S_CYCLE1) +#define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1) + +#define S_Q 0 +#define M_Q 0xffU +#define V_Q(x) ((x) << S_Q) +#define G_Q(x) (((x) >> S_Q) & M_Q) + +#define A_MAC_PORT_MTIP_REVISION 0xa00 + +#define S_CUSTREV 16 +#define M_CUSTREV 0xffffU +#define V_CUSTREV(x) ((x) << S_CUSTREV) +#define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV) + +#define S_VER 8 +#define M_VER 0xffU +#define V_VER(x) ((x) << S_VER) +#define G_VER(x) (((x) >> S_VER) & M_VER) + +#define S_MTIP_REV 0 +#define M_MTIP_REV 0xffU +#define V_MTIP_REV(x) ((x) << S_MTIP_REV) +#define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV) + +#define A_MAC_PORT_MTIP_SCRATCH 0xa04 +#define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08 + +#define S_TX_FLUSH_ENABLE 22 +#define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE) +#define F_TX_FLUSH_ENABLE V_TX_FLUSH_ENABLE(1U) + +#define S_RX_SFD_ANY 21 +#define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY) +#define F_RX_SFD_ANY V_RX_SFD_ANY(1U) + +#define S_PAUSE_PFC_COMP 20 +#define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP) +#define F_PAUSE_PFC_COMP V_PAUSE_PFC_COMP(1U) + +#define S_PFC_MODE 19 +#define V_PFC_MODE(x) ((x) << S_PFC_MODE) +#define F_PFC_MODE V_PFC_MODE(1U) + +#define S_RS_COL_CNT_EXT 18 +#define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT) +#define F_RS_COL_CNT_EXT V_RS_COL_CNT_EXT(1U) + +#define S_NO_LGTH_CHECK 17 +#define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK) +#define F_NO_LGTH_CHECK V_NO_LGTH_CHECK(1U) + +#define S_SEND_IDLE 16 +#define V_SEND_IDLE(x) ((x) << S_SEND_IDLE) +#define F_SEND_IDLE V_SEND_IDLE(1U) + +#define S_PHY_TXENA 15 +#define V_PHY_TXENA(x) ((x) << S_PHY_TXENA) +#define F_PHY_TXENA V_PHY_TXENA(1U) + +#define S_RX_ERR_DISC 14 +#define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC) +#define F_RX_ERR_DISC V_RX_ERR_DISC(1U) + +#define S_CMD_FRAME_ENA 13 +#define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA) +#define F_CMD_FRAME_ENA V_CMD_FRAME_ENA(1U) + +#define S_SW_RESET 12 +#define V_SW_RESET(x) ((x) << S_SW_RESET) +#define F_SW_RESET V_SW_RESET(1U) + +#define S_TX_PAD_EN 11 +#define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN) +#define F_TX_PAD_EN V_TX_PAD_EN(1U) + +#define S_PHY_LOOPBACK_EN 10 +#define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN) +#define F_PHY_LOOPBACK_EN V_PHY_LOOPBACK_EN(1U) + +#define S_TX_ADDR_INS 9 +#define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS) +#define F_TX_ADDR_INS V_TX_ADDR_INS(1U) + +#define S_PAUSE_IGNORE 8 +#define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE) +#define F_PAUSE_IGNORE V_PAUSE_IGNORE(1U) + +#define S_PAUSE_FWD 7 +#define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD) +#define F_PAUSE_FWD V_PAUSE_FWD(1U) + +#define S_CRC_FWD 6 +#define V_CRC_FWD(x) ((x) << S_CRC_FWD) +#define F_CRC_FWD V_CRC_FWD(1U) + +#define S_PAD_EN 5 +#define V_PAD_EN(x) ((x) << S_PAD_EN) +#define F_PAD_EN V_PAD_EN(1U) + +#define S_PROMIS_EN 4 +#define V_PROMIS_EN(x) ((x) << S_PROMIS_EN) +#define F_PROMIS_EN V_PROMIS_EN(1U) + +#define S_WAN_MODE 3 +#define V_WAN_MODE(x) ((x) << S_WAN_MODE) +#define F_WAN_MODE V_WAN_MODE(1U) + +#define S_RX_ENA 1 +#define V_RX_ENA(x) ((x) << S_RX_ENA) +#define F_RX_ENA V_RX_ENA(1U) + +#define S_TX_ENA 0 +#define V_TX_ENA(x) ((x) << S_TX_ENA) +#define F_TX_ENA V_TX_ENA(1U) + +#define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c +#define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10 + +#define S_MACADDRHI 0 +#define M_MACADDRHI 0xffffU +#define V_MACADDRHI(x) ((x) << S_MACADDRHI) +#define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI) + +#define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14 + +#define S_LEN 0 +#define M_LEN 0xffffU +#define V_LEN(x) ((x) << S_LEN) +#define G_LEN(x) (((x) >> S_LEN) & M_LEN) + +#define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c + +#define S_AVAIL 16 +#define M_AVAIL 0xffffU +#define V_AVAIL(x) ((x) << S_AVAIL) +#define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL) + +#define S_EMPTY 0 +#define M_EMPTY 0xffffU +#define V_EMPTY(x) ((x) << S_EMPTY) +#define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY) + +#define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20 +#define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24 + +#define S_ALMSTFULL 16 +#define M_ALMSTFULL 0xffffU +#define V_ALMSTFULL(x) ((x) << S_ALMSTFULL) +#define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL) + +#define S_ALMSTEMPTY 0 +#define M_ALMSTEMPTY 0xffffU +#define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY) +#define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY) + +#define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28 +#define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c + +#define S_ENABLE_MCAST_RX 8 +#define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX) +#define F_ENABLE_MCAST_RX V_ENABLE_MCAST_RX(1U) + +#define S_HASHTABLE_ADDR 0 +#define M_HASHTABLE_ADDR 0x3fU +#define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR) +#define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR) + +#define A_MAC_PORT_MTIP_MAC_STATUS 0xa40 + +#define S_TS_AVAIL 3 +#define V_TS_AVAIL(x) ((x) << S_TS_AVAIL) +#define F_TS_AVAIL V_TS_AVAIL(1U) + +#define S_PHY_LOS 2 +#define V_PHY_LOS(x) ((x) << S_PHY_LOS) +#define F_PHY_LOS V_PHY_LOS(1U) + +#define S_RX_REM_FAULT 1 +#define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT) +#define F_RX_REM_FAULT V_RX_REM_FAULT(1U) + +#define S_RX_LOC_FAULT 0 +#define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT) +#define F_RX_LOC_FAULT V_RX_LOC_FAULT(1U) + +#define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44 + +#define S_IPG 0 +#define M_IPG 0x7fU +#define V_IPG(x) ((x) << S_IPG) +#define G_IPG(x) (((x) >> S_IPG) & M_IPG) + +#define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48 + +#define S_RXFIFORST 0 +#define V_RXFIFORST(x) ((x) << S_RXFIFORST) +#define F_RXFIFORST V_RXFIFORST(1U) + +#define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c + +#define S_MACCRDRST 0 +#define M_MACCRDRST 0xffU +#define V_MACCRDRST(x) ((x) << S_MACCRDRST) +#define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST) + +#define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50 + +#define S_INITCREDIT 0 +#define M_INITCREDIT 0xffU +#define V_INITCREDIT(x) ((x) << S_INITCREDIT) +#define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT) + +#define A_MAC_PORT_RX_PAUSE_STATUS 0xa74 + +#define S_STATUS 0 +#define M_STATUS 0xffU +#define V_STATUS(x) ((x) << S_STATUS) +#define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS) + +#define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c +#define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80 +#define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84 +#define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88 +#define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c +#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90 +#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94 +#define A_MAC_PORT_AALIGNMENTERRORS 0xa98 +#define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c +#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac +#define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0 +#define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4 +#define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8 +#define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc +#define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0 +#define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4 +#define A_MAC_PORT_VLANRECEIVEDOK 0xac8 +#define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc +#define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0 +#define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4 +#define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8 +#define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc +#define A_MAC_PORT_IFINUCASTPKTS 0xae0 +#define A_MAC_PORT_IFINUCASTPKTSHI 0xae4 +#define A_MAC_PORT_IFINMULTICASTPKTS 0xae8 +#define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec +#define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0 +#define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4 +#define A_MAC_PORT_IFOUTERRORS 0xaf8 +#define A_MAC_PORT_IFOUTERRORSHI 0xafc +#define A_MAC_PORT_IFOUTUCASTPKTS 0xb08 +#define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c +#define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10 +#define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14 +#define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18 +#define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c +#define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20 +#define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24 +#define A_MAC_PORT_ETHERSTATSOCTETS 0xb28 +#define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c +#define A_MAC_PORT_ETHERSTATSPKTS 0xb30 +#define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34 +#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38 +#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c +#define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40 +#define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44 +#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48 +#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c +#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50 +#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54 +#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58 +#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c +#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60 +#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64 +#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68 +#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c +#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70 +#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74 +#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78 +#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c +#define A_MAC_PORT_ETHERSTATSJABBERS 0xb80 +#define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84 +#define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88 +#define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c +#define A_MAC_PORT_IFINERRORS 0xb90 +#define A_MAC_PORT_IFINERRORSHI 0xb94 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14 +#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18 +#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c +#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20 +#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24 +#define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00 + +#define S_RESET 15 +#define V_RESET(x) ((x) << S_RESET) +#define F_RESET V_RESET(1U) + +#define S_LOOPBACK 14 +#define V_LOOPBACK(x) ((x) << S_LOOPBACK) +#define F_LOOPBACK V_LOOPBACK(1U) + +#define S_SPPEDSEL1 13 +#define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1) +#define F_SPPEDSEL1 V_SPPEDSEL1(1U) + +#define S_AN_EN 12 +#define V_AN_EN(x) ((x) << S_AN_EN) +#define F_AN_EN V_AN_EN(1U) + +#define S_PWRDWN 11 +#define V_PWRDWN(x) ((x) << S_PWRDWN) +#define F_PWRDWN V_PWRDWN(1U) + +#define S_ISOLATE 10 +#define V_ISOLATE(x) ((x) << S_ISOLATE) +#define F_ISOLATE V_ISOLATE(1U) + +#define S_AN_RESTART 9 +#define V_AN_RESTART(x) ((x) << S_AN_RESTART) +#define F_AN_RESTART V_AN_RESTART(1U) + +#define S_DPLX 8 +#define V_DPLX(x) ((x) << S_DPLX) +#define F_DPLX V_DPLX(1U) + +#define S_COLLISIONTEST 7 +#define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST) +#define F_COLLISIONTEST V_COLLISIONTEST(1U) + +#define S_SPEEDSEL0 6 +#define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0) +#define F_SPEEDSEL0 V_SPEEDSEL0(1U) + +#define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04 + +#define S_100BASET4 15 +#define V_100BASET4(x) ((x) << S_100BASET4) +#define F_100BASET4 V_100BASET4(1U) + +#define S_100BASEXFULLDPLX 14 +#define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX) +#define F_100BASEXFULLDPLX V_100BASEXFULLDPLX(1U) + +#define S_100BASEXHALFDPLX 13 +#define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX) +#define F_100BASEXHALFDPLX V_100BASEXHALFDPLX(1U) + +#define S_10MBPSFULLDPLX 12 +#define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX) +#define F_10MBPSFULLDPLX V_10MBPSFULLDPLX(1U) + +#define S_10MBPSHALFDPLX 11 +#define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX) +#define F_10MBPSHALFDPLX V_10MBPSHALFDPLX(1U) + +#define S_100BASET2FULLDPLX 10 +#define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX) +#define F_100BASET2FULLDPLX V_100BASET2FULLDPLX(1U) + +#define S_100BASET2HALFDPLX 9 +#define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX) +#define F_100BASET2HALFDPLX V_100BASET2HALFDPLX(1U) + +#define S_EXTDSTATUS 8 +#define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS) +#define F_EXTDSTATUS V_EXTDSTATUS(1U) + +#define S_SGMII_REM_FAULT 4 +#define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT) +#define F_SGMII_REM_FAULT V_SGMII_REM_FAULT(1U) + +#define S_JABBERDETECT 1 +#define V_JABBERDETECT(x) ((x) << S_JABBERDETECT) +#define F_JABBERDETECT V_JABBERDETECT(1U) + +#define S_EXTDCAPABILITY 0 +#define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY) +#define F_EXTDCAPABILITY V_EXTDCAPABILITY(1U) + +#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08 +#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c +#define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10 + +#define S_RF2 13 +#define V_RF2(x) ((x) << S_RF2) +#define F_RF2 V_RF2(1U) + +#define S_RF1 12 +#define V_RF1(x) ((x) << S_RF1) +#define F_RF1 V_RF1(1U) + +#define S_PS2 8 +#define V_PS2(x) ((x) << S_PS2) +#define F_PS2 V_PS2(1U) + +#define S_PS1 7 +#define V_PS1(x) ((x) << S_PS1) +#define F_PS1 V_PS1(1U) + +#define S_HD 6 +#define V_HD(x) ((x) << S_HD) +#define F_HD V_HD(1U) + +#define S_FD 5 +#define V_FD(x) ((x) << S_FD) +#define F_FD V_FD(1U) + +#define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14 + +#define S_CULINKSTATUS 15 +#define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS) +#define F_CULINKSTATUS V_CULINKSTATUS(1U) + +#define S_CUDPLXSTATUS 12 +#define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS) +#define F_CUDPLXSTATUS V_CUDPLXSTATUS(1U) + +#define S_CUSPEED 10 +#define M_CUSPEED 0x3U +#define V_CUSPEED(x) ((x) << S_CUSPEED) +#define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED) + +#define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18 + +#define S_PGRCVD 1 +#define V_PGRCVD(x) ((x) << S_PGRCVD) +#define F_PGRCVD V_PGRCVD(1U) + +#define S_REALTIMEPGRCVD 0 +#define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD) +#define F_REALTIMEPGRCVD V_REALTIMEPGRCVD(1U) + +#define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c +#define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20 +#define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c +#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48 + +#define S_COUNT_LO 0 +#define M_COUNT_LO 0xffffU +#define V_COUNT_LO(x) ((x) << S_COUNT_LO) +#define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO) + +#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c + +#define S_COUNT_HI 0 +#define M_COUNT_HI 0x1fU +#define V_COUNT_HI(x) ((x) << S_COUNT_HI) +#define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI) + +#define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50 + +#define S_SGMII_PCS_ENABLE 5 +#define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE) +#define F_SGMII_PCS_ENABLE V_SGMII_PCS_ENABLE(1U) + +#define S_SGMII_HDUPLEX 4 +#define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX) +#define F_SGMII_HDUPLEX V_SGMII_HDUPLEX(1U) + +#define S_SGMII_SPEED 2 +#define M_SGMII_SPEED 0x3U +#define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED) +#define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED) + +#define S_USE_SGMII_AN 1 +#define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN) +#define F_USE_SGMII_AN V_USE_SGMII_AN(1U) + +#define S_SGMII_ENA 0 +#define V_SGMII_ENA(x) ((x) << S_SGMII_ENA) +#define F_SGMII_ENA V_SGMII_ENA(1U) + +#define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200 + +#define S_ACTIVE 0 +#define M_ACTIVE 0x3fU +#define V_ACTIVE(x) ((x) << S_ACTIVE) +#define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE) + +#define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204 + +#define S_MODE_CTL 0 +#define M_MODE_CTL 0x3U +#define V_MODE_CTL(x) ((x) << S_MODE_CTL) +#define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL) + +#define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208 + +#define S_TXCLK_CTL 0 +#define M_TXCLK_CTL 0xffffU +#define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL) +#define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL) + +#define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c +#define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220 + +#define S_COL_CNT 0 +#define M_COL_CNT 0xffffU +#define V_COL_CNT(x) ((x) << S_COL_CNT) +#define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT) + +#define A_MAC_PORT_MTIP_VL_INTVL 0x1240 + +#define S_VL_INTVL 1 +#define V_VL_INTVL(x) ((x) << S_VL_INTVL) +#define F_VL_INTVL V_VL_INTVL(1U) + +#define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600 + +#define S_CLK_DIV 7 +#define M_CLK_DIV 0x1ffU +#define V_CLK_DIV(x) ((x) << S_CLK_DIV) +#define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV) + +#define S_CL45_EN 6 +#define V_CL45_EN(x) ((x) << S_CL45_EN) +#define F_CL45_EN V_CL45_EN(1U) + +#define S_DISABLE_PREAMBLE 5 +#define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE) +#define F_DISABLE_PREAMBLE V_DISABLE_PREAMBLE(1U) + +#define S_MDIO_HOLD_TIME 2 +#define M_MDIO_HOLD_TIME 0x7U +#define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME) +#define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME) + +#define S_MDIO_READ_ERR 1 +#define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR) +#define F_MDIO_READ_ERR V_MDIO_READ_ERR(1U) + +#define S_MDIO_BUSY 0 +#define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY) +#define F_MDIO_BUSY V_MDIO_BUSY(1U) + +#define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604 + +#define S_MDIO_CMD_READ 15 +#define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ) +#define F_MDIO_CMD_READ V_MDIO_CMD_READ(1U) + +#define S_READ_INCR 14 +#define V_READ_INCR(x) ((x) << S_READ_INCR) +#define F_READ_INCR V_READ_INCR(1U) + +#define S_PORT_ADDR 5 +#define M_PORT_ADDR 0x1fU +#define V_PORT_ADDR(x) ((x) << S_PORT_ADDR) +#define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR) + +#define S_DEV_ADDR 0 +#define M_DEV_ADDR 0x1fU +#define V_DEV_ADDR(x) ((x) << S_DEV_ADDR) +#define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR) + +#define A_MAC_PORT_MTIP_MDIO_DATA 0x1608 + +#define S_READBUSY 31 +#define V_READBUSY(x) ((x) << S_READBUSY) +#define F_READBUSY V_READBUSY(1U) + +#define S_DATA_WORD 0 +#define M_DATA_WORD 0xffffU +#define V_DATA_WORD(x) ((x) << S_DATA_WORD) +#define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD) + +#define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c + +#define S_MDIO_ADDR 0 +#define M_MDIO_ADDR 0xffffU +#define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR) +#define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR) + +#define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00 + +#if 0 /* M_VLANTAG collides with M_VLANTAG in sys/mbuf.h */ +#define S_VLANTAG 0 +#define M_VLANTAG 0xffffU +#define V_VLANTAG(x) ((x) << S_VLANTAG) +#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG) +#endif + +#define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04 +#define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08 +#define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c +#define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10 +#define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14 +#define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18 +#define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c +#define A_MAC_PORT_MTIP_PCS_CTL 0x1e00 + +#define S_PCS_LPBK 14 +#define V_PCS_LPBK(x) ((x) << S_PCS_LPBK) +#define F_PCS_LPBK V_PCS_LPBK(1U) + +#define S_SPEED_SEL1 13 +#define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1) +#define F_SPEED_SEL1 V_SPEED_SEL1(1U) + +#define S_LP_MODE 11 +#define V_LP_MODE(x) ((x) << S_LP_MODE) +#define F_LP_MODE V_LP_MODE(1U) + +#define S_SPEED_SEL0 6 +#define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0) +#define F_SPEED_SEL0 V_SPEED_SEL0(1U) + +#define S_PCS_SPEED 2 +#define M_PCS_SPEED 0xfU +#define V_PCS_SPEED(x) ((x) << S_PCS_SPEED) +#define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED) + +#define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04 + +#define S_FAULTDET 7 +#define V_FAULTDET(x) ((x) << S_FAULTDET) +#define F_FAULTDET V_FAULTDET(1U) + +#define S_RX_LINK_STATUS 2 +#define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS) +#define F_RX_LINK_STATUS V_RX_LINK_STATUS(1U) + +#define S_LOPWRABL 1 +#define V_LOPWRABL(x) ((x) << S_LOPWRABL) +#define F_LOPWRABL V_LOPWRABL(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08 + +#define S_DEVICE_ID0 0 +#define M_DEVICE_ID0 0xffffU +#define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0) +#define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c + +#define S_DEVICE_ID1 0 +#define M_DEVICE_ID1 0xffffU +#define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1) +#define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1) + +#define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10 + +#define S_100G 8 +#define V_100G(x) ((x) << S_100G) +#define F_100G V_100G(1U) + +#define S_40G 7 +#define V_40G(x) ((x) << S_40G) +#define F_40G V_40G(1U) + +#define S_10BASE_TL 1 +#define V_10BASE_TL(x) ((x) << S_10BASE_TL) +#define F_10BASE_TL V_10BASE_TL(1U) + +#define S_10G 0 +#define V_10G(x) ((x) << S_10G) +#define F_10G V_10G(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14 + +#define S_TC_PRESENT 6 +#define V_TC_PRESENT(x) ((x) << S_TC_PRESENT) +#define F_TC_PRESENT V_TC_PRESENT(1U) + +#define S_DTEXS 5 +#define V_DTEXS(x) ((x) << S_DTEXS) +#define F_DTEXS V_DTEXS(1U) + +#define S_PHYXS 4 +#define V_PHYXS(x) ((x) << S_PHYXS) +#define F_PHYXS V_PHYXS(1U) + +#define S_PCS 3 +#define V_PCS(x) ((x) << S_PCS) +#define F_PCS V_PCS(1U) + +#define S_WIS 2 +#define V_WIS(x) ((x) << S_WIS) +#define F_WIS V_WIS(1U) + +#define S_PMD_PMA 1 +#define V_PMD_PMA(x) ((x) << S_PMD_PMA) +#define F_PMD_PMA V_PMD_PMA(1U) + +#define S_CL22 0 +#define V_CL22(x) ((x) << S_CL22) +#define F_CL22 V_CL22(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18 + +#define S_VENDDEV2 15 +#define V_VENDDEV2(x) ((x) << S_VENDDEV2) +#define F_VENDDEV2 V_VENDDEV2(1U) + +#define S_VENDDEV1 14 +#define V_VENDDEV1(x) ((x) << S_VENDDEV1) +#define F_VENDDEV1 V_VENDDEV1(1U) + +#define S_CL22EXT 13 +#define V_CL22EXT(x) ((x) << S_CL22EXT) +#define F_CL22EXT V_CL22EXT(1U) + +#define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c + +#define S_PCSTYPE 0 +#define M_PCSTYPE 0x7U +#define V_PCSTYPE(x) ((x) << S_PCSTYPE) +#define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE) + +#define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20 + +#define S_PCS_STAT2_DEVICE 15 +#define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE) +#define F_PCS_STAT2_DEVICE V_PCS_STAT2_DEVICE(1U) + +#define S_TXFAULT 7 +#define V_TXFAULT(x) ((x) << S_TXFAULT) +#define F_TXFAULT V_TXFAULT(1U) + +#define S_RXFAULT 6 +#define V_RXFAULT(x) ((x) << S_RXFAULT) +#define F_RXFAULT V_RXFAULT(1U) + +#define S_100BASE_R 5 +#define V_100BASE_R(x) ((x) << S_100BASE_R) +#define F_100BASE_R V_100BASE_R(1U) + +#define S_40GBASE_R 4 +#define V_40GBASE_R(x) ((x) << S_40GBASE_R) +#define F_40GBASE_R V_40GBASE_R(1U) + +#define S_10GBASE_T 3 +#define V_10GBASE_T(x) ((x) << S_10GBASE_T) +#define F_10GBASE_T V_10GBASE_T(1U) + +#define S_10GBASE_W 2 +#define V_10GBASE_W(x) ((x) << S_10GBASE_W) +#define F_10GBASE_W V_10GBASE_W(1U) + +#define S_10GBASE_X 1 +#define V_10GBASE_X(x) ((x) << S_10GBASE_X) +#define F_10GBASE_X V_10GBASE_X(1U) + +#define S_10GBASE_R 0 +#define V_10GBASE_R(x) ((x) << S_10GBASE_R) +#define F_10GBASE_R V_10GBASE_R(1U) + +#define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38 + +#define S_PKG_ID0 0 +#define M_PKG_ID0 0xffffU +#define V_PKG_ID0(x) ((x) << S_PKG_ID0) +#define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0) + +#define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c + +#define S_PKG_ID1 0 +#define M_PKG_ID1 0xffffU +#define V_PKG_ID1(x) ((x) << S_PKG_ID1) +#define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1) + +#define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80 + +#define S_RXLINKSTATUS 12 +#define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS) +#define F_RXLINKSTATUS V_RXLINKSTATUS(1U) + +#define S_RESEREVED 4 +#define M_RESEREVED 0xffU +#define V_RESEREVED(x) ((x) << S_RESEREVED) +#define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED) + +#define S_10GPRBS9 3 +#define V_10GPRBS9(x) ((x) << S_10GPRBS9) +#define F_10GPRBS9 V_10GPRBS9(1U) + +#define S_10GPRBS31 2 +#define V_10GPRBS31(x) ((x) << S_10GPRBS31) +#define F_10GPRBS31 V_10GPRBS31(1U) + +#define S_HIBER 1 +#define V_HIBER(x) ((x) << S_HIBER) +#define F_HIBER V_HIBER(1U) + +#define S_BLOCKLOCK 0 +#define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK) +#define F_BLOCKLOCK V_BLOCKLOCK(1U) + +#define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84 + +#define S_BLOCKLOCKLL 15 +#define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL) +#define F_BLOCKLOCKLL V_BLOCKLOCKLL(1U) + +#define S_HIBERLH 14 +#define V_HIBERLH(x) ((x) << S_HIBERLH) +#define F_HIBERLH V_HIBERLH(1U) + +#define S_HIBERCOUNT 8 +#define M_HIBERCOUNT 0x3fU +#define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT) +#define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT) + +#define S_ERRBLKCNT 0 +#define M_ERRBLKCNT 0xffU +#define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT) +#define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88 + +#define S_SEEDA 0 +#define M_SEEDA 0xffffU +#define V_SEEDA(x) ((x) << S_SEEDA) +#define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c + +#define S_SEEDA1 0 +#define M_SEEDA1 0xffffU +#define V_SEEDA1(x) ((x) << S_SEEDA1) +#define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90 + +#define S_SEEDA2 0 +#define M_SEEDA2 0xffffU +#define V_SEEDA2(x) ((x) << S_SEEDA2) +#define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94 + +#define S_SEEDA3 0 +#define M_SEEDA3 0x3ffU +#define V_SEEDA3(x) ((x) << S_SEEDA3) +#define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98 + +#define S_SEEDB 0 +#define M_SEEDB 0xffffU +#define V_SEEDB(x) ((x) << S_SEEDB) +#define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c + +#define S_SEEDB1 0 +#define M_SEEDB1 0xffffU +#define V_SEEDB1(x) ((x) << S_SEEDB1) +#define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0 + +#define S_SEEDB2 0 +#define M_SEEDB2 0xffffU +#define V_SEEDB2(x) ((x) << S_SEEDB2) +#define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4 + +#define S_SEEDB3 0 +#define M_SEEDB3 0x3ffU +#define V_SEEDB3(x) ((x) << S_SEEDB3) +#define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3) + +#define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8 + +#define S_TXPRBS9 6 +#define V_TXPRBS9(x) ((x) << S_TXPRBS9) +#define F_TXPRBS9 V_TXPRBS9(1U) + +#define S_RXPRBS31 5 +#define V_RXPRBS31(x) ((x) << S_RXPRBS31) +#define F_RXPRBS31 V_RXPRBS31(1U) + +#define S_TXPRBS31 4 +#define V_TXPRBS31(x) ((x) << S_TXPRBS31) +#define F_TXPRBS31 V_TXPRBS31(1U) + +#define S_TXTESTPATEN 3 +#define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN) +#define F_TXTESTPATEN V_TXTESTPATEN(1U) + +#define S_RXTESTPATEN 2 +#define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN) +#define F_RXTESTPATEN V_RXTESTPATEN(1U) + +#define S_TESTPATSEL 1 +#define V_TESTPATSEL(x) ((x) << S_TESTPATSEL) +#define F_TESTPATSEL V_TESTPATSEL(1U) + +#define S_DATAPATSEL 0 +#define V_DATAPATSEL(x) ((x) << S_DATAPATSEL) +#define F_DATAPATSEL V_DATAPATSEL(1U) + +#define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac + +#define S_TEST_ERR_CNT 0 +#define M_TEST_ERR_CNT 0xffffU +#define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT) +#define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT) + +#define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0 + +#define S_BER_CNT_HI 0 +#define M_BER_CNT_HI 0xffffU +#define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI) +#define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI) + +#define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4 + +#define S_HICOUNTPRSNT 15 +#define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT) +#define F_HICOUNTPRSNT V_HICOUNTPRSNT(1U) + +#define S_BLOCK_CNT_HI 0 +#define M_BLOCK_CNT_HI 0x3fffU +#define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI) +#define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8 + +#define S_ALIGNSTATUS 12 +#define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS) +#define F_ALIGNSTATUS V_ALIGNSTATUS(1U) + +#define S_LANE7 7 +#define V_LANE7(x) ((x) << S_LANE7) +#define F_LANE7 V_LANE7(1U) + +#define S_LANE6 6 +#define V_LANE6(x) ((x) << S_LANE6) +#define F_LANE6 V_LANE6(1U) + +#define S_LANE5 5 +#define V_LANE5(x) ((x) << S_LANE5) +#define F_LANE5 V_LANE5(1U) + +#define S_LANE4 4 +#define V_LANE4(x) ((x) << S_LANE4) +#define F_LANE4 V_LANE4(1U) + +#define S_LANE3 3 +#define V_LANE3(x) ((x) << S_LANE3) +#define F_LANE3 V_LANE3(1U) + +#define S_LANE2 2 +#define V_LANE2(x) ((x) << S_LANE2) +#define F_LANE2 V_LANE2(1U) + +#define S_LANE1 1 +#define V_LANE1(x) ((x) << S_LANE1) +#define F_LANE1 V_LANE1(1U) + +#define S_LANE0 0 +#define V_LANE0(x) ((x) << S_LANE0) +#define F_LANE0 V_LANE0(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc + +#define S_LANE19 11 +#define V_LANE19(x) ((x) << S_LANE19) +#define F_LANE19 V_LANE19(1U) + +#define S_LANE18 10 +#define V_LANE18(x) ((x) << S_LANE18) +#define F_LANE18 V_LANE18(1U) + +#define S_LANE17 9 +#define V_LANE17(x) ((x) << S_LANE17) +#define F_LANE17 V_LANE17(1U) + +#define S_LANE16 8 +#define V_LANE16(x) ((x) << S_LANE16) +#define F_LANE16 V_LANE16(1U) + +#define S_LANE15 7 +#define V_LANE15(x) ((x) << S_LANE15) +#define F_LANE15 V_LANE15(1U) + +#define S_LANE14 6 +#define V_LANE14(x) ((x) << S_LANE14) +#define F_LANE14 V_LANE14(1U) + +#define S_LANE13 5 +#define V_LANE13(x) ((x) << S_LANE13) +#define F_LANE13 V_LANE13(1U) + +#define S_LANE12 4 +#define V_LANE12(x) ((x) << S_LANE12) +#define F_LANE12 V_LANE12(1U) + +#define S_LANE11 3 +#define V_LANE11(x) ((x) << S_LANE11) +#define F_LANE11 V_LANE11(1U) + +#define S_LANE10 2 +#define V_LANE10(x) ((x) << S_LANE10) +#define F_LANE10 V_LANE10(1U) + +#define S_LANE9 1 +#define V_LANE9(x) ((x) << S_LANE9) +#define F_LANE9 V_LANE9(1U) + +#define S_LANE8 0 +#define V_LANE8(x) ((x) << S_LANE8) +#define F_LANE8 V_LANE8(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0 + +#define S_AMLOCK7 7 +#define V_AMLOCK7(x) ((x) << S_AMLOCK7) +#define F_AMLOCK7 V_AMLOCK7(1U) + +#define S_AMLOCK6 6 +#define V_AMLOCK6(x) ((x) << S_AMLOCK6) +#define F_AMLOCK6 V_AMLOCK6(1U) + +#define S_AMLOCK5 5 +#define V_AMLOCK5(x) ((x) << S_AMLOCK5) +#define F_AMLOCK5 V_AMLOCK5(1U) + +#define S_AMLOCK4 4 +#define V_AMLOCK4(x) ((x) << S_AMLOCK4) +#define F_AMLOCK4 V_AMLOCK4(1U) + +#define S_AMLOCK3 3 +#define V_AMLOCK3(x) ((x) << S_AMLOCK3) +#define F_AMLOCK3 V_AMLOCK3(1U) + +#define S_AMLOCK2 2 +#define V_AMLOCK2(x) ((x) << S_AMLOCK2) +#define F_AMLOCK2 V_AMLOCK2(1U) + +#define S_AMLOCK1 1 +#define V_AMLOCK1(x) ((x) << S_AMLOCK1) +#define F_AMLOCK1 V_AMLOCK1(1U) + +#define S_AMLOCK0 0 +#define V_AMLOCK0(x) ((x) << S_AMLOCK0) +#define F_AMLOCK0 V_AMLOCK0(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4 + +#define S_AMLOCK19 11 +#define V_AMLOCK19(x) ((x) << S_AMLOCK19) +#define F_AMLOCK19 V_AMLOCK19(1U) + +#define S_AMLOCK18 10 +#define V_AMLOCK18(x) ((x) << S_AMLOCK18) +#define F_AMLOCK18 V_AMLOCK18(1U) + +#define S_AMLOCK17 9 +#define V_AMLOCK17(x) ((x) << S_AMLOCK17) +#define F_AMLOCK17 V_AMLOCK17(1U) + +#define S_AMLOCK16 8 +#define V_AMLOCK16(x) ((x) << S_AMLOCK16) +#define F_AMLOCK16 V_AMLOCK16(1U) + +#define S_AMLOCK15 7 +#define V_AMLOCK15(x) ((x) << S_AMLOCK15) +#define F_AMLOCK15 V_AMLOCK15(1U) + +#define S_AMLOCK14 6 +#define V_AMLOCK14(x) ((x) << S_AMLOCK14) +#define F_AMLOCK14 V_AMLOCK14(1U) + +#define S_AMLOCK13 5 +#define V_AMLOCK13(x) ((x) << S_AMLOCK13) +#define F_AMLOCK13 V_AMLOCK13(1U) + +#define S_AMLOCK12 4 +#define V_AMLOCK12(x) ((x) << S_AMLOCK12) +#define F_AMLOCK12 V_AMLOCK12(1U) + +#define S_AMLOCK11 3 +#define V_AMLOCK11(x) ((x) << S_AMLOCK11) +#define F_AMLOCK11 V_AMLOCK11(1U) + +#define S_AMLOCK10 2 +#define V_AMLOCK10(x) ((x) << S_AMLOCK10) +#define F_AMLOCK10 V_AMLOCK10(1U) + +#define S_AMLOCK9 1 +#define V_AMLOCK9(x) ((x) << S_AMLOCK9) +#define F_AMLOCK9 V_AMLOCK9(1U) + +#define S_AMLOCK8 0 +#define V_AMLOCK8(x) ((x) << S_AMLOCK8) +#define F_AMLOCK8 V_AMLOCK8(1U) + +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68 + +#define S_BIPERR_CNT 0 +#define M_BIPERR_CNT 0xffffU +#define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT) +#define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT) + +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8 + +#define S_MAP 0 +#define M_MAP 0x1fU +#define V_MAP(x) ((x) << S_MAP) +#define G_MAP(x) (((x) >> S_MAP) & M_MAP) + +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004 +#define A_MAC_PORT_BEAN_CTL 0x2200 + +#define S_AN_RESET 15 +#define V_AN_RESET(x) ((x) << S_AN_RESET) +#define F_AN_RESET V_AN_RESET(1U) + +#define S_EXT_NXP_CTRL 13 +#define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL) +#define F_EXT_NXP_CTRL V_EXT_NXP_CTRL(1U) + +#define S_BEAN_EN 12 +#define V_BEAN_EN(x) ((x) << S_BEAN_EN) +#define F_BEAN_EN V_BEAN_EN(1U) + +#define S_RESTART_BEAN 9 +#define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN) +#define F_RESTART_BEAN V_RESTART_BEAN(1U) + +#define A_MAC_PORT_BEAN_STATUS 0x2204 + +#define S_PDF 9 +#define V_PDF(x) ((x) << S_PDF) +#define F_PDF V_PDF(1U) + +#define S_EXT_NXP_STATUS 7 +#define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS) +#define F_EXT_NXP_STATUS V_EXT_NXP_STATUS(1U) + +#define S_PAGE_RCVD 6 +#define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD) +#define F_PAGE_RCVD V_PAGE_RCVD(1U) + +#define S_BEAN_COMPLETE 5 +#define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE) +#define F_BEAN_COMPLETE V_BEAN_COMPLETE(1U) + +#define S_REM_FAULT_STATUS 4 +#define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS) +#define F_REM_FAULT_STATUS V_REM_FAULT_STATUS(1U) + +#define S_BEAN_ABILITY 3 +#define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY) +#define F_BEAN_ABILITY V_BEAN_ABILITY(1U) + +#define S_LP_BEAN_ABILITY 0 +#define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY) +#define F_LP_BEAN_ABILITY V_LP_BEAN_ABILITY(1U) + +#define A_MAC_PORT_BEAN_ABILITY_0 0x2208 + +#define S_NXP 15 +#define V_NXP(x) ((x) << S_NXP) +#define F_NXP V_NXP(1U) + +#define S_REM_FAULT 13 +#define V_REM_FAULT(x) ((x) << S_REM_FAULT) +#define F_REM_FAULT V_REM_FAULT(1U) + +#define S_PAUSE_ABILITY 10 +#define M_PAUSE_ABILITY 0x7U +#define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY) +#define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY) + +#define S_ECHO_NONCE 5 +#define M_ECHO_NONCE 0x1fU +#define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE) +#define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE) + +#define S_SELECTOR 0 +#define M_SELECTOR 0x1fU +#define V_SELECTOR(x) ((x) << S_SELECTOR) +#define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR) + +#define A_MAC_PORT_BEAN_ABILITY_1 0x220c + +#define S_TECH_ABILITY_1 5 +#define M_TECH_ABILITY_1 0x7ffU +#define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1) +#define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1) + +#define S_TX_NONCE 0 +#define M_TX_NONCE 0x1fU +#define V_TX_NONCE(x) ((x) << S_TX_NONCE) +#define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE) + +#define A_MAC_PORT_BEAN_ABILITY_2 0x2210 + +#define S_T5_FEC_ABILITY 14 +#define M_T5_FEC_ABILITY 0x3U +#define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY) +#define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY) + +#define S_TECH_ABILITY_2 0 +#define M_TECH_ABILITY_2 0x3fffU +#define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2) +#define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2) + +#define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214 +#define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218 +#define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c +#define A_MAC_PORT_BEAN_MS_COUNT 0x2220 + +#define S_MS_COUNT 0 +#define M_MS_COUNT 0xffffU +#define V_MS_COUNT(x) ((x) << S_MS_COUNT) +#define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT) + +#define A_MAC_PORT_BEAN_XNP_0 0x2224 + +#define S_XNP 15 +#define V_XNP(x) ((x) << S_XNP) +#define F_XNP V_XNP(1U) + +#define S_ACKNOWLEDGE 14 +#define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE) +#define F_ACKNOWLEDGE V_ACKNOWLEDGE(1U) + +#define S_MP 13 +#define V_MP(x) ((x) << S_MP) +#define F_MP V_MP(1U) + +#define S_ACK2 12 +#define V_ACK2(x) ((x) << S_ACK2) +#define F_ACK2 V_ACK2(1U) + +#define S_MU 0 +#define M_MU 0x7ffU +#define V_MU(x) ((x) << S_MU) +#define G_MU(x) (((x) >> S_MU) & M_MU) + +#define A_MAC_PORT_BEAN_XNP_1 0x2228 + +#define S_UNFORMATED 0 +#define M_UNFORMATED 0xffffU +#define V_UNFORMATED(x) ((x) << S_UNFORMATED) +#define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED) + +#define A_MAC_PORT_BEAN_XNP_2 0x222c +#define A_MAC_PORT_LP_BEAN_XNP_0 0x2230 +#define A_MAC_PORT_LP_BEAN_XNP_1 0x2234 +#define A_MAC_PORT_LP_BEAN_XNP_2 0x2238 +#define A_MAC_PORT_BEAN_ETH_STATUS 0x223c + +#define S_100GCR10 8 +#define V_100GCR10(x) ((x) << S_100GCR10) +#define F_100GCR10 V_100GCR10(1U) + +#define S_40GCR4 6 +#define V_40GCR4(x) ((x) << S_40GCR4) +#define F_40GCR4 V_40GCR4(1U) + +#define S_40GKR4 5 +#define V_40GKR4(x) ((x) << S_40GKR4) +#define F_40GKR4 V_40GKR4(1U) + +#define S_FEC 4 +#define V_FEC(x) ((x) << S_FEC) +#define F_FEC V_FEC(1U) + +#define S_10GKR 3 +#define V_10GKR(x) ((x) << S_10GKR) +#define F_10GKR V_10GKR(1U) + +#define S_10GKX4 2 +#define V_10GKX4(x) ((x) << S_10GKX4) +#define F_10GKX4 V_10GKX4(1U) + +#define S_1GKX 1 +#define V_1GKX(x) ((x) << S_1GKX) +#define F_1GKX V_1GKX(1U) + +#define A_MAC_PORT_BEAN_CTL_LANE1 0x2240 +#define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c +#define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c +#define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260 +#define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264 +#define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268 +#define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c +#define A_MAC_PORT_BEAN_CTL_LANE2 0x2280 +#define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c +#define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c +#define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0 +#define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4 +#define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8 +#define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc +#define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0 +#define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc +#define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc +#define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0 +#define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4 +#define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8 +#define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc +#define A_MAC_PORT_FEC_KR_CONTROL 0x2600 + +#define S_ENABLE_TR 1 +#define V_ENABLE_TR(x) ((x) << S_ENABLE_TR) +#define F_ENABLE_TR V_ENABLE_TR(1U) + +#define S_RESTART_TR 0 +#define V_RESTART_TR(x) ((x) << S_RESTART_TR) +#define F_RESTART_TR V_RESTART_TR(1U) + +#define A_MAC_PORT_FEC_KR_STATUS 0x2604 + +#define S_FECKRSIGDET 15 +#define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET) +#define F_FECKRSIGDET V_FECKRSIGDET(1U) + +#define S_TRAIN_FAIL 3 +#define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL) +#define F_TRAIN_FAIL V_TRAIN_FAIL(1U) + +#define S_STARTUP_STATUS 2 +#define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS) +#define F_STARTUP_STATUS V_STARTUP_STATUS(1U) + +#define S_RX_STATUS 0 +#define V_RX_STATUS(x) ((x) << S_RX_STATUS) +#define F_RX_STATUS V_RX_STATUS(1U) + +#define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608 + +#define S_PRESET 13 +#define V_PRESET(x) ((x) << S_PRESET) +#define F_PRESET V_PRESET(1U) + +#define S_INITIALIZE 12 +#define V_INITIALIZE(x) ((x) << S_INITIALIZE) +#define F_INITIALIZE V_INITIALIZE(1U) + +#define S_CP1_UPD 4 +#define M_CP1_UPD 0x3U +#define V_CP1_UPD(x) ((x) << S_CP1_UPD) +#define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD) + +#define S_C0_UPD 2 +#define M_C0_UPD 0x3U +#define V_C0_UPD(x) ((x) << S_C0_UPD) +#define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD) + +#define S_CN1_UPD 0 +#define M_CN1_UPD 0x3U +#define V_CN1_UPD(x) ((x) << S_CN1_UPD) +#define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD) + +#define A_MAC_PORT_FEC_KR_LP_STAT 0x260c + +#define S_RX_READY 15 +#define V_RX_READY(x) ((x) << S_RX_READY) +#define F_RX_READY V_RX_READY(1U) + +#define S_CP1_STAT 4 +#define M_CP1_STAT 0x3U +#define V_CP1_STAT(x) ((x) << S_CP1_STAT) +#define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT) + +#define S_C0_STAT 2 +#define M_C0_STAT 0x3U +#define V_C0_STAT(x) ((x) << S_C0_STAT) +#define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT) + +#define S_CN1_STAT 0 +#define M_CN1_STAT 0x3U +#define V_CN1_STAT(x) ((x) << S_CN1_STAT) +#define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT) + +#define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610 +#define A_MAC_PORT_FEC_KR_LD_STAT 0x2614 +#define A_MAC_PORT_FEC_ABILITY 0x2618 + +#define S_FEC_IND_ABILITY 1 +#define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY) +#define F_FEC_IND_ABILITY V_FEC_IND_ABILITY(1U) + +#define S_ABILITY 0 +#define V_ABILITY(x) ((x) << S_ABILITY) +#define F_ABILITY V_ABILITY(1U) + +#define A_MAC_PORT_FEC_CONTROL 0x261c + +#define S_FEC_EN_ERR_IND 1 +#define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND) +#define F_FEC_EN_ERR_IND V_FEC_EN_ERR_IND(1U) + +#define S_FEC_EN 0 +#define V_FEC_EN(x) ((x) << S_FEC_EN) +#define F_FEC_EN V_FEC_EN(1U) + +#define A_MAC_PORT_FEC_STATUS 0x2620 + +#define S_FEC_LOCKED_100 1 +#define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100) +#define F_FEC_LOCKED_100 V_FEC_LOCKED_100(1U) + +#define S_FEC_LOCKED 0 +#define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED) +#define F_FEC_LOCKED V_FEC_LOCKED(1U) + +#define A_MAC_PORT_FEC_CERR_CNT_0 0x2624 + +#define S_FEC_CERR_CNT_0 0 +#define M_FEC_CERR_CNT_0 0xffffU +#define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0) +#define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0) + +#define A_MAC_PORT_FEC_CERR_CNT_1 0x2628 + +#define S_FEC_CERR_CNT_1 0 +#define M_FEC_CERR_CNT_1 0xffffU +#define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1) +#define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1) + +#define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c + +#define S_FEC_NCERR_CNT_0 0 +#define M_FEC_NCERR_CNT_0 0xffffU +#define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0) +#define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0) + +#define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630 + +#define S_FEC_NCERR_CNT_1 0 +#define M_FEC_NCERR_CNT_1 0xffffU +#define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1) +#define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1) + +#define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00 + +#define S_T5_RXREQ_C2 4 +#define M_T5_RXREQ_C2 0x3U +#define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2) +#define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2) + +#define S_T5_RXREQ_C1 2 +#define M_T5_RXREQ_C1 0x3U +#define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1) +#define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1) + +#define S_T5_RXREQ_C0 0 +#define M_T5_RXREQ_C0 0x3U +#define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0) +#define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0) + +#define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04 + +#define S_T5_AE0_RXSTAT_RDY 15 +#define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY) +#define F_T5_AE0_RXSTAT_RDY V_T5_AE0_RXSTAT_RDY(1U) + +#define S_T5_AE0_RXSTAT_C2 4 +#define M_T5_AE0_RXSTAT_C2 0x3U +#define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2) +#define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2) + +#define S_T5_AE0_RXSTAT_C1 2 +#define M_T5_AE0_RXSTAT_C1 0x3U +#define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1) +#define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1) + +#define S_T5_AE0_RXSTAT_C0 0 +#define M_T5_AE0_RXSTAT_C0 0x3U +#define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0) +#define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08 + +#define S_T5_TXREQ_C2 4 +#define M_T5_TXREQ_C2 0x3U +#define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2) +#define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2) + +#define S_T5_TXREQ_C1 2 +#define M_T5_TXREQ_C1 0x3U +#define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1) +#define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1) + +#define S_T5_TXREQ_C0 0 +#define M_T5_TXREQ_C0 0x3U +#define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0) +#define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0) + +#define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c + +#define S_T5_TXSTAT_C2 4 +#define M_T5_TXSTAT_C2 0x3U +#define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2) +#define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2) + +#define S_T5_TXSTAT_C1 2 +#define M_T5_TXSTAT_C1 0x3U +#define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1) +#define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1) + +#define S_T5_TXSTAT_C0 0 +#define M_T5_TXSTAT_C0 0x3U +#define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0) +#define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0) + +#define A_MAC_PORT_AE_REG_MODE 0x2a10 + +#define S_AET_RSVD 7 +#define V_AET_RSVD(x) ((x) << S_AET_RSVD) +#define F_AET_RSVD V_AET_RSVD(1U) + +#define S_AET_ENABLE 6 +#define V_AET_ENABLE(x) ((x) << S_AET_ENABLE) +#define F_AET_ENABLE V_AET_ENABLE(1U) + +#define A_MAC_PORT_AE_PRBS_CTL 0x2a14 +#define A_MAC_PORT_AE_FSM_CTL 0x2a18 + +#define S_CIN_ENABLE 15 +#define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE) +#define F_CIN_ENABLE V_CIN_ENABLE(1U) + +#define A_MAC_PORT_AE_FSM_STATE 0x2a1c +#define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20 +#define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24 + +#define S_T5_AE1_RXSTAT_RDY 15 +#define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY) +#define F_T5_AE1_RXSTAT_RDY V_T5_AE1_RXSTAT_RDY(1U) + +#define S_T5_AE1_RXSTAT_C2 4 +#define M_T5_AE1_RXSTAT_C2 0x3U +#define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2) +#define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2) + +#define S_T5_AE1_RXSTAT_C1 2 +#define M_T5_AE1_RXSTAT_C1 0x3U +#define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1) +#define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1) + +#define S_T5_AE1_RXSTAT_C0 0 +#define M_T5_AE1_RXSTAT_C0 0x3U +#define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0) +#define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28 +#define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c +#define A_MAC_PORT_AE_REG_MODE_1 0x2a30 +#define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34 +#define A_MAC_PORT_AE_FSM_CTL_1 0x2a38 +#define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c +#define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40 +#define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44 + +#define S_T5_AE2_RXSTAT_RDY 15 +#define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY) +#define F_T5_AE2_RXSTAT_RDY V_T5_AE2_RXSTAT_RDY(1U) + +#define S_T5_AE2_RXSTAT_C2 4 +#define M_T5_AE2_RXSTAT_C2 0x3U +#define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2) +#define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2) + +#define S_T5_AE2_RXSTAT_C1 2 +#define M_T5_AE2_RXSTAT_C1 0x3U +#define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1) +#define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1) + +#define S_T5_AE2_RXSTAT_C0 0 +#define M_T5_AE2_RXSTAT_C0 0x3U +#define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0) +#define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48 +#define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c +#define A_MAC_PORT_AE_REG_MODE_2 0x2a50 +#define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54 +#define A_MAC_PORT_AE_FSM_CTL_2 0x2a58 +#define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c +#define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60 +#define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64 + +#define S_T5_AE3_RXSTAT_RDY 15 +#define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY) +#define F_T5_AE3_RXSTAT_RDY V_T5_AE3_RXSTAT_RDY(1U) + +#define S_T5_AE3_RXSTAT_C2 4 +#define M_T5_AE3_RXSTAT_C2 0x3U +#define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2) +#define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2) + +#define S_T5_AE3_RXSTAT_C1 2 +#define M_T5_AE3_RXSTAT_C1 0x3U +#define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1) +#define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1) + +#define S_T5_AE3_RXSTAT_C0 0 +#define M_T5_AE3_RXSTAT_C0 0x3U +#define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0) +#define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68 +#define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c +#define A_MAC_PORT_AE_REG_MODE_3 0x2a70 +#define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74 +#define A_MAC_PORT_AE_FSM_CTL_3 0x2a78 +#define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c +#define A_MAC_PORT_AE_TX_DIS 0x2a80 +#define A_MAC_PORT_AE_KR_CTRL 0x2a84 +#define A_MAC_PORT_AE_RX_SIGDET 0x2a88 +#define A_MAC_PORT_AE_KR_STATUS 0x2a8c +#define A_MAC_PORT_AE_TX_DIS_1 0x2a90 +#define A_MAC_PORT_AE_KR_CTRL_1 0x2a94 +#define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98 +#define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c +#define A_MAC_PORT_AE_TX_DIS_2 0x2aa0 +#define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4 +#define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8 +#define A_MAC_PORT_AE_KR_STATUS_2 0x2aac +#define A_MAC_PORT_AE_TX_DIS_3 0x2ab0 +#define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4 +#define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8 +#define A_MAC_PORT_AE_KR_STATUS_3 0x2abc +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00 + +#define S_EN_HOLD_FAIL 14 +#define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL) +#define F_EN_HOLD_FAIL V_EN_HOLD_FAIL(1U) + +#define S_INIT_METH 12 +#define M_INIT_METH 0x3U +#define V_INIT_METH(x) ((x) << S_INIT_METH) +#define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH) + +#define S_CE_DECS 8 +#define M_CE_DECS 0xfU +#define V_CE_DECS(x) ((x) << S_CE_DECS) +#define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS) + +#define S_EN_ZFE 7 +#define V_EN_ZFE(x) ((x) << S_EN_ZFE) +#define F_EN_ZFE V_EN_ZFE(1U) + +#define S_EN_GAIN_TOG 6 +#define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG) +#define F_EN_GAIN_TOG V_EN_GAIN_TOG(1U) + +#define S_EN_AI_C1 5 +#define V_EN_AI_C1(x) ((x) << S_EN_AI_C1) +#define F_EN_AI_C1 V_EN_AI_C1(1U) + +#define S_EN_MAX_ST 4 +#define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST) +#define F_EN_MAX_ST V_EN_MAX_ST(1U) + +#define S_EN_H1T_EQ 3 +#define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ) +#define F_EN_H1T_EQ V_EN_H1T_EQ(1U) + +#define S_H1TEQ_GOAL 0 +#define M_H1TEQ_GOAL 0x7U +#define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL) +#define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL) + +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04 + +#define S_GAIN_TH 6 +#define M_GAIN_TH 0x1fU +#define V_GAIN_TH(x) ((x) << S_GAIN_TH) +#define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH) + +#define S_EN_SD_TH 5 +#define V_EN_SD_TH(x) ((x) << S_EN_SD_TH) +#define F_EN_SD_TH V_EN_SD_TH(1U) + +#define S_EN_AMIN_TH 4 +#define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH) +#define F_EN_AMIN_TH V_EN_AMIN_TH(1U) + +#define S_AMIN_TH 0 +#define M_AMIN_TH 0xfU +#define V_AMIN_TH(x) ((x) << S_AMIN_TH) +#define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH) + +#define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08 + +#define S_ACC_LIM 8 +#define M_ACC_LIM 0xfU +#define V_ACC_LIM(x) ((x) << S_ACC_LIM) +#define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM) + +#define S_CNV_LIM 4 +#define M_CNV_LIM 0xfU +#define V_CNV_LIM(x) ((x) << S_CNV_LIM) +#define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM) + +#define S_TOG_LIM 0 +#define M_TOG_LIM 0xfU +#define V_TOG_LIM(x) ((x) << S_TOG_LIM) +#define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM) + +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c + +#define S_BOOT_LUT7 12 +#define M_BOOT_LUT7 0xfU +#define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7) +#define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7) + +#define S_BOOT_LUT6 8 +#define M_BOOT_LUT6 0xfU +#define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6) +#define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6) + +#define S_BOOT_LUT45 4 +#define M_BOOT_LUT45 0xfU +#define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45) +#define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45) + +#define S_BOOT_LUT0123 2 +#define M_BOOT_LUT0123 0x3U +#define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123) +#define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123) + +#define S_BOOT_DEC_C0 1 +#define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0) +#define F_BOOT_DEC_C0 V_BOOT_DEC_C0(1U) + +#define A_MAC_PORT_AET_STATUS_0 0x2b10 + +#define S_AET_STAT 9 +#define M_AET_STAT 0xfU +#define V_AET_STAT(x) ((x) << S_AET_STAT) +#define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT) + +#define S_NEU_STATE 5 +#define M_NEU_STATE 0xfU +#define V_NEU_STATE(x) ((x) << S_NEU_STATE) +#define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE) + +#define S_CTRL_STATE 0 +#define M_CTRL_STATE 0x1fU +#define V_CTRL_STATE(x) ((x) << S_CTRL_STATE) +#define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE) + +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24 +#define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c +#define A_MAC_PORT_AET_STATUS_1 0x2b30 +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44 +#define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c +#define A_MAC_PORT_AET_STATUS_2 0x2b50 +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64 +#define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c +#define A_MAC_PORT_AET_STATUS_3 0x2b70 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000 + +#define S_T5_TX_LINKEN 15 +#define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN) +#define F_T5_TX_LINKEN V_T5_TX_LINKEN(1U) + +#define S_T5_TX_LINKRST 14 +#define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST) +#define F_T5_TX_LINKRST V_T5_TX_LINKRST(1U) + +#define S_T5_TX_CFGWRT 13 +#define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT) +#define F_T5_TX_CFGWRT V_T5_TX_CFGWRT(1U) + +#define S_T5_TX_CFGPTR 11 +#define M_T5_TX_CFGPTR 0x3U +#define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR) +#define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR) + +#define S_T5_TX_CFGEXT 10 +#define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT) +#define F_T5_TX_CFGEXT V_T5_TX_CFGEXT(1U) + +#define S_T5_TX_CFGACT 9 +#define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT) +#define F_T5_TX_CFGACT V_T5_TX_CFGACT(1U) + +#define S_T5_TX_RSYNCC 8 +#define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC) +#define F_T5_TX_RSYNCC V_T5_TX_RSYNCC(1U) + +#define S_T5_TX_PLLSEL 6 +#define M_T5_TX_PLLSEL 0x3U +#define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL) +#define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL) + +#define S_T5_TX_EXTC16 5 +#define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16) +#define F_T5_TX_EXTC16 V_T5_TX_EXTC16(1U) + +#define S_T5_TX_DCKSEL 4 +#define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL) +#define F_T5_TX_DCKSEL V_T5_TX_DCKSEL(1U) + +#define S_T5_TX_RXLOOP 3 +#define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP) +#define F_T5_TX_RXLOOP V_T5_TX_RXLOOP(1U) + +#define S_T5_TX_BWSEL 2 +#define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL) +#define F_T5_TX_BWSEL V_T5_TX_BWSEL(1U) + +#define S_T5_TX_RTSEL 0 +#define M_T5_TX_RTSEL 0x3U +#define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL) +#define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004 + +#define S_SPSEL 11 +#define M_SPSEL 0x7U +#define V_SPSEL(x) ((x) << S_SPSEL) +#define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL) + +#define S_AFDWEN 7 +#define V_AFDWEN(x) ((x) << S_AFDWEN) +#define F_AFDWEN V_AFDWEN(1U) + +#define S_TPGMD 3 +#define V_TPGMD(x) ((x) << S_TPGMD) +#define F_TPGMD V_TPGMD(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008 + +#define S_ZCALOVRD 8 +#define V_ZCALOVRD(x) ((x) << S_ZCALOVRD) +#define F_ZCALOVRD V_ZCALOVRD(1U) + +#define S_AMMODE 7 +#define V_AMMODE(x) ((x) << S_AMMODE) +#define F_AMMODE V_AMMODE(1U) + +#define S_AEPOL 6 +#define V_AEPOL(x) ((x) << S_AEPOL) +#define F_AEPOL V_AEPOL(1U) + +#define S_AESRC 5 +#define V_AESRC(x) ((x) << S_AESRC) +#define F_AESRC V_AESRC(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c + +#define S_T5DRVHIZ 5 +#define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ) +#define F_T5DRVHIZ V_T5DRVHIZ(1U) + +#define S_T5SASIMP 4 +#define V_T5SASIMP(x) ((x) << S_T5SASIMP) +#define F_T5SASIMP V_T5SASIMP(1U) + +#define S_T5SLEW 2 +#define M_T5SLEW 0x3U +#define V_T5SLEW(x) ((x) << S_T5SLEW) +#define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010 + +#define S_T5C2BUFDCEN 5 +#define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN) +#define F_T5C2BUFDCEN V_T5C2BUFDCEN(1U) + +#define S_T5DCCEN 4 +#define V_T5DCCEN(x) ((x) << S_T5DCCEN) +#define F_T5DCCEN V_T5DCCEN(1U) + +#define S_T5REGBYP 3 +#define V_T5REGBYP(x) ((x) << S_T5REGBYP) +#define F_T5REGBYP V_T5REGBYP(1U) + +#define S_T5REGAEN 2 +#define V_T5REGAEN(x) ((x) << S_T5REGAEN) +#define F_T5REGAEN V_T5REGAEN(1U) + +#define S_T5REGAMP 0 +#define M_T5REGAMP 0x3U +#define V_T5REGAMP(x) ((x) << S_T5REGAMP) +#define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014 + +#define S_RSTEP 15 +#define V_RSTEP(x) ((x) << S_RSTEP) +#define F_RSTEP V_RSTEP(1U) + +#define S_RLOCK 14 +#define V_RLOCK(x) ((x) << S_RLOCK) +#define F_RLOCK V_RLOCK(1U) + +#define S_RPOS 8 +#define M_RPOS 0x3fU +#define V_RPOS(x) ((x) << S_RPOS) +#define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS) + +#define S_DCLKSAM 7 +#define V_DCLKSAM(x) ((x) << S_DCLKSAM) +#define F_DCLKSAM V_DCLKSAM(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018 + +#define S_CALSSTN 3 +#define M_CALSSTN 0x7U +#define V_CALSSTN(x) ((x) << S_CALSSTN) +#define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN) + +#define S_CALSSTP 0 +#define M_CALSSTP 0x7U +#define V_CALSSTP(x) ((x) << S_CALSSTP) +#define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c + +#define S_DRTOL 0 +#define M_DRTOL 0x1fU +#define V_DRTOL(x) ((x) << S_DRTOL) +#define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020 + +#define S_T5NXTT0 0 +#define M_T5NXTT0 0x1fU +#define V_T5NXTT0(x) ((x) << S_T5NXTT0) +#define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024 + +#define S_T5NXTT1 0 +#define M_T5NXTT1 0x3fU +#define V_T5NXTT1(x) ((x) << S_T5NXTT1) +#define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028 + +#define S_T5NXTT2 0 +#define M_T5NXTT2 0x3fU +#define V_T5NXTT2(x) ((x) << S_T5NXTT2) +#define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030 + +#define S_T5TXPWR 0 +#define M_T5TXPWR 0x3fU +#define V_T5TXPWR(x) ((x) << S_T5TXPWR) +#define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034 + +#define S_NXTPOL 0 +#define M_NXTPOL 0x7U +#define V_NXTPOL(x) ((x) << S_NXTPOL) +#define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038 + +#define S_CPREST 13 +#define V_CPREST(x) ((x) << S_CPREST) +#define F_CPREST V_CPREST(1U) + +#define S_CINIT 12 +#define V_CINIT(x) ((x) << S_CINIT) +#define F_CINIT V_CINIT(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044 + +#define S_T5NIDAC1 0 +#define M_T5NIDAC1 0x3fU +#define V_T5NIDAC1(x) ((x) << S_T5NIDAC1) +#define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048 + +#define S_T5NIDAC2 0 +#define M_T5NIDAC2 0x3fU +#define V_T5NIDAC2(x) ((x) << S_T5NIDAC2) +#define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064 + +#define S_T5AIDAC1 0 +#define M_T5AIDAC1 0x3fU +#define V_T5AIDAC1(x) ((x) << S_T5AIDAC1) +#define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070 + +#define S_MAINSC 6 +#define M_MAINSC 0x3fU +#define V_MAINSC(x) ((x) << S_MAINSC) +#define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC) + +#define S_POSTSC 0 +#define M_POSTSC 0x3fU +#define V_POSTSC(x) ((x) << S_POSTSC) +#define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074 + +#define S_PRESC 0 +#define M_PRESC 0x1fU +#define V_PRESC(x) ((x) << S_PRESC) +#define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c + +#define S_T5XADDR 1 +#define M_T5XADDR 0x1fU +#define V_T5XADDR(x) ((x) << S_T5XADDR) +#define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR) + +#define S_T5XWR 0 +#define V_T5XWR(x) ((x) << S_T5XWR) +#define F_T5XWR V_T5XWR(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080 + +#define S_XDAT10 0 +#define M_XDAT10 0xffffU +#define V_XDAT10(x) ((x) << S_XDAT10) +#define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084 + +#define S_XDAT32 0 +#define M_XDAT32 0xffffU +#define V_XDAT32(x) ((x) << S_XDAT32) +#define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088 + +#define S_XDAT4 0 +#define M_XDAT4 0xffU +#define V_XDAT4(x) ((x) << S_XDAT4) +#define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c + +#define S_DCCTIMEDOUT 15 +#define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT) +#define F_DCCTIMEDOUT V_DCCTIMEDOUT(1U) + +#define S_DCCTIMEEN 14 +#define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN) +#define F_DCCTIMEEN V_DCCTIMEEN(1U) + +#define S_DCCLOCK 13 +#define V_DCCLOCK(x) ((x) << S_DCCLOCK) +#define F_DCCLOCK V_DCCLOCK(1U) + +#define S_DCCOFFSET 8 +#define M_DCCOFFSET 0x1fU +#define V_DCCOFFSET(x) ((x) << S_DCCOFFSET) +#define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET) + +#define S_DCCSTEP 6 +#define M_DCCSTEP 0x3U +#define V_DCCSTEP(x) ((x) << S_DCCSTEP) +#define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP) + +#define S_DCCASTEP 1 +#define M_DCCASTEP 0x1fU +#define V_DCCASTEP(x) ((x) << S_DCCASTEP) +#define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP) + +#define S_DCCAEN 0 +#define V_DCCAEN(x) ((x) << S_DCCAEN) +#define F_DCCAEN V_DCCAEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090 + +#define S_DCCOUT 12 +#define V_DCCOUT(x) ((x) << S_DCCOUT) +#define F_DCCOUT V_DCCOUT(1U) + +#define S_DCCCLK 11 +#define V_DCCCLK(x) ((x) << S_DCCCLK) +#define F_DCCCLK V_DCCCLK(1U) + +#define S_DCCHOLD 10 +#define V_DCCHOLD(x) ((x) << S_DCCHOLD) +#define F_DCCHOLD V_DCCHOLD(1U) + +#define S_DCCSIGN 8 +#define M_DCCSIGN 0x3U +#define V_DCCSIGN(x) ((x) << S_DCCSIGN) +#define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN) + +#define S_DCCAMP 1 +#define M_DCCAMP 0x7fU +#define V_DCCAMP(x) ((x) << S_DCCAMP) +#define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP) + +#define S_DCCOEN 0 +#define V_DCCOEN(x) ((x) << S_DCCOEN) +#define F_DCCOEN V_DCCOEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094 + +#define S_DCCASIGN 7 +#define M_DCCASIGN 0x3U +#define V_DCCASIGN(x) ((x) << S_DCCASIGN) +#define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN) + +#define S_DCCAAMP 0 +#define M_DCCAAMP 0x7fU +#define V_DCCAAMP(x) ((x) << S_DCCAAMP) +#define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098 + +#define S_DCCTIMEOUTVAL 0 +#define M_DCCTIMEOUTVAL 0xffffU +#define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL) +#define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c + +#define S_LPIDCLK 4 +#define V_LPIDCLK(x) ((x) << S_LPIDCLK) +#define F_LPIDCLK V_LPIDCLK(1U) + +#define S_LPITERM 2 +#define M_LPITERM 0x3U +#define V_LPITERM(x) ((x) << S_LPITERM) +#define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM) + +#define S_LPIPRCD 0 +#define M_LPIPRCD 0x3U +#define V_LPIPRCD(x) ((x) << S_LPIPRCD) +#define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0 + +#define S_SDOVRDEN 8 +#define V_SDOVRDEN(x) ((x) << S_SDOVRDEN) +#define F_SDOVRDEN V_SDOVRDEN(1U) + +#define S_SDOVRD 0 +#define M_SDOVRD 0xffU +#define V_SDOVRD(x) ((x) << S_SDOVRD) +#define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4 + +#define S_SLEWCODE 1 +#define M_SLEWCODE 0x3U +#define V_SLEWCODE(x) ((x) << S_SLEWCODE) +#define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE) + +#define S_ASEGEN 0 +#define V_ASEGEN(x) ((x) << S_ASEGEN) +#define F_ASEGEN V_ASEGEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8 + +#define S_AECMDVAL 14 +#define V_AECMDVAL(x) ((x) << S_AECMDVAL) +#define F_AECMDVAL V_AECMDVAL(1U) + +#define S_AECMD1312 12 +#define M_AECMD1312 0x3U +#define V_AECMD1312(x) ((x) << S_AECMD1312) +#define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312) + +#define S_AECMD70 0 +#define M_AECMD70 0xffU +#define V_AECMD70(x) ((x) << S_AECMD70) +#define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc + +#define S_C48DIVCTL 12 +#define M_C48DIVCTL 0x7U +#define V_C48DIVCTL(x) ((x) << S_C48DIVCTL) +#define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL) + +#define S_RATEDIVCTL 9 +#define M_RATEDIVCTL 0x7U +#define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL) +#define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL) + +#define S_ANLGFLSH 8 +#define V_ANLGFLSH(x) ((x) << S_ANLGFLSH) +#define F_ANLGFLSH V_ANLGFLSH(1U) + +#define S_DCCTSTOUT 7 +#define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT) +#define F_DCCTSTOUT V_DCCTSTOUT(1U) + +#define S_BSOUT 6 +#define V_BSOUT(x) ((x) << S_BSOUT) +#define F_BSOUT V_BSOUT(1U) + +#define S_BSIN 5 +#define V_BSIN(x) ((x) << S_BSIN) +#define F_BSIN V_BSIN(1U) + +#define S_JTAGAMPL 3 +#define M_JTAGAMPL 0x3U +#define V_JTAGAMPL(x) ((x) << S_JTAGAMPL) +#define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL) + +#define S_JTAGTS 2 +#define V_JTAGTS(x) ((x) << S_JTAGTS) +#define F_JTAGTS V_JTAGTS(1U) + +#define S_TS 1 +#define V_TS(x) ((x) << S_TS) +#define F_TS V_TS(1U) + +#define S_OBS 0 +#define V_OBS(x) ((x) << S_OBS) +#define F_OBS V_OBS(1U) + +#define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc +#define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200 + +#define S_T5_RX_LINKEN 15 +#define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN) +#define F_T5_RX_LINKEN V_T5_RX_LINKEN(1U) + +#define S_T5_RX_LINKRST 14 +#define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST) +#define F_T5_RX_LINKRST V_T5_RX_LINKRST(1U) + +#define S_T5_RX_CFGWRT 13 +#define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT) +#define F_T5_RX_CFGWRT V_T5_RX_CFGWRT(1U) + +#define S_T5_RX_CFGPTR 11 +#define M_T5_RX_CFGPTR 0x3U +#define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR) +#define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR) + +#define S_T5_RX_CFGEXT 10 +#define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT) +#define F_T5_RX_CFGEXT V_T5_RX_CFGEXT(1U) + +#define S_T5_RX_CFGACT 9 +#define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT) +#define F_T5_RX_CFGACT V_T5_RX_CFGACT(1U) + +#define S_T5_RX_AUXCLK 8 +#define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK) +#define F_T5_RX_AUXCLK V_T5_RX_AUXCLK(1U) + +#define S_T5_RX_PLLSEL 6 +#define M_T5_RX_PLLSEL 0x3U +#define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL) +#define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL) + +#define S_T5_RX_DMSEL 4 +#define M_T5_RX_DMSEL 0x3U +#define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL) +#define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL) + +#define S_T5_RX_BWSEL 2 +#define M_T5_RX_BWSEL 0x3U +#define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL) +#define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL) + +#define S_T5_RX_RTSEL 0 +#define M_T5_RX_RTSEL 0x3U +#define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL) +#define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204 + +#define S_FERRST 10 +#define V_FERRST(x) ((x) << S_FERRST) +#define F_FERRST V_FERRST(1U) + +#define S_ERRST 9 +#define V_ERRST(x) ((x) << S_ERRST) +#define F_ERRST V_ERRST(1U) + +#define S_SYNCST 8 +#define V_SYNCST(x) ((x) << S_SYNCST) +#define F_SYNCST V_SYNCST(1U) + +#define S_WRPSM 7 +#define V_WRPSM(x) ((x) << S_WRPSM) +#define F_WRPSM V_WRPSM(1U) + +#define S_WPLPEN 6 +#define V_WPLPEN(x) ((x) << S_WPLPEN) +#define F_WPLPEN V_WPLPEN(1U) + +#define S_WRPMD 5 +#define V_WRPMD(x) ((x) << S_WRPMD) +#define F_WRPMD V_WRPMD(1U) + +#define S_PATSEL 0 +#define M_PATSEL 0x7U +#define V_PATSEL(x) ((x) << S_PATSEL) +#define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208 + +#define S_RSTUCK 3 +#define V_RSTUCK(x) ((x) << S_RSTUCK) +#define F_RSTUCK V_RSTUCK(1U) + +#define S_FRZFW 2 +#define V_FRZFW(x) ((x) << S_FRZFW) +#define F_FRZFW V_FRZFW(1U) + +#define S_RSTFW 1 +#define V_RSTFW(x) ((x) << S_RSTFW) +#define F_RSTFW V_RSTFW(1U) + +#define S_SSCEN 0 +#define V_SSCEN(x) ((x) << S_SSCEN) +#define F_SSCEN V_SSCEN(1U) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210 + +#define S_ROT00 0 +#define M_ROT00 0x3fU +#define V_ROT00(x) ((x) << S_ROT00) +#define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214 + +#define S_FREQFW 8 +#define M_FREQFW 0xffU +#define V_FREQFW(x) ((x) << S_FREQFW) +#define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW) + +#define S_FWSNAP 7 +#define V_FWSNAP(x) ((x) << S_FWSNAP) +#define F_FWSNAP V_FWSNAP(1U) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218 +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c + +#define S_RBOOFF 10 +#define M_RBOOFF 0x1fU +#define V_RBOOFF(x) ((x) << S_RBOOFF) +#define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF) + +#define S_RBEOFF 5 +#define M_RBEOFF 0x1fU +#define V_RBEOFF(x) ((x) << S_RBEOFF) +#define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF) + +#define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220 +#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224 + +#define S_T5BYTE1 8 +#define M_T5BYTE1 0xffU +#define V_T5BYTE1(x) ((x) << S_T5BYTE1) +#define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1) + +#define S_T5BYTE0 0 +#define M_T5BYTE0 0xffU +#define V_T5BYTE0(x) ((x) << S_T5BYTE0) +#define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0) + +#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228 + +#define S_T5_RX_SMODE 8 +#define M_T5_RX_SMODE 0x7U +#define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE) +#define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE) + +#define S_T5_RX_ADCORR 7 +#define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR) +#define F_T5_RX_ADCORR V_T5_RX_ADCORR(1U) + +#define S_T5_RX_TRAINEN 6 +#define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN) +#define F_T5_RX_TRAINEN V_T5_RX_TRAINEN(1U) + +#define S_T5_RX_ASAMPQ 3 +#define M_T5_RX_ASAMPQ 0x7U +#define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ) +#define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ) + +#define S_T5_RX_ASAMP 0 +#define M_T5_RX_ASAMP 0x7U +#define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP) +#define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230 + +#define S_T5SHORTV 10 +#define V_T5SHORTV(x) ((x) << S_T5SHORTV) +#define F_T5SHORTV V_T5SHORTV(1U) + +#define S_T5VGAIN 0 +#define M_T5VGAIN 0x1fU +#define V_T5VGAIN(x) ((x) << S_T5VGAIN) +#define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234 +#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238 + +#define S_IQSEP 10 +#define M_IQSEP 0x1fU +#define V_IQSEP(x) ((x) << S_IQSEP) +#define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP) + +#define S_DUTYQ 5 +#define M_DUTYQ 0x1fU +#define V_DUTYQ(x) ((x) << S_DUTYQ) +#define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ) + +#define S_DUTYI 0 +#define M_DUTYI 0x1fU +#define V_DUTYI(x) ((x) << S_DUTYI) +#define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240 + +#define S_DTHR 8 +#define M_DTHR 0x3fU +#define V_DTHR(x) ((x) << S_DTHR) +#define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR) + +#define S_SNUL 0 +#define M_SNUL 0x1fU +#define V_SNUL(x) ((x) << S_SNUL) +#define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248 +#define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c +#define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250 + +#define S_ADSN_READWRITE 8 +#define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE) +#define F_ADSN_READWRITE V_ADSN_READWRITE(1U) + +#define S_ADSN_READONLY 7 +#define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY) +#define F_ADSN_READONLY V_ADSN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c + +#define S_H1O2 8 +#define M_H1O2 0x3fU +#define V_H1O2(x) ((x) << S_H1O2) +#define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2) + +#define S_H1E2 0 +#define M_H1E2 0x3fU +#define V_H1E2(x) ((x) << S_H1E2) +#define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260 + +#define S_H1O3 8 +#define M_H1O3 0x3fU +#define V_H1O3(x) ((x) << S_H1O3) +#define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3) + +#define S_H1E3 0 +#define M_H1E3 0x3fU +#define V_H1E3(x) ((x) << S_H1E3) +#define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264 + +#define S_H1O4 8 +#define M_H1O4 0x3fU +#define V_H1O4(x) ((x) << S_H1O4) +#define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4) + +#define S_H1E4 0 +#define M_H1E4 0x3fU +#define V_H1E4(x) ((x) << S_H1E4) +#define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4) + +#define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270 + +#define S_DPCMD 14 +#define V_DPCMD(x) ((x) << S_DPCMD) +#define F_DPCMD V_DPCMD(1U) + +#define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274 +#define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278 + +#define S_T5BER6VAL 15 +#define V_T5BER6VAL(x) ((x) << S_T5BER6VAL) +#define F_T5BER6VAL V_T5BER6VAL(1U) + +#define S_T5BER6 14 +#define V_T5BER6(x) ((x) << S_T5BER6) +#define F_T5BER6 V_T5BER6(1U) + +#define S_T5BER3VAL 13 +#define V_T5BER3VAL(x) ((x) << S_T5BER3VAL) +#define F_T5BER3VAL V_T5BER3VAL(1U) + +#define S_T5TOOFAST 12 +#define V_T5TOOFAST(x) ((x) << S_T5TOOFAST) +#define F_T5TOOFAST V_T5TOOFAST(1U) + +#define S_T5DPCCMP 9 +#define V_T5DPCCMP(x) ((x) << S_T5DPCCMP) +#define F_T5DPCCMP V_T5DPCCMP(1U) + +#define S_T5DACCMP 8 +#define V_T5DACCMP(x) ((x) << S_T5DACCMP) +#define F_T5DACCMP V_T5DACCMP(1U) + +#define S_T5DDCCMP 7 +#define V_T5DDCCMP(x) ((x) << S_T5DDCCMP) +#define F_T5DDCCMP V_T5DDCCMP(1U) + +#define S_T5AERRFLG 6 +#define V_T5AERRFLG(x) ((x) << S_T5AERRFLG) +#define F_T5AERRFLG V_T5AERRFLG(1U) + +#define S_T5WERRFLG 5 +#define V_T5WERRFLG(x) ((x) << S_T5WERRFLG) +#define F_T5WERRFLG V_T5WERRFLG(1U) + +#define S_T5TRCMP 4 +#define V_T5TRCMP(x) ((x) << S_T5TRCMP) +#define F_T5TRCMP V_T5TRCMP(1U) + +#define S_T5VLCKF 3 +#define V_T5VLCKF(x) ((x) << S_T5VLCKF) +#define F_T5VLCKF V_T5VLCKF(1U) + +#define S_T5ROCCMP 2 +#define V_T5ROCCMP(x) ((x) << S_T5ROCCMP) +#define F_T5ROCCMP V_T5ROCCMP(1U) + +#define S_T5DQCCCMP 1 +#define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP) +#define F_T5DQCCCMP V_T5DQCCCMP(1U) + +#define S_T5OCCMP 0 +#define V_T5OCCMP(x) ((x) << S_T5OCCMP) +#define F_T5OCCMP V_T5OCCMP(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c + +#define S_FLOFF 1 +#define V_FLOFF(x) ((x) << S_FLOFF) +#define F_FLOFF V_FLOFF(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280 + +#define S_H25SPC 15 +#define V_H25SPC(x) ((x) << S_H25SPC) +#define F_H25SPC V_H25SPC(1U) + +#define S_FTOOFAST 8 +#define V_FTOOFAST(x) ((x) << S_FTOOFAST) +#define F_FTOOFAST V_FTOOFAST(1U) + +#define S_FINTTRIM 7 +#define V_FINTTRIM(x) ((x) << S_FINTTRIM) +#define F_FINTTRIM V_FINTTRIM(1U) + +#define S_FDINV 6 +#define V_FDINV(x) ((x) << S_FDINV) +#define F_FDINV V_FDINV(1U) + +#define S_FHGS 5 +#define V_FHGS(x) ((x) << S_FHGS) +#define F_FHGS V_FHGS(1U) + +#define S_FH6H12 4 +#define V_FH6H12(x) ((x) << S_FH6H12) +#define F_FH6H12 V_FH6H12(1U) + +#define S_FH1CAL 3 +#define V_FH1CAL(x) ((x) << S_FH1CAL) +#define F_FH1CAL V_FH1CAL(1U) + +#define S_FINTCAL 2 +#define V_FINTCAL(x) ((x) << S_FINTCAL) +#define F_FINTCAL V_FINTCAL(1U) + +#define S_FDCA 1 +#define V_FDCA(x) ((x) << S_FDCA) +#define F_FDCA V_FDCA(1U) + +#define S_FDQCC 0 +#define V_FDQCC(x) ((x) << S_FDQCC) +#define F_FDQCC V_FDQCC(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284 + +#define S_LOFE2S_READWRITE 16 +#define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE) +#define F_LOFE2S_READWRITE V_LOFE2S_READWRITE(1U) + +#define S_LOFE2S_READONLY 14 +#define M_LOFE2S_READONLY 0x3U +#define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY) +#define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY) + +#define S_LOFE2 8 +#define M_LOFE2 0x3fU +#define V_LOFE2(x) ((x) << S_LOFE2) +#define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2) + +#define S_LOFE1S_READWRITE 7 +#define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE) +#define F_LOFE1S_READWRITE V_LOFE1S_READWRITE(1U) + +#define S_LOFE1S_READONLY 6 +#define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY) +#define F_LOFE1S_READONLY V_LOFE1S_READONLY(1U) + +#define S_LOFE1 0 +#define M_LOFE1 0x3fU +#define V_LOFE1(x) ((x) << S_LOFE1) +#define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288 + +#define S_LOFO2S_READWRITE 15 +#define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE) +#define F_LOFO2S_READWRITE V_LOFO2S_READWRITE(1U) + +#define S_LOFO2S_READONLY 14 +#define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY) +#define F_LOFO2S_READONLY V_LOFO2S_READONLY(1U) + +#define S_LOFO2 8 +#define M_LOFO2 0x3fU +#define V_LOFO2(x) ((x) << S_LOFO2) +#define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2) + +#define S_LOFO1S_READWRITE 7 +#define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE) +#define F_LOFO1S_READWRITE V_LOFO1S_READWRITE(1U) + +#define S_LOFO1S_READONLY 6 +#define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY) +#define F_LOFO1S_READONLY V_LOFO1S_READONLY(1U) + +#define S_LOFO1 0 +#define M_LOFO1 0x3fU +#define V_LOFO1(x) ((x) << S_LOFO1) +#define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c + +#define S_LOFE4S_READWRITE 15 +#define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE) +#define F_LOFE4S_READWRITE V_LOFE4S_READWRITE(1U) + +#define S_LOFE4S_READONLY 14 +#define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY) +#define F_LOFE4S_READONLY V_LOFE4S_READONLY(1U) + +#define S_LOFE 8 +#define M_LOFE 0x3fU +#define V_LOFE(x) ((x) << S_LOFE) +#define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE) + +#define S_LOFE3S_READWRITE 7 +#define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE) +#define F_LOFE3S_READWRITE V_LOFE3S_READWRITE(1U) + +#define S_LOFE3S_READONLY 6 +#define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY) +#define F_LOFE3S_READONLY V_LOFE3S_READONLY(1U) + +#define S_LOFE3 0 +#define M_LOFE3 0x3fU +#define V_LOFE3(x) ((x) << S_LOFE3) +#define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290 + +#define S_LOFO4S_READWRITE 15 +#define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE) +#define F_LOFO4S_READWRITE V_LOFO4S_READWRITE(1U) + +#define S_LOFO4S_READONLY 14 +#define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY) +#define F_LOFO4S_READONLY V_LOFO4S_READONLY(1U) + +#define S_LOFO4 8 +#define M_LOFO4 0x3fU +#define V_LOFO4(x) ((x) << S_LOFO4) +#define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4) + +#define S_LOFO3S_READWRITE 7 +#define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE) +#define F_LOFO3S_READWRITE V_LOFO3S_READWRITE(1U) + +#define S_LOFO3S_READONLY 6 +#define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY) +#define F_LOFO3S_READONLY V_LOFO3S_READONLY(1U) + +#define S_LOFO3 0 +#define M_LOFO3 0x3fU +#define V_LOFO3(x) ((x) << S_LOFO3) +#define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3) + +#define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294 + +#define S_T5E1SN_READWRITE 15 +#define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE) +#define F_T5E1SN_READWRITE V_T5E1SN_READWRITE(1U) + +#define S_T5E1SN_READONLY 14 +#define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY) +#define F_T5E1SN_READONLY V_T5E1SN_READONLY(1U) + +#define S_T5E1AMP 8 +#define M_T5E1AMP 0x3fU +#define V_T5E1AMP(x) ((x) << S_T5E1AMP) +#define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP) + +#define S_T5E0SN_READWRITE 7 +#define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE) +#define F_T5E0SN_READWRITE V_T5E0SN_READWRITE(1U) + +#define S_T5E0SN_READONLY 6 +#define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY) +#define F_T5E0SN_READONLY V_T5E0SN_READONLY(1U) + +#define S_T5E0AMP 0 +#define M_T5E0AMP 0x3fU +#define V_T5E0AMP(x) ((x) << S_T5E0AMP) +#define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298 + +#define S_T5LFREG 12 +#define V_T5LFREG(x) ((x) << S_T5LFREG) +#define F_T5LFREG V_T5LFREG(1U) + +#define S_T5LFRC 11 +#define V_T5LFRC(x) ((x) << S_T5LFRC) +#define F_T5LFRC V_T5LFRC(1U) + +#define S_T5LFSEL 8 +#define M_T5LFSEL 0x7U +#define V_T5LFSEL(x) ((x) << S_T5LFSEL) +#define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c + +#define S_OFFSN_READWRITE 14 +#define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE) +#define F_OFFSN_READWRITE V_OFFSN_READWRITE(1U) + +#define S_OFFSN_READONLY 13 +#define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY) +#define F_OFFSN_READONLY V_OFFSN_READONLY(1U) + +#define S_OFFAMP 8 +#define M_OFFAMP 0x1fU +#define V_OFFAMP(x) ((x) << S_OFFAMP) +#define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP) + +#define S_SDACDC 7 +#define V_SDACDC(x) ((x) << S_SDACDC) +#define F_SDACDC V_SDACDC(1U) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0 + +#define S_T5_RX_SETHDIS 7 +#define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS) +#define F_T5_RX_SETHDIS V_T5_RX_SETHDIS(1U) + +#define S_T5_RX_PDTERM 6 +#define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM) +#define F_T5_RX_PDTERM V_T5_RX_PDTERM(1U) + +#define S_T5_RX_BYPASS 5 +#define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS) +#define F_T5_RX_BYPASS V_T5_RX_BYPASS(1U) + +#define S_T5_RX_LPFEN 4 +#define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN) +#define F_T5_RX_LPFEN V_T5_RX_LPFEN(1U) + +#define S_T5_RX_VGABOD 3 +#define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD) +#define F_T5_RX_VGABOD V_T5_RX_VGABOD(1U) + +#define S_T5_RX_VTBYP 2 +#define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP) +#define F_T5_RX_VTBYP V_T5_RX_VTBYP(1U) + +#define S_T5_RX_VTERM 0 +#define M_T5_RX_VTERM 0x3U +#define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM) +#define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM) + +#define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4 + +#define S_ISTRIMS 14 +#define M_ISTRIMS 0x3U +#define V_ISTRIMS(x) ((x) << S_ISTRIMS) +#define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS) + +#define S_ISTRIM 8 +#define M_ISTRIM 0x3fU +#define V_ISTRIM(x) ((x) << S_ISTRIM) +#define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM) + +#define S_HALF1 7 +#define V_HALF1(x) ((x) << S_HALF1) +#define F_HALF1 V_HALF1(1U) + +#define S_HALF2 6 +#define V_HALF2(x) ((x) << S_HALF2) +#define F_HALF2 V_HALF2(1U) + +#define S_INTDAC 0 +#define M_INTDAC 0x3fU +#define V_INTDAC(x) ((x) << S_INTDAC) +#define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8 + +#define S_MINWDTH 5 +#define M_MINWDTH 0x1fU +#define V_MINWDTH(x) ((x) << S_MINWDTH) +#define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac + +#define S_T5SMQM 13 +#define M_T5SMQM 0x7U +#define V_T5SMQM(x) ((x) << S_T5SMQM) +#define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM) + +#define S_T5SMQ 5 +#define M_T5SMQ 0xffU +#define V_T5SMQ(x) ((x) << S_T5SMQ) +#define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ) + +#define S_T5EMMD 3 +#define M_T5EMMD 0x3U +#define V_T5EMMD(x) ((x) << S_T5EMMD) +#define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD) + +#define S_T5EMBRDY 2 +#define V_T5EMBRDY(x) ((x) << S_T5EMBRDY) +#define F_T5EMBRDY V_T5EMBRDY(1U) + +#define S_T5EMBUMP 1 +#define V_T5EMBUMP(x) ((x) << S_T5EMBUMP) +#define F_T5EMBUMP V_T5EMBUMP(1U) + +#define S_T5EMEN 0 +#define V_T5EMEN(x) ((x) << S_T5EMEN) +#define F_T5EMEN V_T5EMEN(1U) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0 + +#define S_EMF8 15 +#define V_EMF8(x) ((x) << S_EMF8) +#define F_EMF8 V_EMF8(1U) + +#define S_EMCNT 4 +#define M_EMCNT 0xffU +#define V_EMCNT(x) ((x) << S_EMCNT) +#define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT) + +#define S_EMOFLO 2 +#define V_EMOFLO(x) ((x) << S_EMOFLO) +#define F_EMOFLO V_EMOFLO(1U) + +#define S_EMCRST 1 +#define V_EMCRST(x) ((x) << S_EMCRST) +#define F_EMCRST V_EMCRST(1U) + +#define S_EMCEN 0 +#define V_EMCEN(x) ((x) << S_EMCEN) +#define F_EMCEN V_EMCEN(1U) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4 + +#define S_SM2RDY 15 +#define V_SM2RDY(x) ((x) << S_SM2RDY) +#define F_SM2RDY V_SM2RDY(1U) + +#define S_SM2RST 14 +#define V_SM2RST(x) ((x) << S_SM2RST) +#define F_SM2RST V_SM2RST(1U) + +#define S_APDF 0 +#define M_APDF 0xfffU +#define V_APDF(x) ((x) << S_APDF) +#define G_APDF(x) (((x) >> S_APDF) & M_APDF) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8 + +#define S_SM0LEN 0 +#define M_SM0LEN 0x7fffU +#define V_SM0LEN(x) ((x) << S_SM0LEN) +#define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN) + +#define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0 + +#define S_H_EN 1 +#define M_H_EN 0xfffU +#define V_H_EN(x) ((x) << S_H_EN) +#define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN) + +#define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4 +#define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8 + +#define S_H2OSN_READWRITE 14 +#define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE) +#define F_H2OSN_READWRITE V_H2OSN_READWRITE(1U) + +#define S_H2OSN_READONLY 13 +#define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY) +#define F_H2OSN_READONLY V_H2OSN_READONLY(1U) + +#define S_H2ESN_READWRITE 6 +#define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE) +#define F_H2ESN_READWRITE V_H2ESN_READWRITE(1U) + +#define S_H2ESN_READONLY 5 +#define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY) +#define F_H2ESN_READONLY V_H2ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc + +#define S_H3OSN_READWRITE 13 +#define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE) +#define F_H3OSN_READWRITE V_H3OSN_READWRITE(1U) + +#define S_H3OSN_READONLY 12 +#define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY) +#define F_H3OSN_READONLY V_H3OSN_READONLY(1U) + +#define S_H3ESN_READWRITE 5 +#define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE) +#define F_H3ESN_READWRITE V_H3ESN_READWRITE(1U) + +#define S_H3ESN_READONLY 4 +#define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY) +#define F_H3ESN_READONLY V_H3ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0 + +#define S_H4OGS 14 +#define M_H4OGS 0x3U +#define V_H4OGS(x) ((x) << S_H4OGS) +#define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS) + +#define S_H4OSN_READWRITE 13 +#define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE) +#define F_H4OSN_READWRITE V_H4OSN_READWRITE(1U) + +#define S_H4OSN_READONLY 12 +#define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY) +#define F_H4OSN_READONLY V_H4OSN_READONLY(1U) + +#define S_H4EGS 6 +#define M_H4EGS 0x3U +#define V_H4EGS(x) ((x) << S_H4EGS) +#define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS) + +#define S_H4ESN_READWRITE 5 +#define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE) +#define F_H4ESN_READWRITE V_H4ESN_READWRITE(1U) + +#define S_H4ESN_READONLY 4 +#define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY) +#define F_H4ESN_READONLY V_H4ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4 + +#define S_H5OGS 14 +#define M_H5OGS 0x3U +#define V_H5OGS(x) ((x) << S_H5OGS) +#define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS) + +#define S_H5OSN_READWRITE 13 +#define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE) +#define F_H5OSN_READWRITE V_H5OSN_READWRITE(1U) + +#define S_H5OSN_READONLY 12 +#define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY) +#define F_H5OSN_READONLY V_H5OSN_READONLY(1U) + +#define S_H5EGS 6 +#define M_H5EGS 0x3U +#define V_H5EGS(x) ((x) << S_H5EGS) +#define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS) + +#define S_H5ESN_READWRITE 5 +#define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE) +#define F_H5ESN_READWRITE V_H5ESN_READWRITE(1U) + +#define S_H5ESN_READONLY 4 +#define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY) +#define F_H5ESN_READONLY V_H5ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8 + +#define S_H7GS 14 +#define M_H7GS 0x3U +#define V_H7GS(x) ((x) << S_H7GS) +#define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS) + +#define S_H7SN_READWRITE 13 +#define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE) +#define F_H7SN_READWRITE V_H7SN_READWRITE(1U) + +#define S_H7SN_READONLY 12 +#define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY) +#define F_H7SN_READONLY V_H7SN_READONLY(1U) + +#define S_H7MAG 8 +#define M_H7MAG 0xfU +#define V_H7MAG(x) ((x) << S_H7MAG) +#define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG) + +#define S_H6GS 6 +#define M_H6GS 0x3U +#define V_H6GS(x) ((x) << S_H6GS) +#define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS) + +#define S_H6SN_READWRITE 5 +#define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE) +#define F_H6SN_READWRITE V_H6SN_READWRITE(1U) + +#define S_H6SN_READONLY 4 +#define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY) +#define F_H6SN_READONLY V_H6SN_READONLY(1U) + +#define S_H6MAG 0 +#define M_H6MAG 0xfU +#define V_H6MAG(x) ((x) << S_H6MAG) +#define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc + +#define S_H9GS 14 +#define M_H9GS 0x3U +#define V_H9GS(x) ((x) << S_H9GS) +#define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS) + +#define S_H9SN_READWRITE 13 +#define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE) +#define F_H9SN_READWRITE V_H9SN_READWRITE(1U) + +#define S_H9SN_READONLY 12 +#define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY) +#define F_H9SN_READONLY V_H9SN_READONLY(1U) + +#define S_H9MAG 8 +#define M_H9MAG 0xfU +#define V_H9MAG(x) ((x) << S_H9MAG) +#define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG) + +#define S_H8GS 6 +#define M_H8GS 0x3U +#define V_H8GS(x) ((x) << S_H8GS) +#define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS) + +#define S_H8SN_READWRITE 5 +#define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE) +#define F_H8SN_READWRITE V_H8SN_READWRITE(1U) + +#define S_H8SN_READONLY 4 +#define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY) +#define F_H8SN_READONLY V_H8SN_READONLY(1U) + +#define S_H8MAG 0 +#define M_H8MAG 0xfU +#define V_H8MAG(x) ((x) << S_H8MAG) +#define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0 + +#define S_H11GS 14 +#define M_H11GS 0x3U +#define V_H11GS(x) ((x) << S_H11GS) +#define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS) + +#define S_H11SN_READWRITE 13 +#define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE) +#define F_H11SN_READWRITE V_H11SN_READWRITE(1U) + +#define S_H11SN_READONLY 12 +#define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY) +#define F_H11SN_READONLY V_H11SN_READONLY(1U) + +#define S_H11MAG 8 +#define M_H11MAG 0xfU +#define V_H11MAG(x) ((x) << S_H11MAG) +#define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG) + +#define S_H10GS 6 +#define M_H10GS 0x3U +#define V_H10GS(x) ((x) << S_H10GS) +#define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS) + +#define S_H10SN_READWRITE 5 +#define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE) +#define F_H10SN_READWRITE V_H10SN_READWRITE(1U) + +#define S_H10SN_READONLY 4 +#define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY) +#define F_H10SN_READONLY V_H10SN_READONLY(1U) + +#define S_H10MAG 0 +#define M_H10MAG 0xfU +#define V_H10MAG(x) ((x) << S_H10MAG) +#define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4 + +#define S_H12GS 6 +#define M_H12GS 0x3U +#define V_H12GS(x) ((x) << S_H12GS) +#define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS) + +#define S_H12SN_READWRITE 5 +#define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE) +#define F_H12SN_READWRITE V_H12SN_READWRITE(1U) + +#define S_H12SN_READONLY 4 +#define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY) +#define F_H12SN_READONLY V_H12SN_READONLY(1U) + +#define S_H12MAG 0 +#define M_H12MAG 0xfU +#define V_H12MAG(x) ((x) << S_H12MAG) +#define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8 + +#define S_DFEDACLSSD 6 +#define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD) +#define F_DFEDACLSSD V_DFEDACLSSD(1U) + +#define S_SDLSSD 5 +#define V_SDLSSD(x) ((x) << S_SDLSSD) +#define F_SDLSSD V_SDLSSD(1U) + +#define S_DFEOBSBIAS 4 +#define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS) +#define F_DFEOBSBIAS V_DFEOBSBIAS(1U) + +#define S_GBOFSTLSSD 3 +#define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD) +#define F_GBOFSTLSSD V_GBOFSTLSSD(1U) + +#define S_RXDOBS 2 +#define V_RXDOBS(x) ((x) << S_RXDOBS) +#define F_RXDOBS V_RXDOBS(1U) + +#define S_ACJZPT 1 +#define V_ACJZPT(x) ((x) << S_ACJZPT) +#define F_ACJZPT V_ACJZPT(1U) + +#define S_ACJZNT 0 +#define V_ACJZNT(x) ((x) << S_ACJZNT) +#define F_ACJZNT V_ACJZNT(1U) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc + +#define S_PHSLOCK 10 +#define V_PHSLOCK(x) ((x) << S_PHSLOCK) +#define F_PHSLOCK V_PHSLOCK(1U) + +#define S_TESTMODE 9 +#define V_TESTMODE(x) ((x) << S_TESTMODE) +#define F_TESTMODE V_TESTMODE(1U) + +#define S_CALMODE 8 +#define V_CALMODE(x) ((x) << S_CALMODE) +#define F_CALMODE V_CALMODE(1U) + +#define S_AMPSEL 7 +#define V_AMPSEL(x) ((x) << S_AMPSEL) +#define F_AMPSEL V_AMPSEL(1U) + +#define S_WHICHNRZ 6 +#define V_WHICHNRZ(x) ((x) << S_WHICHNRZ) +#define F_WHICHNRZ V_WHICHNRZ(1U) + +#define S_BANKA 5 +#define V_BANKA(x) ((x) << S_BANKA) +#define F_BANKA V_BANKA(1U) + +#define S_BANKB 4 +#define V_BANKB(x) ((x) << S_BANKB) +#define F_BANKB V_BANKB(1U) + +#define S_ACJPDP 3 +#define V_ACJPDP(x) ((x) << S_ACJPDP) +#define F_ACJPDP V_ACJPDP(1U) + +#define S_ACJPDN 2 +#define V_ACJPDN(x) ((x) << S_ACJPDN) +#define F_ACJPDN V_ACJPDN(1U) + +#define S_LSSDT 1 +#define V_LSSDT(x) ((x) << S_LSSDT) +#define F_LSSDT V_LSSDT(1U) + +#define S_MTHOLD 0 +#define V_MTHOLD(x) ((x) << S_MTHOLD) +#define F_MTHOLD V_MTHOLD(1U) + +#define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300 +#define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c +#define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320 +#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324 +#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328 +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330 +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c +#define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350 +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360 +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364 +#define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370 +#define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374 +#define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378 +#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c +#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390 +#define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394 +#define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398 +#define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c +#define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0 +#define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8 +#define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0 +#define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4 +#define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8 +#define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc +#define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0 +#define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4 +#define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8 +#define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc +#define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0 +#define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4 +#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8 +#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc +#define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc +#define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc +#define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600 +#define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c +#define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620 +#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624 +#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628 +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630 +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c +#define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650 +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660 +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664 +#define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670 +#define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674 +#define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678 +#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c +#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690 +#define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694 +#define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698 +#define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c +#define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0 +#define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8 +#define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0 +#define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4 +#define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8 +#define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc +#define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0 +#define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4 +#define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8 +#define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc +#define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0 +#define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4 +#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8 +#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc +#define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700 +#define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c +#define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720 +#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724 +#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728 +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730 +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c +#define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750 +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760 +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764 +#define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770 +#define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774 +#define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778 +#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c +#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790 +#define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794 +#define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798 +#define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c +#define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0 +#define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8 +#define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0 +#define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4 +#define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8 +#define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc +#define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0 +#define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4 +#define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8 +#define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc +#define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0 +#define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4 +#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8 +#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc +#define A_MAC_PORT_ANALOG_TEST_MUX 0x3814 +#define A_MAC_PORT_BANDGAP_CONTROL 0x382c + +#define S_T5BGCTL 0 +#define M_T5BGCTL 0xfU +#define V_T5BGCTL(x) ((x) << S_T5BGCTL) +#define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880 + +#define S_RCCTL1 5 +#define V_RCCTL1(x) ((x) << S_RCCTL1) +#define F_RCCTL1 V_RCCTL1(1U) + +#define S_RCCTL0 4 +#define V_RCCTL0(x) ((x) << S_RCCTL0) +#define F_RCCTL0 V_RCCTL0(1U) + +#define S_RCAMP1 3 +#define V_RCAMP1(x) ((x) << S_RCAMP1) +#define F_RCAMP1 V_RCAMP1(1U) + +#define S_RCAMP0 2 +#define V_RCAMP0(x) ((x) << S_RCAMP0) +#define F_RCAMP0 V_RCAMP0(1U) + +#define S_RCAMPEN 1 +#define V_RCAMPEN(x) ((x) << S_RCAMPEN) +#define F_RCAMPEN V_RCAMPEN(1U) + +#define S_RCRST 0 +#define V_RCRST(x) ((x) << S_RCRST) +#define F_RCRST V_RCRST(1U) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884 + +#define S_RCERR 1 +#define V_RCERR(x) ((x) << S_RCERR) +#define F_RCERR V_RCERR(1U) + +#define S_RCCOMP 0 +#define V_RCCOMP(x) ((x) << S_RCCOMP) +#define F_RCCOMP V_RCCOMP(1U) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888 + +#define S_RESREG2 0 +#define M_RESREG2 0xffU +#define V_RESREG2(x) ((x) << S_RESREG2) +#define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c + +#define S_RESREG3 0 +#define M_RESREG3 0xffU +#define V_RESREG3(x) ((x) << S_RESREG3) +#define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3) + +#define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8 + +#define S_LBIST 7 +#define V_LBIST(x) ((x) << S_LBIST) +#define F_LBIST V_LBIST(1U) + +#define S_LOGICTEST 6 +#define V_LOGICTEST(x) ((x) << S_LOGICTEST) +#define F_LOGICTEST V_LOGICTEST(1U) + +#define S_MAVDHI 5 +#define V_MAVDHI(x) ((x) << S_MAVDHI) +#define F_MAVDHI V_MAVDHI(1U) + +#define S_AUXEN 4 +#define V_AUXEN(x) ((x) << S_AUXEN) +#define F_AUXEN V_AUXEN(1U) + +#define S_JTAGMD 3 +#define V_JTAGMD(x) ((x) << S_JTAGMD) +#define F_JTAGMD V_JTAGMD(1U) + +#define S_RXACMODE 2 +#define V_RXACMODE(x) ((x) << S_RXACMODE) +#define F_RXACMODE V_RXACMODE(1U) + +#define S_HSSACJPC 1 +#define V_HSSACJPC(x) ((x) << S_HSSACJPC) +#define F_HSSACJPC V_HSSACJPC(1U) + +#define S_HSSACJAC 0 +#define V_HSSACJAC(x) ((x) << S_HSSACJAC) +#define F_HSSACJAC V_HSSACJAC(1U) + +#define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec + +#define S_REFVALIDD 6 +#define V_REFVALIDD(x) ((x) << S_REFVALIDD) +#define F_REFVALIDD V_REFVALIDD(1U) + +#define S_REFVALIDC 5 +#define V_REFVALIDC(x) ((x) << S_REFVALIDC) +#define F_REFVALIDC V_REFVALIDC(1U) + +#define S_REFVALIDB 4 +#define V_REFVALIDB(x) ((x) << S_REFVALIDB) +#define F_REFVALIDB V_REFVALIDB(1U) + +#define S_REFVALIDA 3 +#define V_REFVALIDA(x) ((x) << S_REFVALIDA) +#define F_REFVALIDA V_REFVALIDA(1U) + +#define S_REFSELRESET 2 +#define V_REFSELRESET(x) ((x) << S_REFSELRESET) +#define F_REFSELRESET V_REFSELRESET(1U) + +#define S_SOFTRESET 1 +#define V_SOFTRESET(x) ((x) << S_SOFTRESET) +#define F_SOFTRESET V_SOFTRESET(1U) + +#define S_MACROTEST 0 +#define V_MACROTEST(x) ((x) << S_MACROTEST) +#define F_MACROTEST V_MACROTEST(1U) + +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c +#define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20 +#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24 +#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64 +#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70 +#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78 +#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c +#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90 +#define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0 +#define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc +#define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc +#define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10 +#define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28 + +#define S_T5CPISEL 0 +#define M_T5CPISEL 0x7U +#define V_T5CPISEL(x) ((x) << S_T5CPISEL) +#define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL) + +#define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c + +#define S_SPEDIV 3 +#define M_SPEDIV 0x1fU +#define V_SPEDIV(x) ((x) << S_SPEDIV) +#define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV) + +#define S_PCKSEL 0 +#define M_PCKSEL 0x7U +#define V_PCKSEL(x) ((x) << S_PCKSEL) +#define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40 + +#define S_EMIL 2 +#define V_EMIL(x) ((x) << S_EMIL) +#define F_EMIL V_EMIL(1U) + +#define S_EMID 1 +#define V_EMID(x) ((x) << S_EMID) +#define F_EMID V_EMID(1U) + +#define S_EMIS 0 +#define V_EMIS(x) ((x) << S_EMIS) +#define F_EMIS V_EMIS(1U) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44 + +#define S_EMIL1 0 +#define M_EMIL1 0xffU +#define V_EMIL1(x) ((x) << S_EMIL1) +#define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48 + +#define S_EMIL2 0 +#define M_EMIL2 0xffU +#define V_EMIL2(x) ((x) << S_EMIL2) +#define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c + +#define S_EMIL3 0 +#define M_EMIL3 0xffU +#define V_EMIL3(x) ((x) << S_EMIL3) +#define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50 + +#define S_EMIL4 0 +#define M_EMIL4 0xffU +#define V_EMIL4(x) ((x) << S_EMIL4) +#define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0 + +#define S_VBST 1 +#define M_VBST 0x7U +#define V_VBST(x) ((x) << S_VBST) +#define G_VBST(x) (((x) >> S_VBST) & M_VBST) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4 + +#define S_RESYNC 6 +#define V_RESYNC(x) ((x) << S_RESYNC) +#define F_RESYNC V_RESYNC(1U) + +#define S_RXCLKSEL 5 +#define V_RXCLKSEL(x) ((x) << S_RXCLKSEL) +#define F_RXCLKSEL V_RXCLKSEL(1U) + +#define S_FRCBAND 4 +#define V_FRCBAND(x) ((x) << S_FRCBAND) +#define F_FRCBAND V_FRCBAND(1U) + +#define S_PLLBYP 3 +#define V_PLLBYP(x) ((x) << S_PLLBYP) +#define F_PLLBYP V_PLLBYP(1U) + +#define S_PDWNP 2 +#define V_PDWNP(x) ((x) << S_PDWNP) +#define F_PDWNP V_PDWNP(1U) + +#define S_VCOSEL 1 +#define V_VCOSEL(x) ((x) << S_VCOSEL) +#define F_VCOSEL V_VCOSEL(1U) + +#define S_DIVSEL8 0 +#define V_DIVSEL8(x) ((x) << S_DIVSEL8) +#define F_DIVSEL8 V_DIVSEL8(1U) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8 + +#define S_DIVSEL 0 +#define M_DIVSEL 0xffU +#define V_DIVSEL(x) ((x) << S_DIVSEL) +#define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc + +#define S_CONFIG 0 +#define M_CONFIG 0xffU +#define V_CONFIG(x) ((x) << S_CONFIG) +#define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG) + +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10 +#define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28 +#define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 + +#define S_STEP 0 +#define M_STEP 0x7U +#define V_STEP(x) ((x) << S_STEP) +#define G_STEP(x) (((x) >> S_STEP) & M_STEP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 + +#define S_C0INIT 0 +#define M_C0INIT 0x1fU +#define V_C0INIT(x) ((x) << S_C0INIT) +#define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 + +#define S_C0MAX 8 +#define M_C0MAX 0x1fU +#define V_C0MAX(x) ((x) << S_C0MAX) +#define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX) + +#define S_C0MIN 0 +#define M_C0MIN 0x1fU +#define V_C0MIN(x) ((x) << S_C0MIN) +#define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 + +#define S_C1INIT 0 +#define M_C1INIT 0x7fU +#define V_C1INIT(x) ((x) << S_C1INIT) +#define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 + +#define S_C1MAX 8 +#define M_C1MAX 0x7fU +#define V_C1MAX(x) ((x) << S_C1MAX) +#define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX) + +#define S_C1MIN 0 +#define M_C1MIN 0x7fU +#define V_C1MIN(x) ((x) << S_C1MIN) +#define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 + +#define S_C2INIT 0 +#define M_C2INIT 0x3fU +#define V_C2INIT(x) ((x) << S_C2INIT) +#define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 + +#define S_C2MAX 8 +#define M_C2MAX 0x3fU +#define V_C2MAX(x) ((x) << S_C2MAX) +#define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX) + +#define S_C2MIN 0 +#define M_C2MIN 0x3fU +#define V_C2MIN(x) ((x) << S_C2MIN) +#define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 + +#define S_VMMAX 0 +#define M_VMMAX 0x7fU +#define V_VMMAX(x) ((x) << S_VMMAX) +#define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 + +#define S_V2MIN 0 +#define M_V2MIN 0x7fU +#define V_V2MIN(x) ((x) << S_V2MIN) +#define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN) + +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 + +/* registers for module MC_0 */ +#define MC_0_BASE_ADDR 0x40000 + +#define A_MC_UPCTL_SCFG 0x40000 + +#define S_BBFLAGS_TIMING 8 +#define M_BBFLAGS_TIMING 0xfU +#define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING) +#define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING) + +#define S_NFIFO_NIF1_DIS 6 +#define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS) +#define F_NFIFO_NIF1_DIS V_NFIFO_NIF1_DIS(1U) + +#define A_MC_UPCTL_SCTL 0x40004 +#define A_MC_UPCTL_STAT 0x40008 + +#define S_LP_TRIG 4 +#define M_LP_TRIG 0x7U +#define V_LP_TRIG(x) ((x) << S_LP_TRIG) +#define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG) + +#define A_MC_UPCTL_INTRSTAT 0x4000c + +#define S_PARITY_INTR 1 +#define V_PARITY_INTR(x) ((x) << S_PARITY_INTR) +#define F_PARITY_INTR V_PARITY_INTR(1U) + +#define S_ECC_INTR 0 +#define V_ECC_INTR(x) ((x) << S_ECC_INTR) +#define F_ECC_INTR V_ECC_INTR(1U) + +#define A_MC_UPCTL_MCMD 0x40040 + +#define S_CMD_OPCODE0 0 +#define M_CMD_OPCODE0 0xfU +#define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0) +#define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0) + +#define A_MC_UPCTL_POWCTL 0x40044 +#define A_MC_UPCTL_POWSTAT 0x40048 +#define A_MC_UPCTL_CMDTSTAT 0x4004c + +#define S_CMD_TSTAT 0 +#define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT) +#define F_CMD_TSTAT V_CMD_TSTAT(1U) + +#define A_MC_UPCTL_CMDTSTATEN 0x40050 + +#define S_CMD_TSTAT_EN 0 +#define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN) +#define F_CMD_TSTAT_EN V_CMD_TSTAT_EN(1U) + +#define A_MC_UPCTL_MRRCFG0 0x40060 + +#define S_MRR_BYTE_SEL 0 +#define M_MRR_BYTE_SEL 0xfU +#define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL) +#define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL) + +#define A_MC_UPCTL_MRRSTAT0 0x40064 + +#define S_MRRSTAT_BEAT3 24 +#define M_MRRSTAT_BEAT3 0xffU +#define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3) +#define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3) + +#define S_MRRSTAT_BEAT2 16 +#define M_MRRSTAT_BEAT2 0xffU +#define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2) +#define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2) + +#define S_MRRSTAT_BEAT1 8 +#define M_MRRSTAT_BEAT1 0xffU +#define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1) +#define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1) + +#define S_MRRSTAT_BEAT0 0 +#define M_MRRSTAT_BEAT0 0xffU +#define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0) +#define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0) + +#define A_MC_UPCTL_MRRSTAT1 0x40068 + +#define S_MRRSTAT_BEAT7 24 +#define M_MRRSTAT_BEAT7 0xffU +#define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7) +#define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7) + +#define S_MRRSTAT_BEAT6 16 +#define M_MRRSTAT_BEAT6 0xffU +#define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6) +#define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6) + +#define S_MRRSTAT_BEAT5 8 +#define M_MRRSTAT_BEAT5 0xffU +#define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5) +#define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5) + +#define S_MRRSTAT_BEAT4 0 +#define M_MRRSTAT_BEAT4 0xffU +#define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4) +#define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4) + +#define A_MC_UPCTL_MCFG1 0x4007c + +#define S_HW_EXIT_IDLE_EN 31 +#define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN) +#define F_HW_EXIT_IDLE_EN V_HW_EXIT_IDLE_EN(1U) + +#define S_HW_IDLE 16 +#define M_HW_IDLE 0xffU +#define V_HW_IDLE(x) ((x) << S_HW_IDLE) +#define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE) + +#define S_SR_IDLE 0 +#define M_SR_IDLE 0xffU +#define V_SR_IDLE(x) ((x) << S_SR_IDLE) +#define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE) + +#define A_MC_UPCTL_MCFG 0x40080 + +#define S_MDDR_LPDDR2_CLK_STOP_IDLE 24 +#define M_MDDR_LPDDR2_CLK_STOP_IDLE 0xffU +#define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE) +#define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE) + +#define S_MDDR_LPDDR2_EN 22 +#define M_MDDR_LPDDR2_EN 0x3U +#define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN) +#define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN) + +#define S_MDDR_LPDDR2_BL 20 +#define M_MDDR_LPDDR2_BL 0x3U +#define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL) +#define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL) + +#define S_LPDDR2_S4 6 +#define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4) +#define F_LPDDR2_S4 V_LPDDR2_S4(1U) + +#define S_STAGGER_CS 4 +#define V_STAGGER_CS(x) ((x) << S_STAGGER_CS) +#define F_STAGGER_CS V_STAGGER_CS(1U) + +#define S_CKE_OR_EN 1 +#define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN) +#define F_CKE_OR_EN V_CKE_OR_EN(1U) + +#define A_MC_UPCTL_PPCFG 0x40084 +#define A_MC_UPCTL_MSTAT 0x40088 + +#define S_SELF_REFRESH 2 +#define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH) +#define F_SELF_REFRESH V_SELF_REFRESH(1U) + +#define S_CLOCK_STOP 1 +#define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP) +#define F_CLOCK_STOP V_CLOCK_STOP(1U) + +#define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c + +#define S_ZQCL_OP 24 +#define M_ZQCL_OP 0xffU +#define V_ZQCL_OP(x) ((x) << S_ZQCL_OP) +#define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP) + +#define S_ZQCL_MA 16 +#define M_ZQCL_MA 0xffU +#define V_ZQCL_MA(x) ((x) << S_ZQCL_MA) +#define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA) + +#define S_ZQCS_OP 8 +#define M_ZQCS_OP 0xffU +#define V_ZQCS_OP(x) ((x) << S_ZQCS_OP) +#define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP) + +#define S_ZQCS_MA 0 +#define M_ZQCS_MA 0xffU +#define V_ZQCS_MA(x) ((x) << S_ZQCS_MA) +#define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA) + +#define A_MC_UPCTL_DTUPDES 0x40094 + +#define S_DTU_ERR_B7 7 +#define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7) +#define F_DTU_ERR_B7 V_DTU_ERR_B7(1U) + +#define A_MC_UPCTL_DTUNA 0x40098 +#define A_MC_UPCTL_DTUNE 0x4009c +#define A_MC_UPCTL_DTUPRD0 0x400a0 +#define A_MC_UPCTL_DTUPRD1 0x400a4 +#define A_MC_UPCTL_DTUPRD2 0x400a8 +#define A_MC_UPCTL_DTUPRD3 0x400ac +#define A_MC_UPCTL_DTUAWDT 0x400b0 +#define A_MC_UPCTL_TOGCNT1U 0x400c0 +#define A_MC_UPCTL_TINIT 0x400c4 +#define A_MC_UPCTL_TRSTH 0x400c8 +#define A_MC_UPCTL_TOGCNT100N 0x400cc +#define A_MC_UPCTL_TREFI 0x400d0 +#define A_MC_UPCTL_TMRD 0x400d4 +#define A_MC_UPCTL_TRFC 0x400d8 + +#define S_T_RFC0 0 +#define M_T_RFC0 0x1ffU +#define V_T_RFC0(x) ((x) << S_T_RFC0) +#define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0) + +#define A_MC_UPCTL_TRP 0x400dc + +#define S_PREA_EXTRA 16 +#define M_PREA_EXTRA 0x3U +#define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA) +#define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA) + +#define A_MC_UPCTL_TRTW 0x400e0 + +#define S_T_RTW0 0 +#define M_T_RTW0 0xfU +#define V_T_RTW0(x) ((x) << S_T_RTW0) +#define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0) + +#define A_MC_UPCTL_TAL 0x400e4 +#define A_MC_UPCTL_TCL 0x400e8 +#define A_MC_UPCTL_TCWL 0x400ec +#define A_MC_UPCTL_TRAS 0x400f0 +#define A_MC_UPCTL_TRC 0x400f4 +#define A_MC_UPCTL_TRCD 0x400f8 +#define A_MC_UPCTL_TRRD 0x400fc +#define A_MC_UPCTL_TRTP 0x40100 + +#define S_T_RTP0 0 +#define M_T_RTP0 0xfU +#define V_T_RTP0(x) ((x) << S_T_RTP0) +#define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0) + +#define A_MC_UPCTL_TWR 0x40104 + +#define S_U_T_WR 0 +#define M_U_T_WR 0x1fU +#define V_U_T_WR(x) ((x) << S_U_T_WR) +#define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR) + +#define A_MC_UPCTL_TWTR 0x40108 + +#define S_T_WTR0 0 +#define M_T_WTR0 0xfU +#define V_T_WTR0(x) ((x) << S_T_WTR0) +#define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0) + +#define A_MC_UPCTL_TEXSR 0x4010c +#define A_MC_UPCTL_TXP 0x40110 +#define A_MC_UPCTL_TXPDLL 0x40114 +#define A_MC_UPCTL_TZQCS 0x40118 +#define A_MC_UPCTL_TZQCSI 0x4011c +#define A_MC_UPCTL_TDQS 0x40120 +#define A_MC_UPCTL_TCKSRE 0x40124 + +#define S_T_CKSRE0 0 +#define M_T_CKSRE0 0x1fU +#define V_T_CKSRE0(x) ((x) << S_T_CKSRE0) +#define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0) + +#define A_MC_UPCTL_TCKSRX 0x40128 + +#define S_T_CKSRX0 0 +#define M_T_CKSRX0 0x1fU +#define V_T_CKSRX0(x) ((x) << S_T_CKSRX0) +#define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0) + +#define A_MC_UPCTL_TCKE 0x4012c +#define A_MC_UPCTL_TMOD 0x40130 + +#define S_T_MOD0 0 +#define M_T_MOD0 0x1fU +#define V_T_MOD0(x) ((x) << S_T_MOD0) +#define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0) + +#define A_MC_UPCTL_TRSTL 0x40134 + +#define S_T_RSTL 0 +#define M_T_RSTL 0x7fU +#define V_T_RSTL(x) ((x) << S_T_RSTL) +#define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL) + +#define A_MC_UPCTL_TZQCL 0x40138 +#define A_MC_UPCTL_TMRR 0x4013c + +#define S_T_MRR 0 +#define M_T_MRR 0xffU +#define V_T_MRR(x) ((x) << S_T_MRR) +#define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR) + +#define A_MC_UPCTL_TCKESR 0x40140 + +#define S_T_CKESR 0 +#define M_T_CKESR 0xfU +#define V_T_CKESR(x) ((x) << S_T_CKESR) +#define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR) + +#define A_MC_UPCTL_TDPD 0x40144 + +#define S_T_DPD 0 +#define M_T_DPD 0x3ffU +#define V_T_DPD(x) ((x) << S_T_DPD) +#define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD) + +#define A_MC_UPCTL_ECCCFG 0x40180 +#define A_MC_UPCTL_ECCTST 0x40184 + +#define S_ECC_TEST_MASK0 0 +#define M_ECC_TEST_MASK0 0x7fU +#define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0) +#define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0) + +#define A_MC_UPCTL_ECCCLR 0x40188 +#define A_MC_UPCTL_ECCLOG 0x4018c +#define A_MC_UPCTL_DTUWACTL 0x40200 + +#define S_DTU_WR_ROW0 13 +#define M_DTU_WR_ROW0 0xffffU +#define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0) +#define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0) + +#define A_MC_UPCTL_DTURACTL 0x40204 + +#define S_DTU_RD_ROW0 13 +#define M_DTU_RD_ROW0 0xffffU +#define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0) +#define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0) + +#define A_MC_UPCTL_DTUCFG 0x40208 +#define A_MC_UPCTL_DTUECTL 0x4020c +#define A_MC_UPCTL_DTUWD0 0x40210 +#define A_MC_UPCTL_DTUWD1 0x40214 +#define A_MC_UPCTL_DTUWD2 0x40218 +#define A_MC_UPCTL_DTUWD3 0x4021c +#define A_MC_UPCTL_DTUWDM 0x40220 +#define A_MC_UPCTL_DTURD0 0x40224 +#define A_MC_UPCTL_DTURD1 0x40228 +#define A_MC_UPCTL_DTURD2 0x4022c +#define A_MC_UPCTL_DTURD3 0x40230 +#define A_MC_UPCTL_DTULFSRWD 0x40234 +#define A_MC_UPCTL_DTULFSRRD 0x40238 +#define A_MC_UPCTL_DTUEAF 0x4023c + +#define S_EA_ROW0 13 +#define M_EA_ROW0 0xffffU +#define V_EA_ROW0(x) ((x) << S_EA_ROW0) +#define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0) + +#define A_MC_UPCTL_DFITCTRLDELAY 0x40240 + +#define S_TCTRL_DELAY 0 +#define M_TCTRL_DELAY 0xfU +#define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY) +#define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY) + +#define A_MC_UPCTL_DFIODTCFG 0x40244 + +#define S_RANK3_ODT_WRITE_NSEL 26 +#define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL) +#define F_RANK3_ODT_WRITE_NSEL V_RANK3_ODT_WRITE_NSEL(1U) + +#define A_MC_UPCTL_DFIODTCFG1 0x40248 + +#define S_ODT_LEN_B8_R 24 +#define M_ODT_LEN_B8_R 0x7U +#define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R) +#define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R) + +#define S_ODT_LEN_BL8_W 16 +#define M_ODT_LEN_BL8_W 0x7U +#define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W) +#define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W) + +#define S_ODT_LAT_R 8 +#define M_ODT_LAT_R 0x1fU +#define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R) +#define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R) + +#define S_ODT_LAT_W 0 +#define M_ODT_LAT_W 0x1fU +#define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W) +#define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W) + +#define A_MC_UPCTL_DFIODTRANKMAP 0x4024c + +#define S_ODT_RANK_MAP3 12 +#define M_ODT_RANK_MAP3 0xfU +#define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3) +#define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3) + +#define S_ODT_RANK_MAP2 8 +#define M_ODT_RANK_MAP2 0xfU +#define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2) +#define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2) + +#define S_ODT_RANK_MAP1 4 +#define M_ODT_RANK_MAP1 0xfU +#define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1) +#define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1) + +#define S_ODT_RANK_MAP0 0 +#define M_ODT_RANK_MAP0 0xfU +#define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0) +#define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0) + +#define A_MC_UPCTL_DFITPHYWRDATA 0x40250 + +#define S_TPHY_WRDATA 0 +#define M_TPHY_WRDATA 0x1fU +#define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA) +#define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA) + +#define A_MC_UPCTL_DFITPHYWRLAT 0x40254 + +#define S_TPHY_WRLAT 0 +#define M_TPHY_WRLAT 0x1fU +#define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT) +#define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT) + +#define A_MC_UPCTL_DFITRDDATAEN 0x40260 + +#define S_TRDDATA_EN 0 +#define M_TRDDATA_EN 0x1fU +#define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN) +#define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN) + +#define A_MC_UPCTL_DFITPHYRDLAT 0x40264 + +#define S_TPHY_RDLAT 0 +#define M_TPHY_RDLAT 0x3fU +#define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT) +#define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT) + +#define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270 + +#define S_TPHYUPD_TYPE0 0 +#define M_TPHYUPD_TYPE0 0xfffU +#define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0) +#define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0) + +#define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274 + +#define S_TPHYUPD_TYPE1 0 +#define M_TPHYUPD_TYPE1 0xfffU +#define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1) +#define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1) + +#define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278 + +#define S_TPHYUPD_TYPE2 0 +#define M_TPHYUPD_TYPE2 0xfffU +#define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2) +#define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2) + +#define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c + +#define S_TPHYUPD_TYPE3 0 +#define M_TPHYUPD_TYPE3 0xfffU +#define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3) +#define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3) + +#define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280 + +#define S_TCTRLUPD_MIN 0 +#define M_TCTRLUPD_MIN 0xffffU +#define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN) +#define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN) + +#define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284 + +#define S_TCTRLUPD_MAX 0 +#define M_TCTRLUPD_MAX 0xffffU +#define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX) +#define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX) + +#define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288 + +#define S_TCTRLUPD_DLY 0 +#define M_TCTRLUPD_DLY 0xfU +#define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY) +#define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY) + +#define A_MC_UPCTL_DFIUPDCFG 0x40290 + +#define S_DFI_PHYUPD_EN 1 +#define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN) +#define F_DFI_PHYUPD_EN V_DFI_PHYUPD_EN(1U) + +#define S_DFI_CTRLUPD_EN 0 +#define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN) +#define F_DFI_CTRLUPD_EN V_DFI_CTRLUPD_EN(1U) + +#define A_MC_UPCTL_DFITREFMSKI 0x40294 + +#define S_TREFMSKI 0 +#define M_TREFMSKI 0xffU +#define V_TREFMSKI(x) ((x) << S_TREFMSKI) +#define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI) + +#define A_MC_UPCTL_DFITCTRLUPDI 0x40298 +#define A_MC_UPCTL_DFITRCFG0 0x402ac + +#define S_DFI_WRLVL_RANK_SEL 16 +#define M_DFI_WRLVL_RANK_SEL 0xfU +#define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL) +#define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL) + +#define S_DFI_RDLVL_EDGE 4 +#define M_DFI_RDLVL_EDGE 0x1ffU +#define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE) +#define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE) + +#define S_DFI_RDLVL_RANK_SEL 0 +#define M_DFI_RDLVL_RANK_SEL 0xfU +#define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL) +#define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL) + +#define A_MC_UPCTL_DFITRSTAT0 0x402b0 + +#define S_DFI_WRLVL_MODE 16 +#define M_DFI_WRLVL_MODE 0x3U +#define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE) +#define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE) + +#define S_DFI_RDLVL_GATE_MODE 8 +#define M_DFI_RDLVL_GATE_MODE 0x3U +#define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE) +#define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE) + +#define S_DFI_RDLVL_MODE 0 +#define M_DFI_RDLVL_MODE 0x3U +#define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE) +#define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE) + +#define A_MC_UPCTL_DFITRWRLVLEN 0x402b4 + +#define S_DFI_WRLVL_EN 0 +#define M_DFI_WRLVL_EN 0x1ffU +#define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN) +#define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN) + +#define A_MC_UPCTL_DFITRRDLVLEN 0x402b8 + +#define S_DFI_RDLVL_EN 0 +#define M_DFI_RDLVL_EN 0x1ffU +#define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN) +#define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN) + +#define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc + +#define S_DFI_RDLVL_GATE_EN 0 +#define M_DFI_RDLVL_GATE_EN 0x1ffU +#define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN) +#define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN) + +#define A_MC_UPCTL_DFISTSTAT0 0x402c0 + +#define S_DFI_DATA_BYTE_DISABLE 16 +#define M_DFI_DATA_BYTE_DISABLE 0x1ffU +#define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE) +#define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE) + +#define S_DFI_FREQ_RATIO 4 +#define M_DFI_FREQ_RATIO 0x3U +#define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO) +#define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO) + +#define S_DFI_INIT_START0 1 +#define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0) +#define F_DFI_INIT_START0 V_DFI_INIT_START0(1U) + +#define S_DFI_INIT_COMPLETE 0 +#define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE) +#define F_DFI_INIT_COMPLETE V_DFI_INIT_COMPLETE(1U) + +#define A_MC_UPCTL_DFISTCFG0 0x402c4 + +#define S_DFI_DATA_BYTE_DISABLE_EN 2 +#define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN) +#define F_DFI_DATA_BYTE_DISABLE_EN V_DFI_DATA_BYTE_DISABLE_EN(1U) + +#define S_DFI_FREQ_RATIO_EN 1 +#define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN) +#define F_DFI_FREQ_RATIO_EN V_DFI_FREQ_RATIO_EN(1U) + +#define S_DFI_INIT_START 0 +#define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START) +#define F_DFI_INIT_START V_DFI_INIT_START(1U) + +#define A_MC_UPCTL_DFISTCFG1 0x402c8 + +#define S_DFI_DRAM_CLK_DISABLE_EN_DPD 1 +#define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD) +#define F_DFI_DRAM_CLK_DISABLE_EN_DPD V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U) + +#define S_DFI_DRAM_CLK_DISABLE_EN 0 +#define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN) +#define F_DFI_DRAM_CLK_DISABLE_EN V_DFI_DRAM_CLK_DISABLE_EN(1U) + +#define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0 + +#define S_TDRAM_CLK_ENABLE 0 +#define M_TDRAM_CLK_ENABLE 0xfU +#define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE) +#define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE) + +#define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4 + +#define S_TDRAM_CLK_DISABLE 0 +#define M_TDRAM_CLK_DISABLE 0xfU +#define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE) +#define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE) + +#define A_MC_UPCTL_DFISTCFG2 0x402d8 + +#define S_PARITY_EN 1 +#define V_PARITY_EN(x) ((x) << S_PARITY_EN) +#define F_PARITY_EN V_PARITY_EN(1U) + +#define S_PARITY_INTR_EN 0 +#define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN) +#define F_PARITY_INTR_EN V_PARITY_INTR_EN(1U) + +#define A_MC_UPCTL_DFISTPARCLR 0x402dc + +#define S_PARITY_LOG_CLR 1 +#define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR) +#define F_PARITY_LOG_CLR V_PARITY_LOG_CLR(1U) + +#define S_PARITY_INTR_CLR 0 +#define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR) +#define F_PARITY_INTR_CLR V_PARITY_INTR_CLR(1U) + +#define A_MC_UPCTL_DFISTPARLOG 0x402e0 +#define A_MC_UPCTL_DFILPCFG0 0x402f0 + +#define S_DFI_LP_WAKEUP_DPD 28 +#define M_DFI_LP_WAKEUP_DPD 0xfU +#define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD) +#define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD) + +#define S_DFI_LP_EN_DPD 24 +#define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD) +#define F_DFI_LP_EN_DPD V_DFI_LP_EN_DPD(1U) + +#define S_DFI_TLP_RESP 16 +#define M_DFI_TLP_RESP 0xfU +#define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP) +#define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP) + +#define S_DFI_LP_EN_SR 8 +#define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR) +#define F_DFI_LP_EN_SR V_DFI_LP_EN_SR(1U) + +#define S_DFI_LP_WAKEUP_PD 4 +#define M_DFI_LP_WAKEUP_PD 0xfU +#define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD) +#define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD) + +#define S_DFI_LP_EN_PD 0 +#define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD) +#define F_DFI_LP_EN_PD V_DFI_LP_EN_PD(1U) + +#define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300 +#define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304 +#define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308 + +#define S_DFI_WRLVL_RESP2 0 +#define M_DFI_WRLVL_RESP2 0xffU +#define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2) +#define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2) + +#define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c +#define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310 +#define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314 + +#define S_DFI_RDLVL_RESP2 0 +#define M_DFI_RDLVL_RESP2 0xffU +#define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2) +#define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2) + +#define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318 +#define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c +#define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320 + +#define S_DFI_WRLVL_DELAY2 0 +#define M_DFI_WRLVL_DELAY2 0xffU +#define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2) +#define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2) + +#define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324 +#define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328 +#define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c + +#define S_DFI_RDLVL_DELAY2 0 +#define M_DFI_RDLVL_DELAY2 0xffU +#define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2) +#define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2) + +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330 +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334 +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338 + +#define S_DFI_RDLVL_GATE_DELAY2 0 +#define M_DFI_RDLVL_GATE_DELAY2 0xffU +#define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2) +#define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2) + +#define A_MC_UPCTL_DFITRCMD 0x4033c + +#define S_DFITRCMD_START 31 +#define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START) +#define F_DFITRCMD_START V_DFITRCMD_START(1U) + +#define S_DFITRCMD_EN 4 +#define M_DFITRCMD_EN 0x1ffU +#define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN) +#define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN) + +#define S_DFITRCMD_OPCODE 0 +#define M_DFITRCMD_OPCODE 0x3U +#define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE) +#define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE) + +#define A_MC_UPCTL_IPVR 0x403f8 +#define A_MC_UPCTL_IPTR 0x403fc +#define A_MC_P_DDRPHY_RST_CTRL 0x41300 + +#define S_PHY_DRAM_WL 17 +#define M_PHY_DRAM_WL 0x1fU +#define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL) +#define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL) + +#define S_PHY_CALIB_DONE 5 +#define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE) +#define F_PHY_CALIB_DONE V_PHY_CALIB_DONE(1U) + +#define S_CTL_CAL_REQ 4 +#define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ) +#define F_CTL_CAL_REQ V_CTL_CAL_REQ(1U) + +#define S_CTL_CKE 3 +#define V_CTL_CKE(x) ((x) << S_CTL_CKE) +#define F_CTL_CKE V_CTL_CKE(1U) + +#define S_CTL_RST_N 2 +#define V_CTL_RST_N(x) ((x) << S_CTL_RST_N) +#define F_CTL_RST_N V_CTL_RST_N(1U) + +#define A_MC_P_PERFORMANCE_CTRL 0x41304 +#define A_MC_P_ECC_CTRL 0x41308 +#define A_MC_P_PAR_ENABLE 0x4130c +#define A_MC_P_PAR_CAUSE 0x41310 +#define A_MC_P_INT_ENABLE 0x41314 +#define A_MC_P_INT_CAUSE 0x41318 +#define A_MC_P_ECC_STATUS 0x4131c +#define A_MC_P_PHY_CTRL 0x41320 +#define A_MC_P_STATIC_CFG_STATUS 0x41324 + +#define S_STATIC_AWEN 23 +#define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN) +#define F_STATIC_AWEN V_STATIC_AWEN(1U) + +#define S_STATIC_SWLAT 18 +#define M_STATIC_SWLAT 0x1fU +#define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT) +#define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT) + +#define S_STATIC_WLAT 17 +#define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT) +#define F_STATIC_WLAT V_STATIC_WLAT(1U) + +#define S_STATIC_ALIGN 16 +#define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN) +#define F_STATIC_ALIGN V_STATIC_ALIGN(1U) + +#define S_STATIC_SLAT 11 +#define M_STATIC_SLAT 0x1fU +#define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT) +#define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT) + +#define S_STATIC_LAT 10 +#define V_STATIC_LAT(x) ((x) << S_STATIC_LAT) +#define F_STATIC_LAT V_STATIC_LAT(1U) + +#define A_MC_P_CORE_PCTL_STAT 0x41328 +#define A_MC_P_DEBUG_CNT 0x4132c +#define A_MC_CE_ERR_DATA_RDATA 0x41330 +#define A_MC_CE_COR_DATA_RDATA 0x41350 +#define A_MC_UE_ERR_DATA_RDATA 0x41370 +#define A_MC_UE_COR_DATA_RDATA 0x41390 +#define A_MC_CE_ADDR 0x413b0 +#define A_MC_UE_ADDR 0x413b4 +#define A_MC_P_DEEP_SLEEP 0x413b8 + +#define S_SLEEPSTATUS 1 +#define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS) +#define F_SLEEPSTATUS V_SLEEPSTATUS(1U) + +#define S_SLEEPREQ 0 +#define V_SLEEPREQ(x) ((x) << S_SLEEPREQ) +#define F_SLEEPREQ V_SLEEPREQ(1U) + +#define A_MC_P_FPGA_BONUS 0x413bc +#define A_MC_P_DEBUG_CFG 0x413c0 +#define A_MC_P_DEBUG_RPT 0x413c4 +#define A_MC_P_BIST_CMD 0x41400 + +#define S_BURST_LEN 16 +#define M_BURST_LEN 0x3U +#define V_BURST_LEN(x) ((x) << S_BURST_LEN) +#define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN) + +#define A_MC_P_BIST_CMD_ADDR 0x41404 +#define A_MC_P_BIST_CMD_LEN 0x41408 +#define A_MC_P_BIST_DATA_PATTERN 0x4140c +#define A_MC_P_BIST_USER_WDATA0 0x41414 +#define A_MC_P_BIST_USER_WDATA1 0x41418 +#define A_MC_P_BIST_USER_WDATA2 0x4141c + +#define S_USER_DATA_MASK 8 +#define M_USER_DATA_MASK 0x1ffU +#define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK) +#define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK) + +#define A_MC_P_BIST_NUM_ERR 0x41480 +#define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484 +#define A_MC_P_BIST_STATUS_RDATA 0x41488 +#define A_MC_P_BIST_CRC_SEED 0x414d0 +#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000 + +#define S_DATA_BIT_ENABLE_0_15 0 +#define M_DATA_BIT_ENABLE_0_15 0xffffU +#define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15) +#define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004 + +#define S_DATA_BIT_ENABLE_16_23 8 +#define M_DATA_BIT_ENABLE_16_23 0xffU +#define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23) +#define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23) + +#define S_DFT_FORCE_OUTPUTS 7 +#define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS) +#define F_DFT_FORCE_OUTPUTS V_DFT_FORCE_OUTPUTS(1U) + +#define S_DFT_PRBS7_GEN_EN 6 +#define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN) +#define F_DFT_PRBS7_GEN_EN V_DFT_PRBS7_GEN_EN(1U) + +#define S_WRAPSEL 5 +#define V_WRAPSEL(x) ((x) << S_WRAPSEL) +#define F_WRAPSEL V_WRAPSEL(1U) + +#define S_MRS_CMD_DATA_N0 3 +#define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0) +#define F_MRS_CMD_DATA_N0 V_MRS_CMD_DATA_N0(1U) + +#define S_MRS_CMD_DATA_N1 2 +#define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1) +#define F_MRS_CMD_DATA_N1 V_MRS_CMD_DATA_N1(1U) + +#define S_MRS_CMD_DATA_N2 1 +#define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2) +#define F_MRS_CMD_DATA_N2 V_MRS_CMD_DATA_N2(1U) + +#define S_MRS_CMD_DATA_N3 0 +#define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3) +#define F_MRS_CMD_DATA_N3 V_MRS_CMD_DATA_N3(1U) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008 + +#define S_DATA_BIT_DIR_0_15 0 +#define M_DATA_BIT_DIR_0_15 0xffffU +#define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15) +#define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c + +#define S_DATA_BIT_DIR_16_23 8 +#define M_DATA_BIT_DIR_16_23 0xffU +#define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23) +#define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23) + +#define S_WL_ADVANCE_DISABLE 7 +#define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE) +#define F_WL_ADVANCE_DISABLE V_WL_ADVANCE_DISABLE(1U) + +#define S_DISABLE_PING_PONG 6 +#define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG) +#define F_DISABLE_PING_PONG V_DISABLE_PING_PONG(1U) + +#define S_DELAY_PING_PONG_HALF 5 +#define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF) +#define F_DELAY_PING_PONG_HALF V_DELAY_PING_PONG_HALF(1U) + +#define S_ADVANCE_PING_PONG 4 +#define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG) +#define F_ADVANCE_PING_PONG V_ADVANCE_PING_PONG(1U) + +#define S_ATEST_MUX_CTL0 3 +#define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0) +#define F_ATEST_MUX_CTL0 V_ATEST_MUX_CTL0(1U) + +#define S_ATEST_MUX_CTL1 2 +#define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1) +#define F_ATEST_MUX_CTL1 V_ATEST_MUX_CTL1(1U) + +#define S_ATEST_MUX_CTL2 1 +#define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2) +#define F_ATEST_MUX_CTL2 V_ATEST_MUX_CTL2(1U) + +#define S_ATEST_MUX_CTL3 0 +#define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3) +#define F_ATEST_MUX_CTL3 V_ATEST_MUX_CTL3(1U) + +#define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010 + +#define S_QUAD0_CLK16_BIT0 15 +#define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0) +#define F_QUAD0_CLK16_BIT0 V_QUAD0_CLK16_BIT0(1U) + +#define S_QUAD1_CLK16_BIT1 14 +#define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1) +#define F_QUAD1_CLK16_BIT1 V_QUAD1_CLK16_BIT1(1U) + +#define S_QUAD2_CLK16_BIT2 13 +#define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2) +#define F_QUAD2_CLK16_BIT2 V_QUAD2_CLK16_BIT2(1U) + +#define S_QUAD3_CLK16_BIT3 12 +#define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3) +#define F_QUAD3_CLK16_BIT3 V_QUAD3_CLK16_BIT3(1U) + +#define S_QUAD0_CLK18_BIT4 11 +#define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4) +#define F_QUAD0_CLK18_BIT4 V_QUAD0_CLK18_BIT4(1U) + +#define S_QUAD1_CLK18_BIT5 10 +#define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5) +#define F_QUAD1_CLK18_BIT5 V_QUAD1_CLK18_BIT5(1U) + +#define S_QUAD2_CLK20_BIT6 9 +#define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6) +#define F_QUAD2_CLK20_BIT6 V_QUAD2_CLK20_BIT6(1U) + +#define S_QUAD3_CLK20_BIT7 8 +#define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7) +#define F_QUAD3_CLK20_BIT7 V_QUAD3_CLK20_BIT7(1U) + +#define S_QUAD2_CLK22_BIT8 7 +#define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8) +#define F_QUAD2_CLK22_BIT8 V_QUAD2_CLK22_BIT8(1U) + +#define S_QUAD3_CLK22_BIT9 6 +#define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9) +#define F_QUAD3_CLK22_BIT9 V_QUAD3_CLK22_BIT9(1U) + +#define S_CLK16_SINGLE_ENDED_BIT10 5 +#define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10) +#define F_CLK16_SINGLE_ENDED_BIT10 V_CLK16_SINGLE_ENDED_BIT10(1U) + +#define S_CLK18_SINGLE_ENDED_BIT11 4 +#define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11) +#define F_CLK18_SINGLE_ENDED_BIT11 V_CLK18_SINGLE_ENDED_BIT11(1U) + +#define S_CLK20_SINGLE_ENDED_BIT12 3 +#define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12) +#define F_CLK20_SINGLE_ENDED_BIT12 V_CLK20_SINGLE_ENDED_BIT12(1U) + +#define S_CLK22_SINGLE_ENDED_BIT13 2 +#define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13) +#define F_CLK22_SINGLE_ENDED_BIT13 V_CLK22_SINGLE_ENDED_BIT13(1U) + +#define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014 + +#define S_QUAD2_CLK18_BIT14 1 +#define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14) +#define F_QUAD2_CLK18_BIT14 V_QUAD2_CLK18_BIT14(1U) + +#define S_QUAD3_CLK18_BIT15 0 +#define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15) +#define F_QUAD3_CLK18_BIT15 V_QUAD3_CLK18_BIT15(1U) + +#define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018 + +#define S_PEAK_AMP_CTL_SIDE0 13 +#define M_PEAK_AMP_CTL_SIDE0 0x7U +#define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0) +#define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0) + +#define S_PEAK_AMP_CTL_SIDE1 9 +#define M_PEAK_AMP_CTL_SIDE1 0x7U +#define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1) +#define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1) + +#define S_SXMCVREF_0_3 4 +#define M_SXMCVREF_0_3 0xfU +#define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3) +#define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3) + +#define S_SXPODVREF 3 +#define V_SXPODVREF(x) ((x) << S_SXPODVREF) +#define F_SXPODVREF V_SXPODVREF(1U) + +#define S_DISABLE_TERMINATION 2 +#define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION) +#define F_DISABLE_TERMINATION V_DISABLE_TERMINATION(1U) + +#define S_READ_CENTERING_MODE 0 +#define M_READ_CENTERING_MODE 0x3U +#define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE) +#define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE) + +#define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c + +#define S_SYSCLK_PHASE_ALIGN_RESET 6 +#define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET) +#define F_SYSCLK_PHASE_ALIGN_RESET V_SYSCLK_PHASE_ALIGN_RESET(1U) + +#define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020 + +#define S_DIGITAL_EYE_EN 15 +#define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN) +#define F_DIGITAL_EYE_EN V_DIGITAL_EYE_EN(1U) + +#define S_BUMP 14 +#define V_BUMP(x) ((x) << S_BUMP) +#define F_BUMP V_BUMP(1U) + +#define S_TRIG_PERIOD 13 +#define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD) +#define F_TRIG_PERIOD V_TRIG_PERIOD(1U) + +#define S_CNTL_POL 12 +#define V_CNTL_POL(x) ((x) << S_CNTL_POL) +#define F_CNTL_POL V_CNTL_POL(1U) + +#define S_CNTL_SRC 8 +#define V_CNTL_SRC(x) ((x) << S_CNTL_SRC) +#define F_CNTL_SRC V_CNTL_SRC(1U) + +#define S_DIGITAL_EYE_VALUE 0 +#define M_DIGITAL_EYE_VALUE 0xffU +#define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE) +#define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE) + +#define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024 + +#define S_DQSCLK_SELECT0 14 +#define M_DQSCLK_SELECT0 0x3U +#define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0) +#define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0) + +#define S_RDCLK_SELECT0 12 +#define M_RDCLK_SELECT0 0x3U +#define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0) +#define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0) + +#define S_DQSCLK_SELECT1 10 +#define M_DQSCLK_SELECT1 0x3U +#define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1) +#define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1) + +#define S_RDCLK_SELECT1 8 +#define M_RDCLK_SELECT1 0x3U +#define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1) +#define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1) + +#define S_DQSCLK_SELECT2 6 +#define M_DQSCLK_SELECT2 0x3U +#define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2) +#define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2) + +#define S_RDCLK_SELECT2 4 +#define M_RDCLK_SELECT2 0x3U +#define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2) +#define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2) + +#define S_DQSCLK_SELECT3 2 +#define M_DQSCLK_SELECT3 0x3U +#define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3) +#define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3) + +#define S_RDCLK_SELECT3 0 +#define M_RDCLK_SELECT3 0x3U +#define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3) +#define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3) + +#define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028 + +#define S_MIN_RD_EYE_SIZE 8 +#define M_MIN_RD_EYE_SIZE 0x3fU +#define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE) +#define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE) + +#define S_MAX_DQS_DRIFT 0 +#define M_MAX_DQS_DRIFT 0x3fU +#define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT) +#define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT) + +#define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c + +#define S_HS_PROBE_A_SEL 11 +#define M_HS_PROBE_A_SEL 0x1fU +#define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL) +#define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL) + +#define S_HS_PROBE_B_SEL 6 +#define M_HS_PROBE_B_SEL 0x1fU +#define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL) +#define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL) + +#define S_RD_DEBUG_SEL 3 +#define M_RD_DEBUG_SEL 0x7U +#define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL) +#define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL) + +#define S_WR_DEBUG_SEL 0 +#define M_WR_DEBUG_SEL 0x7U +#define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL) +#define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL) + +#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030 + +#define S_OFFSET_BITS1_7 8 +#define M_OFFSET_BITS1_7 0x7fU +#define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7) +#define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7) + +#define S_OFFSET_BITS9_15 0 +#define M_OFFSET_BITS9_15 0x7fU +#define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15) +#define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15) + +#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034 +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038 + +#define S_LEADING_EDGE_NOT_FOUND_0 0 +#define M_LEADING_EDGE_NOT_FOUND_0 0xffffU +#define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0) +#define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c + +#define S_LEADING_EDGE_NOT_FOUND_1 8 +#define M_LEADING_EDGE_NOT_FOUND_1 0xffU +#define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1) +#define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040 + +#define S_TRAILING_EDGE_NOT_FOUND 0 +#define M_TRAILING_EDGE_NOT_FOUND 0xffffU +#define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND) +#define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044 + +#define S_TRAILING_EDGE_NOT_FOUND_16_23 8 +#define M_TRAILING_EDGE_NOT_FOUND_16_23 0xffU +#define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23) +#define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048 + +#define S_DYN_POWER_CNTL_EN 15 +#define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN) +#define F_DYN_POWER_CNTL_EN V_DYN_POWER_CNTL_EN(1U) + +#define S_DYN_MCTERM_CNTL_EN 14 +#define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN) +#define F_DYN_MCTERM_CNTL_EN V_DYN_MCTERM_CNTL_EN(1U) + +#define S_DYN_RX_GATE_CNTL_EN 13 +#define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN) +#define F_DYN_RX_GATE_CNTL_EN V_DYN_RX_GATE_CNTL_EN(1U) + +#define S_CALGATE_ON 12 +#define V_CALGATE_ON(x) ((x) << S_CALGATE_ON) +#define F_CALGATE_ON V_CALGATE_ON(1U) + +#define S_PER_RDCLK_UPDATE_DIS 11 +#define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS) +#define F_PER_RDCLK_UPDATE_DIS V_PER_RDCLK_UPDATE_DIS(1U) + +#define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c + +#define S_DQS_GATE_DELAY_N0 12 +#define M_DQS_GATE_DELAY_N0 0x7U +#define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0) +#define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0) + +#define S_DQS_GATE_DELAY_N1 8 +#define M_DQS_GATE_DELAY_N1 0x7U +#define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1) +#define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1) + +#define S_DQS_GATE_DELAY_N2 4 +#define M_DQS_GATE_DELAY_N2 0x7U +#define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2) +#define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2) + +#define S_DQS_GATE_DELAY_N3 0 +#define M_DQS_GATE_DELAY_N3 0x7U +#define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3) +#define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3) + +#define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050 + +#define S_NO_EYE_DETECTED 15 +#define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED) +#define F_NO_EYE_DETECTED V_NO_EYE_DETECTED(1U) + +#define S_LEADING_EDGE_FOUND 14 +#define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND) +#define F_LEADING_EDGE_FOUND V_LEADING_EDGE_FOUND(1U) + +#define S_TRAILING_EDGE_FOUND 13 +#define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND) +#define F_TRAILING_EDGE_FOUND V_TRAILING_EDGE_FOUND(1U) + +#define S_INCOMPLETE_RD_CAL_N0 12 +#define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0) +#define F_INCOMPLETE_RD_CAL_N0 V_INCOMPLETE_RD_CAL_N0(1U) + +#define S_INCOMPLETE_RD_CAL_N1 11 +#define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1) +#define F_INCOMPLETE_RD_CAL_N1 V_INCOMPLETE_RD_CAL_N1(1U) + +#define S_INCOMPLETE_RD_CAL_N2 10 +#define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2) +#define F_INCOMPLETE_RD_CAL_N2 V_INCOMPLETE_RD_CAL_N2(1U) + +#define S_INCOMPLETE_RD_CAL_N3 9 +#define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3) +#define F_INCOMPLETE_RD_CAL_N3 V_INCOMPLETE_RD_CAL_N3(1U) + +#define S_COARSE_PATTERN_ERR_N0 8 +#define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0) +#define F_COARSE_PATTERN_ERR_N0 V_COARSE_PATTERN_ERR_N0(1U) + +#define S_COARSE_PATTERN_ERR_N1 7 +#define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1) +#define F_COARSE_PATTERN_ERR_N1 V_COARSE_PATTERN_ERR_N1(1U) + +#define S_COARSE_PATTERN_ERR_N2 6 +#define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2) +#define F_COARSE_PATTERN_ERR_N2 V_COARSE_PATTERN_ERR_N2(1U) + +#define S_COARSE_PATTERN_ERR_N3 5 +#define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3) +#define F_COARSE_PATTERN_ERR_N3 V_COARSE_PATTERN_ERR_N3(1U) + +#define S_EYE_CLIPPING 4 +#define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING) +#define F_EYE_CLIPPING V_EYE_CLIPPING(1U) + +#define S_NO_DQS 3 +#define V_NO_DQS(x) ((x) << S_NO_DQS) +#define F_NO_DQS V_NO_DQS(1U) + +#define S_NO_LOCK 2 +#define V_NO_LOCK(x) ((x) << S_NO_LOCK) +#define F_NO_LOCK V_NO_LOCK(1U) + +#define S_DRIFT_ERROR 1 +#define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR) +#define F_DRIFT_ERROR V_DRIFT_ERROR(1U) + +#define S_MIN_EYE 0 +#define V_MIN_EYE(x) ((x) << S_MIN_EYE) +#define F_MIN_EYE V_MIN_EYE(1U) + +#define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054 + +#define S_NO_EYE_DETECTED_MASK 15 +#define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK) +#define F_NO_EYE_DETECTED_MASK V_NO_EYE_DETECTED_MASK(1U) + +#define S_LEADING_EDGE_FOUND_MASK 14 +#define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK) +#define F_LEADING_EDGE_FOUND_MASK V_LEADING_EDGE_FOUND_MASK(1U) + +#define S_TRAILING_EDGE_FOUND_MASK 13 +#define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK) +#define F_TRAILING_EDGE_FOUND_MASK V_TRAILING_EDGE_FOUND_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N0_MASK 12 +#define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK) +#define F_INCOMPLETE_RD_CAL_N0_MASK V_INCOMPLETE_RD_CAL_N0_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N1_MASK 11 +#define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK) +#define F_INCOMPLETE_RD_CAL_N1_MASK V_INCOMPLETE_RD_CAL_N1_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N2_MASK 10 +#define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK) +#define F_INCOMPLETE_RD_CAL_N2_MASK V_INCOMPLETE_RD_CAL_N2_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N3_MASK 9 +#define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK) +#define F_INCOMPLETE_RD_CAL_N3_MASK V_INCOMPLETE_RD_CAL_N3_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N0_MASK 8 +#define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK) +#define F_COARSE_PATTERN_ERR_N0_MASK V_COARSE_PATTERN_ERR_N0_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N1_MASK 7 +#define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK) +#define F_COARSE_PATTERN_ERR_N1_MASK V_COARSE_PATTERN_ERR_N1_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N2_MASK 6 +#define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK) +#define F_COARSE_PATTERN_ERR_N2_MASK V_COARSE_PATTERN_ERR_N2_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N3_MASK 5 +#define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK) +#define F_COARSE_PATTERN_ERR_N3_MASK V_COARSE_PATTERN_ERR_N3_MASK(1U) + +#define S_EYE_CLIPPING_MASK 4 +#define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK) +#define F_EYE_CLIPPING_MASK V_EYE_CLIPPING_MASK(1U) + +#define S_NO_DQS_MASK 3 +#define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK) +#define F_NO_DQS_MASK V_NO_DQS_MASK(1U) + +#define S_NO_LOCK_MASK 2 +#define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK) +#define F_NO_LOCK_MASK V_NO_LOCK_MASK(1U) + +#define S_DRIFT_ERROR_MASK 1 +#define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK) +#define F_DRIFT_ERROR_MASK V_DRIFT_ERROR_MASK(1U) + +#define S_MIN_EYE_MASK 0 +#define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK) +#define F_MIN_EYE_MASK V_MIN_EYE_MASK(1U) + +#define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c + +#define S_CLK_LEVEL 14 +#define M_CLK_LEVEL 0x3U +#define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL) +#define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL) + +#define S_FINE_STEPPING 13 +#define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING) +#define F_FINE_STEPPING V_FINE_STEPPING(1U) + +#define S_DONE 12 +#define V_DONE(x) ((x) << S_DONE) +#define F_DONE V_DONE(1U) + +#define S_WL_ERR_CLK16_ST 11 +#define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST) +#define F_WL_ERR_CLK16_ST V_WL_ERR_CLK16_ST(1U) + +#define S_WL_ERR_CLK18_ST 10 +#define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST) +#define F_WL_ERR_CLK18_ST V_WL_ERR_CLK18_ST(1U) + +#define S_WL_ERR_CLK20_ST 9 +#define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST) +#define F_WL_ERR_CLK20_ST V_WL_ERR_CLK20_ST(1U) + +#define S_WL_ERR_CLK22_ST 8 +#define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST) +#define F_WL_ERR_CLK22_ST V_WL_ERR_CLK22_ST(1U) + +#define S_ZERO_DETECTED 7 +#define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED) +#define F_ZERO_DETECTED V_ZERO_DETECTED(1U) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060 + +#define S_BIT_CENTERED 11 +#define M_BIT_CENTERED 0x1fU +#define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED) +#define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED) + +#define S_SMALL_STEP_LEFT 10 +#define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT) +#define F_SMALL_STEP_LEFT V_SMALL_STEP_LEFT(1U) + +#define S_BIG_STEP_RIGHT 9 +#define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT) +#define F_BIG_STEP_RIGHT V_BIG_STEP_RIGHT(1U) + +#define S_MATCH_STEP_RIGHT 8 +#define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT) +#define F_MATCH_STEP_RIGHT V_MATCH_STEP_RIGHT(1U) + +#define S_JUMP_BACK_RIGHT 7 +#define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT) +#define F_JUMP_BACK_RIGHT V_JUMP_BACK_RIGHT(1U) + +#define S_SMALL_STEP_RIGHT 6 +#define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT) +#define F_SMALL_STEP_RIGHT V_SMALL_STEP_RIGHT(1U) + +#define S_DDONE 5 +#define V_DDONE(x) ((x) << S_DDONE) +#define F_DDONE V_DDONE(1U) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064 + +#define S_FW_LEFT_SIDE 5 +#define M_FW_LEFT_SIDE 0x7ffU +#define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE) +#define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068 + +#define S_FW_RIGHT_SIDE 5 +#define M_FW_RIGHT_SIDE 0x7ffU +#define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE) +#define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE) + +#define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c + +#define S_WL_ERR_CLK16 15 +#define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16) +#define F_WL_ERR_CLK16 V_WL_ERR_CLK16(1U) + +#define S_WL_ERR_CLK18 14 +#define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18) +#define F_WL_ERR_CLK18 V_WL_ERR_CLK18(1U) + +#define S_WL_ERR_CLK20 13 +#define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20) +#define F_WL_ERR_CLK20 V_WL_ERR_CLK20(1U) + +#define S_WL_ERR_CLK22 12 +#define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22) +#define F_WL_ERR_CLK22 V_WL_ERR_CLK22(1U) + +#define S_VALID_NS_BIG_L 7 +#define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L) +#define F_VALID_NS_BIG_L V_VALID_NS_BIG_L(1U) + +#define S_INVALID_NS_SMALL_L 6 +#define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L) +#define F_INVALID_NS_SMALL_L V_INVALID_NS_SMALL_L(1U) + +#define S_VALID_NS_BIG_R 5 +#define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R) +#define F_VALID_NS_BIG_R V_VALID_NS_BIG_R(1U) + +#define S_INVALID_NS_BIG_R 4 +#define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R) +#define F_INVALID_NS_BIG_R V_INVALID_NS_BIG_R(1U) + +#define S_VALID_NS_JUMP_BACK 3 +#define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK) +#define F_VALID_NS_JUMP_BACK V_VALID_NS_JUMP_BACK(1U) + +#define S_INVALID_NS_SMALL_R 2 +#define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R) +#define F_INVALID_NS_SMALL_R V_INVALID_NS_SMALL_R(1U) + +#define S_OFFSET_ERR 1 +#define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR) +#define F_OFFSET_ERR V_OFFSET_ERR(1U) + +#define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070 + +#define S_WL_ERR_CLK16_MASK 15 +#define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK) +#define F_WL_ERR_CLK16_MASK V_WL_ERR_CLK16_MASK(1U) + +#define S_WL_ERR_CLK18_MASK 14 +#define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK) +#define F_WL_ERR_CLK18_MASK V_WL_ERR_CLK18_MASK(1U) + +#define S_WL_ERR_CLK20_MASK 13 +#define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK) +#define F_WL_ERR_CLK20_MASK V_WL_ERR_CLK20_MASK(1U) + +#define S_WR_ERR_CLK22_MASK 12 +#define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK) +#define F_WR_ERR_CLK22_MASK V_WR_ERR_CLK22_MASK(1U) + +#define S_VALID_NS_BIG_L_MASK 7 +#define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK) +#define F_VALID_NS_BIG_L_MASK V_VALID_NS_BIG_L_MASK(1U) + +#define S_INVALID_NS_SMALL_L_MASK 6 +#define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK) +#define F_INVALID_NS_SMALL_L_MASK V_INVALID_NS_SMALL_L_MASK(1U) + +#define S_VALID_NS_BIG_R_MASK 5 +#define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK) +#define F_VALID_NS_BIG_R_MASK V_VALID_NS_BIG_R_MASK(1U) + +#define S_INVALID_NS_BIG_R_MASK 4 +#define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK) +#define F_INVALID_NS_BIG_R_MASK V_INVALID_NS_BIG_R_MASK(1U) + +#define S_VALID_NS_JUMP_BACK_MASK 3 +#define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK) +#define F_VALID_NS_JUMP_BACK_MASK V_VALID_NS_JUMP_BACK_MASK(1U) + +#define S_INVALID_NS_SMALL_R_MASK 2 +#define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK) +#define F_INVALID_NS_SMALL_R_MASK V_INVALID_NS_SMALL_R_MASK(1U) + +#define S_OFFSET_ERR_MASK 1 +#define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK) +#define F_OFFSET_ERR_MASK V_OFFSET_ERR_MASK(1U) + +#define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074 + +#define S_CHECKER_RESET 14 +#define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET) +#define F_CHECKER_RESET V_CHECKER_RESET(1U) + +#define S_DP18_DFT_SYNC 6 +#define M_DP18_DFT_SYNC 0x3fU +#define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC) +#define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC) + +#define S_ERROR 0 +#define M_ERROR 0x3fU +#define V_ERROR(x) ((x) << S_ERROR) +#define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078 +#define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0 + +#define S_DQSCLK_ROT_CLK_N0_N2 8 +#define M_DQSCLK_ROT_CLK_N0_N2 0x7fU +#define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2) +#define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2) + +#define S_DQSCLK_ROT_CLK_N1_N3 0 +#define M_DQSCLK_ROT_CLK_N1_N3 0x7fU +#define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3) +#define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3) + +#define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4 +#define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8 + +#define S_MEMINTD00_POS 14 +#define M_MEMINTD00_POS 0x3U +#define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS) +#define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS) + +#define S_MEMINTD01_PO 12 +#define M_MEMINTD01_PO 0x3U +#define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO) +#define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO) + +#define S_MEMINTD02_POS 10 +#define M_MEMINTD02_POS 0x3U +#define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS) +#define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS) + +#define S_MEMINTD03_POS 8 +#define M_MEMINTD03_POS 0x3U +#define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS) +#define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS) + +#define S_MEMINTD04_POS 6 +#define M_MEMINTD04_POS 0x3U +#define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS) +#define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS) + +#define S_MEMINTD05_POS 4 +#define M_MEMINTD05_POS 0x3U +#define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS) +#define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS) + +#define S_MEMINTD06_POS 2 +#define M_MEMINTD06_POS 0x3U +#define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS) +#define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS) + +#define S_MEMINTD07_POS 0 +#define M_MEMINTD07_POS 0x3U +#define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS) +#define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS) + +#define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc + +#define S_MEMINTD08_POS 14 +#define M_MEMINTD08_POS 0x3U +#define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS) +#define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS) + +#define S_MEMINTD09_POS 12 +#define M_MEMINTD09_POS 0x3U +#define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS) +#define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS) + +#define S_MEMINTD10_POS 10 +#define M_MEMINTD10_POS 0x3U +#define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS) +#define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS) + +#define S_MEMINTD11_POS 8 +#define M_MEMINTD11_POS 0x3U +#define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS) +#define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS) + +#define S_MEMINTD12_POS 6 +#define M_MEMINTD12_POS 0x3U +#define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS) +#define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS) + +#define S_MEMINTD13_POS 4 +#define M_MEMINTD13_POS 0x3U +#define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS) +#define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS) + +#define S_MEMINTD14_POS 2 +#define M_MEMINTD14_POS 0x3U +#define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS) +#define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS) + +#define S_MEMINTD15_POS 0 +#define M_MEMINTD15_POS 0x3U +#define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS) +#define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS) + +#define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0 + +#define S_MEMINTD16_POS 14 +#define M_MEMINTD16_POS 0x3U +#define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS) +#define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS) + +#define S_MEMINTD17_POS 12 +#define M_MEMINTD17_POS 0x3U +#define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS) +#define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS) + +#define S_MEMINTD18_POS 10 +#define M_MEMINTD18_POS 0x3U +#define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS) +#define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS) + +#define S_MEMINTD19_POS 8 +#define M_MEMINTD19_POS 0x3U +#define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS) +#define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS) + +#define S_MEMINTD20_POS 6 +#define M_MEMINTD20_POS 0x3U +#define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS) +#define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS) + +#define S_MEMINTD21_POS 4 +#define M_MEMINTD21_POS 0x3U +#define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS) +#define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS) + +#define S_MEMINTD22_POS 2 +#define M_MEMINTD22_POS 0x3U +#define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS) +#define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS) + +#define S_MEMINTD23_POS 0 +#define M_MEMINTD23_POS 0x3U +#define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS) +#define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4 +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8 +#define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc + +#define S_DQS_OFFSET 8 +#define M_DQS_OFFSET 0x7fU +#define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET) +#define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET) + +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0 + +#define S_WR_DELAY 6 +#define M_WR_DELAY 0x3ffU +#define V_WR_DELAY(x) ((x) << S_WR_DELAY) +#define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY) + +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c +#define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140 + +#define S_RD_DELAY_BITS0_6 9 +#define M_RD_DELAY_BITS0_6 0x7fU +#define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6) +#define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6) + +#define S_RD_DELAY_BITS8_14 1 +#define M_RD_DELAY_BITS8_14 0x7fU +#define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14) +#define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14) + +#define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144 +#define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148 +#define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c +#define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150 +#define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154 +#define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158 +#define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c +#define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160 +#define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164 +#define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168 +#define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c +#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170 + +#define S_INITIAL_DQS_ROT_N0_N2 8 +#define M_INITIAL_DQS_ROT_N0_N2 0x7fU +#define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2) +#define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2) + +#define S_INITIAL_DQS_ROT_N1_N3 0 +#define M_INITIAL_DQS_ROT_N1_N3 0x7fU +#define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3) +#define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3) + +#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180 + +#define S_RD_EYE_SIZE_BITS2_7 8 +#define M_RD_EYE_SIZE_BITS2_7 0x3fU +#define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7) +#define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7) + +#define S_RD_EYE_SIZE_BITS10_15 0 +#define M_RD_EYE_SIZE_BITS10_15 0x3fU +#define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15) +#define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15) + +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4 +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8 +#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0 + +#define S_REFERENCE_BITS1_7 8 +#define M_REFERENCE_BITS1_7 0x7fU +#define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7) +#define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7) + +#define S_REFERENCE_BITS9_15 0 +#define M_REFERENCE_BITS9_15 0x7fU +#define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15) +#define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15) + +#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4 +#define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8 + +#define S_REFERENCE 8 +#define M_REFERENCE 0x7fU +#define V_REFERENCE(x) ((x) << S_REFERENCE) +#define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE) + +#define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc +#define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0 +#define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4 + +#define S_INTERP_SIG_SLEW 12 +#define M_INTERP_SIG_SLEW 0xfU +#define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW) +#define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW) + +#define S_POST_CURSOR 8 +#define M_POST_CURSOR 0xfU +#define V_POST_CURSOR(x) ((x) << S_POST_CURSOR) +#define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR) + +#define S_SLEW_CTL 4 +#define M_SLEW_CTL 0xfU +#define V_SLEW_CTL(x) ((x) << S_SLEW_CTL) +#define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL) + +#define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8 +#define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc + +#define S_CE0DLTVCCA 7 +#define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA) +#define F_CE0DLTVCCA V_CE0DLTVCCA(1U) + +#define S_CE0DLTVCCD1 4 +#define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1) +#define F_CE0DLTVCCD1 V_CE0DLTVCCD1(1U) + +#define S_CE0DLTVCCD2 3 +#define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2) +#define F_CE0DLTVCCD2 V_CE0DLTVCCD2(1U) + +#define S_S0INSDLYTAP 2 +#define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP) +#define F_S0INSDLYTAP V_S0INSDLYTAP(1U) + +#define S_S1INSDLYTAP 1 +#define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP) +#define F_S1INSDLYTAP V_S1INSDLYTAP(1U) + +#define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0 + +#define S_EN_SLICE_N_WR 8 +#define M_EN_SLICE_N_WR 0xffU +#define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR) +#define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR) + +#define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4 +#define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8 + +#define S_EN_TERM_N_WR 8 +#define M_EN_TERM_N_WR 0xffU +#define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR) +#define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR) + +#define S_EN_TERM_N_WR_FFE 4 +#define M_EN_TERM_N_WR_FFE 0xfU +#define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE) +#define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE) + +#define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec + +#define S_EN_TERM_P_WR 8 +#define M_EN_TERM_P_WR 0xffU +#define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR) +#define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR) + +#define S_EN_TERM_P_WR_FFE 4 +#define M_EN_TERM_P_WR_FFE 0xfU +#define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE) +#define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0 + +#define S_DATA_BIT_DISABLE_0_15 0 +#define M_DATA_BIT_DISABLE_0_15 0xffffU +#define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15) +#define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4 + +#define S_DATA_BIT_DISABLE_16_23 8 +#define M_DATA_BIT_DISABLE_16_23 0xffU +#define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23) +#define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23) + +#define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8 + +#define S_DQ_WR_OFFSET_N0 12 +#define M_DQ_WR_OFFSET_N0 0xfU +#define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0) +#define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0) + +#define S_DQ_WR_OFFSET_N1 8 +#define M_DQ_WR_OFFSET_N1 0xfU +#define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1) +#define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1) + +#define S_DQ_WR_OFFSET_N2 4 +#define M_DQ_WR_OFFSET_N2 0xfU +#define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2) +#define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2) + +#define S_DQ_WR_OFFSET_N3 0 +#define M_DQ_WR_OFFSET_N3 0xfU +#define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3) +#define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3) + +#define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc +#define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000 + +#define S_BIT_ENABLE_0_11 4 +#define M_BIT_ENABLE_0_11 0xfffU +#define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11) +#define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11) + +#define S_BIT_ENABLE_12_15 0 +#define M_BIT_ENABLE_12_15 0xfU +#define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15) +#define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15) + +#define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004 + +#define S_DI_ADR0_ADR1 15 +#define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1) +#define F_DI_ADR0_ADR1 V_DI_ADR0_ADR1(1U) + +#define S_DI_ADR2_ADR3 14 +#define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3) +#define F_DI_ADR2_ADR3 V_DI_ADR2_ADR3(1U) + +#define S_DI_ADR4_ADR5 13 +#define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5) +#define F_DI_ADR4_ADR5 V_DI_ADR4_ADR5(1U) + +#define S_DI_ADR6_ADR7 12 +#define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7) +#define F_DI_ADR6_ADR7 V_DI_ADR6_ADR7(1U) + +#define S_DI_ADR8_ADR9 11 +#define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9) +#define F_DI_ADR8_ADR9 V_DI_ADR8_ADR9(1U) + +#define S_DI_ADR10_ADR11 10 +#define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11) +#define F_DI_ADR10_ADR11 V_DI_ADR10_ADR11(1U) + +#define S_DI_ADR12_ADR13 9 +#define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13) +#define F_DI_ADR12_ADR13 V_DI_ADR12_ADR13(1U) + +#define S_DI_ADR14_ADR15 8 +#define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15) +#define F_DI_ADR14_ADR15 V_DI_ADR14_ADR15(1U) + +#define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010 + +#define S_ADR_DELAY_BITS1_7 8 +#define M_ADR_DELAY_BITS1_7 0x7fU +#define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7) +#define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7) + +#define S_ADR_DELAY_BITS9_15 0 +#define M_ADR_DELAY_BITS9_15 0x7fU +#define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15) +#define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15) + +#define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014 +#define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018 +#define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c +#define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020 +#define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024 +#define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028 +#define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c +#define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030 + +#define S_ADR_TEST_LANE_PAIR_FAIL 8 +#define M_ADR_TEST_LANE_PAIR_FAIL 0xffU +#define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL) +#define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL) + +#define S_ADR_TEST_DATA_EN 7 +#define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN) +#define F_ADR_TEST_DATA_EN V_ADR_TEST_DATA_EN(1U) + +#define S_DADR_TEST_MODE 5 +#define M_DADR_TEST_MODE 0x3U +#define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE) +#define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE) + +#define S_ADR_TEST_4TO1_MODE 4 +#define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE) +#define F_ADR_TEST_4TO1_MODE V_ADR_TEST_4TO1_MODE(1U) + +#define S_ADR_TEST_RESET 3 +#define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET) +#define F_ADR_TEST_RESET V_ADR_TEST_RESET(1U) + +#define S_ADR_TEST_GEN_EN 2 +#define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN) +#define F_ADR_TEST_GEN_EN V_ADR_TEST_GEN_EN(1U) + +#define S_ADR_TEST_CLEAR_ERROR 1 +#define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR) +#define F_ADR_TEST_CLEAR_ERROR V_ADR_TEST_CLEAR_ERROR(1U) + +#define S_ADR_TEST_CHECK_EN 0 +#define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN) +#define F_ADR_TEST_CHECK_EN V_ADR_TEST_CHECK_EN(1U) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040 + +#define S_EN_SLICE_N_WR_0 8 +#define M_EN_SLICE_N_WR_0 0xffU +#define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0) +#define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0) + +#define S_EN_SLICE_N_WR_FFE 4 +#define M_EN_SLICE_N_WR_FFE 0xfU +#define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE) +#define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044 + +#define S_EN_SLICE_N_WR_1 8 +#define M_EN_SLICE_N_WR_1 0xffU +#define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1) +#define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048 + +#define S_EN_SLICE_N_WR_2 8 +#define M_EN_SLICE_N_WR_2 0xffU +#define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2) +#define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c + +#define S_EN_SLICE_N_WR_3 8 +#define M_EN_SLICE_N_WR_3 0xffU +#define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3) +#define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3) + +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050 + +#define S_EN_SLICE_P_WR 8 +#define M_EN_SLICE_P_WR 0xffU +#define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR) +#define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR) + +#define S_EN_SLICE_P_WR_FFE 4 +#define M_EN_SLICE_P_WR_FFE 0xfU +#define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE) +#define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE) + +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054 +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058 +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060 + +#define S_POST_CURSOR0 12 +#define M_POST_CURSOR0 0xfU +#define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0) +#define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0) + +#define S_POST_CURSOR1 8 +#define M_POST_CURSOR1 0xfU +#define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1) +#define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1) + +#define S_POST_CURSOR2 4 +#define M_POST_CURSOR2 0xfU +#define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2) +#define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2) + +#define S_POST_CURSOR3 0 +#define M_POST_CURSOR3 0xfU +#define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3) +#define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3) + +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068 + +#define S_SLEW_CTL0 12 +#define M_SLEW_CTL0 0xfU +#define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0) +#define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0) + +#define S_SLEW_CTL1 8 +#define M_SLEW_CTL1 0xfU +#define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1) +#define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1) + +#define S_SLEW_CTL2 4 +#define M_SLEW_CTL2 0xfU +#define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2) +#define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2) + +#define S_SLEW_CTL3 0 +#define M_SLEW_CTL3 0xfU +#define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3) +#define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3) + +#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080 + +#define S_SLICE_SEL_REG_BITS0_1 14 +#define M_SLICE_SEL_REG_BITS0_1 0x3U +#define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1) +#define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1) + +#define S_SLICE_SEL_REG_BITS2_3 12 +#define M_SLICE_SEL_REG_BITS2_3 0x3U +#define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3) +#define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3) + +#define S_SLICE_SEL_REG_BITS4_5 10 +#define M_SLICE_SEL_REG_BITS4_5 0x3U +#define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5) +#define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5) + +#define S_SLICE_SEL_REG_BITS6_7 8 +#define M_SLICE_SEL_REG_BITS6_7 0x3U +#define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7) +#define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7) + +#define S_SLICE_SEL_REG_BITS8_9 6 +#define M_SLICE_SEL_REG_BITS8_9 0x3U +#define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9) +#define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9) + +#define S_SLICE_SEL_REG_BITS10_11 4 +#define M_SLICE_SEL_REG_BITS10_11 0x3U +#define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11) +#define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11) + +#define S_SLICE_SEL_REG_BITS12_13 2 +#define M_SLICE_SEL_REG_BITS12_13 0x3U +#define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13) +#define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13) + +#define S_SLICE_SEL_REG_BITS14_15 0 +#define M_SLICE_SEL_REG_BITS14_15 0x3U +#define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15) +#define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084 +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0 + +#define S_POST_CUR_SEL_BITS0_1 14 +#define M_POST_CUR_SEL_BITS0_1 0x3U +#define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1) +#define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1) + +#define S_POST_CUR_SEL_BITS2_3 12 +#define M_POST_CUR_SEL_BITS2_3 0x3U +#define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3) +#define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3) + +#define S_POST_CUR_SEL_BITS4_5 10 +#define M_POST_CUR_SEL_BITS4_5 0x3U +#define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5) +#define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5) + +#define S_POST_CUR_SEL_BITS6_7 8 +#define M_POST_CUR_SEL_BITS6_7 0x3U +#define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7) +#define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7) + +#define S_POST_CUR_SEL_BITS8_9 6 +#define M_POST_CUR_SEL_BITS8_9 0x3U +#define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9) +#define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9) + +#define S_POST_CUR_SEL_BITS10_11 4 +#define M_POST_CUR_SEL_BITS10_11 0x3U +#define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11) +#define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11) + +#define S_POST_CUR_SEL_BITS12_13 2 +#define M_POST_CUR_SEL_BITS12_13 0x3U +#define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13) +#define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13) + +#define S_POST_CUR_SEL_BITS14_15 0 +#define M_POST_CUR_SEL_BITS14_15 0x3U +#define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15) +#define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4 +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8 + +#define S_SLEW_CTL_SEL_BITS0_1 14 +#define M_SLEW_CTL_SEL_BITS0_1 0x3U +#define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1) +#define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1) + +#define S_SLEW_CTL_SEL_BITS2_3 12 +#define M_SLEW_CTL_SEL_BITS2_3 0x3U +#define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3) +#define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3) + +#define S_SLEW_CTL_SEL_BITS4_5 10 +#define M_SLEW_CTL_SEL_BITS4_5 0x3U +#define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5) +#define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5) + +#define S_SLEW_CTL_SEL_BITS6_7 8 +#define M_SLEW_CTL_SEL_BITS6_7 0x3U +#define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7) +#define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7) + +#define S_SLEW_CTL_SEL_BITS8_9 6 +#define M_SLEW_CTL_SEL_BITS8_9 0x3U +#define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9) +#define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9) + +#define S_SLEW_CTL_SEL_BITS10_11 4 +#define M_SLEW_CTL_SEL_BITS10_11 0x3U +#define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11) +#define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11) + +#define S_SLEW_CTL_SEL_BITS12_13 2 +#define M_SLEW_CTL_SEL_BITS12_13 0x3U +#define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13) +#define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13) + +#define S_SLEW_CTL_SEL_BITS14_15 0 +#define M_SLEW_CTL_SEL_BITS14_15 0x3U +#define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15) +#define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac +#define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0 + +#define S_ADR_LANE_0_11_PD 4 +#define M_ADR_LANE_0_11_PD 0xfffU +#define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD) +#define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD) + +#define S_ADR_LANE_12_15_PD 0 +#define M_ADR_LANE_12_15_PD 0xfU +#define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD) +#define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD) + +#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0 + +#define S_PLL_TUNE_0_2 13 +#define M_PLL_TUNE_0_2 0x7U +#define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2) +#define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2) + +#define S_PLL_TUNECP_0_2 10 +#define M_PLL_TUNECP_0_2 0x7U +#define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2) +#define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2) + +#define S_PLL_TUNEF_0_5 4 +#define M_PLL_TUNEF_0_5 0x3fU +#define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5) +#define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5) + +#define S_PLL_TUNEVCO_0_1 2 +#define M_PLL_TUNEVCO_0_1 0x3U +#define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1) +#define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1) + +#define S_PLL_PLLXTR_0_1 0 +#define M_PLL_PLLXTR_0_1 0x3U +#define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1) +#define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1) + +#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4 + +#define S_PLL_TUNETDIV_0_2 13 +#define M_PLL_TUNETDIV_0_2 0x7U +#define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2) +#define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2) + +#define S_PLL_TUNEMDIV_0_1 11 +#define M_PLL_TUNEMDIV_0_1 0x3U +#define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1) +#define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1) + +#define S_PLL_TUNEATST 10 +#define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST) +#define F_PLL_TUNEATST V_PLL_TUNEATST(1U) + +#define S_VREG_RANGE_0_1 8 +#define M_VREG_RANGE_0_1 0x3U +#define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1) +#define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1) + +#define S_VREG_VREGSPARE 7 +#define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE) +#define F_VREG_VREGSPARE V_VREG_VREGSPARE(1U) + +#define S_VREG_VCCTUNE_0_1 5 +#define M_VREG_VCCTUNE_0_1 0x3U +#define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1) +#define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1) + +#define S_INTERP_SIG_SLEW_0_3 1 +#define M_INTERP_SIG_SLEW_0_3 0xfU +#define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3) +#define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3) + +#define S_ANALOG_WRAPON 0 +#define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON) +#define F_ANALOG_WRAPON V_ANALOG_WRAPON(1U) + +#define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8 + +#define S_SYSCLK_ENABLE 15 +#define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE) +#define F_SYSCLK_ENABLE V_SYSCLK_ENABLE(1U) + +#define S_SYSCLK_ROT_OVERRIDE 8 +#define M_SYSCLK_ROT_OVERRIDE 0x7fU +#define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE) +#define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE) + +#define S_SYSCLK_ROT_OVERRIDE_EN 7 +#define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN) +#define F_SYSCLK_ROT_OVERRIDE_EN V_SYSCLK_ROT_OVERRIDE_EN(1U) + +#define S_SYSCLK_PHASE_ALIGN_RESE 6 +#define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE) +#define F_SYSCLK_PHASE_ALIGN_RESE V_SYSCLK_PHASE_ALIGN_RESE(1U) + +#define S_SYSCLK_PHASE_CNTL_EN 5 +#define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN) +#define F_SYSCLK_PHASE_CNTL_EN V_SYSCLK_PHASE_CNTL_EN(1U) + +#define S_SYSCLK_PHASE_DEFAULT_EN 4 +#define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN) +#define F_SYSCLK_PHASE_DEFAULT_EN V_SYSCLK_PHASE_DEFAULT_EN(1U) + +#define S_SYSCLK_POS_EDGE_ALIGN 3 +#define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN) +#define F_SYSCLK_POS_EDGE_ALIGN V_SYSCLK_POS_EDGE_ALIGN(1U) + +#define S_CONTINUOUS_UPDATE 2 +#define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE) +#define F_CONTINUOUS_UPDATE V_CONTINUOUS_UPDATE(1U) + +#define S_CE0DLTVCC 0 +#define M_CE0DLTVCC 0x3U +#define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC) +#define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC) + +#define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc + +#define S_TSYS_WRCLK 8 +#define M_TSYS_WRCLK 0x7fU +#define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK) +#define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK) + +#define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0 + +#define S_SLEW_LATE_SAMPLE 15 +#define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE) +#define F_SLEW_LATE_SAMPLE V_SLEW_LATE_SAMPLE(1U) + +#define S_SYSCLK_ROT 8 +#define M_SYSCLK_ROT 0x7fU +#define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT) +#define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT) + +#define S_BB_LOCK 7 +#define V_BB_LOCK(x) ((x) << S_BB_LOCK) +#define F_BB_LOCK V_BB_LOCK(1U) + +#define S_SLEW_EARLY_SAMPLE 6 +#define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE) +#define F_SLEW_EARLY_SAMPLE V_SLEW_EARLY_SAMPLE(1U) + +#define S_SLEW_DONE_STATUS 4 +#define M_SLEW_DONE_STATUS 0x3U +#define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS) +#define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS) + +#define S_SLEW_CNTL 0 +#define M_SLEW_CNTL 0xfU +#define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL) +#define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL) + +#define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4 + +#define S_FLUSH 15 +#define V_FLUSH(x) ((x) << S_FLUSH) +#define F_FLUSH V_FLUSH(1U) + +#define S_GIANT_MUX_TEST_EN 14 +#define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN) +#define F_GIANT_MUX_TEST_EN V_GIANT_MUX_TEST_EN(1U) + +#define S_GIANT_MUX_TEST_VAL 13 +#define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL) +#define F_GIANT_MUX_TEST_VAL V_GIANT_MUX_TEST_VAL(1U) + +#define S_HS_PROBE_A_SEL_ 8 +#define M_HS_PROBE_A_SEL_ 0xfU +#define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_) +#define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_) + +#define S_HS_PROBE_B_SEL_ 4 +#define M_HS_PROBE_B_SEL_ 0xfU +#define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_) +#define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_) + +#define S_ATEST1CTL0 3 +#define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0) +#define F_ATEST1CTL0 V_ATEST1CTL0(1U) + +#define S_ATEST1CTL1 2 +#define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1) +#define F_ATEST1CTL1 V_ATEST1CTL1(1U) + +#define S_ATEST1CTL2 1 +#define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2) +#define F_ATEST1CTL2 V_ATEST1CTL2(1U) + +#define S_ATEST1CTL3 0 +#define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3) +#define F_ATEST1CTL3 V_ATEST1CTL3(1U) + +#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8 + +#define S_GIANT_MUX_TEST_RESULTS 0 +#define M_GIANT_MUX_TEST_RESULTS 0xffffU +#define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS) +#define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS) + +#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc +#define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0 + +#define S_MASTER_PD_CNTL 15 +#define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL) +#define F_MASTER_PD_CNTL V_MASTER_PD_CNTL(1U) + +#define S_ANALOG_INPUT_STAB2 14 +#define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2) +#define F_ANALOG_INPUT_STAB2 V_ANALOG_INPUT_STAB2(1U) + +#define S_ANALOG_INPUT_STAB1 8 +#define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1) +#define F_ANALOG_INPUT_STAB1 V_ANALOG_INPUT_STAB1(1U) + +#define S_SYSCLK_CLK_GATE 6 +#define M_SYSCLK_CLK_GATE 0x3U +#define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE) +#define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE) + +#define S_WR_FIFO_STAB 5 +#define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB) +#define F_WR_FIFO_STAB V_WR_FIFO_STAB(1U) + +#define S_ADR_RX_PD 4 +#define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD) +#define F_ADR_RX_PD V_ADR_RX_PD(1U) + +#define S_TX_TRISTATE_CNTL 1 +#define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL) +#define F_TX_TRISTATE_CNTL V_TX_TRISTATE_CNTL(1U) + +#define S_DVCC_REG_PD 0 +#define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD) +#define F_DVCC_REG_PD V_DVCC_REG_PD(1U) + +#define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4 + +#define S_SLEW_CAL_ENABLE 15 +#define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE) +#define F_SLEW_CAL_ENABLE V_SLEW_CAL_ENABLE(1U) + +#define S_SLEW_CAL_START 14 +#define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START) +#define F_SLEW_CAL_START V_SLEW_CAL_START(1U) + +#define S_SLEW_CAL_OVERRIDE_EN 12 +#define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN) +#define F_SLEW_CAL_OVERRIDE_EN V_SLEW_CAL_OVERRIDE_EN(1U) + +#define S_SLEW_CAL_OVERRIDE 8 +#define M_SLEW_CAL_OVERRIDE 0xfU +#define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE) +#define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE) + +#define S_SLEW_TARGET_PR_OFFSET 0 +#define M_SLEW_TARGET_PR_OFFSET 0x1fU +#define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET) +#define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET) + +#define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000 + +#define S_DP18_PLL_LOCK 1 +#define M_DP18_PLL_LOCK 0x7fffU +#define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK) +#define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK) + +#define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004 + +#define S_AD32S_PLL_LOCK 14 +#define M_AD32S_PLL_LOCK 0x3U +#define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK) +#define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK) + +#define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008 + +#define S_RANK_PAIR0_PRI 13 +#define M_RANK_PAIR0_PRI 0x7U +#define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI) +#define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI) + +#define S_RANK_PAIR0_PRI_V 12 +#define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V) +#define F_RANK_PAIR0_PRI_V V_RANK_PAIR0_PRI_V(1U) + +#define S_RANK_PAIR0_SEC 9 +#define M_RANK_PAIR0_SEC 0x7U +#define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC) +#define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC) + +#define S_RANK_PAIR0_SEC_V 8 +#define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V) +#define F_RANK_PAIR0_SEC_V V_RANK_PAIR0_SEC_V(1U) + +#define S_RANK_PAIR1_PRI 5 +#define M_RANK_PAIR1_PRI 0x7U +#define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI) +#define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI) + +#define S_RANK_PAIR1_PRI_V 4 +#define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V) +#define F_RANK_PAIR1_PRI_V V_RANK_PAIR1_PRI_V(1U) + +#define S_RANK_PAIR1_SEC 1 +#define M_RANK_PAIR1_SEC 0x7U +#define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC) +#define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC) + +#define S_RANK_PAIR1_SEC_V 0 +#define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V) +#define F_RANK_PAIR1_SEC_V V_RANK_PAIR1_SEC_V(1U) + +#define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c + +#define S_RANK_PAIR2_PRI 13 +#define M_RANK_PAIR2_PRI 0x7U +#define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI) +#define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI) + +#define S_RANK_PAIR2_PRI_V 12 +#define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V) +#define F_RANK_PAIR2_PRI_V V_RANK_PAIR2_PRI_V(1U) + +#define S_RANK_PAIR2_SEC 9 +#define M_RANK_PAIR2_SEC 0x7U +#define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC) +#define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC) + +#define S_RANK_PAIR2_SEC_V 8 +#define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V) +#define F_RANK_PAIR2_SEC_V V_RANK_PAIR2_SEC_V(1U) + +#define S_RANK_PAIR3_PRI 5 +#define M_RANK_PAIR3_PRI 0x7U +#define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI) +#define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI) + +#define S_RANK_PAIR3_PRI_V 4 +#define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V) +#define F_RANK_PAIR3_PRI_V V_RANK_PAIR3_PRI_V(1U) + +#define S_RANK_PAIR3_SEC 1 +#define M_RANK_PAIR3_SEC 0x7U +#define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC) +#define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC) + +#define S_RANK_PAIR3_SEC_V 0 +#define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V) +#define F_RANK_PAIR3_SEC_V V_RANK_PAIR3_SEC_V(1U) + +#define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010 + +#define S_PERIODIC_BASE_CNTR0 0 +#define M_PERIODIC_BASE_CNTR0 0xffffU +#define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0) +#define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0) + +#define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014 + +#define S_PERIODIC_CAL_REQ_EN 15 +#define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN) +#define F_PERIODIC_CAL_REQ_EN V_PERIODIC_CAL_REQ_EN(1U) + +#define S_PERIODIC_RELOAD_VALUE0 0 +#define M_PERIODIC_RELOAD_VALUE0 0x7fffU +#define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0) +#define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0) + +#define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018 + +#define S_PERIODIC_BASE_CNTR1 0 +#define M_PERIODIC_BASE_CNTR1 0xffffU +#define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1) +#define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1) + +#define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c + +#define S_PERIODIC_CAL_TIMER 0 +#define M_PERIODIC_CAL_TIMER 0xffffU +#define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER) +#define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER) + +#define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020 + +#define S_PERIODIC_TIMER_RELOAD_VALUE 0 +#define M_PERIODIC_TIMER_RELOAD_VALUE 0xffffU +#define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE) +#define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE) + +#define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024 + +#define S_PERIODIC_ZCAL_TIMER 0 +#define M_PERIODIC_ZCAL_TIMER 0xffffU +#define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER) +#define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER) + +#define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028 +#define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c + +#define S_PER_ENA_RANK_PAIR 12 +#define M_PER_ENA_RANK_PAIR 0xfU +#define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR) +#define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR) + +#define S_PER_ENA_ZCAL 11 +#define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL) +#define F_PER_ENA_ZCAL V_PER_ENA_ZCAL(1U) + +#define S_PER_ENA_SYSCLK_ALIGN 10 +#define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN) +#define F_PER_ENA_SYSCLK_ALIGN V_PER_ENA_SYSCLK_ALIGN(1U) + +#define S_ENA_PER_RDCLK_ALIGN 9 +#define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN) +#define F_ENA_PER_RDCLK_ALIGN V_ENA_PER_RDCLK_ALIGN(1U) + +#define S_ENA_PER_DQS_ALIGN 8 +#define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN) +#define F_ENA_PER_DQS_ALIGN V_ENA_PER_DQS_ALIGN(1U) + +#define S_ENA_PER_READ_CTR 7 +#define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR) +#define F_ENA_PER_READ_CTR V_ENA_PER_READ_CTR(1U) + +#define S_PER_NEXT_RANK_PAIR 5 +#define M_PER_NEXT_RANK_PAIR 0x3U +#define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR) +#define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR) + +#define S_FAST_SIM_PER_CNTR 4 +#define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR) +#define F_FAST_SIM_PER_CNTR V_FAST_SIM_PER_CNTR(1U) + +#define S_START_INIT_CAL 3 +#define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL) +#define F_START_INIT_CAL V_START_INIT_CAL(1U) + +#define S_START_PER_CAL 2 +#define V_START_PER_CAL(x) ((x) << S_START_PER_CAL) +#define F_START_PER_CAL V_START_PER_CAL(1U) + +#define A_MC_DDRPHY_PC_CONFIG0 0x47030 + +#define S_PROTOCOL_DDR 12 +#define M_PROTOCOL_DDR 0xfU +#define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR) +#define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR) + +#define S_DATA_MUX4_1MODE 11 +#define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE) +#define F_DATA_MUX4_1MODE V_DATA_MUX4_1MODE(1U) + +#define S_DDR4_CMD_SIG_REDUCTION 9 +#define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION) +#define F_DDR4_CMD_SIG_REDUCTION V_DDR4_CMD_SIG_REDUCTION(1U) + +#define S_SYSCLK_2X_MEMINTCLKO 8 +#define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO) +#define F_SYSCLK_2X_MEMINTCLKO V_SYSCLK_2X_MEMINTCLKO(1U) + +#define S_RANK_OVERRIDE 7 +#define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE) +#define F_RANK_OVERRIDE V_RANK_OVERRIDE(1U) + +#define S_RANK_OVERRIDE_VALUE 4 +#define M_RANK_OVERRIDE_VALUE 0x7U +#define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE) +#define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE) + +#define S_LOW_LATENCY 3 +#define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY) +#define F_LOW_LATENCY V_LOW_LATENCY(1U) + +#define S_DDR4_BANK_REFRESH 2 +#define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH) +#define F_DDR4_BANK_REFRESH V_DDR4_BANK_REFRESH(1U) + +#define S_DDR4_VLEVEL_BANK_GROUP 1 +#define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP) +#define F_DDR4_VLEVEL_BANK_GROUP V_DDR4_VLEVEL_BANK_GROUP(1U) + +#define A_MC_DDRPHY_PC_CONFIG1 0x47034 + +#define S_WRITE_LATENCY_OFFSET 12 +#define M_WRITE_LATENCY_OFFSET 0xfU +#define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET) +#define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET) + +#define S_READ_LATENCY_OFFSET 8 +#define M_READ_LATENCY_OFFSET 0xfU +#define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET) +#define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET) + +#define S_MEMCTL_CIC_FAST 7 +#define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST) +#define F_MEMCTL_CIC_FAST V_MEMCTL_CIC_FAST(1U) + +#define S_MEMCTL_CTRN_IGNORE 6 +#define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE) +#define F_MEMCTL_CTRN_IGNORE V_MEMCTL_CTRN_IGNORE(1U) + +#define S_DISABLE_MEMCTL_CAL 5 +#define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL) +#define F_DISABLE_MEMCTL_CAL V_DISABLE_MEMCTL_CAL(1U) + +#define A_MC_DDRPHY_PC_RESETS 0x47038 + +#define S_PLL_RESET 15 +#define V_PLL_RESET(x) ((x) << S_PLL_RESET) +#define F_PLL_RESET V_PLL_RESET(1U) + +#define S_SYSCLK_RESET 14 +#define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET) +#define F_SYSCLK_RESET V_SYSCLK_RESET(1U) + +#define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c + +#define S_PER_ZCAL_ENA_RANK 8 +#define M_PER_ZCAL_ENA_RANK 0xffU +#define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK) +#define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK) + +#define S_PER_ZCAL_NEXT_RANK 5 +#define M_PER_ZCAL_NEXT_RANK 0x7U +#define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK) +#define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK) + +#define S_START_PER_ZCAL 4 +#define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL) +#define F_START_PER_ZCAL V_START_PER_ZCAL(1U) + +#define A_MC_DDRPHY_PC_RANK_GROUP 0x47044 + +#define S_ADDR_MIRROR_RP0_PRI 15 +#define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI) +#define F_ADDR_MIRROR_RP0_PRI V_ADDR_MIRROR_RP0_PRI(1U) + +#define S_ADDR_MIRROR_RP0_SEC 14 +#define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC) +#define F_ADDR_MIRROR_RP0_SEC V_ADDR_MIRROR_RP0_SEC(1U) + +#define S_ADDR_MIRROR_RP1_PRI 13 +#define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI) +#define F_ADDR_MIRROR_RP1_PRI V_ADDR_MIRROR_RP1_PRI(1U) + +#define S_ADDR_MIRROR_RP1_SEC 12 +#define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC) +#define F_ADDR_MIRROR_RP1_SEC V_ADDR_MIRROR_RP1_SEC(1U) + +#define S_ADDR_MIRROR_RP2_PRI 11 +#define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI) +#define F_ADDR_MIRROR_RP2_PRI V_ADDR_MIRROR_RP2_PRI(1U) + +#define S_ADDR_MIRROR_RP2_SEC 10 +#define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC) +#define F_ADDR_MIRROR_RP2_SEC V_ADDR_MIRROR_RP2_SEC(1U) + +#define S_ADDR_MIRROR_RP3_PRI 9 +#define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI) +#define F_ADDR_MIRROR_RP3_PRI V_ADDR_MIRROR_RP3_PRI(1U) + +#define S_ADDR_MIRROR_RP3_SEC 8 +#define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC) +#define F_ADDR_MIRROR_RP3_SEC V_ADDR_MIRROR_RP3_SEC(1U) + +#define S_RANK_GROUPING 6 +#define M_RANK_GROUPING 0x3U +#define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING) +#define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING) + +#define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048 + +#define S_RC_ERROR 15 +#define V_RC_ERROR(x) ((x) << S_RC_ERROR) +#define F_RC_ERROR V_RC_ERROR(1U) + +#define S_WC_ERROR 14 +#define V_WC_ERROR(x) ((x) << S_WC_ERROR) +#define F_WC_ERROR V_WC_ERROR(1U) + +#define S_SEQ_ERROR 13 +#define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR) +#define F_SEQ_ERROR V_SEQ_ERROR(1U) + +#define S_CC_ERROR 12 +#define V_CC_ERROR(x) ((x) << S_CC_ERROR) +#define F_CC_ERROR V_CC_ERROR(1U) + +#define S_APB_ERROR 11 +#define V_APB_ERROR(x) ((x) << S_APB_ERROR) +#define F_APB_ERROR V_APB_ERROR(1U) + +#define S_PC_ERROR 10 +#define V_PC_ERROR(x) ((x) << S_PC_ERROR) +#define F_PC_ERROR V_PC_ERROR(1U) + +#define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c + +#define S_RC_ERROR_MASK 15 +#define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK) +#define F_RC_ERROR_MASK V_RC_ERROR_MASK(1U) + +#define S_WC_ERROR_MASK 14 +#define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK) +#define F_WC_ERROR_MASK V_WC_ERROR_MASK(1U) + +#define S_SEQ_ERROR_MASK 13 +#define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK) +#define F_SEQ_ERROR_MASK V_SEQ_ERROR_MASK(1U) + +#define S_CC_ERROR_MASK 12 +#define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK) +#define F_CC_ERROR_MASK V_CC_ERROR_MASK(1U) + +#define S_APB_ERROR_MASK 11 +#define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK) +#define F_APB_ERROR_MASK V_APB_ERROR_MASK(1U) + +#define S_PC_ERROR_MASK 10 +#define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK) +#define F_PC_ERROR_MASK V_PC_ERROR_MASK(1U) + +#define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050 + +#define S_PVTP 11 +#define M_PVTP 0x1fU +#define V_PVTP(x) ((x) << S_PVTP) +#define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP) + +#define S_PVTN 6 +#define M_PVTN 0x1fU +#define V_PVTN(x) ((x) << S_PVTN) +#define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN) + +#define S_PVT_OVERRIDE 5 +#define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE) +#define F_PVT_OVERRIDE V_PVT_OVERRIDE(1U) + +#define S_ENABLE_ZCAL 4 +#define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL) +#define F_ENABLE_ZCAL V_ENABLE_ZCAL(1U) + +#define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054 + +#define S_VREFDQ0DSGN 15 +#define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN) +#define F_VREFDQ0DSGN V_VREFDQ0DSGN(1U) + +#define S_VREFDQ0D 11 +#define M_VREFDQ0D 0xfU +#define V_VREFDQ0D(x) ((x) << S_VREFDQ0D) +#define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D) + +#define S_VREFDQ1DSGN 10 +#define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN) +#define F_VREFDQ1DSGN V_VREFDQ1DSGN(1U) + +#define S_VREFDQ1D 6 +#define M_VREFDQ1D 0xfU +#define V_VREFDQ1D(x) ((x) << S_VREFDQ1D) +#define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D) + +#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058 + +#define S_ENA_WR_LEVEL 15 +#define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL) +#define F_ENA_WR_LEVEL V_ENA_WR_LEVEL(1U) + +#define S_ENA_INITIAL_PAT_WR 14 +#define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR) +#define F_ENA_INITIAL_PAT_WR V_ENA_INITIAL_PAT_WR(1U) + +#define S_ENA_DQS_ALIGN 13 +#define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN) +#define F_ENA_DQS_ALIGN V_ENA_DQS_ALIGN(1U) + +#define S_ENA_RDCLK_ALIGN 12 +#define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN) +#define F_ENA_RDCLK_ALIGN V_ENA_RDCLK_ALIGN(1U) + +#define S_ENA_READ_CTR 11 +#define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR) +#define F_ENA_READ_CTR V_ENA_READ_CTR(1U) + +#define S_ENA_WRITE_CTR 10 +#define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR) +#define F_ENA_WRITE_CTR V_ENA_WRITE_CTR(1U) + +#define S_ENA_INITIAL_COARSE_WR 9 +#define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR) +#define F_ENA_INITIAL_COARSE_WR V_ENA_INITIAL_COARSE_WR(1U) + +#define S_ENA_COARSE_RD 8 +#define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD) +#define F_ENA_COARSE_RD V_ENA_COARSE_RD(1U) + +#define S_ENA_CUSTOM_RD 7 +#define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD) +#define F_ENA_CUSTOM_RD V_ENA_CUSTOM_RD(1U) + +#define S_ENA_CUSTOM_WR 6 +#define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR) +#define F_ENA_CUSTOM_WR V_ENA_CUSTOM_WR(1U) + +#define S_ABORT_ON_CAL_ERROR 5 +#define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR) +#define F_ABORT_ON_CAL_ERROR V_ABORT_ON_CAL_ERROR(1U) + +#define S_ENA_DIGITAL_EYE 4 +#define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE) +#define F_ENA_DIGITAL_EYE V_ENA_DIGITAL_EYE(1U) + +#define S_ENA_RANK_PAIR 0 +#define M_ENA_RANK_PAIR 0xfU +#define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR) +#define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR) + +#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c + +#define S_REFRESH_COUNT 12 +#define M_REFRESH_COUNT 0xfU +#define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT) +#define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT) + +#define S_REFRESH_CONTROL 10 +#define M_REFRESH_CONTROL 0x3U +#define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL) +#define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL) + +#define S_REFRESH_ALL_RANKS 9 +#define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS) +#define F_REFRESH_ALL_RANKS V_REFRESH_ALL_RANKS(1U) + +#define S_REFRESH_INTERVAL 0 +#define M_REFRESH_INTERVAL 0x7fU +#define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL) +#define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL) + +#define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060 + +#define S_ERROR_WR_LEVEL 15 +#define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL) +#define F_ERROR_WR_LEVEL V_ERROR_WR_LEVEL(1U) + +#define S_ERROR_INITIAL_PAT_WRITE 14 +#define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE) +#define F_ERROR_INITIAL_PAT_WRITE V_ERROR_INITIAL_PAT_WRITE(1U) + +#define S_ERROR_DQS_ALIGN 13 +#define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN) +#define F_ERROR_DQS_ALIGN V_ERROR_DQS_ALIGN(1U) + +#define S_ERROR_RDCLK_ALIGN 12 +#define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN) +#define F_ERROR_RDCLK_ALIGN V_ERROR_RDCLK_ALIGN(1U) + +#define S_ERROR_READ_CTR 11 +#define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR) +#define F_ERROR_READ_CTR V_ERROR_READ_CTR(1U) + +#define S_ERROR_WRITE_CTR 10 +#define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR) +#define F_ERROR_WRITE_CTR V_ERROR_WRITE_CTR(1U) + +#define S_ERROR_INITIAL_COARSE_WR 9 +#define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR) +#define F_ERROR_INITIAL_COARSE_WR V_ERROR_INITIAL_COARSE_WR(1U) + +#define S_ERROR_COARSE_RD 8 +#define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD) +#define F_ERROR_COARSE_RD V_ERROR_COARSE_RD(1U) + +#define S_ERROR_CUSTOM_RD 7 +#define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD) +#define F_ERROR_CUSTOM_RD V_ERROR_CUSTOM_RD(1U) + +#define S_ERROR_CUSTOM_WR 6 +#define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR) +#define F_ERROR_CUSTOM_WR V_ERROR_CUSTOM_WR(1U) + +#define S_ERROR_DIGITAL_EYE 5 +#define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE) +#define F_ERROR_DIGITAL_EYE V_ERROR_DIGITAL_EYE(1U) + +#define S_ERROR_RANK_PAIR 0 +#define M_ERROR_RANK_PAIR 0xfU +#define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR) +#define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR) + +#define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064 + +#define S_INIT_CAL_COMPLETE 12 +#define M_INIT_CAL_COMPLETE 0xfU +#define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE) +#define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE) + +#define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068 + +#define S_ERROR_WR_LEVEL_MASK 15 +#define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK) +#define F_ERROR_WR_LEVEL_MASK V_ERROR_WR_LEVEL_MASK(1U) + +#define S_ERROR_INITIAL_PAT_WRITE_MASK 14 +#define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK) +#define F_ERROR_INITIAL_PAT_WRITE_MASK V_ERROR_INITIAL_PAT_WRITE_MASK(1U) + +#define S_ERROR_DQS_ALIGN_MASK 13 +#define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK) +#define F_ERROR_DQS_ALIGN_MASK V_ERROR_DQS_ALIGN_MASK(1U) + +#define S_ERROR_RDCLK_ALIGN_MASK 12 +#define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK) +#define F_ERROR_RDCLK_ALIGN_MASK V_ERROR_RDCLK_ALIGN_MASK(1U) + +#define S_ERROR_READ_CTR_MASK 11 +#define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK) +#define F_ERROR_READ_CTR_MASK V_ERROR_READ_CTR_MASK(1U) + +#define S_ERROR_WRITE_CTR_MASK 10 +#define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK) +#define F_ERROR_WRITE_CTR_MASK V_ERROR_WRITE_CTR_MASK(1U) + +#define S_ERROR_INITIAL_COARSE_WR_MASK 9 +#define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK) +#define F_ERROR_INITIAL_COARSE_WR_MASK V_ERROR_INITIAL_COARSE_WR_MASK(1U) + +#define S_ERROR_COARSE_RD_MASK 8 +#define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK) +#define F_ERROR_COARSE_RD_MASK V_ERROR_COARSE_RD_MASK(1U) + +#define S_ERROR_CUSTOM_RD_MASK 7 +#define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK) +#define F_ERROR_CUSTOM_RD_MASK V_ERROR_CUSTOM_RD_MASK(1U) + +#define S_ERROR_CUSTOM_WR_MASK 6 +#define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK) +#define F_ERROR_CUSTOM_WR_MASK V_ERROR_CUSTOM_WR_MASK(1U) + +#define S_ERROR_DIGITAL_EYE_MASK 5 +#define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK) +#define F_ERROR_DIGITAL_EYE_MASK V_ERROR_DIGITAL_EYE_MASK(1U) + +#define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c +#define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070 + +#define S_MODEREGISTER0VALUE 0 +#define M_MODEREGISTER0VALUE 0xffffU +#define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE) +#define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE) + +#define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074 + +#define S_MODEREGISTER1VALUE 0 +#define M_MODEREGISTER1VALUE 0xffffU +#define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE) +#define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE) + +#define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078 + +#define S_MODEREGISTER2VALUE 0 +#define M_MODEREGISTER2VALUE 0xffffU +#define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE) +#define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE) + +#define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c + +#define S_MODEREGISTER3VALUE 0 +#define M_MODEREGISTER3VALUE 0xffffU +#define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE) +#define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE) + +#define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080 +#define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084 +#define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088 +#define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c + +#define S_MODE_REGISTER_3_VALUE 0 +#define M_MODE_REGISTER_3_VALUE 0xffffU +#define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE) +#define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE) + +#define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200 + +#define S_DRD_WR_DATA_REG 0 +#define M_DRD_WR_DATA_REG 0xffffU +#define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG) +#define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG) + +#define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204 +#define A_MC_DDRPHY_SEQ_CONFIG0 0x47208 + +#define S_MPR_PATTERN_BIT 15 +#define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT) +#define F_MPR_PATTERN_BIT V_MPR_PATTERN_BIT(1U) + +#define S_TWO_CYCLE_ADDR_EN 14 +#define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN) +#define F_TWO_CYCLE_ADDR_EN V_TWO_CYCLE_ADDR_EN(1U) + +#define S_MR_MASK_EN 10 +#define M_MR_MASK_EN 0xfU +#define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN) +#define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN) + +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c +#define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220 + +#define S_MULTIPLE_REQ_ERROR 15 +#define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR) +#define F_MULTIPLE_REQ_ERROR V_MULTIPLE_REQ_ERROR(1U) + +#define S_INVALID_REQTYPE_ERRO 14 +#define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO) +#define F_INVALID_REQTYPE_ERRO V_INVALID_REQTYPE_ERRO(1U) + +#define S_EARLY_REQ_ERROR 13 +#define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR) +#define F_EARLY_REQ_ERROR V_EARLY_REQ_ERROR(1U) + +#define S_MULTIPLE_REQ_SOURCE 10 +#define M_MULTIPLE_REQ_SOURCE 0x7U +#define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE) +#define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE) + +#define S_INVALID_REQTYPE 6 +#define M_INVALID_REQTYPE 0xfU +#define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE) +#define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE) + +#define S_INVALID_REQ_SOURCE 3 +#define M_INVALID_REQ_SOURCE 0x7U +#define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE) +#define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE) + +#define S_EARLY_REQ_SOURCE 0 +#define M_EARLY_REQ_SOURCE 0x7U +#define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE) +#define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE) + +#define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224 + +#define S_MULT_REQ_ERR_MASK 15 +#define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK) +#define F_MULT_REQ_ERR_MASK V_MULT_REQ_ERR_MASK(1U) + +#define S_INVALID_REQTYPE_ERR_MASK 14 +#define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK) +#define F_INVALID_REQTYPE_ERR_MASK V_INVALID_REQTYPE_ERR_MASK(1U) + +#define S_EARLY_REQ_ERR_MASK 13 +#define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK) +#define F_EARLY_REQ_ERR_MASK V_EARLY_REQ_ERR_MASK(1U) + +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228 + +#define S_ODT_WR_VALUES_BITS0_7 8 +#define M_ODT_WR_VALUES_BITS0_7 0xffU +#define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7) +#define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7) + +#define S_ODT_WR_VALUES_BITS8_15 0 +#define M_ODT_WR_VALUES_BITS8_15 0xffU +#define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15) +#define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15) + +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230 +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234 +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238 + +#define S_ODT_RD_VALUES_X2 8 +#define M_ODT_RD_VALUES_X2 0xffU +#define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2) +#define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2) + +#define S_ODT_RD_VALUES_X2PLUS1 0 +#define M_ODT_RD_VALUES_X2PLUS1 0xffU +#define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1) +#define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1) + +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240 +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244 +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248 + +#define S_TMOD_CYCLES 12 +#define M_TMOD_CYCLES 0xfU +#define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES) +#define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES) + +#define S_TRCD_CYCLES 8 +#define M_TRCD_CYCLES 0xfU +#define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES) +#define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES) + +#define S_TRP_CYCLES 4 +#define M_TRP_CYCLES 0xfU +#define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES) +#define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES) + +#define S_TRFC_CYCLES 0 +#define M_TRFC_CYCLES 0xfU +#define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES) +#define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES) + +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c + +#define S_TZQINIT_CYCLES 12 +#define M_TZQINIT_CYCLES 0xfU +#define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES) +#define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES) + +#define S_TZQCS_CYCLES 8 +#define M_TZQCS_CYCLES 0xfU +#define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES) +#define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES) + +#define S_TWLDQSEN_CYCLES 4 +#define M_TWLDQSEN_CYCLES 0xfU +#define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES) +#define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES) + +#define S_TWRMRD_CYCLES 0 +#define M_TWRMRD_CYCLES 0xfU +#define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES) +#define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES) + +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250 + +#define S_TODTLON_OFF_CYCLES 12 +#define M_TODTLON_OFF_CYCLES 0xfU +#define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES) +#define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES) + +#define S_TRC_CYCLES 8 +#define M_TRC_CYCLES 0xfU +#define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES) +#define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES) + +#define S_TMRSC_CYCLES 4 +#define M_TMRSC_CYCLES 0xfU +#define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES) +#define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES) + +#define A_MC_DDRPHY_RC_CONFIG0 0x47400 + +#define S_GLOBAL_PHY_OFFSET 12 +#define M_GLOBAL_PHY_OFFSET 0xfU +#define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET) +#define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET) + +#define S_ADVANCE_RD_VALID 11 +#define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID) +#define F_ADVANCE_RD_VALID V_ADVANCE_RD_VALID(1U) + +#define S_SINGLE_BIT_MPR_RP0 6 +#define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0) +#define F_SINGLE_BIT_MPR_RP0 V_SINGLE_BIT_MPR_RP0(1U) + +#define S_SINGLE_BIT_MPR_RP1 5 +#define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1) +#define F_SINGLE_BIT_MPR_RP1 V_SINGLE_BIT_MPR_RP1(1U) + +#define S_SINGLE_BIT_MPR_RP2 4 +#define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2) +#define F_SINGLE_BIT_MPR_RP2 V_SINGLE_BIT_MPR_RP2(1U) + +#define S_SINGLE_BIT_MPR_RP3 3 +#define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3) +#define F_SINGLE_BIT_MPR_RP3 V_SINGLE_BIT_MPR_RP3(1U) + +#define S_ALIGN_ON_EVEN_CYCLES 2 +#define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES) +#define F_ALIGN_ON_EVEN_CYCLES V_ALIGN_ON_EVEN_CYCLES(1U) + +#define S_PERFORM_RDCLK_ALIGN 1 +#define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN) +#define F_PERFORM_RDCLK_ALIGN V_PERFORM_RDCLK_ALIGN(1U) + +#define S_STAGGERED_PATTERN 0 +#define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN) +#define F_STAGGERED_PATTERN V_STAGGERED_PATTERN(1U) + +#define A_MC_DDRPHY_RC_CONFIG1 0x47404 + +#define S_OUTER_LOOP_CNT 2 +#define M_OUTER_LOOP_CNT 0x3fffU +#define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT) +#define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT) + +#define A_MC_DDRPHY_RC_CONFIG2 0x47408 + +#define S_CONSEQ_PASS 11 +#define M_CONSEQ_PASS 0x1fU +#define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS) +#define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS) + +#define S_BURST_WINDOW 5 +#define M_BURST_WINDOW 0x3U +#define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW) +#define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW) + +#define S_ALLOW_RD_FIFO_AUTO_R_ESET 4 +#define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET) +#define F_ALLOW_RD_FIFO_AUTO_R_ESET V_ALLOW_RD_FIFO_AUTO_R_ESET(1U) + +#define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414 + +#define S_RD_CNTL_ERROR 15 +#define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR) +#define F_RD_CNTL_ERROR V_RD_CNTL_ERROR(1U) + +#define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418 + +#define S_RD_CNTL_ERROR_MASK 15 +#define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK) +#define F_RD_CNTL_ERROR_MASK V_RD_CNTL_ERROR_MASK(1U) + +#define A_MC_DDRPHY_RC_CONFIG3 0x4741c + +#define S_FINE_CAL_STEP_SIZE 13 +#define M_FINE_CAL_STEP_SIZE 0x7U +#define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE) +#define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE) + +#define S_COARSE_CAL_STEP_SIZE 9 +#define M_COARSE_CAL_STEP_SIZE 0xfU +#define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE) +#define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE) + +#define S_DQ_SEL_QUAD 7 +#define M_DQ_SEL_QUAD 0x3U +#define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD) +#define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD) + +#define S_DQ_SEL_LANE 4 +#define M_DQ_SEL_LANE 0x7U +#define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE) +#define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE) + +#define A_MC_DDRPHY_RC_PERIODIC 0x47420 +#define A_MC_DDRPHY_WC_CONFIG0 0x47600 + +#define S_TWLO_TWLOE 8 +#define M_TWLO_TWLOE 0xffU +#define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE) +#define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE) + +#define S_WL_ONE_DQS_PULSE 7 +#define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE) +#define F_WL_ONE_DQS_PULSE V_WL_ONE_DQS_PULSE(1U) + +#define S_FW_WR_RD 1 +#define M_FW_WR_RD 0x3fU +#define V_FW_WR_RD(x) ((x) << S_FW_WR_RD) +#define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD) + +#define S_CUSTOM_INIT_WRITE 0 +#define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE) +#define F_CUSTOM_INIT_WRITE V_CUSTOM_INIT_WRITE(1U) + +#define A_MC_DDRPHY_WC_CONFIG1 0x47604 + +#define S_BIG_STEP 12 +#define M_BIG_STEP 0xfU +#define V_BIG_STEP(x) ((x) << S_BIG_STEP) +#define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP) + +#define S_SMALL_STEP 9 +#define M_SMALL_STEP 0x7U +#define V_SMALL_STEP(x) ((x) << S_SMALL_STEP) +#define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP) + +#define S_WR_PRE_DLY 3 +#define M_WR_PRE_DLY 0x3fU +#define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY) +#define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY) + +#define A_MC_DDRPHY_WC_CONFIG2 0x47608 + +#define S_NUM_VALID_SAMPLES 12 +#define M_NUM_VALID_SAMPLES 0xfU +#define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES) +#define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES) + +#define S_FW_RD_WR 6 +#define M_FW_RD_WR 0x3fU +#define V_FW_RD_WR(x) ((x) << S_FW_RD_WR) +#define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR) + +#define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c + +#define S_WR_CNTL_ERROR 15 +#define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR) +#define F_WR_CNTL_ERROR V_WR_CNTL_ERROR(1U) + +#define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610 + +#define S_WR_CNTL_ERROR_MASK 15 +#define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK) +#define F_WR_CNTL_ERROR_MASK V_WR_CNTL_ERROR_MASK(1U) + +#define A_MC_DDRPHY_WC_CONFIG3 0x47614 + +#define S_DDR4_MRS_CMD_DQ_EN 15 +#define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN) +#define F_DDR4_MRS_CMD_DQ_EN V_DDR4_MRS_CMD_DQ_EN(1U) + +#define S_MRS_CMD_DQ_ON 9 +#define M_MRS_CMD_DQ_ON 0x3fU +#define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON) +#define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON) + +#define S_MRS_CMD_DQ_OFF 3 +#define M_MRS_CMD_DQ_OFF 0x3fU +#define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF) +#define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF) + +#define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618 + +#define S_WRCLK_CAL_START 15 +#define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START) +#define F_WRCLK_CAL_START V_WRCLK_CAL_START(1U) + +#define S_WRCLK_CAL_DONE 14 +#define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE) +#define F_WRCLK_CAL_DONE V_WRCLK_CAL_DONE(1U) + +#define A_MC_DDRPHY_APB_CONFIG0 0x47800 + +#define S_DISABLE_PARITY_CHECKER 15 +#define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER) +#define F_DISABLE_PARITY_CHECKER V_DISABLE_PARITY_CHECKER(1U) + +#define S_GENERATE_EVEN_PARITY 14 +#define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY) +#define F_GENERATE_EVEN_PARITY V_GENERATE_EVEN_PARITY(1U) + +#define S_FORCE_ON_CLK_GATE 13 +#define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE) +#define F_FORCE_ON_CLK_GATE V_FORCE_ON_CLK_GATE(1U) + +#define S_DEBUG_BUS_SEL_LO 12 +#define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO) +#define F_DEBUG_BUS_SEL_LO V_DEBUG_BUS_SEL_LO(1U) + +#define S_DEBUG_BUS_SEL_HI 8 +#define M_DEBUG_BUS_SEL_HI 0xfU +#define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI) +#define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI) + +#define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804 + +#define S_INVALID_ADDRESS 15 +#define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS) +#define F_INVALID_ADDRESS V_INVALID_ADDRESS(1U) + +#define S_WR_PAR_ERR 14 +#define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR) +#define F_WR_PAR_ERR V_WR_PAR_ERR(1U) + +#define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808 + +#define S_INVALID_ADDRESS_MASK 15 +#define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK) +#define F_INVALID_ADDRESS_MASK V_INVALID_ADDRESS_MASK(1U) + +#define S_WR_PAR_ERR_MASK 14 +#define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK) +#define F_WR_PAR_ERR_MASK V_WR_PAR_ERR_MASK(1U) + +#define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c + +#define S_DP18_0_POPULATED 15 +#define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED) +#define F_DP18_0_POPULATED V_DP18_0_POPULATED(1U) + +#define S_DP18_1_POPULATED 14 +#define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED) +#define F_DP18_1_POPULATED V_DP18_1_POPULATED(1U) + +#define S_DP18_2_POPULATED 13 +#define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED) +#define F_DP18_2_POPULATED V_DP18_2_POPULATED(1U) + +#define S_DP18_3_POPULATED 12 +#define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED) +#define F_DP18_3_POPULATED V_DP18_3_POPULATED(1U) + +#define S_DP18_4_POPULATED 11 +#define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED) +#define F_DP18_4_POPULATED V_DP18_4_POPULATED(1U) + +#define S_DP18_5_POPULATED 10 +#define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED) +#define F_DP18_5_POPULATED V_DP18_5_POPULATED(1U) + +#define S_DP18_6_POPULATED 9 +#define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED) +#define F_DP18_6_POPULATED V_DP18_6_POPULATED(1U) + +#define S_DP18_7_POPULATED 8 +#define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED) +#define F_DP18_7_POPULATED V_DP18_7_POPULATED(1U) + +#define S_DP18_8_POPULATED 7 +#define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED) +#define F_DP18_8_POPULATED V_DP18_8_POPULATED(1U) + +#define S_DP18_9_POPULATED 6 +#define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED) +#define F_DP18_9_POPULATED V_DP18_9_POPULATED(1U) + +#define S_DP18_10_POPULATED 5 +#define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED) +#define F_DP18_10_POPULATED V_DP18_10_POPULATED(1U) + +#define S_DP18_11_POPULATED 4 +#define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED) +#define F_DP18_11_POPULATED V_DP18_11_POPULATED(1U) + +#define S_DP18_12_POPULATED 3 +#define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED) +#define F_DP18_12_POPULATED V_DP18_12_POPULATED(1U) + +#define S_DP18_13_POPULATED 2 +#define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED) +#define F_DP18_13_POPULATED V_DP18_13_POPULATED(1U) + +#define S_DP18_14_POPULATED 1 +#define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED) +#define F_DP18_14_POPULATED V_DP18_14_POPULATED(1U) + +#define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810 + +#define S_ADR16_0_POPULATED 15 +#define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED) +#define F_ADR16_0_POPULATED V_ADR16_0_POPULATED(1U) + +#define S_ADR16_1_POPULATED 14 +#define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED) +#define F_ADR16_1_POPULATED V_ADR16_1_POPULATED(1U) + +#define S_ADR16_2_POPULATED 13 +#define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED) +#define F_ADR16_2_POPULATED V_ADR16_2_POPULATED(1U) + +#define S_ADR16_3_POPULATED 12 +#define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED) +#define F_ADR16_3_POPULATED V_ADR16_3_POPULATED(1U) + +#define S_ADR12_0_POPULATED 7 +#define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED) +#define F_ADR12_0_POPULATED V_ADR12_0_POPULATED(1U) + +#define S_ADR12_1_POPULATED 6 +#define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED) +#define F_ADR12_1_POPULATED V_ADR12_1_POPULATED(1U) + +#define S_ADR12_2_POPULATED 5 +#define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED) +#define F_ADR12_2_POPULATED V_ADR12_2_POPULATED(1U) + +#define S_ADR12_3_POPULATED 4 +#define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED) +#define F_ADR12_3_POPULATED V_ADR12_3_POPULATED(1U) + +#define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814 + +#define S_ATEST_CNTL 10 +#define M_ATEST_CNTL 0x3fU +#define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL) +#define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL) + +/* registers for module MC_1 */ +#define MC_1_BASE_ADDR 0x48000 + +/* registers for module EDC_T50 */ +#define EDC_T50_BASE_ADDR 0x50000 + +#define A_EDC_H_REF 0x50000 + +#define S_EDC_SLEEPSTATUS 31 +#define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS) +#define F_EDC_SLEEPSTATUS V_EDC_SLEEPSTATUS(1U) + +#define S_EDC_SLEEPREQ 30 +#define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ) +#define F_EDC_SLEEPREQ V_EDC_SLEEPREQ(1U) + +#define S_PING_PONG 29 +#define V_PING_PONG(x) ((x) << S_PING_PONG) +#define F_PING_PONG V_PING_PONG(1U) + +#define A_EDC_H_BIST_CMD 0x50004 +#define A_EDC_H_BIST_CMD_ADDR 0x50008 +#define A_EDC_H_BIST_CMD_LEN 0x5000c +#define A_EDC_H_BIST_DATA_PATTERN 0x50010 +#define A_EDC_H_BIST_USER_WDATA0 0x50014 +#define A_EDC_H_BIST_USER_WDATA1 0x50018 +#define A_EDC_H_BIST_USER_WDATA2 0x5001c +#define A_EDC_H_BIST_NUM_ERR 0x50020 +#define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024 +#define A_EDC_H_BIST_STATUS_RDATA 0x50028 +#define A_EDC_H_PAR_ENABLE 0x50070 + +#define S_PERR_PAR_ENABLE 0 +#define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE) +#define F_PERR_PAR_ENABLE V_PERR_PAR_ENABLE(1U) + +#define A_EDC_H_INT_ENABLE 0x50074 +#define A_EDC_H_INT_CAUSE 0x50078 +#define A_EDC_H_ECC_STATUS 0x5007c +#define A_EDC_H_ECC_ERR_SEL 0x50080 + +#define S_CFG 0 +#define M_CFG 0x3U +#define V_CFG(x) ((x) << S_CFG) +#define G_CFG(x) (((x) >> S_CFG) & M_CFG) + +#define A_EDC_H_ECC_ERR_ADDR 0x50084 + +#define S_ECC_ADDR 0 +#define M_ECC_ADDR 0x7fffffU +#define V_ECC_ADDR(x) ((x) << S_ECC_ADDR) +#define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR) + +#define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090 +#define A_EDC_H_BIST_CRC_SEED 0x50400 + +/* registers for module EDC_T51 */ +#define EDC_T51_BASE_ADDR 0x50800 + +/* registers for module HMA_T5 */ +#define HMA_T5_BASE_ADDR 0x51000 + +#define A_HMA_TABLE_ACCESS 0x51000 + +#define S_TRIG 31 +#define V_TRIG(x) ((x) << S_TRIG) +#define F_TRIG V_TRIG(1U) + +#define S_RW 30 +#define V_RW(x) ((x) << S_RW) +#define F_RW V_RW(1U) + +#define S_L_SEL 0 +#define M_L_SEL 0xfU +#define V_L_SEL(x) ((x) << S_L_SEL) +#define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL) + +#define A_HMA_TABLE_LINE0 0x51004 + +#define S_CLIENT_EN 0 +#define M_CLIENT_EN 0x1fffU +#define V_CLIENT_EN(x) ((x) << S_CLIENT_EN) +#define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN) + +#define A_HMA_TABLE_LINE1 0x51008 +#define A_HMA_TABLE_LINE2 0x5100c +#define A_HMA_TABLE_LINE3 0x51010 +#define A_HMA_TABLE_LINE4 0x51014 +#define A_HMA_TABLE_LINE5 0x51018 + +#define S_FID 16 +#define M_FID 0x7ffU +#define V_FID(x) ((x) << S_FID) +#define G_FID(x) (((x) >> S_FID) & M_FID) + +#define S_NOS 15 +#define V_NOS(x) ((x) << S_NOS) +#define F_NOS V_NOS(1U) + +#define S_RO 14 +#define V_RO(x) ((x) << S_RO) +#define F_RO V_RO(1U) + +#define A_HMA_COOKIE 0x5101c + +#define S_C_REQ 31 +#define V_C_REQ(x) ((x) << S_C_REQ) +#define F_C_REQ V_C_REQ(1U) + +#define S_C_FID 18 +#define M_C_FID 0x7ffU +#define V_C_FID(x) ((x) << S_C_FID) +#define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID) + +#define S_C_VAL 8 +#define M_C_VAL 0x3ffU +#define V_C_VAL(x) ((x) << S_C_VAL) +#define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL) + +#define S_C_SEL 0 +#define M_C_SEL 0xfU +#define V_C_SEL(x) ((x) << S_C_SEL) +#define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL) + +#define A_HMA_PAR_ENABLE 0x51300 +#define A_HMA_INT_ENABLE 0x51304 +#define A_HMA_INT_CAUSE 0x51308 diff --git a/sys/dev/cxgbe/osdep.h b/sys/dev/cxgbe/osdep.h index 87d683f571b..78eb2f30ebb 100644 --- a/sys/dev/cxgbe/osdep.h +++ b/sys/dev/cxgbe/osdep.h @@ -64,8 +64,11 @@ typedef uint64_t __be64; #if BYTE_ORDER == BIG_ENDIAN #define __BIG_ENDIAN_BITFIELD +#define htobe32_const(x) (x) #elif BYTE_ORDER == LITTLE_ENDIAN #define __LITTLE_ENDIAN_BITFIELD +#define htobe32_const(x) (((x) >> 24) | (((x) >> 8) & 0xff00) | \ + ((((x) & 0xffffff) << 8) & 0xff0000) | ((((x) & 0xff) << 24) & 0xff000000)) #else #error "Must set BYTE_ORDER" #endif diff --git a/sys/dev/cxgbe/t4_ioctl.h b/sys/dev/cxgbe/t4_ioctl.h index 4a55c116fdd..edfa9330f10 100644 --- a/sys/dev/cxgbe/t4_ioctl.h +++ b/sys/dev/cxgbe/t4_ioctl.h @@ -60,6 +60,7 @@ struct t4_reg { }; #define T4_REGDUMP_SIZE (160 * 1024) +#define T5_REGDUMP_SIZE (332 * 1024) struct t4_regdump { uint32_t version; uint32_t len; /* bytes */ diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index fcea547f63e..d3168805759 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -55,6 +55,10 @@ __FBSDID("$FreeBSD$"); #include #include #include +#if defined(__i386__) || defined(__amd64__) +#include +#include +#endif #include "common/common.h" #include "common/t4_msg.h" @@ -110,6 +114,38 @@ static struct cdevsw t4_cdevsw = { .d_name = "t4nex", }; +/* T5 bus driver interface */ +static int t5_probe(device_t); +static device_method_t t5_methods[] = { + DEVMETHOD(device_probe, t5_probe), + DEVMETHOD(device_attach, t4_attach), + DEVMETHOD(device_detach, t4_detach), + + DEVMETHOD_END +}; +static driver_t t5_driver = { + "t5nex", + t5_methods, + sizeof(struct adapter) +}; + + +/* T5 port (cxl) interface */ +static driver_t cxl_driver = { + "cxl", + cxgbe_methods, + sizeof(struct port_info) +}; + +static struct cdevsw t5_cdevsw = { + .d_version = D_VERSION, + .d_flags = 0, + .d_open = t4_open, + .d_close = t4_close, + .d_ioctl = t4_ioctl, + .d_name = "t5nex", +}; + /* ifnet + media interface */ static void cxgbe_init(void *); static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); @@ -118,7 +154,7 @@ static void cxgbe_qflush(struct ifnet *); static int cxgbe_media_change(struct ifnet *); static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); -MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4 Ethernet driver and services"); +MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); /* * Correct lock order when you need to acquire multiple locks is t4_list_lock, @@ -133,6 +169,13 @@ static SLIST_HEAD(, uld_info) t4_uld_list; /* * Tunables. See tweak_tunables() too. + * + * Each tunable is set to a default value here if it's known at compile-time. + * Otherwise it is set to -1 as an indication to tweak_tunables() that it should + * provide a reasonable default when the driver is loaded. + * + * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to + * T5 are under hw.cxl. */ /* @@ -209,7 +252,10 @@ TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); /* * Configuration file. */ -static char t4_cfg_file[32] = "default"; +#define DEFAULT_CF "default" +#define FLASH_CF "flash" +#define UWIRE_CF "uwire" +static char t4_cfg_file[32] = DEFAULT_CF; TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); /* @@ -241,6 +287,9 @@ TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); static int t4_fcoecaps_allowed = 0; TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); +static int t5_write_combine = 0; +TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); + struct intrs_and_queues { int intr_type; /* INTx, MSI, or MSI-X */ int nirq; /* Number of vectors */ @@ -278,14 +327,19 @@ enum { XGMAC_ALL = 0xffff }; -static int map_bars(struct adapter *); +static int map_bars_0_and_4(struct adapter *); +static int map_bar_2(struct adapter *); static void setup_memwin(struct adapter *); +static int validate_mem_range(struct adapter *, uint32_t, int); +static int validate_mt_off_len(struct adapter *, int, uint32_t, int, + uint32_t *); +static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); +static uint32_t position_memwin(struct adapter *, int, uint32_t); static int cfg_itype_and_nqueues(struct adapter *, int, int, struct intrs_and_queues *); static int prep_firmware(struct adapter *); -static int upload_config_file(struct adapter *, const struct firmware *, - uint32_t *, uint32_t *); -static int partition_resources(struct adapter *, const struct firmware *); +static int partition_resources(struct adapter *, const struct firmware *, + const char *); static int get_params__pre_init(struct adapter *); static int get_params__post_init(struct adapter *); static int set_params__post_init(struct adapter *); @@ -342,6 +396,7 @@ static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); static int sysctl_tids(SYSCTL_HANDLER_ARGS); static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); +static int sysctl_wrwc_stats(SYSCTL_HANDLER_ARGS); #endif static inline void txq_start(struct ifnet *, struct sge_txq *); static uint32_t fconf_to_mode(uint32_t); @@ -358,14 +413,14 @@ static int set_filter_wr(struct adapter *, int); static int del_filter_wr(struct adapter *, int); static int get_sge_context(struct adapter *, struct t4_sge_context *); static int load_fw(struct adapter *, struct t4_data *); -static int read_card_mem(struct adapter *, struct t4_mem_range *); +static int read_card_mem(struct adapter *, int, struct t4_mem_range *); static int read_i2c(struct adapter *, struct t4_i2c_data *); #ifdef TCP_OFFLOAD static int toe_capability(struct port_info *, int); #endif static int t4_mod_event(module_t, int, void *); -struct t4_pciids { +struct { uint16_t device; char *desc; } t4_pciids[] = { @@ -382,6 +437,9 @@ struct t4_pciids { {0x4409, "Chelsio T420-BT"}, {0x440a, "Chelsio T404-BT"}, {0x440e, "Chelsio T440-LP-CR"}, +}, t5_pciids[] = { + {0xb000, "Chelsio Terminator 5 FPGA"}, + {0x5400, "Chelsio T580-dbg"}, }; #ifdef TCP_OFFLOAD @@ -422,6 +480,31 @@ t4_probe(device_t dev) return (ENXIO); } +static int +t5_probe(device_t dev) +{ + int i; + uint16_t v = pci_get_vendor(dev); + uint16_t d = pci_get_device(dev); + uint8_t f = pci_get_function(dev); + + if (v != PCI_VENDOR_ID_CHELSIO) + return (ENXIO); + + /* Attach only to PF0 of the FPGA */ + if (d == 0xb000 && f != 0) + return (ENXIO); + + for (i = 0; i < nitems(t5_pciids); i++) { + if (d == t5_pciids[i].device) { + device_set_desc(dev, t5_pciids[i].desc); + return (BUS_PROBE_DEFAULT); + } + } + + return (ENXIO); +} + static int t4_attach(device_t dev) { @@ -457,7 +540,7 @@ t4_attach(device_t dev) TAILQ_INIT(&sc->sfl); callout_init(&sc->sfl_callout, CALLOUT_MPSAFE); - rc = map_bars(sc); + rc = map_bars_0_and_4(sc); if (rc != 0) goto done; /* error message displayed already */ @@ -477,6 +560,7 @@ t4_attach(device_t dev) for (i = 0; i < nitems(sc->fw_msg_handler); i++) sc->fw_msg_handler[i] = fw_msg_not_handled; t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl); + t4_init_sge_cpl_handlers(sc); /* Prepare the adapter for operation */ rc = -t4_prep_adapter(sc); @@ -491,9 +575,13 @@ t4_attach(device_t dev) * will work even in "recovery mode". */ setup_memwin(sc); - sc->cdev = make_dev(&t4_cdevsw, device_get_unit(dev), UID_ROOT, - GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); - sc->cdev->si_drv1 = sc; + sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw, + device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s", + device_get_nameunit(dev)); + if (sc->cdev == NULL) + device_printf(dev, "failed to create nexus char device.\n"); + else + sc->cdev->si_drv1 = sc; /* Go no further if recovery mode has been requested. */ if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { @@ -506,23 +594,6 @@ t4_attach(device_t dev) if (rc != 0) goto done; /* error message displayed already */ - rc = get_params__pre_init(sc); - if (rc != 0) - goto done; /* error message displayed already */ - - rc = t4_sge_init(sc); - if (rc != 0) - goto done; /* error message displayed already */ - - if (sc->flags & MASTER_PF) { - /* get basic stuff going */ - rc = -t4_fw_initialize(sc, sc->mbox); - if (rc != 0) { - device_printf(dev, "early init failed: %d.\n", rc); - goto done; - } - } - rc = get_params__post_init(sc); if (rc != 0) goto done; /* error message displayed already */ @@ -531,32 +602,9 @@ t4_attach(device_t dev) if (rc != 0) goto done; /* error message displayed already */ - if (sc->flags & MASTER_PF) { - uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); - - /* final tweaks to some settings */ - - t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, - sc->params.b_wnd); - /* 4K, 16K, 64K, 256K DDP "page sizes" */ - t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(0) | V_HPZ1(2) | - V_HPZ2(4) | V_HPZ3(6)); - t4_set_reg_field(sc, A_ULP_RX_CTL, F_TDDPTAGTCB, F_TDDPTAGTCB); - t4_set_reg_field(sc, A_TP_PARA_REG5, - V_INDICATESIZE(M_INDICATESIZE) | - F_REARMDDPOFFSET | F_RESETDDPOFFSET, - V_INDICATESIZE(indsz) | - F_REARMDDPOFFSET | F_RESETDDPOFFSET); - } else { - /* - * XXX: Verify that we can live with whatever the master driver - * has done so far, and hope that it doesn't change any global - * setting from underneath us in the future. - */ - } - - t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1, - A_TP_VLAN_PRI_MAP); + rc = map_bar_2(sc); + if (rc != 0) + goto done; /* error message displayed already */ for (i = 0; i < NCHAN; i++) sc->params.tp.tx_modq[i] = i; @@ -611,7 +659,7 @@ t4_attach(device_t dev) pi->qsize_rxq = t4_qsize_rxq; pi->qsize_txq = t4_qsize_txq; - pi->dev = device_add_child(dev, "cxgbe", -1); + pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1); if (pi->dev == NULL) { device_printf(dev, "failed to add device for port %d.\n", i); @@ -808,6 +856,10 @@ t4_detach(device_t dev) bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); + if (sc->udbs_res) + bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, + sc->udbs_res); + if (sc->msix_res) bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, sc->msix_res); @@ -1296,7 +1348,7 @@ t4_fatal_err(struct adapter *sc) } static int -map_bars(struct adapter *sc) +map_bars_0_and_4(struct adapter *sc) { sc->regs_rid = PCIR_BAR(0); sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, @@ -1308,6 +1360,7 @@ map_bars(struct adapter *sc) sc->bt = rman_get_bustag(sc->regs_res); sc->bh = rman_get_bushandle(sc->regs_res); sc->mmio_len = rman_get_size(sc->regs_res); + setbit(&sc->doorbells, DOORBELL_KDB); sc->msix_rid = PCIR_BAR(4); sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, @@ -1320,37 +1373,273 @@ map_bars(struct adapter *sc) return (0); } +static int +map_bar_2(struct adapter *sc) +{ + + /* + * T4: only iWARP driver uses the userspace doorbells. There is no need + * to map it if RDMA is disabled. + */ + if (is_t4(sc) && sc->rdmacaps == 0) + return (0); + + sc->udbs_rid = PCIR_BAR(2); + sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, + &sc->udbs_rid, RF_ACTIVE); + if (sc->udbs_res == NULL) { + device_printf(sc->dev, "cannot map doorbell BAR.\n"); + return (ENXIO); + } + sc->udbs_base = rman_get_virtual(sc->udbs_res); + + if (is_t5(sc)) { + setbit(&sc->doorbells, DOORBELL_UDB); +#if defined(__i386__) || defined(__amd64__) + if (t5_write_combine) { + int rc; + + /* + * Enable write combining on BAR2. This is the + * userspace doorbell BAR and is split into 128B + * (UDBS_SEG_SIZE) doorbell regions, each associated + * with an egress queue. The first 64B has the doorbell + * and the second 64B can be used to submit a tx work + * request with an implicit doorbell. + */ + + rc = pmap_change_attr((vm_offset_t)sc->udbs_base, + rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); + if (rc == 0) { + clrbit(&sc->doorbells, DOORBELL_UDB); + setbit(&sc->doorbells, DOORBELL_WRWC); + setbit(&sc->doorbells, DOORBELL_UDBWC); + } else { + device_printf(sc->dev, + "couldn't enable write combining: %d\n", + rc); + } + + t4_write_reg(sc, A_SGE_STAT_CFG, + V_STATSOURCE_T5(7) | V_STATMODE(0)); + } +#endif + } + + return (0); +} + +static const struct memwin t4_memwin[] = { + { MEMWIN0_BASE, MEMWIN0_APERTURE }, + { MEMWIN1_BASE, MEMWIN1_APERTURE }, + { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } +}; + +static const struct memwin t5_memwin[] = { + { MEMWIN0_BASE, MEMWIN0_APERTURE }, + { MEMWIN1_BASE, MEMWIN1_APERTURE }, + { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, +}; + static void setup_memwin(struct adapter *sc) { + const struct memwin *mw; + int i, n; uint32_t bar0; - /* - * Read low 32b of bar0 indirectly via the hardware backdoor mechanism. - * Works from within PCI passthrough environments too, where - * rman_get_start() can return a different value. We need to program - * the memory window decoders with the actual addresses that will be - * coming across the PCIe link. - */ - bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); - bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; + if (is_t4(sc)) { + /* + * Read low 32b of bar0 indirectly via the hardware backdoor + * mechanism. Works from within PCI passthrough environments + * too, where rman_get_start() can return a different value. We + * need to program the T4 memory window decoders with the actual + * addresses that will be coming across the PCIe link. + */ + bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); + bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), - (bar0 + MEMWIN0_BASE) | V_BIR(0) | - V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); + mw = &t4_memwin[0]; + n = nitems(t4_memwin); + } else { + /* T5 uses the relative offset inside the PCIe BAR */ + bar0 = 0; - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), - (bar0 + MEMWIN1_BASE) | V_BIR(0) | - V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); + mw = &t5_memwin[0]; + n = nitems(t5_memwin); + } - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), - (bar0 + MEMWIN2_BASE) | V_BIR(0) | - V_WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); + for (i = 0; i < n; i++, mw++) { + t4_write_reg(sc, + PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), + (mw->base + bar0) | V_BIR(0) | + V_WINDOW(ilog2(mw->aperture) - 10)); + } /* flush */ t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); } +/* + * Verify that the memory range specified by the addr/len pair is valid and lies + * entirely within a single region (EDCx or MCx). + */ +static int +validate_mem_range(struct adapter *sc, uint32_t addr, int len) +{ + uint32_t em, addr_len, maddr, mlen; + + /* Memory can only be accessed in naturally aligned 4 byte units */ + if (addr & 3 || len & 3 || len == 0) + return (EINVAL); + + /* Enabled memories */ + em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); + if (em & F_EDRAM0_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); + maddr = G_EDRAM0_BASE(addr_len) << 20; + mlen = G_EDRAM0_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (em & F_EDRAM1_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); + maddr = G_EDRAM1_BASE(addr_len) << 20; + mlen = G_EDRAM1_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (em & F_EXT_MEM_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); + maddr = G_EXT_MEM_BASE(addr_len) << 20; + mlen = G_EXT_MEM_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (!is_t4(sc) && em & F_EXT_MEM1_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + maddr = G_EXT_MEM1_BASE(addr_len) << 20; + mlen = G_EXT_MEM1_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + + return (EFAULT); +} + +/* + * Verify that the memory range specified by the memtype/offset/len pair is + * valid and lies entirely within the memtype specified. The global address of + * the start of the range is returned in addr. + */ +static int +validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, + uint32_t *addr) +{ + uint32_t em, addr_len, maddr, mlen; + + /* Memory can only be accessed in naturally aligned 4 byte units */ + if (off & 3 || len & 3 || len == 0) + return (EINVAL); + + em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); + switch (mtype) { + case MEM_EDC0: + if (!(em & F_EDRAM0_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); + maddr = G_EDRAM0_BASE(addr_len) << 20; + mlen = G_EDRAM0_SIZE(addr_len) << 20; + break; + case MEM_EDC1: + if (!(em & F_EDRAM1_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); + maddr = G_EDRAM1_BASE(addr_len) << 20; + mlen = G_EDRAM1_SIZE(addr_len) << 20; + break; + case MEM_MC: + if (!(em & F_EXT_MEM_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); + maddr = G_EXT_MEM_BASE(addr_len) << 20; + mlen = G_EXT_MEM_SIZE(addr_len) << 20; + break; + case MEM_MC1: + if (is_t4(sc) || !(em & F_EXT_MEM1_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + maddr = G_EXT_MEM1_BASE(addr_len) << 20; + mlen = G_EXT_MEM1_SIZE(addr_len) << 20; + break; + default: + return (EINVAL); + } + + if (mlen > 0 && off < mlen && off + len <= mlen) { + *addr = maddr + off; /* global address */ + return (0); + } + + return (EFAULT); +} + +static void +memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) +{ + const struct memwin *mw; + + if (is_t4(sc)) { + KASSERT(win >= 0 && win < nitems(t4_memwin), + ("%s: incorrect memwin# (%d)", __func__, win)); + mw = &t4_memwin[win]; + } else { + KASSERT(win >= 0 && win < nitems(t5_memwin), + ("%s: incorrect memwin# (%d)", __func__, win)); + mw = &t5_memwin[win]; + } + + if (base != NULL) + *base = mw->base; + if (aperture != NULL) + *aperture = mw->aperture; +} + +/* + * Positions the memory window such that it can be used to access the specified + * address in the chip's address space. The return value is the offset of addr + * from the start of the window. + */ +static uint32_t +position_memwin(struct adapter *sc, int n, uint32_t addr) +{ + uint32_t start, pf; + uint32_t reg; + + KASSERT(n >= 0 && n <= 3, + ("%s: invalid window %d.", __func__, n)); + KASSERT((addr & 3) == 0, + ("%s: addr (0x%x) is not at a 4B boundary.", __func__, addr)); + + if (is_t4(sc)) { + pf = 0; + start = addr & ~0xf; /* start must be 16B aligned */ + } else { + pf = V_PFNUM(sc->pf); + start = addr & ~0x7f; /* start must be 128B aligned */ + } + reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); + + t4_write_reg(sc, reg, start | pf); + t4_read_reg(sc, reg); + + return (addr - start); +} + static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, struct intrs_and_queues *iaq) @@ -1509,56 +1798,152 @@ allocate: return (ENXIO); } +#define FW_VERSION(chip) ( \ + V_FW_HDR_FW_VER_MAJOR(FW_VERSION_MAJOR_##chip) | \ + V_FW_HDR_FW_VER_MINOR(FW_VERSION_MINOR_##chip) | \ + V_FW_HDR_FW_VER_MICRO(FW_VERSION_MICRO_##chip) | \ + V_FW_HDR_FW_VER_BUILD(FW_VERSION_BUILD_##chip)) +#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) + +struct fw_info { + uint8_t chip; + char *kld_name; + char *fw_mod_name; + struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ +} fw_info[] = { + { + .chip = CHELSIO_T4, + .kld_name = "t4fw_cfg", + .fw_mod_name = "t4fw", + .fw_hdr = { + .chip = FW_HDR_CHIP_T4, + .fw_ver = htobe32_const(FW_VERSION(T4)), + .intfver_nic = FW_INTFVER(T4, NIC), + .intfver_vnic = FW_INTFVER(T4, VNIC), + .intfver_ofld = FW_INTFVER(T4, OFLD), + .intfver_ri = FW_INTFVER(T4, RI), + .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), + .intfver_iscsi = FW_INTFVER(T4, ISCSI), + .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), + .intfver_fcoe = FW_INTFVER(T4, FCOE), + }, + }, { + .chip = CHELSIO_T5, + .kld_name = "t5fw_cfg", + .fw_mod_name = "t5fw", + .fw_hdr = { + .chip = FW_HDR_CHIP_T5, + .fw_ver = htobe32_const(FW_VERSION(T5)), + .intfver_nic = FW_INTFVER(T5, NIC), + .intfver_vnic = FW_INTFVER(T5, VNIC), + .intfver_ofld = FW_INTFVER(T5, OFLD), + .intfver_ri = FW_INTFVER(T5, RI), + .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), + .intfver_iscsi = FW_INTFVER(T5, ISCSI), + .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), + .intfver_fcoe = FW_INTFVER(T5, FCOE), + }, + } +}; + +static struct fw_info * +find_fw_info(int chip) +{ + int i; + + for (i = 0; i < nitems(fw_info); i++) { + if (fw_info[i].chip == chip) + return (&fw_info[i]); + } + return (NULL); +} + /* - * Is the given firmware compatible with the one the driver was compiled with? + * Is the given firmware API compatible with the one the driver was compiled + * with? */ static int -fw_compatible(const struct fw_hdr *hdr) +fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) { - if (hdr->fw_ver == htonl(FW_VERSION)) + /* short circuit if it's the exact same firmware version */ + if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) return (1); /* * XXX: Is this too conservative? Perhaps I should limit this to the * features that are supported in the driver. */ - if (hdr->intfver_nic == FW_HDR_INTFVER_NIC && - hdr->intfver_vnic == FW_HDR_INTFVER_VNIC && - hdr->intfver_ofld == FW_HDR_INTFVER_OFLD && - hdr->intfver_ri == FW_HDR_INTFVER_RI && - hdr->intfver_iscsipdu == FW_HDR_INTFVER_ISCSIPDU && - hdr->intfver_iscsi == FW_HDR_INTFVER_ISCSI && - hdr->intfver_fcoepdu == FW_HDR_INTFVER_FCOEPDU && - hdr->intfver_fcoe == FW_HDR_INTFVER_FCOEPDU) +#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) + if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && + SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && + SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) return (1); +#undef SAME_INTF return (0); } /* - * Install a compatible firmware (if required), establish contact with it (by - * saying hello), and reset the device. If we end up as the master driver, - * partition adapter resources by providing a configuration file to the - * firmware. + * Establish contact with the firmware and determine if we are the master driver + * or not, and whether we are responsible for chip initialization. */ static int prep_firmware(struct adapter *sc) { - const struct firmware *fw = NULL, *cfg = NULL, *default_cfg; - int rc, card_fw_usable, kld_fw_usable; + const struct firmware *fw = NULL, *default_cfg; + int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; enum dev_state state; - struct fw_hdr *card_fw; - const struct fw_hdr *kld_fw; + struct fw_info *fw_info; + struct fw_hdr *card_fw; /* fw on the card */ + const struct fw_hdr *kld_fw; /* fw in the KLD */ + const struct fw_hdr *drv_fw; /* fw header the driver was compiled + against */ - default_cfg = firmware_get(T4_CFGNAME); + /* Contact firmware. */ + rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); + if (rc < 0 || state == DEV_STATE_ERR) { + rc = -rc; + device_printf(sc->dev, + "failed to connect to the firmware: %d, %d.\n", rc, state); + return (rc); + } + pf = rc; + if (pf == sc->mbox) + sc->flags |= MASTER_PF; + else if (state == DEV_STATE_UNINIT) { + /* + * We didn't get to be the master so we definitely won't be + * configuring the chip. It's a bug if someone else hasn't + * configured it already. + */ + device_printf(sc->dev, "couldn't be master(%d), " + "device not already initialized either(%d).\n", rc, state); + return (EDOOFUS); + } + + /* This is the firmware whose headers the driver was compiled against */ + fw_info = find_fw_info(chip_id(sc)); + if (fw_info == NULL) { + device_printf(sc->dev, + "unable to look up firmware information for chip %d.\n", + chip_id(sc)); + return (EINVAL); + } + drv_fw = &fw_info->fw_hdr; + + /* + * The firmware KLD contains many modules. The KLD name is also the + * name of the module that contains the default config file. + */ + default_cfg = firmware_get(fw_info->kld_name); /* Read the header of the firmware on the card */ card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); rc = -t4_read_flash(sc, FLASH_FW_START, sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); if (rc == 0) - card_fw_usable = fw_compatible((const void*)card_fw); + card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); else { device_printf(sc->dev, "Unable to read card's firmware header: %d\n", rc); @@ -1566,29 +1951,29 @@ prep_firmware(struct adapter *sc) } /* This is the firmware in the KLD */ - fw = firmware_get(T4_FWNAME); + fw = firmware_get(fw_info->fw_mod_name); if (fw != NULL) { kld_fw = (const void *)fw->data; - kld_fw_usable = fw_compatible(kld_fw); + kld_fw_usable = fw_compatible(drv_fw, kld_fw); } else { kld_fw = NULL; kld_fw_usable = 0; } - /* - * Short circuit for the common case: the firmware on the card is an - * exact match and the KLD is an exact match too, or it's - * absent/incompatible, or we're prohibited from using it. Note that - * t4_fw_install = 2 is ignored here -- use cxgbetool loadfw if you want - * to reinstall the same firmware as the one on the card. - */ - if (card_fw_usable && card_fw->fw_ver == htonl(FW_VERSION) && - (!kld_fw_usable || kld_fw->fw_ver == htonl(FW_VERSION) || - t4_fw_install == 0)) - goto hello; - - if (kld_fw_usable && (!card_fw_usable || - ntohl(kld_fw->fw_ver) > ntohl(card_fw->fw_ver) || + if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && + (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver || + t4_fw_install == 0)) { + /* + * Common case: the firmware on the card is an exact match and + * the KLD is an exact match too, or the KLD is + * absent/incompatible, or we're prohibited from using it. Note + * that t4_fw_install = 2 is ignored here -- use cxgbetool + * loadfw if you want to reinstall the same firmware as the one + * on the card. + */ + } else if (kld_fw_usable && state == DEV_STATE_UNINIT && + (!card_fw_usable || + be32toh(kld_fw->fw_ver) > be32toh(card_fw->fw_ver) || (t4_fw_install == 2 && kld_fw->fw_ver != card_fw->fw_ver))) { uint32_t v = ntohl(kld_fw->fw_ver); @@ -1607,30 +1992,31 @@ prep_firmware(struct adapter *sc) /* Installed successfully, update the cached header too. */ memcpy(card_fw, kld_fw, sizeof(*card_fw)); card_fw_usable = 1; + need_fw_reset = 0; /* already reset as part of load_fw */ } if (!card_fw_usable) { - uint32_t c, k; + uint32_t d, c, k; + d = ntohl(drv_fw->fw_ver); c = ntohl(card_fw->fw_ver); k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; device_printf(sc->dev, "Cannot find a usable firmware: " - "fw_install %d, driver compiled with %d.%d.%d.%d, " + "fw_install %d, chip state %d, " + "driver compiled with %d.%d.%d.%d, " "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", - t4_fw_install, - G_FW_HDR_FW_VER_MAJOR(FW_VERSION), - G_FW_HDR_FW_VER_MINOR(FW_VERSION), - G_FW_HDR_FW_VER_MICRO(FW_VERSION), - G_FW_HDR_FW_VER_BUILD(FW_VERSION), + t4_fw_install, state, + G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), + G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); + rc = EINVAL; goto done; } -hello: /* We're using whatever's on the card and it's known to be good. */ sc->params.fw_vers = ntohl(card_fw->fw_ver); snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", @@ -1639,60 +2025,48 @@ hello: G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); - /* Contact firmware. */ - rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); - if (rc < 0) { - rc = -rc; - device_printf(sc->dev, - "failed to connect to the firmware: %d.\n", rc); - goto done; - } - if (rc == sc->mbox) - sc->flags |= MASTER_PF; - /* Reset device */ - rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); - if (rc != 0) { + if (need_fw_reset && + (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { device_printf(sc->dev, "firmware reset failed: %d.\n", rc); if (rc != ETIMEDOUT && rc != EIO) t4_fw_bye(sc, sc->mbox); goto done; } + sc->flags |= FW_OK; + + rc = get_params__pre_init(sc); + if (rc != 0) + goto done; /* error message displayed already */ /* Partition adapter resources as specified in the config file. */ - if (sc->flags & MASTER_PF) { - snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", - pci_get_device(sc->dev) == 0x440a ? "uwire" : t4_cfg_file); - if (strncmp(sc->cfg_file, "default", sizeof(sc->cfg_file))) { - char s[32]; + if (state == DEV_STATE_UNINIT) { - snprintf(s, sizeof(s), "t4fw_cfg_%s", sc->cfg_file); - cfg = firmware_get(s); - if (cfg == NULL) { - device_printf(sc->dev, - "unable to locate %s module, " - "will use default config file.\n", s); - snprintf(sc->cfg_file, sizeof(sc->cfg_file), - "%s", "default"); - } - } + KASSERT(sc->flags & MASTER_PF, + ("%s: trying to change chip settings when not master.", + __func__)); - rc = partition_resources(sc, cfg ? cfg : default_cfg); + rc = partition_resources(sc, default_cfg, fw_info->kld_name); if (rc != 0) goto done; /* error message displayed already */ - } else { - snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "notme"); - sc->cfcsum = (u_int)-1; - } - sc->flags |= FW_OK; + t4_tweak_chip_settings(sc); + + /* get basic stuff going */ + rc = -t4_fw_initialize(sc, sc->mbox); + if (rc != 0) { + device_printf(sc->dev, "fw init failed: %d.\n", rc); + goto done; + } + } else { + snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); + sc->cfcsum = 0; + } done: free(card_fw, M_CXGBE); if (fw != NULL) firmware_put(fw, FIRMWARE_UNLOAD); - if (cfg != NULL) - firmware_put(cfg, FIRMWARE_UNLOAD); if (default_cfg != NULL) firmware_put(default_cfg, FIRMWARE_UNLOAD); @@ -1707,115 +2081,131 @@ done: V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) /* - * Upload configuration file to card's memory. + * Partition chip resources for use between various PFs, VFs, etc. */ static int -upload_config_file(struct adapter *sc, const struct firmware *fw, uint32_t *mt, - uint32_t *ma) +partition_resources(struct adapter *sc, const struct firmware *default_cfg, + const char *name_prefix) { - int rc, i; - uint32_t param, val, mtype, maddr, bar, off, win, remaining; - const uint32_t *b; - - /* Figure out where the firmware wants us to upload it. */ - param = FW_PARAM_DEV(CF); - rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); - if (rc != 0) { - /* Firmwares without config file support will fail this way */ - device_printf(sc->dev, - "failed to query config file location: %d.\n", rc); - return (rc); - } - *mt = mtype = G_FW_PARAMS_PARAM_Y(val); - *ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16; - - if (maddr & 3) { - device_printf(sc->dev, - "cannot upload config file (type %u, addr %x).\n", - mtype, maddr); - return (EFAULT); - } - - /* Translate mtype/maddr to an address suitable for the PCIe window */ - val = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); - val &= F_EDRAM0_ENABLE | F_EDRAM1_ENABLE | F_EXT_MEM_ENABLE; - switch (mtype) { - case FW_MEMTYPE_CF_EDC0: - if (!(val & F_EDRAM0_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EDRAM0_BAR); - maddr += G_EDRAM0_BASE(bar) << 20; - break; - - case FW_MEMTYPE_CF_EDC1: - if (!(val & F_EDRAM1_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EDRAM1_BAR); - maddr += G_EDRAM1_BASE(bar) << 20; - break; - - case FW_MEMTYPE_CF_EXTMEM: - if (!(val & F_EXT_MEM_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); - maddr += G_EXT_MEM_BASE(bar) << 20; - break; - - default: -err: - device_printf(sc->dev, - "cannot upload config file (type %u, enabled %u).\n", - mtype, val); - return (EFAULT); - } - - /* - * Position the PCIe window (we use memwin2) to the 16B aligned area - * just at/before the upload location. - */ - win = maddr & ~0xf; - off = maddr - win; /* offset from the start of the window. */ - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win); - t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2)); - - remaining = fw->datasize; - if (remaining > FLASH_CFG_MAX_SIZE || - remaining > MEMWIN2_APERTURE - off) { - device_printf(sc->dev, "cannot upload config file all at once " - "(size %u, max %u, room %u).\n", - remaining, FLASH_CFG_MAX_SIZE, MEMWIN2_APERTURE - off); - return (EFBIG); - } - - /* - * XXX: sheer laziness. We deliberately added 4 bytes of useless - * stuffing/comments at the end of the config file so it's ok to simply - * throw away the last remaining bytes when the config file is not an - * exact multiple of 4. - */ - b = fw->data; - for (i = 0; remaining >= 4; i += 4, remaining -= 4) - t4_write_reg(sc, MEMWIN2_BASE + off + i, *b++); - - return (rc); -} - -/* - * Partition chip resources for use between various PFs, VFs, etc. This is done - * by uploading the firmware configuration file to the adapter and instructing - * the firmware to process it. - */ -static int -partition_resources(struct adapter *sc, const struct firmware *cfg) -{ - int rc; + const struct firmware *cfg = NULL; + int rc = 0; struct fw_caps_config_cmd caps; - uint32_t mtype, maddr, finicsum, cfcsum; + uint32_t mtype, moff, finicsum, cfcsum; - rc = cfg ? upload_config_file(sc, cfg, &mtype, &maddr) : ENOENT; - if (rc != 0) { + /* + * Figure out what configuration file to use. Pick the default config + * file for the card if the user hasn't specified one explicitly. + */ + snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); + if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { + /* Card specific overrides go here. */ + if (pci_get_device(sc->dev) == 0x440a) + snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); + } + + /* + * We need to load another module if the profile is anything except + * "default" or "flash". + */ + if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && + strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { + char s[32]; + + snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); + cfg = firmware_get(s); + if (cfg == NULL) { + device_printf(sc->dev, "unable to load module \"%s\" " + "for configuration profile \"%s\", ", + s, sc->cfg_file); + if (default_cfg != NULL) { + device_printf(sc->dev, "will use the default " + "config file instead.\n"); + snprintf(sc->cfg_file, sizeof(sc->cfg_file), + "%s", DEFAULT_CF); + } else { + device_printf(sc->dev, "will use the config " + "file on the card's flash instead.\n"); + snprintf(sc->cfg_file, sizeof(sc->cfg_file), + "%s", FLASH_CF); + } + } + } + + if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && + default_cfg == NULL) { + device_printf(sc->dev, + "default config file not available, will use the config " + "file on the card's flash instead.\n"); + snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); + } + + if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { + u_int cflen, i, n; + const uint32_t *cfdata; + uint32_t param, val, addr, off, mw_base, mw_aperture; + + KASSERT(cfg != NULL || default_cfg != NULL, + ("%s: no config to upload", __func__)); + + /* + * Ask the firmware where it wants us to upload the config file. + */ + param = FW_PARAM_DEV(CF); + rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); + if (rc != 0) { + /* No support for config file? Shouldn't happen. */ + device_printf(sc->dev, + "failed to query config file location: %d.\n", rc); + goto done; + } + mtype = G_FW_PARAMS_PARAM_Y(val); + moff = G_FW_PARAMS_PARAM_Z(val) << 16; + + /* + * XXX: sheer laziness. We deliberately added 4 bytes of + * useless stuffing/comments at the end of the config file so + * it's ok to simply throw away the last remaining bytes when + * the config file is not an exact multiple of 4. This also + * helps with the validate_mt_off_len check. + */ + if (cfg != NULL) { + cflen = cfg->datasize & ~3; + cfdata = cfg->data; + } else { + cflen = default_cfg->datasize & ~3; + cfdata = default_cfg->data; + } + + if (cflen > FLASH_CFG_MAX_SIZE) { + device_printf(sc->dev, + "config file too long (%d, max allowed is %d). " + "Will try to use the config on the card, if any.\n", + cflen, FLASH_CFG_MAX_SIZE); + goto use_config_on_flash; + } + + rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); + if (rc != 0) { + device_printf(sc->dev, + "%s: addr (%d/0x%x) or len %d is not valid: %d. " + "Will try to use the config on the card, if any.\n", + __func__, mtype, moff, cflen, rc); + goto use_config_on_flash; + } + + memwin_info(sc, 2, &mw_base, &mw_aperture); + while (cflen) { + off = position_memwin(sc, 2, addr); + n = min(cflen, mw_aperture - off); + for (i = 0; i < n; i += 4) + t4_write_reg(sc, mw_base + off + i, *cfdata++); + cflen -= n; + addr += n; + } + } else { +use_config_on_flash: mtype = FW_MEMTYPE_CF_FLASH; - maddr = t4_flash_cfg_addr(sc); + moff = t4_flash_cfg_addr(sc); } bzero(&caps, sizeof(caps)); @@ -1823,12 +2213,13 @@ partition_resources(struct adapter *sc, const struct firmware *cfg) F_FW_CMD_REQUEST | F_FW_CMD_READ); caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | - V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | FW_LEN16(caps)); + V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); if (rc != 0) { device_printf(sc->dev, - "failed to pre-process config file: %d.\n", rc); - return (rc); + "failed to pre-process config file: %d (mtype %d).\n", rc, + mtype); + goto done; } finicsum = be32toh(caps.finicsum); @@ -1864,15 +2255,15 @@ partition_resources(struct adapter *sc, const struct firmware *cfg) if (rc != 0) { device_printf(sc->dev, "failed to process config file: %d.\n", rc); - return (rc); } - - return (0); +done: + if (cfg != NULL) + firmware_put(cfg, FIRMWARE_UNLOAD); + return (rc); } /* - * Retrieve parameters that are needed (or nice to have) prior to calling - * t4_sge_init and t4_fw_initialize. + * Retrieve parameters that are needed (or nice to have) very early. */ static int get_params__pre_init(struct adapter *sc) @@ -2037,11 +2428,11 @@ get_params__post_init(struct adapter *sc) sc->vres.iscsi.size = val[1] - val[0] + 1; } - /* These are finalized by FW initialization, load their values now */ - val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); - sc->params.tp.tre = G_TIMERRESOLUTION(val[0]); - sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(val[0]); - t4_read_mtu_tbl(sc, sc->params.mtus, NULL); + /* + * We've got the params we wanted to query via the firmware. Now grab + * some others directly from the chip. + */ + rc = t4_read_chip_settings(sc); return (rc); } @@ -2083,7 +2474,8 @@ t4_set_desc(struct adapter *sc) struct adapter_params *p = &sc->params; snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, E/C:%s", - p->vpd.id, is_offload(sc) ? "R" : "", p->rev, p->vpd.sn, p->vpd.ec); + p->vpd.id, is_offload(sc) ? "R" : "", chip_rev(sc), p->vpd.sn, + p->vpd.ec); device_set_desc_copy(sc->dev, buf); } @@ -2804,8 +3196,9 @@ reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, static void t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) { - int i; - static const unsigned int reg_ranges[] = { + int i, n; + const unsigned int *reg_ranges; + static const unsigned int t4_reg_ranges[] = { 0x1008, 0x1108, 0x1180, 0x11b4, 0x11fc, 0x123c, @@ -3024,9 +3417,455 @@ t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 0x27c80, 0x27d7c, 0x27e00, 0x27e04 }; + static const unsigned int t5_reg_ranges[] = { + 0x1008, 0x1148, + 0x1180, 0x11b4, + 0x11fc, 0x123c, + 0x1280, 0x173c, + 0x1800, 0x18fc, + 0x3000, 0x3028, + 0x3060, 0x30d8, + 0x30e0, 0x30fc, + 0x3140, 0x357c, + 0x35a8, 0x35cc, + 0x35ec, 0x35ec, + 0x3600, 0x5624, + 0x56cc, 0x575c, + 0x580c, 0x5814, + 0x5890, 0x58bc, + 0x5940, 0x59dc, + 0x59fc, 0x5a18, + 0x5a60, 0x5a9c, + 0x5b94, 0x5bfc, + 0x6000, 0x6040, + 0x6058, 0x614c, + 0x7700, 0x7798, + 0x77c0, 0x78fc, + 0x7b00, 0x7c54, + 0x7d00, 0x7efc, + 0x8dc0, 0x8de0, + 0x8df8, 0x8e84, + 0x8ea0, 0x8f84, + 0x8fc0, 0x90f8, + 0x9400, 0x9470, + 0x9600, 0x96f4, + 0x9800, 0x9808, + 0x9820, 0x983c, + 0x9850, 0x9864, + 0x9c00, 0x9c6c, + 0x9c80, 0x9cec, + 0x9d00, 0x9d6c, + 0x9d80, 0x9dec, + 0x9e00, 0x9e6c, + 0x9e80, 0x9eec, + 0x9f00, 0x9f6c, + 0x9f80, 0xa020, + 0xd004, 0xd03c, + 0xdfc0, 0xdfe0, + 0xe000, 0x11088, + 0x1109c, 0x1117c, + 0x11190, 0x11204, + 0x19040, 0x1906c, + 0x19078, 0x19080, + 0x1908c, 0x19124, + 0x19150, 0x191b0, + 0x191d0, 0x191e8, + 0x19238, 0x19290, + 0x193f8, 0x19474, + 0x19490, 0x194cc, + 0x194f0, 0x194f8, + 0x19c00, 0x19c60, + 0x19c94, 0x19e10, + 0x19e50, 0x19f34, + 0x19f40, 0x19f50, + 0x19f90, 0x19fe4, + 0x1a000, 0x1a06c, + 0x1a0b0, 0x1a120, + 0x1a128, 0x1a138, + 0x1a190, 0x1a1c4, + 0x1a1fc, 0x1a1fc, + 0x1e008, 0x1e00c, + 0x1e040, 0x1e04c, + 0x1e284, 0x1e290, + 0x1e2c0, 0x1e2c0, + 0x1e2e0, 0x1e2e0, + 0x1e300, 0x1e384, + 0x1e3c0, 0x1e3c8, + 0x1e408, 0x1e40c, + 0x1e440, 0x1e44c, + 0x1e684, 0x1e690, + 0x1e6c0, 0x1e6c0, + 0x1e6e0, 0x1e6e0, + 0x1e700, 0x1e784, + 0x1e7c0, 0x1e7c8, + 0x1e808, 0x1e80c, + 0x1e840, 0x1e84c, + 0x1ea84, 0x1ea90, + 0x1eac0, 0x1eac0, + 0x1eae0, 0x1eae0, + 0x1eb00, 0x1eb84, + 0x1ebc0, 0x1ebc8, + 0x1ec08, 0x1ec0c, + 0x1ec40, 0x1ec4c, + 0x1ee84, 0x1ee90, + 0x1eec0, 0x1eec0, + 0x1eee0, 0x1eee0, + 0x1ef00, 0x1ef84, + 0x1efc0, 0x1efc8, + 0x1f008, 0x1f00c, + 0x1f040, 0x1f04c, + 0x1f284, 0x1f290, + 0x1f2c0, 0x1f2c0, + 0x1f2e0, 0x1f2e0, + 0x1f300, 0x1f384, + 0x1f3c0, 0x1f3c8, + 0x1f408, 0x1f40c, + 0x1f440, 0x1f44c, + 0x1f684, 0x1f690, + 0x1f6c0, 0x1f6c0, + 0x1f6e0, 0x1f6e0, + 0x1f700, 0x1f784, + 0x1f7c0, 0x1f7c8, + 0x1f808, 0x1f80c, + 0x1f840, 0x1f84c, + 0x1fa84, 0x1fa90, + 0x1fac0, 0x1fac0, + 0x1fae0, 0x1fae0, + 0x1fb00, 0x1fb84, + 0x1fbc0, 0x1fbc8, + 0x1fc08, 0x1fc0c, + 0x1fc40, 0x1fc4c, + 0x1fe84, 0x1fe90, + 0x1fec0, 0x1fec0, + 0x1fee0, 0x1fee0, + 0x1ff00, 0x1ff84, + 0x1ffc0, 0x1ffc8, + 0x30000, 0x30040, + 0x30100, 0x30144, + 0x30190, 0x301d0, + 0x30200, 0x30318, + 0x30400, 0x3052c, + 0x30540, 0x3061c, + 0x30800, 0x30834, + 0x308c0, 0x30908, + 0x30910, 0x309ac, + 0x30a00, 0x30a04, + 0x30a0c, 0x30a2c, + 0x30a44, 0x30a50, + 0x30a74, 0x30c24, + 0x30d08, 0x30d14, + 0x30d1c, 0x30d20, + 0x30d3c, 0x30d50, + 0x31200, 0x3120c, + 0x31220, 0x31220, + 0x31240, 0x31240, + 0x31600, 0x31600, + 0x31608, 0x3160c, + 0x31a00, 0x31a1c, + 0x31e04, 0x31e20, + 0x31e38, 0x31e3c, + 0x31e80, 0x31e80, + 0x31e88, 0x31ea8, + 0x31eb0, 0x31eb4, + 0x31ec8, 0x31ed4, + 0x31fb8, 0x32004, + 0x32208, 0x3223c, + 0x32248, 0x3227c, + 0x32288, 0x322bc, + 0x322c8, 0x322fc, + 0x32600, 0x32630, + 0x32a00, 0x32abc, + 0x32b00, 0x32b70, + 0x33000, 0x33048, + 0x33060, 0x3309c, + 0x330f0, 0x33148, + 0x33160, 0x3319c, + 0x331f0, 0x332e4, + 0x332f8, 0x333e4, + 0x333f8, 0x33448, + 0x33460, 0x3349c, + 0x334f0, 0x33548, + 0x33560, 0x3359c, + 0x335f0, 0x336e4, + 0x336f8, 0x337e4, + 0x337f8, 0x337fc, + 0x33814, 0x33814, + 0x3382c, 0x3382c, + 0x33880, 0x3388c, + 0x338e8, 0x338ec, + 0x33900, 0x33948, + 0x33960, 0x3399c, + 0x339f0, 0x33ae4, + 0x33af8, 0x33b10, + 0x33b28, 0x33b28, + 0x33b3c, 0x33b50, + 0x33bf0, 0x33c10, + 0x33c28, 0x33c28, + 0x33c3c, 0x33c50, + 0x33cf0, 0x33cfc, + 0x34000, 0x34040, + 0x34100, 0x34144, + 0x34190, 0x341d0, + 0x34200, 0x34318, + 0x34400, 0x3452c, + 0x34540, 0x3461c, + 0x34800, 0x34834, + 0x348c0, 0x34908, + 0x34910, 0x349ac, + 0x34a00, 0x34a04, + 0x34a0c, 0x34a2c, + 0x34a44, 0x34a50, + 0x34a74, 0x34c24, + 0x34d08, 0x34d14, + 0x34d1c, 0x34d20, + 0x34d3c, 0x34d50, + 0x35200, 0x3520c, + 0x35220, 0x35220, + 0x35240, 0x35240, + 0x35600, 0x35600, + 0x35608, 0x3560c, + 0x35a00, 0x35a1c, + 0x35e04, 0x35e20, + 0x35e38, 0x35e3c, + 0x35e80, 0x35e80, + 0x35e88, 0x35ea8, + 0x35eb0, 0x35eb4, + 0x35ec8, 0x35ed4, + 0x35fb8, 0x36004, + 0x36208, 0x3623c, + 0x36248, 0x3627c, + 0x36288, 0x362bc, + 0x362c8, 0x362fc, + 0x36600, 0x36630, + 0x36a00, 0x36abc, + 0x36b00, 0x36b70, + 0x37000, 0x37048, + 0x37060, 0x3709c, + 0x370f0, 0x37148, + 0x37160, 0x3719c, + 0x371f0, 0x372e4, + 0x372f8, 0x373e4, + 0x373f8, 0x37448, + 0x37460, 0x3749c, + 0x374f0, 0x37548, + 0x37560, 0x3759c, + 0x375f0, 0x376e4, + 0x376f8, 0x377e4, + 0x377f8, 0x377fc, + 0x37814, 0x37814, + 0x3782c, 0x3782c, + 0x37880, 0x3788c, + 0x378e8, 0x378ec, + 0x37900, 0x37948, + 0x37960, 0x3799c, + 0x379f0, 0x37ae4, + 0x37af8, 0x37b10, + 0x37b28, 0x37b28, + 0x37b3c, 0x37b50, + 0x37bf0, 0x37c10, + 0x37c28, 0x37c28, + 0x37c3c, 0x37c50, + 0x37cf0, 0x37cfc, + 0x38000, 0x38040, + 0x38100, 0x38144, + 0x38190, 0x381d0, + 0x38200, 0x38318, + 0x38400, 0x3852c, + 0x38540, 0x3861c, + 0x38800, 0x38834, + 0x388c0, 0x38908, + 0x38910, 0x389ac, + 0x38a00, 0x38a04, + 0x38a0c, 0x38a2c, + 0x38a44, 0x38a50, + 0x38a74, 0x38c24, + 0x38d08, 0x38d14, + 0x38d1c, 0x38d20, + 0x38d3c, 0x38d50, + 0x39200, 0x3920c, + 0x39220, 0x39220, + 0x39240, 0x39240, + 0x39600, 0x39600, + 0x39608, 0x3960c, + 0x39a00, 0x39a1c, + 0x39e04, 0x39e20, + 0x39e38, 0x39e3c, + 0x39e80, 0x39e80, + 0x39e88, 0x39ea8, + 0x39eb0, 0x39eb4, + 0x39ec8, 0x39ed4, + 0x39fb8, 0x3a004, + 0x3a208, 0x3a23c, + 0x3a248, 0x3a27c, + 0x3a288, 0x3a2bc, + 0x3a2c8, 0x3a2fc, + 0x3a600, 0x3a630, + 0x3aa00, 0x3aabc, + 0x3ab00, 0x3ab70, + 0x3b000, 0x3b048, + 0x3b060, 0x3b09c, + 0x3b0f0, 0x3b148, + 0x3b160, 0x3b19c, + 0x3b1f0, 0x3b2e4, + 0x3b2f8, 0x3b3e4, + 0x3b3f8, 0x3b448, + 0x3b460, 0x3b49c, + 0x3b4f0, 0x3b548, + 0x3b560, 0x3b59c, + 0x3b5f0, 0x3b6e4, + 0x3b6f8, 0x3b7e4, + 0x3b7f8, 0x3b7fc, + 0x3b814, 0x3b814, + 0x3b82c, 0x3b82c, + 0x3b880, 0x3b88c, + 0x3b8e8, 0x3b8ec, + 0x3b900, 0x3b948, + 0x3b960, 0x3b99c, + 0x3b9f0, 0x3bae4, + 0x3baf8, 0x3bb10, + 0x3bb28, 0x3bb28, + 0x3bb3c, 0x3bb50, + 0x3bbf0, 0x3bc10, + 0x3bc28, 0x3bc28, + 0x3bc3c, 0x3bc50, + 0x3bcf0, 0x3bcfc, + 0x3c000, 0x3c040, + 0x3c100, 0x3c144, + 0x3c190, 0x3c1d0, + 0x3c200, 0x3c318, + 0x3c400, 0x3c52c, + 0x3c540, 0x3c61c, + 0x3c800, 0x3c834, + 0x3c8c0, 0x3c908, + 0x3c910, 0x3c9ac, + 0x3ca00, 0x3ca04, + 0x3ca0c, 0x3ca2c, + 0x3ca44, 0x3ca50, + 0x3ca74, 0x3cc24, + 0x3cd08, 0x3cd14, + 0x3cd1c, 0x3cd20, + 0x3cd3c, 0x3cd50, + 0x3d200, 0x3d20c, + 0x3d220, 0x3d220, + 0x3d240, 0x3d240, + 0x3d600, 0x3d600, + 0x3d608, 0x3d60c, + 0x3da00, 0x3da1c, + 0x3de04, 0x3de20, + 0x3de38, 0x3de3c, + 0x3de80, 0x3de80, + 0x3de88, 0x3dea8, + 0x3deb0, 0x3deb4, + 0x3dec8, 0x3ded4, + 0x3dfb8, 0x3e004, + 0x3e208, 0x3e23c, + 0x3e248, 0x3e27c, + 0x3e288, 0x3e2bc, + 0x3e2c8, 0x3e2fc, + 0x3e600, 0x3e630, + 0x3ea00, 0x3eabc, + 0x3eb00, 0x3eb70, + 0x3f000, 0x3f048, + 0x3f060, 0x3f09c, + 0x3f0f0, 0x3f148, + 0x3f160, 0x3f19c, + 0x3f1f0, 0x3f2e4, + 0x3f2f8, 0x3f3e4, + 0x3f3f8, 0x3f448, + 0x3f460, 0x3f49c, + 0x3f4f0, 0x3f548, + 0x3f560, 0x3f59c, + 0x3f5f0, 0x3f6e4, + 0x3f6f8, 0x3f7e4, + 0x3f7f8, 0x3f7fc, + 0x3f814, 0x3f814, + 0x3f82c, 0x3f82c, + 0x3f880, 0x3f88c, + 0x3f8e8, 0x3f8ec, + 0x3f900, 0x3f948, + 0x3f960, 0x3f99c, + 0x3f9f0, 0x3fae4, + 0x3faf8, 0x3fb10, + 0x3fb28, 0x3fb28, + 0x3fb3c, 0x3fb50, + 0x3fbf0, 0x3fc10, + 0x3fc28, 0x3fc28, + 0x3fc3c, 0x3fc50, + 0x3fcf0, 0x3fcfc, + 0x40000, 0x4000c, + 0x40040, 0x40068, + 0x4007c, 0x40144, + 0x40180, 0x4018c, + 0x40200, 0x40298, + 0x402ac, 0x4033c, + 0x403f8, 0x403fc, + 0x41300, 0x413c4, + 0x41400, 0x4141c, + 0x41480, 0x414d0, + 0x44000, 0x44078, + 0x440c0, 0x44278, + 0x442c0, 0x44478, + 0x444c0, 0x44678, + 0x446c0, 0x44878, + 0x448c0, 0x449fc, + 0x45000, 0x45068, + 0x45080, 0x45084, + 0x450a0, 0x450b0, + 0x45200, 0x45268, + 0x45280, 0x45284, + 0x452a0, 0x452b0, + 0x460c0, 0x460e4, + 0x47000, 0x4708c, + 0x47200, 0x47250, + 0x47400, 0x47420, + 0x47600, 0x47618, + 0x47800, 0x47814, + 0x48000, 0x4800c, + 0x48040, 0x48068, + 0x4807c, 0x48144, + 0x48180, 0x4818c, + 0x48200, 0x48298, + 0x482ac, 0x4833c, + 0x483f8, 0x483fc, + 0x49300, 0x493c4, + 0x49400, 0x4941c, + 0x49480, 0x494d0, + 0x4c000, 0x4c078, + 0x4c0c0, 0x4c278, + 0x4c2c0, 0x4c478, + 0x4c4c0, 0x4c678, + 0x4c6c0, 0x4c878, + 0x4c8c0, 0x4c9fc, + 0x4d000, 0x4d068, + 0x4d080, 0x4d084, + 0x4d0a0, 0x4d0b0, + 0x4d200, 0x4d268, + 0x4d280, 0x4d284, + 0x4d2a0, 0x4d2b0, + 0x4e0c0, 0x4e0e4, + 0x4f000, 0x4f08c, + 0x4f200, 0x4f250, + 0x4f400, 0x4f420, + 0x4f600, 0x4f618, + 0x4f800, 0x4f814, + 0x50000, 0x500cc, + 0x50400, 0x50400, + 0x50800, 0x508cc, + 0x50c00, 0x50c00, + 0x51000, 0x5101c, + 0x51300, 0x51308, + }; - regs->version = 4 | (sc->params.rev << 10); - for (i = 0; i < nitems(reg_ranges); i += 2) + if (is_t4(sc)) { + reg_ranges = &t4_reg_ranges[0]; + n = nitems(t4_reg_ranges); + } else { + reg_ranges = &t5_reg_ranges[0]; + n = nitems(t5_reg_ranges); + } + + regs->version = chip_id(sc) | chip_rev(sc) << 10; + for (i = 0; i < n; i += 2) reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); } @@ -3190,6 +4029,7 @@ t4_sysctls(struct adapter *sc) "\5INITIATOR_SSNOFLD\6TARGET_SSNOFLD", "\20\1INITIATOR\2TARGET\3CTRL_OFLD" /* caps[5] fcoecaps */ }; + static char *doorbells = {"\20\1UDB\2WRWC\3UDBWC\4KDB"}; ctx = device_get_sysctl_ctx(sc->dev); @@ -3199,11 +4039,11 @@ t4_sysctls(struct adapter *sc) oid = device_get_sysctl_tree(sc->dev); c0 = children = SYSCTL_CHILDREN(oid); - SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, - &sc->params.nports, 0, "# of ports"); + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, + sc->params.nports, "# of ports"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, - &sc->params.rev, 0, "chip hardware revision"); + NULL, chip_rev(sc), "chip hardware revision"); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); @@ -3211,8 +4051,12 @@ t4_sysctls(struct adapter *sc) SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", CTLFLAG_RD, &sc->cfg_file, 0, "configuration file"); - SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, - &sc->cfcsum, 0, "config file checksum"); + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, + sc->cfcsum, "config file checksum"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", + CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, + sysctl_bitfield, "A", "available doorbells"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkcaps", CTLTYPE_STRING | CTLFLAG_RD, caps[0], sc->linkcaps, @@ -3238,8 +4082,8 @@ t4_sysctls(struct adapter *sc) CTLTYPE_STRING | CTLFLAG_RD, caps[5], sc->fcoecaps, sysctl_bitfield, "A", "available FCoE capabilities"); - SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, - &sc->params.vpd.cclk, 0, "core clock frequency (in KHz)"); + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, + sc->params.vpd.cclk, "core clock frequency (in KHz)"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", CTLTYPE_STRING | CTLFLAG_RD, sc->sge.timer_val, @@ -3316,6 +4160,16 @@ t4_sysctls(struct adapter *sc) CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); + if (is_t5(sc)) { + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", + CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", + CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); + } + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_qcfg, "A", "CIM queue configuration"); @@ -3379,6 +4233,12 @@ t4_sysctls(struct adapter *sc) SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tx_rate, "A", "Tx rate"); + + if (is_t5(sc)) { + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wrwc_stats", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_wrwc_stats, "A", "work request (WC) statistics"); + } #endif #ifdef TCP_OFFLOAD @@ -3843,9 +4703,10 @@ sysctl_cctrl(SYSCTL_HANDLER_ARGS) return (rc); } -static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ] = { +static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ - "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI" /* obq's */ + "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ + "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ }; static int @@ -3856,8 +4717,9 @@ sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) int rc, i, n, qid = arg2; uint32_t *buf, *p; char *qtype; + u_int cim_num_obq = is_t4(sc) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; - KASSERT(qid >= 0 && qid < nitems(qname), + KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, ("%s: bad qid %d\n", __func__, qid)); if (qid < CIM_NUM_IBQ) { @@ -3870,7 +4732,7 @@ sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) /* outbound queue */ qtype = "OBQ"; qid -= CIM_NUM_IBQ; - n = 4 * 6 * CIM_OBQ_SIZE; + n = 4 * cim_num_obq * CIM_OBQ_SIZE; buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); rc = t4_read_cim_obq(sc, qid, buf, n); } @@ -3885,7 +4747,7 @@ sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) if (rc != 0) goto done; - sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); if (sb == NULL) { rc = ENOMEM; goto done; @@ -3971,16 +4833,27 @@ sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) struct adapter *sc = arg1; struct sbuf *sb; int rc, i; - uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ]; - uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ]; + uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; + uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; uint16_t thres[CIM_NUM_IBQ]; - uint32_t obq_wr[2 * CIM_NUM_OBQ], *wr = obq_wr; - uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ)], *p = stat; + uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; + uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; + u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; - rc = -t4_cim_read(sc, A_UP_IBQ_0_RDADDR, nitems(stat), stat); + if (is_t4(sc)) { + cim_num_obq = CIM_NUM_OBQ; + ibq_rdaddr = A_UP_IBQ_0_RDADDR; + obq_rdaddr = A_UP_OBQ_0_REALADDR; + } else { + cim_num_obq = CIM_NUM_OBQ_T5; + ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; + obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; + } + nq = CIM_NUM_IBQ + cim_num_obq; + + rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); if (rc == 0) - rc = -t4_cim_read(sc, A_UP_OBQ_0_REALADDR, nitems(obq_wr), - obq_wr); + rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); if (rc != 0) return (rc); @@ -3990,19 +4863,19 @@ sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) if (rc != 0) return (rc); - sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); if (sb == NULL) return (ENOMEM); sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) - sbuf_printf(sb, "\n%5s %5x %5u %4u %6x %4x %4u %4u %5u", + sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16); - for ( ; i < CIM_NUM_IBQ + CIM_NUM_OBQ; i++, p += 4, wr += 2) - sbuf_printf(sb, "\n%5s %5x %5u %11x %4x %4u %4u %5u", qname[i], + for ( ; i < nq; i++, p += 4, wr += 2) + sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16); @@ -4117,8 +4990,11 @@ sysctl_devlog(SYSCTL_HANDLER_ARGS) struct sbuf *sb; uint64_t ftstamp = UINT64_MAX; - if (dparams->start == 0) - return (ENXIO); + if (dparams->start == 0) { + dparams->memtype = 0; + dparams->start = 0x84000; + dparams->size = 32768; + } nentries = dparams->size / sizeof(struct fw_devlog_e); @@ -4359,17 +5235,18 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) struct adapter *sc = arg1; struct sbuf *sb; int rc, i, n; - uint32_t lo, hi; - static const char *memory[] = { "EDC0:", "EDC1:", "MC:" }; + uint32_t lo, hi, used, alloc; + static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; static const char *region[] = { "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", "TDDP region:", "TPT region:", "STAG region:", "RQ region:", - "RQUDP region:", "PBL region:", "TXPBL region:", "ULPRX state:", - "ULPTX state:", "On-chip queues:" + "RQUDP region:", "PBL region:", "TXPBL region:", + "DBVFIFO region:", "ULPRX state:", "ULPTX state:", + "On-chip queues:" }; - struct mem_desc avail[3]; + struct mem_desc avail[4]; struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ struct mem_desc *md = mem; @@ -4406,8 +5283,17 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) if (lo & F_EXT_MEM_ENABLE) { hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); avail[i].base = G_EXT_MEM_BASE(hi) << 20; - avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); - avail[i].idx = 2; + avail[i].limit = avail[i].base + + (G_EXT_MEM_SIZE(hi) << 20); + avail[i].idx = is_t4(sc) ? 2 : 3; /* Call it MC for T4 */ + i++; + } + if (!is_t4(sc) && lo & F_EXT_MEM1_ENABLE) { + hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + avail[i].base = G_EXT_MEM1_BASE(hi) << 20; + avail[i].limit = avail[i].base + + (G_EXT_MEM1_SIZE(hi) << 20); + avail[i].idx = 4; i++; } if (!i) /* no memory available */ @@ -4461,6 +5347,15 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) ulp_region(TX_PBL); #undef ulp_region + md->base = 0; + md->idx = nitems(region); + if (!is_t4(sc) && t4_read_reg(sc, A_SGE_CONTROL2) & F_VFIFO_ENABLE) { + md->base = G_BASEADDR(t4_read_reg(sc, A_SGE_DBVFIFO_BADDR)); + md->limit = md->base + (G_DBVFIFO_SIZE((t4_read_reg(sc, + A_SGE_DBVFIFO_SIZE))) << 2) - 1; + } + md++; + md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); md->limit = md->base + sc->tids.ntids - 1; md++; @@ -4525,14 +5420,28 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) for (i = 0; i < 4; i++) { lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); + if (is_t4(sc)) { + used = G_USED(lo); + alloc = G_ALLOC(lo); + } else { + used = G_T5_USED(lo); + alloc = G_T5_ALLOC(lo); + } sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", - i, G_USED(lo), G_ALLOC(lo)); + i, used, alloc); } for (i = 0; i < 4; i++) { lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); + if (is_t4(sc)) { + used = G_USED(lo); + alloc = G_ALLOC(lo); + } else { + used = G_T5_USED(lo); + alloc = G_T5_ALLOC(lo); + } sbuf_printf(sb, "\nLoopback %d using %u pages out of %u allocated", - i, G_USED(lo), G_ALLOC(lo)); + i, used, alloc); } rc = sbuf_finish(sb); @@ -4807,6 +5716,39 @@ sysctl_tx_rate(SYSCTL_HANDLER_ARGS) return (rc); } + +static int +sysctl_wrwc_stats(SYSCTL_HANDLER_ARGS) +{ + struct adapter *sc = arg1; + struct sbuf *sb; + int rc, v; + + rc = sysctl_wire_old_buffer(req, 0); + if (rc != 0) + return (rc); + + sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + if (sb == NULL) + return (ENOMEM); + + v = t4_read_reg(sc, A_SGE_STAT_CFG); + if (G_STATSOURCE_T5(v) == 7) { + if (G_STATMODE(v) == 0) { + sbuf_printf(sb, "\ntotal %d, incomplete %d", + t4_read_reg(sc, A_SGE_STAT_TOTAL), + t4_read_reg(sc, A_SGE_STAT_MATCH)); + } else if (G_STATMODE(v) == 1) { + sbuf_printf(sb, "\ntotal %d, data overflow %d", + t4_read_reg(sc, A_SGE_STAT_TOTAL), + t4_read_reg(sc, A_SGE_STAT_MATCH)); + } + } + rc = sbuf_finish(sb); + sbuf_delete(sb); + + return (rc); +} #endif static inline void @@ -5061,13 +6003,13 @@ done: static inline uint64_t get_filter_hits(struct adapter *sc, uint32_t fid) { - uint32_t tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); + uint32_t mw_base, off, tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); uint64_t hits; - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 0), + memwin_info(sc, 0, &mw_base, NULL); + off = position_memwin(sc, 0, tcb_base + (fid + sc->tids.ftid_base) * TCB_SIZE); - t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 0)); - hits = t4_read_reg64(sc, MEMWIN0_BASE + 16); + hits = t4_read_reg64(sc, mw_base + off + 16); return (be64toh(hits)); } @@ -5533,80 +6475,43 @@ done: } static int -read_card_mem(struct adapter *sc, struct t4_mem_range *mr) +read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) { - uint32_t base, size, lo, hi, win, off, remaining, i, n; + uint32_t addr, off, remaining, i, n; uint32_t *buf, *b; + uint32_t mw_base, mw_aperture; int rc; + uint8_t *dst; - /* reads are in multiples of 32 bits */ - if (mr->addr & 3 || mr->len & 3 || mr->len == 0) - return (EINVAL); + rc = validate_mem_range(sc, mr->addr, mr->len); + if (rc != 0) + return (rc); - /* - * We don't want to deal with potential holes so we mandate that the - * requested region must lie entirely within one of the 3 memories. - */ - lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); - if (lo & F_EDRAM0_ENABLE) { - hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); - base = G_EDRAM0_BASE(hi) << 20; - size = G_EDRAM0_SIZE(hi) << 20; - if (size > 0 && - mr->addr >= base && mr->addr < base + size && - mr->addr + mr->len <= base + size) - goto proceed; - } - if (lo & F_EDRAM1_ENABLE) { - hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); - base = G_EDRAM1_BASE(hi) << 20; - size = G_EDRAM1_SIZE(hi) << 20; - if (size > 0 && - mr->addr >= base && mr->addr < base + size && - mr->addr + mr->len <= base + size) - goto proceed; - } - if (lo & F_EXT_MEM_ENABLE) { - hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); - base = G_EXT_MEM_BASE(hi) << 20; - size = G_EXT_MEM_SIZE(hi) << 20; - if (size > 0 && - mr->addr >= base && mr->addr < base + size && - mr->addr + mr->len <= base + size) - goto proceed; - } - return (ENXIO); - -proceed: - buf = b = malloc(mr->len, M_CXGBE, M_WAITOK); - - /* - * Position the PCIe window (we use memwin2) to the 16B aligned area - * just at/before the requested region. - */ - win = mr->addr & ~0xf; - off = mr->addr - win; /* offset of the requested region in the win */ + memwin_info(sc, win, &mw_base, &mw_aperture); + buf = b = malloc(min(mr->len, mw_aperture), M_CXGBE, M_WAITOK); + addr = mr->addr; remaining = mr->len; + dst = (void *)mr->data; while (remaining) { - t4_write_reg(sc, - PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win); - t4_read_reg(sc, - PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2)); + off = position_memwin(sc, win, addr); /* number of bytes that we'll copy in the inner loop */ - n = min(remaining, MEMWIN2_APERTURE - off); + n = min(remaining, mw_aperture - off); + for (i = 0; i < n; i += 4) + *b++ = t4_read_reg(sc, mw_base + off + i); - for (i = 0; i < n; i += 4, remaining -= 4) - *b++ = t4_read_reg(sc, MEMWIN2_BASE + off + i); + rc = copyout(buf, dst, n); + if (rc != 0) + break; - win += MEMWIN2_APERTURE; - off = 0; + b = buf; + dst += n; + remaining -= n; + addr += n; } - rc = copyout(buf, mr->data, mr->len); free(buf, M_CXGBE); - return (rc); } @@ -5776,7 +6681,7 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, } case CHELSIO_T4_REGDUMP: { struct t4_regdump *regs = (struct t4_regdump *)data; - int reglen = T4_REGDUMP_SIZE; + int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE; uint8_t *buf; if (regs->len < reglen) { @@ -5813,7 +6718,7 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, rc = load_fw(sc, (struct t4_data *)data); break; case CHELSIO_T4_GET_MEM: - rc = read_card_mem(sc, (struct t4_mem_range *)data); + rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); break; case CHELSIO_T4_GET_I2C: rc = read_i2c(sc, (struct t4_i2c_data *)data); @@ -6133,11 +7038,17 @@ t4_mod_event(module_t mod, int cmd, void *arg) return (rc); } -static devclass_t t4_devclass; -static devclass_t cxgbe_devclass; +static devclass_t t4_devclass, t5_devclass; +static devclass_t cxgbe_devclass, cxl_devclass; DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, t4_mod_event, 0); MODULE_VERSION(t4nex, 1); +DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, 0, 0); +MODULE_VERSION(t5nex, 1); + DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); MODULE_VERSION(cxgbe, 1); + +DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); +MODULE_VERSION(cxl, 1); diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c index 578f06f7f8c..c25b88a9927 100644 --- a/sys/dev/cxgbe/t4_sge.c +++ b/sys/dev/cxgbe/t4_sge.c @@ -68,6 +68,12 @@ static struct fl_buf_info fl_buf_info[FL_BUF_SIZES]; #define FL_BUF_TYPE(x) (fl_buf_info[x].type) #define FL_BUF_ZONE(x) (fl_buf_info[x].zone) +#ifdef T4_PKT_TIMESTAMP +#define RX_COPY_THRESHOLD (MINCLSIZE - 8) +#else +#define RX_COPY_THRESHOLD MINCLSIZE +#endif + /* * Ethernet frames are DMA'd at this byte offset into the freelist buffer. * 0-7 are valid values. @@ -262,29 +268,38 @@ t4_sge_modload(void) } } -/** - * t4_sge_init - initialize SGE - * @sc: the adapter - * - * Performs SGE initialization needed every time after a chip reset. - * We do not initialize any of the queues here, instead the driver - * top-level must request them individually. - */ -int -t4_sge_init(struct adapter *sc) +void +t4_init_sge_cpl_handlers(struct adapter *sc) { - struct sge *s = &sc->sge; - int i, rc = 0; - uint32_t ctrl_mask, ctrl_val, hpsize, v; - ctrl_mask = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | - V_INGPADBOUNDARY(M_INGPADBOUNDARY) | - F_EGRSTATUSPAGESIZE; - ctrl_val = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | + t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); + t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); + t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); + t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); + + t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); +} + +void +t4_tweak_chip_settings(struct adapter *sc) +{ + int i; + uint32_t v, m; + int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; + int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ + uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); + + KASSERT(sc->flags & MASTER_PF, + ("%s: trying to change chip settings when not master.", __func__)); + + m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | + V_INGPADBOUNDARY(M_INGPADBOUNDARY) | F_EGRSTATUSPAGESIZE; + v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | V_INGPADBOUNDARY(ilog2(fl_pad) - 5) | V_EGRSTATUSPAGESIZE(spg_len == 128); + t4_set_reg_field(sc, A_SGE_CONTROL, m, v); - hpsize = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | + v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | @@ -292,50 +307,80 @@ t4_sge_init(struct adapter *sc) V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); + t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); - if (sc->flags & MASTER_PF) { - int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; - int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ - - t4_set_reg_field(sc, A_SGE_CONTROL, ctrl_mask, ctrl_val); - t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, hpsize); - for (i = 0; i < FL_BUF_SIZES; i++) { - t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), - FL_BUF_SIZE(i)); - } - - t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, - V_THRESHOLD_0(intr_pktcount[0]) | - V_THRESHOLD_1(intr_pktcount[1]) | - V_THRESHOLD_2(intr_pktcount[2]) | - V_THRESHOLD_3(intr_pktcount[3])); - - t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, - V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | - V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]))); - t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, - V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | - V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]))); - t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, - V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | - V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]))); - - if (cong_drop == 0) { - t4_set_reg_field(sc, A_TP_PARA_REG3, F_TUNNELCNGDROP0 | - F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | - F_TUNNELCNGDROP3, 0); - } + for (i = 0; i < FL_BUF_SIZES; i++) { + t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), + FL_BUF_SIZE(i)); } - v = t4_read_reg(sc, A_SGE_CONTROL); - if ((v & ctrl_mask) != ctrl_val) { - device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", v); + v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | + V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); + t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); + + /* adap->params.vpd.cclk must be set up before this */ + v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | + V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); + t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); + v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | + V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); + t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); + v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | + V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); + t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); + + if (cong_drop == 0) { + m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | + F_TUNNELCNGDROP3; + t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); + } + + /* 4K, 16K, 64K, 256K DDP "page sizes" */ + v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); + t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); + + m = v = F_TDDPTAGTCB; + t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); + + m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | + F_RESETDDPOFFSET; + v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; + t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); +} + +/* + * XXX: driver really should be able to deal with unexpected settings. + */ +int +t4_read_chip_settings(struct adapter *sc) +{ + struct sge *s = &sc->sge; + int i, rc = 0; + uint32_t m, v, r; + uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); + + m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | + V_INGPADBOUNDARY(M_INGPADBOUNDARY) | F_EGRSTATUSPAGESIZE; + v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | + V_INGPADBOUNDARY(ilog2(fl_pad) - 5) | + V_EGRSTATUSPAGESIZE(spg_len == 128); + r = t4_read_reg(sc, A_SGE_CONTROL); + if ((r & m) != v) { + device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); rc = EINVAL; } - v = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); - if (v != hpsize) { - device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", v); + v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | + V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); + r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); + if (r != v) { + device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); rc = EINVAL; } @@ -348,31 +393,75 @@ t4_sge_init(struct adapter *sc) } } - v = t4_read_reg(sc, A_SGE_CONM_CTRL); - s->fl_starve_threshold = G_EGRTHRESHOLD(v) * 2 + 1; + r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); + s->counter_val[0] = G_THRESHOLD_0(r); + s->counter_val[1] = G_THRESHOLD_1(r); + s->counter_val[2] = G_THRESHOLD_2(r); + s->counter_val[3] = G_THRESHOLD_3(r); - v = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); - sc->sge.counter_val[0] = G_THRESHOLD_0(v); - sc->sge.counter_val[1] = G_THRESHOLD_1(v); - sc->sge.counter_val[2] = G_THRESHOLD_2(v); - sc->sge.counter_val[3] = G_THRESHOLD_3(v); + r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); + s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); + s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); + r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); + s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); + s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); + r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); + s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); + s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); - v = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); - sc->sge.timer_val[0] = G_TIMERVALUE0(v) / core_ticks_per_usec(sc); - sc->sge.timer_val[1] = G_TIMERVALUE1(v) / core_ticks_per_usec(sc); - v = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); - sc->sge.timer_val[2] = G_TIMERVALUE2(v) / core_ticks_per_usec(sc); - sc->sge.timer_val[3] = G_TIMERVALUE3(v) / core_ticks_per_usec(sc); - v = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); - sc->sge.timer_val[4] = G_TIMERVALUE4(v) / core_ticks_per_usec(sc); - sc->sge.timer_val[5] = G_TIMERVALUE5(v) / core_ticks_per_usec(sc); + if (cong_drop == 0) { + m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | + F_TUNNELCNGDROP3; + r = t4_read_reg(sc, A_TP_PARA_REG3); + if (r & m) { + device_printf(sc->dev, + "invalid TP_PARA_REG3(0x%x)\n", r); + rc = EINVAL; + } + } - t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); - t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); - t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); - t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); + v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); + r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); + if (r != v) { + device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); + rc = EINVAL; + } - t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); + m = v = F_TDDPTAGTCB; + r = t4_read_reg(sc, A_ULP_RX_CTL); + if ((r & m) != v) { + device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); + rc = EINVAL; + } + + m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | + F_RESETDDPOFFSET; + v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; + r = t4_read_reg(sc, A_TP_PARA_REG5); + if ((r & m) != v) { + device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); + rc = EINVAL; + } + + r = t4_read_reg(sc, A_SGE_CONM_CTRL); + s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; + + if (is_t5(sc)) { + r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); + r >>= S_QUEUESPERPAGEPF0 + + (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; + s->s_qpp = r & M_QUEUESPERPAGEPF0; + } + + r = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); + sc->params.tp.tre = G_TIMERRESOLUTION(r); + sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(r); + + t4_read_mtu_tbl(sc, sc->params.mtus, NULL); + t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); + + t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &sc->filter_mode, 1, + A_TP_VLAN_PRI_MAP); return (rc); } @@ -549,7 +638,7 @@ mtu_to_bufsize(int mtu) /* large enough for a frame even when VLAN extraction is disabled */ bufsize = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + mtu; - bufsize = roundup(bufsize + fl_pktshift, fl_pad); + bufsize = roundup2(bufsize + fl_pktshift, fl_pad); return (bufsize); } @@ -1487,7 +1576,7 @@ init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, iq->intr_params |= F_QINTR_CNT_EN; iq->intr_pktc_idx = pktc_idx; } - iq->qsize = roundup(qsize, 16); /* See FW_IQ_CMD/iqsize */ + iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ } @@ -1661,7 +1750,7 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, return (rc); } fl->needed = fl->cap; - fl->lowat = roundup(sc->sge.fl_starve_threshold, 8); + fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8); c.iqns_to_fl0congen |= htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | @@ -2164,6 +2253,7 @@ alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) eq->spg = (void *)&eq->desc[eq->cap]; eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ eq->pidx = eq->cidx = 0; + eq->doorbells = sc->doorbells; switch (eq->flags & EQ_TYPEMASK) { case EQ_CTRL: @@ -2192,6 +2282,25 @@ alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; + if (isset(&eq->doorbells, DOORBELL_UDB) || + isset(&eq->doorbells, DOORBELL_UDBWC) || + isset(&eq->doorbells, DOORBELL_WRWC)) { + uint32_t s_qpp = sc->sge.s_qpp; + uint32_t mask = (1 << s_qpp) - 1; + volatile uint8_t *udb; + + udb = sc->udbs_base + UDBS_DB_OFFSET; + udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ + eq->udb_qid = eq->cntxt_id & mask; /* id in page */ + if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) + clrbit(&eq->doorbells, DOORBELL_WRWC); + else { + udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ + eq->udb_qid = 0; + } + eq->udb = (volatile void *)udb; + } + return (rc); } @@ -2437,6 +2546,7 @@ static inline void ring_fl_db(struct adapter *sc, struct sge_fl *fl) { int ndesc = fl->pending / 8; + uint32_t v; if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) ndesc--; /* hold back one credit */ @@ -2444,10 +2554,13 @@ ring_fl_db(struct adapter *sc, struct sge_fl *fl) if (ndesc <= 0) return; /* nothing to do */ + v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); + if (is_t5(sc)) + v |= F_DBTYPE; + wmb(); - t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), F_DBPRIO | - V_QID(fl->cntxt_id) | V_PIDX(ndesc)); + t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); fl->pending -= ndesc * 8; } @@ -3312,10 +3425,53 @@ copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) static inline void ring_eq_db(struct adapter *sc, struct sge_eq *eq) { - wmb(); - t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), - V_QID(eq->cntxt_id) | V_PIDX(eq->pending)); + u_int db, pending; + + db = eq->doorbells; + pending = eq->pending; + if (pending > 1) + clrbit(&db, DOORBELL_WRWC); eq->pending = 0; + wmb(); + + switch (ffs(db) - 1) { + case DOORBELL_UDB: + *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); + return; + + case DOORBELL_WRWC: { + volatile uint64_t *dst, *src; + int i; + + /* + * Queues whose 128B doorbell segment fits in the page do not + * use relative qid (udb_qid is always 0). Only queues with + * doorbell segments can do WRWC. + */ + KASSERT(eq->udb_qid == 0 && pending == 1, + ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", + __func__, eq->doorbells, pending, eq->pidx, eq)); + + dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - + UDBS_DB_OFFSET); + i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; + src = (void *)&eq->desc[i]; + while (src != (void *)&eq->desc[i + 1]) + *dst++ = *src++; + wmb(); + return; + } + + case DOORBELL_UDBWC: + *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); + wmb(); + return; + + case DOORBELL_KDB: + t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), + V_QID(eq->cntxt_id) | V_PIDX(pending)); + return; + } } static inline int diff --git a/sys/dev/cxgbe/tom/t4_connect.c b/sys/dev/cxgbe/tom/t4_connect.c index 17ed1d336e9..9d755531f70 100644 --- a/sys/dev/cxgbe/tom/t4_connect.c +++ b/sys/dev/cxgbe/tom/t4_connect.c @@ -241,8 +241,11 @@ calc_opt2a(struct socket *so, struct toepcb *toep) opt2 |= F_CCTRL_ECN; opt2 |= V_TX_QUEUE(sc->params.tp.tx_modq[pi->tx_chan]); - opt2 |= F_RX_COALESCE_VALID | V_RX_COALESCE(M_RX_COALESCE); opt2 |= F_RSS_QUEUE_VALID | V_RSS_QUEUE(toep->ofld_rxq->iq.abs_id); + if (is_t4(sc)) + opt2 |= F_RX_COALESCE_VALID | V_RX_COALESCE(M_RX_COALESCE); + else + opt2 |= F_T5_OPT_2_VALID | V_RX_COALESCE(M_RX_COALESCE); #ifdef USE_DDP_RX_FLOW_CONTROL if (toep->ulp_mode == ULP_MODE_TCPDDP) @@ -266,6 +269,24 @@ t4_init_connect_cpl_handlers(struct adapter *sc) goto failed; \ } while (0) +static inline int +act_open_cpl_size(struct adapter *sc, int isipv6) +{ + static const int sz_t4[] = { + sizeof (struct cpl_act_open_req), + sizeof (struct cpl_act_open_req6) + }; + static const int sz_t5[] = { + sizeof (struct cpl_t5_act_open_req), + sizeof (struct cpl_t5_act_open_req6) + }; + + if (is_t4(sc)) + return (sz_t4[!!isipv6]); + else + return (sz_t5[!!isipv6]); +} + /* * active open (soconnect). * @@ -320,8 +341,7 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt, DONT_OFFLOAD_ACTIVE_OPEN(ENOMEM); isipv6 = nam->sa_family == AF_INET6; - wr = alloc_wrqe(isipv6 ? sizeof(struct cpl_act_open_req6) : - sizeof(struct cpl_act_open_req), toep->ctrlq); + wr = alloc_wrqe(act_open_cpl_size(sc, isipv6), toep->ctrlq); if (wr == NULL) DONT_OFFLOAD_ACTIVE_OPEN(ENOMEM); @@ -373,8 +393,17 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt, cpl->peer_ip_lo = *(uint64_t *)&inp->in6p_faddr.s6_addr[8]; cpl->opt0 = calc_opt0(so, pi, toep->l2te, mtu_idx, rscale, toep->rx_credits, toep->ulp_mode); - cpl->params = select_ntuple(pi, toep->l2te, sc->filter_mode); cpl->opt2 = calc_opt2a(so, toep); + if (is_t4(sc)) { + cpl->params = select_ntuple(pi, toep->l2te, + sc->filter_mode); + } else { + struct cpl_t5_act_open_req6 *c5 = (void *)cpl; + + c5->rsvd = 0; + c5->params = select_ntuple(pi, toep->l2te, + sc->filter_mode); + } } else { struct cpl_act_open_req *cpl = wrtod(wr); @@ -385,8 +414,17 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt, &cpl->peer_ip, &cpl->peer_port); cpl->opt0 = calc_opt0(so, pi, toep->l2te, mtu_idx, rscale, toep->rx_credits, toep->ulp_mode); - cpl->params = select_ntuple(pi, toep->l2te, sc->filter_mode); cpl->opt2 = calc_opt2a(so, toep); + if (is_t4(sc)) { + cpl->params = select_ntuple(pi, toep->l2te, + sc->filter_mode); + } else { + struct cpl_t5_act_open_req6 *c5 = (void *)cpl; + + c5->rsvd = 0; + c5->params = select_ntuple(pi, toep->l2te, + sc->filter_mode); + } } CTR5(KTR_CXGBE, "%s: atid %u (%s), toep %p, inp %p", __func__, diff --git a/sys/dev/cxgbe/tom/t4_cpl_io.c b/sys/dev/cxgbe/tom/t4_cpl_io.c index 9aead9f8719..5f3861e8a13 100644 --- a/sys/dev/cxgbe/tom/t4_cpl_io.c +++ b/sys/dev/cxgbe/tom/t4_cpl_io.c @@ -88,7 +88,7 @@ send_flowc_wr(struct toepcb *toep, struct flowc_tx_params *ftxp) flowclen = sizeof(*flowc) + nparams * sizeof(struct fw_flowc_mnemval); - wr = alloc_wrqe(roundup(flowclen, 16), toep->ofld_txq); + wr = alloc_wrqe(roundup2(flowclen, 16), toep->ofld_txq); if (wr == NULL) { /* XXX */ panic("%s: allocation failure.", __func__); @@ -632,7 +632,7 @@ unlocked: /* Immediate data tx */ - wr = alloc_wrqe(roundup(sizeof(*txwr) + plen, 16), + wr = alloc_wrqe(roundup2(sizeof(*txwr) + plen, 16), toep->ofld_txq); if (wr == NULL) { /* XXX: how will we recover from this? */ @@ -651,7 +651,7 @@ unlocked: wr_len = sizeof(*txwr) + sizeof(struct ulptx_sgl) + ((3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1)) * 8; - wr = alloc_wrqe(roundup(wr_len, 16), toep->ofld_txq); + wr = alloc_wrqe(roundup2(wr_len, 16), toep->ofld_txq); if (wr == NULL) { /* XXX: how will we recover from this? */ toep->flags |= TPF_TX_SUSPENDED; diff --git a/sys/dev/cxgbe/tom/t4_ddp.c b/sys/dev/cxgbe/tom/t4_ddp.c index 16eb707c70c..f07dfb6c9c8 100644 --- a/sys/dev/cxgbe/tom/t4_ddp.c +++ b/sys/dev/cxgbe/tom/t4_ddp.c @@ -358,8 +358,8 @@ mk_update_tcb_for_ddp(struct adapter *sc, struct toepcb *toep, int db_idx, * The ULPTX master commands that follow must all end at 16B boundaries * too so we round up the size to 16. */ - len = sizeof(*wrh) + 3 * roundup(LEN__SET_TCB_FIELD_ULP, 16) + - roundup(LEN__RX_DATA_ACK_ULP, 16); + len = sizeof(*wrh) + 3 * roundup2(LEN__SET_TCB_FIELD_ULP, 16) + + roundup2(LEN__RX_DATA_ACK_ULP, 16); wr = alloc_wrqe(len, toep->ctrlq); if (wr == NULL) @@ -755,7 +755,7 @@ write_page_pods(struct adapter *sc, struct toepcb *toep, struct ddp_buffer *db) /* How many page pods are we writing in this cycle */ n = min(db->nppods - i, NUM_ULP_TX_SC_IMM_PPODS); chunk = PPOD_SZ(n); - len = roundup(sizeof(*ulpmc) + sizeof(*ulpsc) + chunk, 16); + len = roundup2(sizeof(*ulpmc) + sizeof(*ulpsc) + chunk, 16); wr = alloc_wrqe(len, toep->ctrlq); if (wr == NULL) @@ -764,7 +764,7 @@ write_page_pods(struct adapter *sc, struct toepcb *toep, struct ddp_buffer *db) INIT_ULPTX_WR(ulpmc, len, 0, 0); ulpmc->cmd = htobe32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) | - F_ULP_MEMIO_ORDER); + is_t4(sc) ? F_ULP_MEMIO_ORDER : F_T5_ULP_MEMIO_IMM); ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk / 32)); ulpmc->len16 = htobe32(howmany(len - sizeof(ulpmc->wr), 16)); ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(ppod_addr >> 5)); diff --git a/sys/dev/cxgbe/tom/t4_listen.c b/sys/dev/cxgbe/tom/t4_listen.c index b80702d4ace..30949e896b4 100644 --- a/sys/dev/cxgbe/tom/t4_listen.c +++ b/sys/dev/cxgbe/tom/t4_listen.c @@ -360,13 +360,13 @@ send_reset_synqe(struct toedev *tod, struct synq_entry *synqe) /* The wrqe will have two WRs - a flowc followed by an abort_req */ flowclen = sizeof(*flowc) + nparams * sizeof(struct fw_flowc_mnemval); - wr = alloc_wrqe(roundup(flowclen, EQ_ESIZE) + sizeof(*req), ofld_txq); + wr = alloc_wrqe(roundup2(flowclen, EQ_ESIZE) + sizeof(*req), ofld_txq); if (wr == NULL) { /* XXX */ panic("%s: allocation failure.", __func__); } flowc = wrtod(wr); - req = (void *)((caddr_t)flowc + roundup(flowclen, EQ_ESIZE)); + req = (void *)((caddr_t)flowc + roundup2(flowclen, EQ_ESIZE)); /* First the flowc ... */ memset(flowc, 0, wr->wr_len); @@ -944,7 +944,7 @@ get_qids_from_mbuf(struct mbuf *m, int *txqid, int *rxqid) static struct synq_entry * mbuf_to_synqe(struct mbuf *m) { - int len = roundup(sizeof (struct synq_entry), 8); + int len = roundup2(sizeof (struct synq_entry), 8); int tspace = M_TRAILINGSPACE(m); struct synq_entry *synqe = NULL; @@ -1006,8 +1006,11 @@ calc_opt2p(struct adapter *sc, struct port_info *pi, int rxqid, opt2 |= F_CCTRL_ECN; opt2 |= V_TX_QUEUE(sc->params.tp.tx_modq[pi->tx_chan]); - opt2 |= F_RX_COALESCE_VALID | V_RX_COALESCE(M_RX_COALESCE); opt2 |= F_RSS_QUEUE_VALID | V_RSS_QUEUE(ofld_rxq->iq.abs_id); + if (is_t4(sc)) + opt2 |= F_RX_COALESCE_VALID | V_RX_COALESCE(M_RX_COALESCE); + else + opt2 |= F_T5_OPT_2_VALID | V_RX_COALESCE(M_RX_COALESCE); #ifdef USE_DDP_RX_FLOW_CONTROL if (ulp_mode == ULP_MODE_TCPDDP) diff --git a/sys/dev/cxgbe/tom/t4_tom.c b/sys/dev/cxgbe/tom/t4_tom.c index 64e8b26fac7..6ab4d21f77f 100644 --- a/sys/dev/cxgbe/tom/t4_tom.c +++ b/sys/dev/cxgbe/tom/t4_tom.c @@ -512,7 +512,7 @@ calc_opt0(struct socket *so, struct port_info *pi, struct l2t_entry *e, #define VLAN_NONE 0xfff #define FILTER_SEL_VLAN_NONE 0xffff -uint32_t +uint64_t select_ntuple(struct port_info *pi, struct l2t_entry *e, uint32_t filter_mode) { uint16_t viid = pi->viid; @@ -535,7 +535,10 @@ select_ntuple(struct port_info *pi, struct l2t_entry *e, uint32_t filter_mode) ntuple |= IPPROTO_TCP << FILTER_SEL_WIDTH_VLD_TAG_P_FC; } - return (htobe32(ntuple)); + if (is_t4(pi->adapter)) + return (htobe32(ntuple)); + else + return (htobe64(V_FILTER_TUPLE(ntuple))); } void diff --git a/sys/dev/cxgbe/tom/t4_tom.h b/sys/dev/cxgbe/tom/t4_tom.h index d0fbbd2103e..595dd30a0c4 100644 --- a/sys/dev/cxgbe/tom/t4_tom.h +++ b/sys/dev/cxgbe/tom/t4_tom.h @@ -234,7 +234,7 @@ u_long select_rcv_wnd(struct socket *); int select_rcv_wscale(void); uint64_t calc_opt0(struct socket *, struct port_info *, struct l2t_entry *, int, int, int, int); -uint32_t select_ntuple(struct port_info *, struct l2t_entry *, uint32_t); +uint64_t select_ntuple(struct port_info *, struct l2t_entry *, uint32_t); void set_tcpddp_ulp_mode(struct toepcb *); int negative_advice(int); struct clip_entry *hold_lip(struct tom_data *, struct in6_addr *); diff --git a/sys/modules/cxgbe/Makefile b/sys/modules/cxgbe/Makefile index 5ec8dccd3c0..2f848b677a2 100644 --- a/sys/modules/cxgbe/Makefile +++ b/sys/modules/cxgbe/Makefile @@ -3,7 +3,8 @@ # SUBDIR = if_cxgbe -SUBDIR+= firmware +SUBDIR+= t4_firmware +#SUBDIR+= t5_firmware SUBDIR+= ${_tom} .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" diff --git a/sys/modules/cxgbe/firmware/Makefile b/sys/modules/cxgbe/t4_firmware/Makefile similarity index 100% rename from sys/modules/cxgbe/firmware/Makefile rename to sys/modules/cxgbe/t4_firmware/Makefile diff --git a/tools/tools/cxgbetool/cxgbetool.c b/tools/tools/cxgbetool/cxgbetool.c index 32f6d2694b8..60a21df609a 100644 --- a/tools/tools/cxgbetool/cxgbetool.c +++ b/tools/tools/cxgbetool/cxgbetool.c @@ -77,6 +77,7 @@ struct field_desc { #include "reg_defs_t4.c" #include "reg_defs_t4vf.c" +#include "reg_defs_t5.c" static void usage(FILE *fp) @@ -354,34 +355,75 @@ dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs) ARRAY_SIZE(t4vf_mod)); } +#define T5_MODREGS(name) { #name, t5_##name##_regs } +static int +dump_regs_t5(int argc, const char *argv[], const uint32_t *regs) +{ + static struct mod_regs t5_mod[] = { + T5_MODREGS(sge), + { "pci", t5_pcie_regs }, + T5_MODREGS(dbg), + { "mc0", t5_mc_0_regs }, + { "mc1", t5_mc_1_regs }, + T5_MODREGS(ma), + { "edc0", t5_edc_t50_regs }, + { "edc1", t5_edc_t51_regs }, + T5_MODREGS(cim), + T5_MODREGS(tp), + { "ulprx", t5_ulp_rx_regs }, + { "ulptx", t5_ulp_tx_regs }, + { "pmrx", t5_pm_rx_regs }, + { "pmtx", t5_pm_tx_regs }, + T5_MODREGS(mps), + { "cplsw", t5_cpl_switch_regs }, + T5_MODREGS(smb), + { "i2c", t5_i2cm_regs }, + T5_MODREGS(mi), + T5_MODREGS(uart), + T5_MODREGS(pmu), + T5_MODREGS(sf), + T5_MODREGS(pl), + T5_MODREGS(le), + T5_MODREGS(ncsi), + T5_MODREGS(mac), + { "hma", t5_hma_t5_regs } + }; + + return dump_regs_table(argc, argv, regs, t5_mod, ARRAY_SIZE(t5_mod)); +} +#undef T5_MODREGS + static int dump_regs(int argc, const char *argv[]) { - int vers, revision, is_pcie, rc; + int vers, revision, rc; struct t4_regdump regs; + uint32_t len; - regs.data = calloc(1, T4_REGDUMP_SIZE); + len = max(T4_REGDUMP_SIZE, T5_REGDUMP_SIZE); + regs.data = calloc(1, len); if (regs.data == NULL) { warnc(ENOMEM, "regdump"); return (ENOMEM); } - regs.len = T4_REGDUMP_SIZE; + regs.len = len; rc = doit(CHELSIO_T4_REGDUMP, ®s); if (rc != 0) return (rc); vers = get_card_vers(regs.version); revision = (regs.version >> 10) & 0x3f; - is_pcie = (regs.version & 0x80000000) != 0; if (vers == 4) { if (revision == 0x3f) rc = dump_regs_t4vf(argc, argv, regs.data); else rc = dump_regs_t4(argc, argv, regs.data); - } else { - warnx("%s (type %d, rev %d) is not a T4 card.", + } else if (vers == 5) + rc = dump_regs_t5(argc, argv, regs.data); + else { + warnx("%s (type %d, rev %d) is not a known card.", nexus, vers, revision); return (ENOTSUP); } diff --git a/tools/tools/cxgbetool/reg_defs_t5.c b/tools/tools/cxgbetool/reg_defs_t5.c new file mode 100644 index 00000000000..adc1ecee436 --- /dev/null +++ b/tools/tools/cxgbetool/reg_defs_t5.c @@ -0,0 +1,65039 @@ +/* This file is automatically generated --- changes will be lost */ +__FBSDID("$FreeBSD$"); + +struct reg_info t5_sge_regs[] = { + { "SGE_PF_KDOORBELL", 0x1e000, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e004, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 }, + { "SGE_PF_KDOORBELL", 0x1e400, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e404, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 }, + { "SGE_PF_KDOORBELL", 0x1e800, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e804, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 }, + { "SGE_PF_KDOORBELL", 0x1ec00, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1ec04, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f000, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f004, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f400, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f404, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f800, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f804, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 }, + { "SGE_PF_KDOORBELL", 0x1fc00, 0 }, + { "QID", 15, 17 }, + { "Priority", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1fc04, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 }, + { "SGE_CONTROL", 0x1008, 0 }, + { "IgrAllCPLtoFL", 31, 1 }, + { "FLSplitMin", 22, 9 }, + { "RxPktCPLMode", 18, 1 }, + { "EgrStatusPageSize", 17, 1 }, + { "IngHintEnable1", 15, 1 }, + { "IngHintEnable0", 14, 1 }, + { "IngIntCompareIDX", 13, 1 }, + { "PktShift", 10, 3 }, + { "IngPCIeBoundary", 7, 3 }, + { "IngPadBoundary", 4, 3 }, + { "GlobalEnable", 0, 1 }, + { "SGE_HOST_PAGE_SIZE", 0x100c, 0 }, + { "HostPageSizePF7", 28, 4 }, + { "HostPageSizePF6", 24, 4 }, + { "HostPageSizePF5", 20, 4 }, + { "HostPageSizePF4", 16, 4 }, + { "HostPageSizePF3", 12, 4 }, + { "HostPageSizePF2", 8, 4 }, + { "HostPageSizePF1", 4, 4 }, + { "HostPageSizePF0", 0, 4 }, + { "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 }, + { "QueuesPerPagePF7", 28, 4 }, + { "QueuesPerPagePF6", 24, 4 }, + { "QueuesPerPagePF5", 20, 4 }, + { "QueuesPerPagePF4", 16, 4 }, + { "QueuesPerPagePF3", 12, 4 }, + { "QueuesPerPagePF2", 8, 4 }, + { "QueuesPerPagePF1", 4, 4 }, + { "QueuesPerPagePF0", 0, 4 }, + { "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 }, + { "QueuesPerPageVFPF7", 28, 4 }, + { "QueuesPerPageVFPF6", 24, 4 }, + { "QueuesPerPageVFPF5", 20, 4 }, + { "QueuesPerPageVFPF4", 16, 4 }, + { "QueuesPerPageVFPF3", 12, 4 }, + { "QueuesPerPageVFPF2", 8, 4 }, + { "QueuesPerPageVFPF1", 4, 4 }, + { "QueuesPerPageVFPF0", 0, 4 }, + { "SGE_USER_MODE_LIMITS", 0x1018, 0 }, + { "Opcode_Min", 24, 8 }, + { "Opcode_Max", 16, 8 }, + { "Length_Min", 8, 8 }, + { "Length_Max", 0, 8 }, + { "SGE_WR_ERROR", 0x101c, 0 }, + { "SGE_PERR_INJECT", 0x1020, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "SGE_INT_CAUSE1", 0x1024, 0 }, + { "perr_pc_chpi_rsp2", 31, 1 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_pc_mctag", 24, 1 }, + { "perr_pc_chpi_rsp1", 23, 1 }, + { "perr_pc_chpi_rsp0", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_INT_ENABLE1", 0x1028, 0 }, + { "perr_pc_chpi_rsp2", 31, 1 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_pc_mctag", 24, 1 }, + { "perr_pc_chpi_rsp1", 23, 1 }, + { "perr_pc_chpi_rsp0", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_PERR_ENABLE1", 0x102c, 0 }, + { "perr_pc_chpi_rsp2", 31, 1 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_pc_mctag", 24, 1 }, + { "perr_pc_chpi_rsp1", 23, 1 }, + { "perr_pc_chpi_rsp0", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_INT_CAUSE2", 0x1030, 0 }, + { "perr_dbp_hint_fl_fifo", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "perr_eswitch_fifo3", 21, 1 }, + { "perr_eswitch_fifo2", 20, 1 }, + { "perr_eswitch_fifo1", 19, 1 }, + { "perr_eswitch_fifo0", 18, 1 }, + { "perr_pc_dbp1", 17, 1 }, + { "perr_pc_dbp0", 16, 1 }, + { "perr_pc_dbp2", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_pc_mc_rsp", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "perr_dbp_hint_fifo", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_dbp_lp_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_INT_ENABLE2", 0x1034, 0 }, + { "perr_dbp_hint_fl_fifo", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "perr_eswitch_fifo3", 21, 1 }, + { "perr_eswitch_fifo2", 20, 1 }, + { "perr_eswitch_fifo1", 19, 1 }, + { "perr_eswitch_fifo0", 18, 1 }, + { "perr_pc_dbp1", 17, 1 }, + { "perr_pc_dbp0", 16, 1 }, + { "perr_pc_dbp2", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_pc_mc_rsp", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "perr_dbp_hint_fifo", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_dbp_lp_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_PERR_ENABLE2", 0x1038, 0 }, + { "perr_dbp_hint_fl_fifo", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "perr_eswitch_fifo3", 21, 1 }, + { "perr_eswitch_fifo2", 20, 1 }, + { "perr_eswitch_fifo1", 19, 1 }, + { "perr_eswitch_fifo0", 18, 1 }, + { "perr_pc_dbp1", 17, 1 }, + { "perr_pc_dbp0", 16, 1 }, + { "perr_pc_dbp2", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_pc_mc_rsp", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "perr_dbp_hint_fifo", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_dbp_lp_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_INT_CAUSE3", 0x103c, 0 }, + { "err_flm_dbp", 31, 1 }, + { "err_flm_idma1", 30, 1 }, + { "err_flm_idma0", 29, 1 }, + { "err_flm_hint", 28, 1 }, + { "err_pcie_error3", 27, 1 }, + { "err_pcie_error2", 26, 1 }, + { "err_pcie_error1", 25, 1 }, + { "err_pcie_error0", 24, 1 }, + { "err_timer_above_max_qid", 23, 1 }, + { "err_cpl_exceed_iqe_size", 22, 1 }, + { "err_invalid_cidx_inc", 21, 1 }, + { "err_itp_time_paused", 20, 1 }, + { "err_cpl_opcode_0", 19, 1 }, + { "err_dropped_db", 18, 1 }, + { "err_data_cpl_on_high_qid1", 17, 1 }, + { "err_data_cpl_on_high_qid0", 16, 1 }, + { "err_bad_db_pidx3", 15, 1 }, + { "err_bad_db_pidx2", 14, 1 }, + { "err_bad_db_pidx1", 13, 1 }, + { "err_bad_db_pidx0", 12, 1 }, + { "err_ing_pcie_chan", 11, 1 }, + { "err_ing_ctxt_prio", 10, 1 }, + { "err_egr_ctxt_prio", 9, 1 }, + { "dbfifo_hp_int", 8, 1 }, + { "dbfifo_lp_int", 7, 1 }, + { "reg_address_err", 6, 1 }, + { "ingress_size_err", 5, 1 }, + { "egress_size_err", 4, 1 }, + { "err_inv_ctxt3", 3, 1 }, + { "err_inv_ctxt2", 2, 1 }, + { "err_inv_ctxt1", 1, 1 }, + { "err_inv_ctxt0", 0, 1 }, + { "SGE_INT_ENABLE3", 0x1040, 0 }, + { "err_flm_dbp", 31, 1 }, + { "err_flm_idma1", 30, 1 }, + { "err_flm_idma0", 29, 1 }, + { "err_flm_hint", 28, 1 }, + { "err_pcie_error3", 27, 1 }, + { "err_pcie_error2", 26, 1 }, + { "err_pcie_error1", 25, 1 }, + { "err_pcie_error0", 24, 1 }, + { "err_timer_above_max_qid", 23, 1 }, + { "err_cpl_exceed_iqe_size", 22, 1 }, + { "err_invalid_cidx_inc", 21, 1 }, + { "err_itp_time_paused", 20, 1 }, + { "err_cpl_opcode_0", 19, 1 }, + { "err_dropped_db", 18, 1 }, + { "err_data_cpl_on_high_qid1", 17, 1 }, + { "err_data_cpl_on_high_qid0", 16, 1 }, + { "err_bad_db_pidx3", 15, 1 }, + { "err_bad_db_pidx2", 14, 1 }, + { "err_bad_db_pidx1", 13, 1 }, + { "err_bad_db_pidx0", 12, 1 }, + { "err_ing_pcie_chan", 11, 1 }, + { "err_ing_ctxt_prio", 10, 1 }, + { "err_egr_ctxt_prio", 9, 1 }, + { "dbfifo_hp_int", 8, 1 }, + { "dbfifo_lp_int", 7, 1 }, + { "reg_address_err", 6, 1 }, + { "ingress_size_err", 5, 1 }, + { "egress_size_err", 4, 1 }, + { "err_inv_ctxt3", 3, 1 }, + { "err_inv_ctxt2", 2, 1 }, + { "err_inv_ctxt1", 1, 1 }, + { "err_inv_ctxt0", 0, 1 }, + { "SGE_FL_BUFFER_SIZE0", 0x1044, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE1", 0x1048, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE2", 0x104c, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE3", 0x1050, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE4", 0x1054, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE5", 0x1058, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE6", 0x105c, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE7", 0x1060, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE8", 0x1064, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE9", 0x1068, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE10", 0x106c, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE11", 0x1070, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE12", 0x1074, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE13", 0x1078, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE14", 0x107c, 0 }, + { "Size", 4, 28 }, + { "SGE_FL_BUFFER_SIZE15", 0x1080, 0 }, + { "Size", 4, 28 }, + { "SGE_DBQ_CTXT_BADDR", 0x1084, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_IMSG_CTXT_BADDR", 0x1088, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_FLM_CACHE_BADDR", 0x108c, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_FLM_CFG", 0x1090, 0 }, + { "OpMode", 26, 6 }, + { "NoHdr", 18, 1 }, + { "CachePtrCnt", 16, 2 }, + { "EDRAMPtrCnt", 14, 2 }, + { "HdrStartFLQ", 11, 3 }, + { "FetchThresh", 6, 5 }, + { "CreditCnt", 4, 2 }, + { "CreditCntPacking", 2, 2 }, + { "NoEDRAM", 0, 1 }, + { "SGE_CONM_CTRL", 0x1094, 0 }, + { "EgrThresholdPacking", 14, 6 }, + { "EgrThreshold", 8, 6 }, + { "IngThreshold", 2, 6 }, + { "SGE_TIMESTAMP_LO", 0x1098, 0 }, + { "SGE_TIMESTAMP_HI", 0x109c, 0 }, + { "Opcode", 28, 2 }, + { "Value", 0, 28 }, + { "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 }, + { "Threshold_0", 24, 6 }, + { "Threshold_1", 16, 6 }, + { "Threshold_2", 8, 6 }, + { "Threshold_3", 0, 6 }, + { "SGE_DBFIFO_STATUS", 0x10a4, 0 }, + { "Bar2Valid", 31, 1 }, + { "Bar2Full", 30, 1 }, + { "LP_Int_Thresh", 18, 12 }, + { "LP_Count", 0, 18 }, + { "SGE_DOORBELL_CONTROL", 0x10a8, 0 }, + { "HintDepthCtl", 27, 5 }, + { "NoCoalesce", 26, 1 }, + { "HP_Weight", 24, 2 }, + { "HP_Disable", 23, 1 }, + { "ForceUserDBtoLP", 22, 1 }, + { "ForceVFPF0DBtoLP", 21, 1 }, + { "ForceVFPF1DBtoLP", 20, 1 }, + { "ForceVFPF2DBtoLP", 19, 1 }, + { "ForceVFPF3DBtoLP", 18, 1 }, + { "ForceVFPF4DBtoLP", 17, 1 }, + { "ForceVFPF5DBtoLP", 16, 1 }, + { "ForceVFPF6DBtoLP", 15, 1 }, + { "ForceVFPF7DBtoLP", 14, 1 }, + { "Enable_Drop", 13, 1 }, + { "Drop_Timeout", 1, 12 }, + { "Dropped_DB", 0, 1 }, + { "SGE_DROPPED_DOORBELL", 0x10ac, 0 }, + { "SGE_DOORBELL_THROTTLE_CONTROL", 0x10b0, 0 }, + { "Bar2ThrottleCount", 16, 8 }, + { "ClrCoalesceDisable", 15, 1 }, + { "OpenBar2GateOnce", 14, 1 }, + { "ForceOpenBar2Gate", 13, 1 }, + { "Throttle_Count", 1, 12 }, + { "Throttle_Enable", 0, 1 }, + { "SGE_ITP_CONTROL", 0x10b4, 0 }, + { "Critical_Time", 10, 15 }, + { "LL_Empty", 4, 6 }, + { "LL_Read_Wait_Disable", 0, 1 }, + { "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 }, + { "TimerValue0", 16, 16 }, + { "TimerValue1", 0, 16 }, + { "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 }, + { "TimerValue2", 16, 16 }, + { "TimerValue3", 0, 16 }, + { "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 }, + { "TimerValue4", 16, 16 }, + { "TimerValue5", 0, 16 }, + { "SGE_DEBUG_INDEX", 0x10cc, 0 }, + { "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 }, + { "SGE_DEBUG_DATA_LOW", 0x10d4, 0 }, + { "SGE_REVISION", 0x10d8, 0 }, + { "SGE_INT_CAUSE4", 0x10dc, 0 }, + { "bar2_egress_len_or_addr_err", 29, 1 }, + { "err_cpl_exceed_max_iqe_size1", 28, 1 }, + { "err_cpl_exceed_max_iqe_size0", 27, 1 }, + { "err_wr_len_too_large3", 26, 1 }, + { "err_wr_len_too_large2", 25, 1 }, + { "err_wr_len_too_large1", 24, 1 }, + { "err_wr_len_too_large0", 23, 1 }, + { "err_large_minfetch_with_txcoal3", 22, 1 }, + { "err_large_minfetch_with_txcoal2", 21, 1 }, + { "err_large_minfetch_with_txcoal1", 20, 1 }, + { "err_large_minfetch_with_txcoal0", 19, 1 }, + { "coal_with_hp_disable_err", 18, 1 }, + { "bar2_egress_coal0_err", 17, 1 }, + { "bar2_egress_size_err", 16, 1 }, + { "flm_pc_rsp_err", 15, 1 }, + { "dbfifo_hp_int_low", 14, 1 }, + { "dbfifo_lp_int_low", 13, 1 }, + { "dbfifo_fl_int_low", 12, 1 }, + { "dbfifo_fl_int", 11, 1 }, + { "err_rx_cpl_packet_size1", 10, 1 }, + { "err_rx_cpl_packet_size0", 9, 1 }, + { "err_bad_upfl_inc_credit3", 8, 1 }, + { "err_bad_upfl_inc_credit2", 7, 1 }, + { "err_bad_upfl_inc_credit1", 6, 1 }, + { "err_bad_upfl_inc_credit0", 5, 1 }, + { "err_physaddr_len0_idma1", 4, 1 }, + { "err_physaddr_len0_idma0", 3, 1 }, + { "err_flm_invalid_pkt_drop1", 2, 1 }, + { "err_flm_invalid_pkt_drop0", 1, 1 }, + { "err_unexpected_timer", 0, 1 }, + { "SGE_INT_ENABLE4", 0x10e0, 0 }, + { "bar2_egress_len_or_addr_err", 29, 1 }, + { "err_cpl_exceed_max_iqe_size1", 28, 1 }, + { "err_cpl_exceed_max_iqe_size0", 27, 1 }, + { "err_wr_len_too_large3", 26, 1 }, + { "err_wr_len_too_large2", 25, 1 }, + { "err_wr_len_too_large1", 24, 1 }, + { "err_wr_len_too_large0", 23, 1 }, + { "err_large_minfetch_with_txcoal3", 22, 1 }, + { "err_large_minfetch_with_txcoal2", 21, 1 }, + { "err_large_minfetch_with_txcoal1", 20, 1 }, + { "err_large_minfetch_with_txcoal0", 19, 1 }, + { "coal_with_hp_disable_err", 18, 1 }, + { "bar2_egress_coal0_err", 17, 1 }, + { "bar2_egress_size_err", 16, 1 }, + { "flm_pc_rsp_err", 15, 1 }, + { "dbfifo_hp_int_low", 14, 1 }, + { "dbfifo_lp_int_low", 13, 1 }, + { "dbfifo_fl_int_low", 12, 1 }, + { "dbfifo_fl_int", 11, 1 }, + { "err_rx_cpl_packet_size1", 10, 1 }, + { "err_rx_cpl_packet_size0", 9, 1 }, + { "err_bad_upfl_inc_credit3", 8, 1 }, + { "err_bad_upfl_inc_credit2", 7, 1 }, + { "err_bad_upfl_inc_credit1", 6, 1 }, + { "err_bad_upfl_inc_credit0", 5, 1 }, + { "err_physaddr_len0_idma1", 4, 1 }, + { "err_physaddr_len0_idma0", 3, 1 }, + { "err_flm_invalid_pkt_drop1", 2, 1 }, + { "err_flm_invalid_pkt_drop0", 1, 1 }, + { "err_unexpected_timer", 0, 1 }, + { "SGE_STAT_TOTAL", 0x10e4, 0 }, + { "SGE_STAT_MATCH", 0x10e8, 0 }, + { "SGE_STAT_CFG", 0x10ec, 0 }, + { "StatSource", 9, 4 }, + { "ITPOpMode", 8, 1 }, + { "EgrCtxtOpMode", 6, 2 }, + { "IngCtxtOpMode", 4, 2 }, + { "StatMode", 2, 2 }, + { "SGE_HINT_CFG", 0x10f0, 0 }, + { "uPCutoffThreshLp", 12, 11 }, + { "HintsAllowedNoHdr", 6, 6 }, + { "HintsAllowedHdr", 0, 6 }, + { "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 }, + { "QueuesPerPagePF7", 28, 4 }, + { "QueuesPerPagePF6", 24, 4 }, + { "QueuesPerPagePF5", 20, 4 }, + { "QueuesPerPagePF4", 16, 4 }, + { "QueuesPerPagePF3", 12, 4 }, + { "QueuesPerPagePF2", 8, 4 }, + { "QueuesPerPagePF1", 4, 4 }, + { "QueuesPerPagePF0", 0, 4 }, + { "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 }, + { "QueuesPerPageVFPF7", 28, 4 }, + { "QueuesPerPageVFPF6", 24, 4 }, + { "QueuesPerPageVFPF5", 20, 4 }, + { "QueuesPerPageVFPF4", 16, 4 }, + { "QueuesPerPageVFPF3", 12, 4 }, + { "QueuesPerPageVFPF2", 8, 4 }, + { "QueuesPerPageVFPF1", 4, 4 }, + { "QueuesPerPageVFPF0", 0, 4 }, + { "SGE_ERROR_STATS", 0x1100, 0 }, + { "Cause_Register", 24, 3 }, + { "Cause_Bit", 19, 5 }, + { "Uncaptured_Error", 18, 1 }, + { "Error_QID_Valid", 17, 1 }, + { "Error_QID", 0, 17 }, + { "SGE_INT_CAUSE5", 0x110c, 0 }, + { "err_T_RxCRC", 31, 1 }, + { "perr_MC_RspData", 30, 1 }, + { "perr_PC_RspData", 29, 1 }, + { "perr_PD_RdRspData", 28, 1 }, + { "perr_U_RxData", 27, 1 }, + { "perr_UD_RxData", 26, 1 }, + { "perr_uP_Data", 25, 1 }, + { "perr_CIM2SGE_RxData", 24, 1 }, + { "perr_hint_delay_fifo1", 23, 1 }, + { "perr_hint_delay_fifo0", 22, 1 }, + { "perr_imsg_pd_fifo", 21, 1 }, + { "perr_ulptx_fifo1", 20, 1 }, + { "perr_ulptx_fifo0", 19, 1 }, + { "perr_idma2imsg_fifo1", 18, 1 }, + { "perr_idma2imsg_fifo0", 17, 1 }, + { "perr_pointer_data_fifo0", 16, 1 }, + { "perr_pointer_data_fifo1", 15, 1 }, + { "perr_pointer_hdr_fifo0", 14, 1 }, + { "perr_pointer_hdr_fifo1", 13, 1 }, + { "perr_payload_fifo0", 12, 1 }, + { "perr_payload_fifo1", 11, 1 }, + { "perr_edma_input_fifo3", 10, 1 }, + { "perr_edma_input_fifo2", 9, 1 }, + { "perr_edma_input_fifo1", 8, 1 }, + { "perr_edma_input_fifo0", 7, 1 }, + { "perr_mgt_bar2_fifo", 6, 1 }, + { "perr_headersplit_fifo1", 5, 1 }, + { "perr_headersplit_fifo0", 4, 1 }, + { "perr_cim_fifo1", 3, 1 }, + { "perr_cim_fifo0", 2, 1 }, + { "perr_idma_switch_output_fifo1", 1, 1 }, + { "perr_idma_switch_output_fifo0", 0, 1 }, + { "SGE_INT_ENABLE5", 0x1110, 0 }, + { "err_T_RxCRC", 31, 1 }, + { "perr_MC_RspData", 30, 1 }, + { "perr_PC_RspData", 29, 1 }, + { "perr_PD_RdRspData", 28, 1 }, + { "perr_U_RxData", 27, 1 }, + { "perr_UD_RxData", 26, 1 }, + { "perr_uP_Data", 25, 1 }, + { "perr_CIM2SGE_RxData", 24, 1 }, + { "perr_hint_delay_fifo1", 23, 1 }, + { "perr_hint_delay_fifo0", 22, 1 }, + { "perr_imsg_pd_fifo", 21, 1 }, + { "perr_ulptx_fifo1", 20, 1 }, + { "perr_ulptx_fifo0", 19, 1 }, + { "perr_idma2imsg_fifo1", 18, 1 }, + { "perr_idma2imsg_fifo0", 17, 1 }, + { "perr_pointer_data_fifo0", 16, 1 }, + { "perr_pointer_data_fifo1", 15, 1 }, + { "perr_pointer_hdr_fifo0", 14, 1 }, + { "perr_pointer_hdr_fifo1", 13, 1 }, + { "perr_payload_fifo0", 12, 1 }, + { "perr_payload_fifo1", 11, 1 }, + { "perr_edma_input_fifo3", 10, 1 }, + { "perr_edma_input_fifo2", 9, 1 }, + { "perr_edma_input_fifo1", 8, 1 }, + { "perr_edma_input_fifo0", 7, 1 }, + { "perr_mgt_bar2_fifo", 6, 1 }, + { "perr_headersplit_fifo1", 5, 1 }, + { "perr_headersplit_fifo0", 4, 1 }, + { "perr_cim_fifo1", 3, 1 }, + { "perr_cim_fifo0", 2, 1 }, + { "perr_idma_switch_output_fifo1", 1, 1 }, + { "perr_idma_switch_output_fifo0", 0, 1 }, + { "SGE_PERR_ENABLE5", 0x1114, 0 }, + { "err_T_RxCRC", 31, 1 }, + { "perr_MC_RspData", 30, 1 }, + { "perr_PC_RspData", 29, 1 }, + { "perr_PD_RdRspData", 28, 1 }, + { "perr_U_RxData", 27, 1 }, + { "perr_UD_RxData", 26, 1 }, + { "perr_uP_Data", 25, 1 }, + { "perr_CIM2SGE_RxData", 24, 1 }, + { "perr_hint_delay_fifo1", 23, 1 }, + { "perr_hint_delay_fifo0", 22, 1 }, + { "perr_imsg_pd_fifo", 21, 1 }, + { "perr_ulptx_fifo1", 20, 1 }, + { "perr_ulptx_fifo0", 19, 1 }, + { "perr_idma2imsg_fifo1", 18, 1 }, + { "perr_idma2imsg_fifo0", 17, 1 }, + { "perr_pointer_data_fifo0", 16, 1 }, + { "perr_pointer_data_fifo1", 15, 1 }, + { "perr_pointer_hdr_fifo0", 14, 1 }, + { "perr_pointer_hdr_fifo1", 13, 1 }, + { "perr_payload_fifo0", 12, 1 }, + { "perr_payload_fifo1", 11, 1 }, + { "perr_edma_input_fifo3", 10, 1 }, + { "perr_edma_input_fifo2", 9, 1 }, + { "perr_edma_input_fifo1", 8, 1 }, + { "perr_edma_input_fifo0", 7, 1 }, + { "perr_mgt_bar2_fifo", 6, 1 }, + { "perr_headersplit_fifo1", 5, 1 }, + { "perr_headersplit_fifo0", 4, 1 }, + { "perr_cim_fifo1", 3, 1 }, + { "perr_cim_fifo0", 2, 1 }, + { "perr_idma_switch_output_fifo1", 1, 1 }, + { "perr_idma_switch_output_fifo0", 0, 1 }, + { "SGE_DBFIFO_STATUS2", 0x1118, 0 }, + { "FL_Int_Thresh", 24, 4 }, + { "FL_Count", 14, 10 }, + { "HP_Int_Thresh", 10, 4 }, + { "HP_Count", 0, 10 }, + { "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 }, + { "FetchBurstMax0", 16, 10 }, + { "FetchBurstMax1", 0, 10 }, + { "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 }, + { "FetchBurstMax2", 16, 10 }, + { "FetchBurstMax3", 0, 10 }, + { "SGE_CONTROL2", 0x1124, 0 }, + { "uPFLCutoffDis", 21, 1 }, + { "RxCplSizeAutocorrect", 20, 1 }, + { "IdmaArbRoundRobin", 19, 1 }, + { "IngPackBoundary", 16, 3 }, + { "CGEN_Egress_Context", 15, 1 }, + { "CGEN_Ingress_Context", 14, 1 }, + { "CGEN_IDMA", 13, 1 }, + { "CGEN_DBP", 12, 1 }, + { "CGEN_EDMA", 11, 1 }, + { "VFIFO_Enable", 10, 1 }, + { "FLM_Reschedule_Mode", 9, 1 }, + { "HintDepthCtlFL", 4, 5 }, + { "Force_Ordering", 3, 1 }, + { "TX_Coalesce_Size", 2, 1 }, + { "Coal_Strict_CIM_Pri", 1, 1 }, + { "TX_Coalesce_Pri", 0, 1 }, + { "SGE_DEEP_SLEEP", 0x1128, 0 }, + { "IDMA1_Sleep_Status", 11, 1 }, + { "IDMA0_Sleep_Status", 10, 1 }, + { "IDMA1_Sleep_Req", 9, 1 }, + { "IDMA0_Sleep_Req", 8, 1 }, + { "EDMA3_Sleep_Status", 7, 1 }, + { "EDMA2_Sleep_Status", 6, 1 }, + { "EDMA1_Sleep_Status", 5, 1 }, + { "EDMA0_Sleep_Status", 4, 1 }, + { "EDMA3_Sleep_Req", 3, 1 }, + { "EDMA2_Sleep_Req", 2, 1 }, + { "EDMA1_Sleep_Req", 1, 1 }, + { "EDMA0_Sleep_Req", 0, 1 }, + { "SGE_DOORBELL_THROTTLE_THRESHOLD", 0x112c, 0 }, + { "Throttle_Threshold_fl", 16, 4 }, + { "Throttle_Threshold_hp", 12, 4 }, + { "Throttle_Threshold_lp", 0, 12 }, + { "SGE_DBP_FETCH_THRESHOLD", 0x1130, 0 }, + { "dbp_fetch_threshold_fl", 21, 4 }, + { "dbp_fetch_threshold_hp", 17, 4 }, + { "dbp_fetch_threshold_lp", 5, 12 }, + { "dbp_fetch_threshold_mode", 4, 1 }, + { "dbp_fetch_threshold_en3", 3, 1 }, + { "dbp_fetch_threshold_en2", 2, 1 }, + { "dbp_fetch_threshold_en1", 1, 1 }, + { "dbp_fetch_threshold_en0", 0, 1 }, + { "SGE_DBP_FETCH_THRESHOLD_QUEUE", 0x1134, 0 }, + { "dbp_fetch_threshold_iq1", 16, 16 }, + { "dbp_fetch_threshold_iq0", 0, 16 }, + { "SGE_DBVFIFO_BADDR", 0x1138, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_DBVFIFO_SIZE", 0x113c, 0 }, + { "Size", 6, 12 }, + { "SGE_DBFIFO_STATUS3", 0x1140, 0 }, + { "LP_Ptrs_Equal", 21, 1 }, + { "LP_Snaphot", 20, 1 }, + { "FL_Int_Thresh_Low", 16, 4 }, + { "HP_Int_Thresh_Low", 12, 4 }, + { "LP_Int_Thresh_Low", 0, 12 }, + { "SGE_CHANGESET", 0x1144, 0 }, + { "SGE_PC_RSP_ERROR", 0x1148, 0 }, + { "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 }, + { "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 }, + { "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 }, + { "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 }, + { "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 }, + { "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 }, + { "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 }, + { "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 }, + { "SGE_CTXT_CMD", 0x11fc, 0 }, + { "Busy", 31, 1 }, + { "Opcode", 28, 2 }, + { "CtxtType", 24, 2 }, + { "QID", 0, 17 }, + { "SGE_CTXT_DATA0", 0x1200, 0 }, + { "SGE_CTXT_DATA1", 0x1204, 0 }, + { "SGE_CTXT_DATA2", 0x1208, 0 }, + { "SGE_CTXT_DATA3", 0x120c, 0 }, + { "SGE_CTXT_DATA4", 0x1210, 0 }, + { "SGE_CTXT_DATA5", 0x1214, 0 }, + { "SGE_CTXT_DATA6", 0x1218, 0 }, + { "SGE_CTXT_DATA7", 0x121c, 0 }, + { "SGE_CTXT_MASK0", 0x1220, 0 }, + { "SGE_CTXT_MASK1", 0x1224, 0 }, + { "SGE_CTXT_MASK2", 0x1228, 0 }, + { "SGE_CTXT_MASK3", 0x122c, 0 }, + { "SGE_CTXT_MASK4", 0x1230, 0 }, + { "SGE_CTXT_MASK5", 0x1234, 0 }, + { "SGE_CTXT_MASK6", 0x1238, 0 }, + { "SGE_CTXT_MASK7", 0x123c, 0 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 }, + { "CIM_WM", 24, 2 }, + { "debug_uP_SOP_cnt", 20, 4 }, + { "debug_uP_EOP_cnt", 16, 4 }, + { "debug_CIM_SOP1_cnt", 12, 4 }, + { "debug_CIM_EOP1_cnt", 8, 4 }, + { "debug_CIM_SOP0_cnt", 4, 4 }, + { "debug_CIM_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 }, + { "debug_T_Rx_SOP1_cnt", 28, 4 }, + { "debug_T_Rx_EOP1_cnt", 24, 4 }, + { "debug_T_Rx_SOP0_cnt", 20, 4 }, + { "debug_T_Rx_EOP0_cnt", 16, 4 }, + { "debug_U_Rx_SOP1_cnt", 12, 4 }, + { "debug_U_Rx_EOP1_cnt", 8, 4 }, + { "debug_U_Rx_SOP0_cnt", 4, 4 }, + { "debug_U_Rx_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 }, + { "debug_UD_Rx_SOP3_cnt", 28, 4 }, + { "debug_UD_Rx_EOP3_cnt", 24, 4 }, + { "debug_UD_Rx_SOP2_cnt", 20, 4 }, + { "debug_UD_Rx_EOP2_cnt", 16, 4 }, + { "debug_UD_Rx_SOP1_cnt", 12, 4 }, + { "debug_UD_Rx_EOP1_cnt", 8, 4 }, + { "debug_UD_Rx_SOP0_cnt", 4, 4 }, + { "debug_UD_Rx_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c, 0 }, + { "debug_U_Tx_SOP3_cnt", 28, 4 }, + { "debug_U_Tx_EOP3_cnt", 24, 4 }, + { "debug_U_Tx_SOP2_cnt", 20, 4 }, + { "debug_U_Tx_EOP2_cnt", 16, 4 }, + { "debug_U_Tx_SOP1_cnt", 12, 4 }, + { "debug_U_Tx_EOP1_cnt", 8, 4 }, + { "debug_U_Tx_SOP0_cnt", 4, 4 }, + { "debug_U_Tx_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290, 0 }, + { "debug_PC_Rsp_SOP1_cnt", 28, 4 }, + { "debug_PC_Rsp_EOP1_cnt", 24, 4 }, + { "debug_PC_Rsp_SOP0_cnt", 20, 4 }, + { "debug_PC_Rsp_EOP0_cnt", 16, 4 }, + { "debug_PC_Req_SOP1_cnt", 12, 4 }, + { "debug_PC_Req_EOP1_cnt", 8, 4 }, + { "debug_PC_Req_SOP0_cnt", 4, 4 }, + { "debug_PC_Req_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294, 0 }, + { "debug_PD_RdReq_SOP3_cnt", 28, 4 }, + { "debug_PD_RdReq_EOP3_cnt", 24, 4 }, + { "debug_PD_RdReq_SOP2_cnt", 20, 4 }, + { "debug_PD_RdReq_EOP2_cnt", 16, 4 }, + { "debug_PD_RdReq_SOP1_cnt", 12, 4 }, + { "debug_PD_RdReq_EOP1_cnt", 8, 4 }, + { "debug_PD_RdReq_SOP0_cnt", 4, 4 }, + { "debug_PD_RdReq_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298, 0 }, + { "debug_PD_RdRsp_SOP3_cnt", 28, 4 }, + { "debug_PD_RdRsp_EOP3_cnt", 24, 4 }, + { "debug_PD_RdRsp_SOP2_cnt", 20, 4 }, + { "debug_PD_RdRsp_EOP2_cnt", 16, 4 }, + { "debug_PD_RdRsp_SOP1_cnt", 12, 4 }, + { "debug_PD_RdRsp_EOP1_cnt", 8, 4 }, + { "debug_PD_RdRsp_SOP0_cnt", 4, 4 }, + { "debug_PD_RdRsp_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 }, + { "debug_PD_WrReq_SOP3_cnt", 28, 4 }, + { "debug_PD_WrReq_EOP3_cnt", 24, 4 }, + { "debug_PD_WrReq_SOP2_cnt", 20, 4 }, + { "debug_PD_WrReq_EOP2_cnt", 16, 4 }, + { "debug_PD_WrReq_SOP1_cnt", 12, 4 }, + { "debug_PD_WrReq_EOP1_cnt", 8, 4 }, + { "debug_PD_WrReq_SOP0_cnt", 4, 4 }, + { "debug_PD_WrReq_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 }, + { "GlobalEnable_Off", 29, 1 }, + { "debug_CIM2SGE_RxAFull_d", 27, 2 }, + { "debug_CPLSW_CIM_TxAFull_d", 25, 2 }, + { "debug_uP_Full", 24, 1 }, + { "debug_M_rd_req_outstanding_PC", 23, 1 }, + { "debug_M_rd_req_outstanding_VFIFO", 22, 1 }, + { "debug_M_rd_req_outstanding_IMSG", 21, 1 }, + { "debug_M_rd_req_outstanding_CMARB", 20, 1 }, + { "debug_M_rd_req_outstanding_FLM", 19, 1 }, + { "debug_M_ReqVld", 18, 1 }, + { "debug_M_ReqRdy", 17, 1 }, + { "debug_M_RspVld", 16, 1 }, + { "debug_PD_WrReq_Int3_cnt", 12, 4 }, + { "debug_PD_WrReq_Int2_cnt", 8, 4 }, + { "debug_PD_WrReq_Int1_cnt", 4, 4 }, + { "debug_PD_WrReq_Int0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 }, + { "debug_CPLSW_TP_Rx_SOP1_cnt", 28, 4 }, + { "debug_CPLSW_TP_Rx_EOP1_cnt", 24, 4 }, + { "debug_CPLSW_TP_Rx_SOP0_cnt", 20, 4 }, + { "debug_CPLSW_TP_Rx_EOP0_cnt", 16, 4 }, + { "debug_CPLSW_CIM_SOP1_cnt", 12, 4 }, + { "debug_CPLSW_CIM_EOP1_cnt", 8, 4 }, + { "debug_CPLSW_CIM_SOP0_cnt", 4, 4 }, + { "debug_CPLSW_CIM_EOP0_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 }, + { "debug_T_RxAFull_d", 30, 2 }, + { "debug_PD_RdRspAFull_d", 26, 4 }, + { "debug_PD_RdReqAFull_d", 22, 4 }, + { "debug_PD_WrReqAFull_d", 18, 4 }, + { "debug_PC_RspAFull_d", 15, 3 }, + { "debug_PC_ReqAFull_d", 12, 3 }, + { "debug_U_TxAFull_d", 8, 4 }, + { "debug_UD_RxAFull_d", 4, 4 }, + { "debug_U_RxAFull_d", 2, 2 }, + { "debug_CIM_AFull_d", 0, 2 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 }, + { "debug_flm_idma1_cache_data_active", 24, 1 }, + { "debug_flm_idma1_cache_hdr_active", 23, 1 }, + { "debug_flm_idma1_ctxt_data_active", 22, 1 }, + { "debug_flm_idma1_ctxt_hdr_active", 21, 1 }, + { "debug_st_flm_idma1_cache", 19, 2 }, + { "debug_st_flm_idma1_ctxt", 16, 3 }, + { "debug_flm_idma0_cache_data_active", 8, 1 }, + { "debug_flm_idma0_cache_hdr_active", 7, 1 }, + { "debug_flm_idma0_ctxt_data_active", 6, 1 }, + { "debug_flm_idma0_ctxt_hdr_active", 5, 1 }, + { "debug_st_flm_idma0_cache", 3, 2 }, + { "debug_st_flm_idma0_ctxt", 0, 3 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 }, + { "debug_CPLSW_SOP1_cnt", 28, 4 }, + { "debug_CPLSW_EOP1_cnt", 24, 4 }, + { "debug_CPLSW_SOP0_cnt", 20, 4 }, + { "debug_CPLSW_EOP0_cnt", 16, 4 }, + { "debug_PC_Rsp_SOP2_cnt", 12, 4 }, + { "debug_PC_Rsp_EOP2_cnt", 8, 4 }, + { "debug_PC_Req_SOP2_cnt", 4, 4 }, + { "debug_PC_Req_EOP2_cnt", 0, 4 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 }, + { "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 }, + { "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 }, + { "debug_st_idma1_flm_req", 29, 3 }, + { "debug_st_idma0_flm_req", 26, 3 }, + { "debug_st_imsg_ctxt", 23, 3 }, + { "debug_st_imsg", 18, 5 }, + { "debug_st_idma1_ialn", 16, 2 }, + { "debug_st_idma1_idma_sm", 9, 6 }, + { "debug_st_idma0_ialn", 7, 2 }, + { "debug_st_idma0_idma_sm", 0, 6 }, + { "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 }, + { "debug_itp_empty", 12, 6 }, + { "debug_itp_expired", 6, 6 }, + { "debug_itp_pause", 5, 1 }, + { "debug_itp_del_done", 4, 1 }, + { "debug_itp_add_done", 3, 1 }, + { "debug_itp_evr_state", 0, 3 }, + { "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 }, + { "debug_st_dbp_thread2_cimfl", 25, 5 }, + { "debug_st_dbp_thread2_main", 20, 5 }, + { "debug_st_dbp_thread1_cimfl", 15, 5 }, + { "debug_st_dbp_thread1_main", 10, 5 }, + { "debug_st_dbp_thread0_cimfl", 5, 5 }, + { "debug_st_dbp_thread0_main", 0, 5 }, + { "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 }, + { "debug_st_dbp_upcp_main", 14, 5 }, + { "debug_st_dbp_dbfifo_main", 13, 1 }, + { "debug_st_dbp_ctxt", 10, 3 }, + { "debug_st_dbp_thread3_cimfl", 5, 5 }, + { "debug_st_dbp_thread3_main", 0, 5 }, + { "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 }, + { "debug_st_edma3_align_sub", 29, 3 }, + { "debug_st_edma3_align", 27, 2 }, + { "debug_st_edma3_req", 24, 3 }, + { "debug_st_edma2_align_sub", 21, 3 }, + { "debug_st_edma2_align", 19, 2 }, + { "debug_st_edma2_req", 16, 3 }, + { "debug_st_edma1_align_sub", 13, 3 }, + { "debug_st_edma1_align", 11, 2 }, + { "debug_st_edma1_req", 8, 3 }, + { "debug_st_edma0_align_sub", 5, 3 }, + { "debug_st_edma0_align", 3, 2 }, + { "debug_st_edma0_req", 0, 3 }, + { "SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4, 0 }, + { "debug_st_flm_dbptr", 30, 2 }, + { "debug_flm_cache_locked_count", 23, 7 }, + { "debug_flm_cache_agent", 20, 3 }, + { "debug_st_flm_cache", 16, 4 }, + { "debug_flm_dbptr_cidx_stall", 12, 1 }, + { "debug_flm_dbptr_qid", 0, 12 }, + { "SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8, 0 }, + { "SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc, 0 }, + { "SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0, 0 }, + { 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16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1504, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x150c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1514, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x151c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1524, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x152c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1534, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x153c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1544, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x154c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1554, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x155c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1564, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x156c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1574, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x157c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1584, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x158c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1594, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x159c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15a4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15ac, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15b4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15bc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15c4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15cc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15d4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15dc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15e4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15ec, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15f4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x15fc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1604, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x160c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1614, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x161c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1624, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x162c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1634, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x163c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1644, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x164c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1654, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x165c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1664, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x166c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1674, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x167c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1684, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x168c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1694, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x169c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16a4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16ac, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16b4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16bc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16c4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16cc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16d4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16dc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16e4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16ec, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16f4, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x16fc, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1704, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x170c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1714, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x171c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1724, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x172c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x1734, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_QUEUE_BASE_MAP_LOW", 0x173c, 0 }, + { "Ingress2_Base", 16, 16 }, + { "Ingress1_Base", 0, 16 }, + { "SGE_LA_RDPTR_0", 0x1800, 0 }, + { "SGE_LA_RDDATA_0", 0x1804, 0 }, + { "SGE_LA_WRPTR_0", 0x1808, 0 }, + { "SGE_LA_RESERVED_0", 0x180c, 0 }, + { "SGE_LA_RDPTR_1", 0x1810, 0 }, + { "SGE_LA_RDDATA_1", 0x1814, 0 }, + { "SGE_LA_WRPTR_1", 0x1818, 0 }, + { "SGE_LA_RESERVED_1", 0x181c, 0 }, + { "SGE_LA_RDPTR_2", 0x1820, 0 }, + { "SGE_LA_RDDATA_2", 0x1824, 0 }, + { "SGE_LA_WRPTR_2", 0x1828, 0 }, + { "SGE_LA_RESERVED_2", 0x182c, 0 }, + { "SGE_LA_RDPTR_3", 0x1830, 0 }, + { "SGE_LA_RDDATA_3", 0x1834, 0 }, + { "SGE_LA_WRPTR_3", 0x1838, 0 }, + { "SGE_LA_RESERVED_3", 0x183c, 0 }, + { "SGE_LA_RDPTR_4", 0x1840, 0 }, + { "SGE_LA_RDDATA_4", 0x1844, 0 }, + { "SGE_LA_WRPTR_4", 0x1848, 0 }, + { "SGE_LA_RESERVED_4", 0x184c, 0 }, + { "SGE_LA_RDPTR_5", 0x1850, 0 }, + { "SGE_LA_RDDATA_5", 0x1854, 0 }, + { "SGE_LA_WRPTR_5", 0x1858, 0 }, + { "SGE_LA_RESERVED_5", 0x185c, 0 }, + { "SGE_LA_RDPTR_6", 0x1860, 0 }, + { "SGE_LA_RDDATA_6", 0x1864, 0 }, + { "SGE_LA_WRPTR_6", 0x1868, 0 }, + { "SGE_LA_RESERVED_6", 0x186c, 0 }, + { "SGE_LA_RDPTR_7", 0x1870, 0 }, + { "SGE_LA_RDDATA_7", 0x1874, 0 }, + { "SGE_LA_WRPTR_7", 0x1878, 0 }, + { "SGE_LA_RESERVED_7", 0x187c, 0 }, + { "SGE_LA_RDPTR_8", 0x1880, 0 }, + { "SGE_LA_RDDATA_8", 0x1884, 0 }, + { "SGE_LA_WRPTR_8", 0x1888, 0 }, + { "SGE_LA_RESERVED_8", 0x188c, 0 }, + { "SGE_LA_RDPTR_9", 0x1890, 0 }, + { "SGE_LA_RDDATA_9", 0x1894, 0 }, + { "SGE_LA_WRPTR_9", 0x1898, 0 }, + { "SGE_LA_RESERVED_9", 0x189c, 0 }, + { "SGE_LA_RDPTR_10", 0x18a0, 0 }, + { "SGE_LA_RDDATA_10", 0x18a4, 0 }, + { "SGE_LA_WRPTR_10", 0x18a8, 0 }, + { "SGE_LA_RESERVED_10", 0x18ac, 0 }, + { "SGE_LA_RDPTR_11", 0x18b0, 0 }, + { "SGE_LA_RDDATA_11", 0x18b4, 0 }, + { "SGE_LA_WRPTR_11", 0x18b8, 0 }, + { "SGE_LA_RESERVED_11", 0x18bc, 0 }, + { "SGE_LA_RDPTR_12", 0x18c0, 0 }, + { "SGE_LA_RDDATA_12", 0x18c4, 0 }, + { "SGE_LA_WRPTR_12", 0x18c8, 0 }, + { "SGE_LA_RESERVED_12", 0x18cc, 0 }, + { "SGE_LA_RDPTR_13", 0x18d0, 0 }, + { "SGE_LA_RDDATA_13", 0x18d4, 0 }, + { "SGE_LA_WRPTR_13", 0x18d8, 0 }, + { "SGE_LA_RESERVED_13", 0x18dc, 0 }, + { "SGE_LA_RDPTR_14", 0x18e0, 0 }, + { "SGE_LA_RDDATA_14", 0x18e4, 0 }, + { "SGE_LA_WRPTR_14", 0x18e8, 0 }, + { "SGE_LA_RESERVED_14", 0x18ec, 0 }, + { "SGE_LA_RDPTR_15", 0x18f0, 0 }, + { "SGE_LA_RDDATA_15", 0x18f4, 0 }, + { "SGE_LA_WRPTR_15", 0x18f8, 0 }, + { "SGE_LA_RESERVED_15", 0x18fc, 0 }, + { NULL } +}; + +struct reg_info t5_pcie_regs[] = { + { "PCIE_INT_ENABLE", 0x3000, 0 }, + { "IPGrpPerr", 31, 1 }, + { "NonFatalErr", 30, 1 }, + { "RdRspErr", 29, 1 }, + { "TRGT1GrpPerr", 28, 1 }, + { "IPSOTPerr", 27, 1 }, + { "IPRetryPerr", 26, 1 }, + { "IPRxDataGrpPerr", 25, 1 }, + { "IPRxHdrGrpPerr", 24, 1 }, + { "PIOTagQPerr", 23, 1 }, + { "MAGrpPerr", 22, 1 }, + { "VFIDPerr", 21, 1 }, + { "FIDPerr", 20, 1 }, + { "CfgSnpPerr", 19, 1 }, + { "HRspPerr", 18, 1 }, + { "HReqRdPerr", 17, 1 }, + { "HReqWrPerr", 16, 1 }, + { "DRspPerr", 15, 1 }, + { "DReqRdPerr", 14, 1 }, + { "DReqWrPerr", 13, 1 }, + { "CRspPerr", 12, 1 }, + { "CReqRdPerr", 11, 1 }, + { "MstTagQPerr", 10, 1 }, + { "TgtTagQPerr", 9, 1 }, + { "PIOReqGrpPerr", 8, 1 }, + { "PIOCplGrpPerr", 7, 1 }, + { "MSIXDIPerr", 6, 1 }, + { "MSIXDataPerr", 5, 1 }, + { "MSIXAddrHPerr", 4, 1 }, + { "MSIXAddrLPerr", 3, 1 }, + { "MSIXStiPerr", 2, 1 }, + { "MstTimeoutPerr", 1, 1 }, + { "MstGrpPerr", 0, 1 }, + { "PCIE_INT_CAUSE", 0x3004, 0 }, + { "IPGrpPerr", 31, 1 }, + { "NonFatalErr", 30, 1 }, + { "RdRspErr", 29, 1 }, + { "TRGT1GrpPerr", 28, 1 }, + { "IPSOTPerr", 27, 1 }, + { "IPRetryPerr", 26, 1 }, + { "IPRxDataGrpPerr", 25, 1 }, + { "IPRxHdrGrpPerr", 24, 1 }, + { "PIOTagQPerr", 23, 1 }, + { "MAGrpPerr", 22, 1 }, + { "VFIDPerr", 21, 1 }, + { "FIDPerr", 20, 1 }, + { "CfgSnpPerr", 19, 1 }, + { "HRspPerr", 18, 1 }, + { "HReqRdPerr", 17, 1 }, + { "HReqWrPerr", 16, 1 }, + { "DRspPerr", 15, 1 }, + { "DReqRdPerr", 14, 1 }, + { "DReqWrPerr", 13, 1 }, + { "CRspPerr", 12, 1 }, + { "CReqRdPerr", 11, 1 }, + { "MstTagQPerr", 10, 1 }, + { "TgtTagQPerr", 9, 1 }, + { "PIOReqGrpPerr", 8, 1 }, + { "PIOCplGrpPerr", 7, 1 }, + { "MSIXDIPerr", 6, 1 }, + { "MSIXDataPerr", 5, 1 }, + { "MSIXAddrHPerr", 4, 1 }, + { "MSIXAddrLPerr", 3, 1 }, + { "MSIXStiPerr", 2, 1 }, + { "MstTimeoutPerr", 1, 1 }, + { "MstGrpPerr", 0, 1 }, + { "PCIE_PERR_ENABLE", 0x3008, 0 }, + { "IPGrpPerr", 31, 1 }, + { "TRGT1GrpPerr", 28, 1 }, + { "IPSOTPerr", 27, 1 }, + { "IPRetryPerr", 26, 1 }, + { "IPRxDataGrpPerr", 25, 1 }, + { "IPRxHdrGrpPerr", 24, 1 }, + { "PIOTagQPerr", 23, 1 }, + { "MAGrpPerr", 22, 1 }, + { "VFIDPerr", 21, 1 }, + { "FIDPerr", 20, 1 }, + { "CfgSnpPerr", 19, 1 }, + { "HRspPerr", 18, 1 }, + { "HReqRdPerr", 17, 1 }, + { "HReqWrPerr", 16, 1 }, + { "DRspPerr", 15, 1 }, + { "DReqRdPerr", 14, 1 }, + { "DReqWrPerr", 13, 1 }, + { "CRspPerr", 12, 1 }, + { "CReqRdPerr", 11, 1 }, + { "MstTagQPerr", 10, 1 }, + { "TgtTagQPerr", 9, 1 }, + { "PIOReqGrpPerr", 8, 1 }, + { "PIOCplGrpPerr", 7, 1 }, + { "MSIXDIPerr", 6, 1 }, + { "MSIXDataPerr", 5, 1 }, + { "MSIXAddrHPerr", 4, 1 }, + { "MSIXAddrLPerr", 3, 1 }, + { "MSIXStiPerr", 2, 1 }, + { "MstTimeoutPerr", 1, 1 }, + { "MstGrpPerr", 0, 1 }, + { "PCIE_PERR_INJECT", 0x300c, 0 }, + { "MemSel", 1, 5 }, + { "IDE", 0, 1 }, + { "PCIE_NONFAT_ERR", 0x3010, 0 }, + { "MAReqTimeout", 29, 1 }, + { "TRGT1BARTypeErr", 28, 1 }, + { "MAExtraRspErr", 27, 1 }, + { "MARspTimeout", 26, 1 }, + { "INTVFAllMSIDisErr", 25, 1 }, + { "INTVFRangeErr", 24, 1 }, + { "INTPLIRspErr", 23, 1 }, + { "MEMReqRdTagErr", 22, 1 }, + { "CFGInitDoneErr", 21, 1 }, + { "BAR2Timeout", 20, 1 }, + { "VPDTimeout", 19, 1 }, + { "MEMRspRdTagErr", 18, 1 }, + { "MEMRspWrTagErr", 17, 1 }, + { "PIORspRdTagErr", 16, 1 }, + { "PIORspWrTagErr", 15, 1 }, + { "DBITimeout", 14, 1 }, + { "PIOUnAlindWr", 13, 1 }, + { "BAR2RdErr", 12, 1 }, + { "MAWrEOPErr", 11, 1 }, + { "MARdEOPErr", 10, 1 }, + { "RdRspErr", 9, 1 }, + { "VPDRspErr", 8, 1 }, + { "MemReq", 4, 1 }, + { "PIOReq", 3, 1 }, + { "BAR2Req", 2, 1 }, + { "CfgSnp", 0, 1 }, + { "PCIE_CFG", 0x3014, 0 }, + { "PIOStopEn", 31, 1 }, + { "DiagCtrlBus", 28, 3 }, + { "IPPerrEn", 27, 1 }, + { "CfgdExtTagEn", 26, 1 }, + { "CfgdMaxPyldSz", 23, 3 }, + { "CfgdMaxRdReqSz", 20, 3 }, + { "DCAEn", 17, 1 }, + { "CMDReqPriority", 16, 1 }, + { "VPDReqProtect", 14, 2 }, + { "DroppedRdRspData", 12, 1 }, + { "AI_INTX_ReAssertEn", 11, 1 }, + { "AutoTxnDisable", 10, 1 }, + { "TC0_Stamp", 9, 1 }, + { "AI_TCVal", 6, 3 }, + { "DMAStopEn", 5, 1 }, + { "DevStateRstMode", 4, 1 }, + { "LinkReqRstPCIeCRstMode", 3, 1 }, + { "LinkDnRstEn", 0, 1 }, + { "PCIE_CFG2", 0x3018, 0 }, + { "VPDTimer", 16, 16 }, + { "BAR2Timer", 4, 12 }, + { "MstReqRdRRASimple", 3, 1 }, + { "TotMaxTag", 0, 2 }, + { "PCIE_CFG3", 0x301c, 0 }, + { "AutoPIOCookieMatch", 6, 1 }, + { "FLRPndCplMode", 4, 2 }, + { "HMADCASTFirstOnly", 2, 1 }, + { "CMDDCASTFirstOnly", 1, 1 }, + { "DMADCASTFirstOnly", 0, 1 }, + { "PCIE_CFG4", 0x3020, 0 }, + { "L1ClkRemovalEn", 17, 1 }, + { "ReadyEnterL23", 16, 1 }, + { "ExitL1", 12, 1 }, + { "EnterL1", 8, 1 }, + { "GenPME", 0, 8 }, + { "PCIE_CFG5", 0x3024, 0 }, + { "EnableSKPParityFix", 2, 1 }, + { "EnableL2EntryInL1", 1, 1 }, + { "HoldCplEnteringL1", 0, 1 }, + { "PCIE_CFG6", 0x3028, 0 }, + { "PERstTimerCount", 12, 14 }, + { "PERstTimeout", 8, 1 }, + { "PERstTimer", 0, 4 }, + { "PCIE_CFG_SPACE_REQ", 0x3060, 0 }, + { "Enable", 30, 1 }, + { "AI", 29, 1 }, + { "CS2", 28, 1 }, + { "WrBE", 24, 4 }, + { "VFVld", 23, 1 }, + { "RVF", 16, 7 }, + { "PF", 12, 3 }, + { "ExtRegister", 8, 4 }, + { "Register", 0, 8 }, + { "PCIE_CFG_SPACE_DATA", 0x3064, 0 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 }, + { "PCIEOfst", 10, 22 }, + { "BIR", 8, 2 }, + { "Window", 0, 8 }, + { "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 }, + { "MemOfst", 7, 25 }, + { "PFNum", 0, 3 }, + { "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 }, + { "PCIEOfst", 6, 26 }, + { "BIR", 4, 2 }, + { "Window", 0, 2 }, + { "PCIE_MAILBOX_OFFSET", 0x30ac, 0 }, + { "MemOfst", 7, 25 }, + { "PCIE_MA_CTRL", 0x30b0, 0 }, + { "TagFree", 29, 1 }, + { "MaxRspCnt", 24, 5 }, + { "MaxReqCnt", 16, 7 }, + { "MaxReqSize", 8, 3 }, + { "MaxTag", 0, 5 }, + { "PCIE_FW", 0x30b8, 0 }, + { "PCIE_FW_PF", 0x30bc, 0 }, + { "PCIE_FW_PF", 0x30c0, 0 }, + { "PCIE_FW_PF", 0x30c4, 0 }, + { "PCIE_FW_PF", 0x30c8, 0 }, + { "PCIE_FW_PF", 0x30cc, 0 }, + { "PCIE_FW_PF", 0x30d0, 0 }, + { "PCIE_FW_PF", 0x30d4, 0 }, + { "PCIE_FW_PF", 0x30d8, 0 }, + { "PCIE_PIO_PAUSE", 0x30dc, 0 }, + { "PIOPauseDone", 31, 1 }, + { "MSTPauseDone", 30, 1 }, + { "PauseTime", 4, 24 }, + { "MSTPause", 1, 1 }, + { "PIOPause", 0, 1 }, + { "PCIE_MA_STAT", 0x30e0, 0 }, + { "PCIE_STATIC_CFG1", 0x30e4, 0 }, + { "AUXPOWER_DETECTED", 27, 1 }, + { "PCIE_STATIC_CFG2", 0x30e8, 0 }, + { "PL_CONTROL", 16, 16 }, + { "STATIC_SPARE3", 0, 14 }, + { "PCIE_DBG_INDIR_REQ", 0x30ec, 0 }, + { "Enable", 31, 1 }, + { "AI", 30, 1 }, + { "Pointer", 8, 16 }, + { "Select", 0, 4 }, + { "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 }, + { "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 }, + { "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 }, + { "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 }, + { "PCIE_PF_INT_CFG", 0x3140, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x3144, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3148, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x314c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3150, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x3154, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3158, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x315c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3160, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x3164, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3168, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x316c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3170, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x3174, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_INT_CFG", 0x3178, 0 }, + { "PBAOfst", 28, 4 }, + { "TABOfst", 24, 4 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_PF_INT_CFG2", 0x317c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3180, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3184, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3188, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x318c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3190, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3194, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3198, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x319c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31a0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31a4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31a8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31ac, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31b0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31b4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31b8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31bc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31c0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31c4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31c8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31cc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31d0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31d4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31d8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31dc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31e0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31e4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31e8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31ec, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31f0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31f4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x31f8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x31fc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3200, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3204, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3208, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x320c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3210, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3214, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3218, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x321c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3220, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3224, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3228, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x322c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3230, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3234, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3238, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x323c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3240, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3244, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3248, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x324c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3250, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3254, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3258, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x325c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3260, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3264, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3268, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x326c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3270, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3274, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3278, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x327c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3280, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3284, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3288, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x328c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3290, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3294, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3298, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x329c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32a0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32a4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32a8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32ac, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32b0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32b4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32b8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32bc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32c0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32c4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32c8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32cc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32d0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32d4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32d8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32dc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32e0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32e4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32e8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32ec, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32f0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32f4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x32f8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x32fc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3300, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3304, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3308, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x330c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3310, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3314, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3318, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x331c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3320, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3324, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3328, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x332c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3330, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3334, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3338, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x333c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3340, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3344, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3348, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x334c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3350, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3354, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3358, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x335c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3360, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3364, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3368, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x336c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3370, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3374, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3378, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x337c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3380, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3384, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3388, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x338c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3390, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3394, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3398, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x339c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33a0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33a4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33a8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33ac, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33b0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33b4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33b8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33bc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33c0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33c4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33c8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33cc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33d0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33d4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33d8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33dc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33e0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33e4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33e8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33ec, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33f0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33f4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x33f8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x33fc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3400, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3404, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3408, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x340c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3410, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3414, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3418, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x341c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3420, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3424, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3428, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x342c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3430, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3434, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3438, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x343c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3440, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3444, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3448, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x344c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3450, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3454, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3458, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x345c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3460, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3464, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3468, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x346c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3470, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3474, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3478, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x347c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3480, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3484, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3488, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x348c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3490, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3494, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3498, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x349c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34a0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34a4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34a8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34ac, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34b0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34b4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34b8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34bc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34c0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34c4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34c8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34cc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34d0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34d4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34d8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34dc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34e0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34e4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34e8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34ec, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34f0, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34f4, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x34f8, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x34fc, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3500, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3504, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3508, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x350c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3510, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3514, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3518, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x351c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3520, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3524, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3528, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x352c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3530, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3534, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3538, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x353c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3540, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3544, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3548, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x354c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3550, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3554, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3558, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x355c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3560, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3564, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3568, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x356c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3570, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x3574, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_VF_INT_CFG", 0x3578, 0 }, + { "VecNum", 12, 10 }, + { "VecBase", 0, 11 }, + { "PCIE_VF_INT_CFG2", 0x357c, 0 }, + { "SendFLRRsp", 31, 1 }, + { "ImmFLRRsp", 24, 1 }, + { "TxnDisable", 20, 1 }, + { "PCIE_PF_MSI_EN", 0x35a8, 0 }, + { "PCIE_VF_MSI_EN_0", 0x35ac, 0 }, + { "PCIE_VF_MSI_EN_1", 0x35b0, 0 }, + { "PCIE_VF_MSI_EN_2", 0x35b4, 0 }, + { "PCIE_VF_MSI_EN_3", 0x35b8, 0 }, + { "PCIE_PF_MSIX_EN", 0x35bc, 0 }, + { "PCIE_VF_MSIX_EN_0", 0x35c0, 0 }, + { "PCIE_VF_MSIX_EN_1", 0x35c4, 0 }, + { "PCIE_VF_MSIX_EN_2", 0x35c8, 0 }, + { "PCIE_VF_MSIX_EN_3", 0x35cc, 0 }, + { "PCIE_FID_VFID_SEL", 0x35ec, 0 }, + { "PCIE_FID_VFID", 0x3600, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3604, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3608, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x360c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3610, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3614, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3618, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x361c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3620, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3624, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3628, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x362c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3630, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3634, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3638, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x363c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3640, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3644, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3648, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x364c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3650, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3654, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3658, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x365c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3660, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3664, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3668, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x366c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3670, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3674, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3678, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x367c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3680, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3684, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3688, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x368c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3690, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3694, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3698, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x369c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36a0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36a4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36a8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36ac, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36b0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36b4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36b8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36bc, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36c0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36c4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36c8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36cc, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36d0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36d4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36d8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36dc, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36e0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36e4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36e8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36ec, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36f0, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36f4, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36f8, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x36fc, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3700, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3704, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3708, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x370c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3710, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3714, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3718, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x371c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3720, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3724, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3728, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x372c, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3730, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3734, 0 }, + { "Select", 30, 2 }, + { "IDO", 24, 1 }, + { "VFID", 16, 8 }, + { "TC", 11, 3 }, + { "VFVld", 10, 1 }, + { "PF", 7, 3 }, + { "RVF", 0, 7 }, + { "PCIE_FID_VFID", 0x3738, 0 }, + { "Select", 30, 2 }, + { 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"CookieA", 0, 10 }, + { "PCIE_COOKIE_STAT", 0x5614, 0 }, + { "CookieB", 16, 10 }, + { "CookieA", 0, 10 }, + { "PCIE_COOKIE_STAT", 0x5618, 0 }, + { "CookieB", 16, 10 }, + { "CookieA", 0, 10 }, + { "PCIE_COOKIE_STAT", 0x561c, 0 }, + { "CookieB", 16, 10 }, + { "CookieA", 0, 10 }, + { "PCIE_FLR_PIO", 0x5620, 0 }, + { "RcvdBAR2Cookie", 24, 8 }, + { "RcvdMARspCookie", 16, 8 }, + { "RcvdPIORspCookie", 8, 8 }, + { "ExpdCookie", 0, 8 }, + { "PCIE_FLR_PIO2", 0x5624, 0 }, + { "RcvdMAReqCookie", 16, 8 }, + { "RcvdPIOReqCookie", 8, 8 }, + { "PCIE_VC0_CDTS0", 0x56cc, 0 }, + { "CPLD0", 20, 12 }, + { "PH0", 12, 8 }, + { "PD0", 0, 12 }, + { "PCIE_VC0_CDTS1", 0x56d0, 0 }, + { "CPLH0", 20, 8 }, + { "NPH0", 12, 8 }, + { "NPD0", 0, 12 }, + { "PCIE_VC1_CDTS0", 0x56d4, 0 }, + { "CPLD1", 20, 12 }, + { "PH1", 12, 8 }, + { "PD1", 0, 12 }, + { "PCIE_VC1_CDTS1", 0x56d8, 0 }, + { "CPLH1", 20, 8 }, + { "NPH1", 12, 8 }, + { "NPD1", 0, 12 }, + { "PCIE_FLR_PF_STATUS", 0x56dc, 0 }, + { "PCIE_FLR_VF0_STATUS", 0x56e0, 0 }, + { "PCIE_FLR_VF1_STATUS", 0x56e4, 0 }, + { "PCIE_FLR_VF2_STATUS", 0x56e8, 0 }, + { "PCIE_FLR_VF3_STATUS", 0x56ec, 0 }, + { "PCIE_STAT", 0x56f4, 0 }, + { "PM_Status", 24, 8 }, + { "PM_CurrentState", 20, 3 }, + { "LTSSMEnable", 12, 1 }, + { "StateCfgInitF", 4, 7 }, + { "StateCfgInit", 0, 4 }, + { "PCIE_CRS", 0x56f8, 0 }, + { "PCIE_LTSSM", 0x56fc, 0 }, + { "PCIE_PF_CFG", 0x1e040, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1e044, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1e440, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1e444, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1e840, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1e844, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1ec40, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1ec44, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1f040, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1f044, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1f440, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1f444, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1f840, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1f844, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_PF_CFG", 0x1fc40, 0 }, + { "INTXStat", 16, 1 }, + { "AIVec", 4, 10 }, + { "D3HotEn", 1, 1 }, + { "CLIDecEn", 0, 1 }, + { "PCIE_PF_CLI", 0x1fc44, 0 }, + { "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 }, + { "Offset", 10, 14 }, + { "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 }, + { "Replay_Time_Limit", 16, 16 }, + { "Ack_Latency_Timer_Limit", 0, 16 }, + { "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 }, + { "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 }, + { "Low_Power_Entrance_Count", 24, 8 }, + { "Link_State", 16, 6 }, + { "Force_Link", 15, 1 }, + { "Link_Number", 0, 8 }, + { "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 }, + { "Enter_ASPM_L1_wo_L0s", 30, 1 }, + { "L1_Entrance_Latency", 27, 3 }, + { "L0s_Entrance_Latency", 24, 3 }, + { "Common_Clock_N_FTS", 16, 8 }, + { "N_FTS", 8, 8 }, + { "Ack_Frequency", 0, 8 }, + { "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 }, + { "Crosslink_Active", 23, 1 }, + { "Crosslink_Enable", 22, 1 }, + { "Link_Mode_Enable", 16, 6 }, + { "Fast_Link_Mode", 7, 1 }, + { "DLL_Link_Enable", 5, 1 }, + { "Reset_Assert", 3, 1 }, + { "Loopback_Enable", 2, 1 }, + { "Scramble_Disable", 1, 1 }, + { "Vendor_Specific_DLLP_Request", 0, 1 }, + { "PCIE_CORE_LANE_SKEW", 0x5714, 0 }, + { "Disable_DeSkew", 31, 1 }, + { "Ack_Nak_Disable", 25, 1 }, + { "Flow_Control_Disable", 24, 1 }, + { "Insert_TxSkew", 0, 24 }, + { "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 }, + { "Flow_Control_Timer_Modifier", 24, 5 }, + { "Ack_Nak_Timer_Modifier", 19, 5 }, + { "Replay_Timer_Modifier", 14, 5 }, + { "MaxFunc", 0, 3 }, + { "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 }, + { "Mask_RADM_Filter", 16, 16 }, + { "Disable_FC_Watchdog", 15, 1 }, + { "SKP_Interval", 0, 11 }, + { "PCIE_CORE_FILTER_MASK2", 0x5720, 0 }, + { "PCIE_CORE_DEBUG_0", 0x5728, 0 }, + { "PCIE_CORE_DEBUG_1", 0x572c, 0 }, + { "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 }, + { "TxPH_FC", 12, 8 }, + { "TxPD_FC", 0, 12 }, + { "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 }, + { "TxNPH_FC", 12, 8 }, + { "TxNPD_FC", 0, 12 }, + { "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 }, + { "TxCPLH_FC", 12, 8 }, + { "TxCPLD_FC", 0, 12 }, + { "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 }, + { "RxQueue_Not_Empty", 2, 1 }, + { "TxRetryBuf_Not_Empty", 1, 1 }, + { "RxTLP_FC_Not_Returned", 0, 1 }, + { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 }, + { "VC3_WRR", 24, 8 }, + { "VC2_WRR", 16, 8 }, + { "VC1_WRR", 8, 8 }, + { "VC0_WRR", 0, 8 }, + { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 }, + { "VC7_WRR", 24, 8 }, + { "VC6_WRR", 16, 8 }, + { "VC5_WRR", 8, 8 }, + { "VC4_WRR", 0, 8 }, + { "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 }, + { "VC0_Rx_Ordering", 31, 1 }, + { "VC0_TLP_Ordering", 30, 1 }, + { "VC0_PTLP_Queue_Mode", 21, 3 }, + { "VC0_PH_Credits", 12, 8 }, + { "VC0_PD_Credits", 0, 12 }, + { "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 }, + { "VC0_NPTLP_Queue_Mode", 21, 3 }, + { "VC0_NPH_Credits", 12, 8 }, + { "VC0_NPD_Credits", 0, 12 }, + { "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 }, + { "VC0_CPLTLP_Queue_Mode", 21, 3 }, + { "VC0_CPLH_Credits", 12, 8 }, + { "VC0_CPLD_Credits", 0, 12 }, + { "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 }, + { "VC1_TLP_Ordering", 30, 1 }, + { "VC1_PTLP_Queue_Mode", 21, 3 }, + { "VC1_PH_Credits", 12, 8 }, + { "VC1_PD_Credits", 0, 12 }, + { "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 }, + { "VC1_NPTLP_Queue_Mode", 21, 3 }, + { "VC1_NPH_Credits", 12, 8 }, + { "VC1_NPD_Credits", 0, 12 }, + { "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 }, + { "VC1_CPLTLP_Queue_Mode", 21, 3 }, + { "VC1_CPLH_Credits", 12, 8 }, + { "VC1_CPLD_Credits", 0, 12 }, + { "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 }, + { "Sel_DeEmphasis", 20, 1 }, + { "TxCmplRcv", 19, 1 }, + { "PhyTxSwing", 18, 1 }, + { "DirSpdChange", 17, 1 }, + { "Num_Lanes", 8, 9 }, + { "NFTS_Gen2_3", 0, 8 }, + { "PCIE_CORE_PHY_STATUS", 0x5810, 0 }, + { "PCIE_CORE_PHY_CONTROL", 0x5814, 0 }, + { "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 }, + { "DC_Balance_Disable", 18, 1 }, + { "DLLP_Delay_Disable", 17, 1 }, + { "Eql_Disable", 16, 1 }, + { "Eql_Redo_Disable", 11, 1 }, + { "Eql_EIEOS_CntRst_Disable", 10, 1 }, + { "Eql_PH2_PH3_Disable", 9, 1 }, + { "Disable_Scrambler", 8, 1 }, + { "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 }, + { "Full_Swing", 6, 6 }, + { "Low_Frequency", 0, 6 }, + { "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 }, + { "PostCursor", 12, 6 }, + { "Cursor", 6, 6 }, + { "PreCursor", 0, 6 }, + { "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 }, + { "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 }, + { "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 }, + { "Include_Initial_FOM", 24, 1 }, + { "Preset_Request_Vector", 8, 16 }, + { "Phase23_2ms_Timeout_Disable", 5, 1 }, + { "After24ms", 4, 1 }, + { "Feedback_Mode", 0, 4 }, + { "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 }, + { "WinAperture_CPlus1", 14, 4 }, + { "WinAperture_CMins1", 10, 4 }, + { "Convergence_WinDepth", 5, 5 }, + { "EQMasterPhase_MinTime", 0, 5 }, + { "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 }, + { "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 }, + { "PCIE_DMA_CFG", 0x5940, 0 }, + { "MaxPyldSize", 28, 3 }, + { "MaxReqCnt", 20, 8 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 9 }, + { "SeqChkDis", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_DMA_STAT", 0x5944, 0 }, + { "RspCnt", 20, 12 }, + { "RdReqCnt", 12, 8 }, + { "WrReqCnt", 0, 11 }, + { "PCIE_DMA_STAT2", 0x5948, 0 }, + { "CookieCnt", 24, 4 }, + { "RdSeqNumUpdCnt", 20, 4 }, + { "SIReqCnt", 16, 4 }, + { "WrEOPMatchSOP", 12, 1 }, + { "WrSOPCnt", 8, 4 }, + { "RdSOPCnt", 0, 8 }, + { "PCIE_DMA_STAT3", 0x594c, 0 }, + { "AtmReqSOPCnt", 24, 8 }, + { "AtmEOPMatchSOP", 17, 1 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_DMA_CFG", 0x5950, 0 }, + { "MaxPyldSize", 28, 3 }, + { "MaxReqCnt", 20, 8 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 9 }, + { "SeqChkDis", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_DMA_STAT", 0x5954, 0 }, + { "RspCnt", 20, 12 }, + { "RdReqCnt", 12, 8 }, + { "WrReqCnt", 0, 11 }, + { "PCIE_DMA_STAT2", 0x5958, 0 }, + { "CookieCnt", 24, 4 }, + { "RdSeqNumUpdCnt", 20, 4 }, + { "SIReqCnt", 16, 4 }, + { "WrEOPMatchSOP", 12, 1 }, + { "WrSOPCnt", 8, 4 }, + { "RdSOPCnt", 0, 8 }, + { "PCIE_DMA_STAT3", 0x595c, 0 }, + { "AtmReqSOPCnt", 24, 8 }, + { "AtmEOPMatchSOP", 17, 1 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_DMA_CFG", 0x5960, 0 }, + { "MaxPyldSize", 28, 3 }, + { "MaxReqCnt", 20, 8 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 9 }, + { "SeqChkDis", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_DMA_STAT", 0x5964, 0 }, + { "RspCnt", 20, 12 }, + { "RdReqCnt", 12, 8 }, + { "WrReqCnt", 0, 11 }, + { "PCIE_DMA_STAT2", 0x5968, 0 }, + { "CookieCnt", 24, 4 }, + { "RdSeqNumUpdCnt", 20, 4 }, + { "SIReqCnt", 16, 4 }, + { "WrEOPMatchSOP", 12, 1 }, + { "WrSOPCnt", 8, 4 }, + { "RdSOPCnt", 0, 8 }, + { "PCIE_DMA_STAT3", 0x596c, 0 }, + { "AtmReqSOPCnt", 24, 8 }, + { "AtmEOPMatchSOP", 17, 1 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_DMA_CFG", 0x5970, 0 }, + { "MaxPyldSize", 28, 3 }, + { "MaxReqCnt", 20, 8 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 9 }, + { "SeqChkDis", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_DMA_STAT", 0x5974, 0 }, + { "RspCnt", 20, 12 }, + { "RdReqCnt", 12, 8 }, + { "WrReqCnt", 0, 11 }, + { "PCIE_DMA_STAT2", 0x5978, 0 }, + { "CookieCnt", 24, 4 }, + { "RdSeqNumUpdCnt", 20, 4 }, + { "SIReqCnt", 16, 4 }, + { "WrEOPMatchSOP", 12, 1 }, + { "WrSOPCnt", 8, 4 }, + { "RdSOPCnt", 0, 8 }, + { "PCIE_DMA_STAT3", 0x597c, 0 }, + { "AtmReqSOPCnt", 24, 8 }, + { "AtmEOPMatchSOP", 17, 1 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_CMD_CFG", 0x5980, 0 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 8 }, + { "UseCmdPool", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_CMD_STAT", 0x5984, 0 }, + { "RspCnt", 20, 11 }, + { "RdReqCnt", 12, 5 }, + { "PCIE_CMD_STAT2", 0x5988, 0 }, + { "PCIE_CMD_STAT3", 0x598c, 0 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_CMD_CFG", 0x5990, 0 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 8 }, + { "UseCmdPool", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_CMD_STAT", 0x5994, 0 }, + { "RspCnt", 20, 11 }, + { "RdReqCnt", 12, 5 }, + { "PCIE_CMD_STAT2", 0x5998, 0 }, + { "PCIE_CMD_STAT3", 0x599c, 0 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_CMD_CFG", 0x59a0, 0 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 8 }, + { "UseCmdPool", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_CMD_STAT", 0x59a4, 0 }, + { "RspCnt", 20, 11 }, + { "RdReqCnt", 12, 5 }, + { "PCIE_CMD_STAT2", 0x59a8, 0 }, + { "PCIE_CMD_STAT3", 0x59ac, 0 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_HMA_CFG", 0x59b0, 0 }, + { "MaxPyldSize", 28, 3 }, + { "MaxReqCnt", 20, 5 }, + { "MaxRdReqSize", 17, 3 }, + { "MaxRspCnt", 8, 5 }, + { "SeqChkDis", 7, 1 }, + { "MinTag", 0, 7 }, + { "PCIE_HMA_STAT", 0x59b4, 0 }, + { "RspCnt", 20, 9 }, + { "RdReqCnt", 12, 6 }, + { "WrReqCnt", 0, 9 }, + { "PCIE_HMA_STAT2", 0x59b8, 0 }, + { "CookieCnt", 24, 4 }, + { "RdSeqNumUpdCnt", 20, 4 }, + { "WrEOPMatchSOP", 12, 1 }, + { "WrSOPCnt", 8, 4 }, + { "RdSOPCnt", 0, 8 }, + { "PCIE_HMA_STAT3", 0x59bc, 0 }, + { "RspEOPMatchSOP", 16, 1 }, + { "RspErrCnt", 8, 8 }, + { "RspSOPCnt", 0, 8 }, + { "PCIE_CGEN", 0x59c0, 0 }, + { "VPD_Dynamic_CGEN", 26, 1 }, + { "MA_Dynamic_CGEN", 25, 1 }, + { "Tagq_Dynamic_CGEN", 24, 1 }, + { "ReqCtl_Dynamic_CGEN", 23, 1 }, + { "RspDataProc_Dynamic_CGEN", 22, 1 }, + { "RspRdq_Dynamic_CGEN", 21, 1 }, + { "RspIPif_Dynamic_CGEN", 20, 1 }, + { "HMA_Static_CGEN", 19, 1 }, + { "HMA_Dynamic_CGEN", 18, 1 }, + { "CMD_Static_CGEN", 16, 1 }, + { "CMD_Dynamic_CGEN", 15, 1 }, + { "DMA_Static_CGEN", 13, 1 }, + { "DMA_Dynamic_CGEN", 12, 1 }, + { "VFID_SleepStatus", 10, 1 }, + { "VC1_SleepStatus", 9, 1 }, + { "STI_SleepStatus", 8, 1 }, + { "VFID_SleepReq", 2, 1 }, + { "VC1_SleepReq", 1, 1 }, + { "STI_SleepReq", 0, 1 }, + { "PCIE_MA_RSP", 0x59c4, 0 }, + { "TimerValue", 8, 24 }, + { "MAReqTimerEn", 1, 1 }, + { "TimerEn", 0, 1 }, + { "PCIE_HPRD", 0x59c8, 0 }, + { "NPH_CreditsAvailVC0", 19, 2 }, + { "NPD_CreditsAvailVC0", 17, 2 }, + { "NPH_CreditsAvailVC1", 15, 2 }, + { "NPD_CreditsAvailVC1", 13, 2 }, + { "NPH_CreditsRequired", 11, 2 }, + { "NPD_CreditsRequired", 9, 2 }, + { "ReqBurstCount", 5, 4 }, + { "ReqBurstFrequency", 1, 4 }, + { "EnableVC1", 0, 1 }, + { "PCIE_PERR_GROUP", 0x59d0, 0 }, + { "MST_DataPathPerr", 25, 1 }, + { "MST_RspRdQPerr", 24, 1 }, + { "IP_RxPerr", 23, 1 }, + { "IP_BackTxPerr", 22, 1 }, + { "IP_FrontTxPerr", 21, 1 }, + { "TRGT1_FIDLkUpHdrPerr", 20, 1 }, + { "TRGT1_AlindDataPerr", 19, 1 }, + { "TRGT1_UnAlinDataPerr", 18, 1 }, + { "TRGT1_ReqDataPerr", 17, 1 }, + { "TRGT1_ReqHdrPerr", 16, 1 }, + { "IPRxData_VC1Perr", 15, 1 }, + { "IPRxData_VC0Perr", 14, 1 }, + { "IPRxHdr_VC1Perr", 13, 1 }, + { "IPRxHdr_VC0Perr", 12, 1 }, + { "MA_RspDataPerr", 11, 1 }, + { "MA_CplTagQPerr", 10, 1 }, + { "MA_ReqTagQPerr", 9, 1 }, + { "PIOReq_BAR2CtlPerr", 8, 1 }, + { "PIOReq_MEMCtlPerr", 7, 1 }, + { "PIOReq_PLMCtlPerr", 6, 1 }, + { "PIOReq_BAR2DataPerr", 5, 1 }, + { "PIOReq_MEMDataPerr", 4, 1 }, + { "PIOReq_PLMDataPerr", 3, 1 }, + { "PIOCpl_CtlPerr", 2, 1 }, + { "PIOCpl_DataPerr", 1, 1 }, + { "PIOCpl_PLMRspPerr", 0, 1 }, + { "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 }, + { "CplStatusIntEn", 12, 1 }, + { "TimeoutIntEn", 11, 1 }, + { "DisabledIntEn", 10, 1 }, + { "RspDropFLRIntEn", 9, 1 }, + { "ReqUnderFLRIntEn", 8, 1 }, + { "CplStatusLogEn", 4, 1 }, + { "TimeoutLogEn", 3, 1 }, + { "DisabledLogEn", 2, 1 }, + { "RspDropFLRLogEn", 1, 1 }, + { "ReqUnderFLRLogEn", 0, 1 }, + { "PCIE_RSP_ERR_LOG1", 0x59d8, 0 }, + { "Tag", 25, 7 }, + { "CID", 22, 3 }, + { "ChNum", 19, 3 }, + { "ByteLen", 6, 13 }, + { "Reason", 3, 3 }, + { "CplStatus", 0, 3 }, + { "PCIE_RSP_ERR_LOG2", 0x59dc, 0 }, + { "Valid", 31, 1 }, + { "Addr10b", 8, 10 }, + { "VFID", 0, 8 }, + { "PCIE_REVISION", 0x5a00, 0 }, + { "PCIE_PDEBUG_INDEX", 0x5a04, 0 }, + { "PDEBUGSelH", 16, 6 }, + { "PDEBUGSelL", 0, 6 }, + { "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 }, + { "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 }, + { "PCIE_CDEBUG_INDEX", 0x5a10, 0 }, + { "CDEBUGSelH", 16, 8 }, + { "CDEBUGSelL", 0, 8 }, + { "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 }, + { "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 }, + { "PCIE_BUS_MST_STAT_0", 0x5a60, 0 }, + { "PCIE_BUS_MST_STAT_1", 0x5a64, 0 }, + { "PCIE_BUS_MST_STAT_2", 0x5a68, 0 }, + { "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 }, + { "PCIE_BUS_MST_STAT_4", 0x5a70, 0 }, + { "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 }, + { "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 }, + { "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 }, + { "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 }, + { "PCIE_RSP_ERR_STAT_4", 0x5a90, 0 }, + { "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 }, + { "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 }, + { "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 }, + { "Valid", 31, 1 }, + { "Source", 16, 2 }, + { "Write", 12, 4 }, + { "CS2", 11, 1 }, + { "PF", 8, 3 }, + { "VFVld", 7, 1 }, + { "VF", 0, 7 }, + { "PCIE_PB_CTL", 0x5b94, 0 }, + { "PB_Sel", 16, 8 }, + { "PB_SelReg", 8, 8 }, + { "PB_Func", 0, 3 }, + { "PCIE_PB_DATA", 0x5b98, 0 }, + { "PCIE_CHANGESET", 0x59fc, 0 }, + { "PCIE_CUR_LINK", 0x5b9c, 0 }, + { "CfgInitCoeffDoneSeen", 22, 1 }, + { "CfgInitCoeffDone", 21, 1 }, + { "xmlh_link_up", 20, 1 }, + { "pm_linkst_in_l0s", 19, 1 }, + { "pm_linkst_in_l1", 18, 1 }, + { "pm_linkst_in_l2", 17, 1 }, + { "pm_linkst_l2_exit", 16, 1 }, + { "xmlh_in_rl0s", 15, 1 }, + { "xmlh_ltssm_state_rcvry_eq", 14, 1 }, + { "NegotiatedWidth", 8, 6 }, + { "ActiveLanes", 0, 8 }, + { "PCIE_PHY_REQRXPWR", 0x5ba0, 0 }, + { "LnH_RxStateDone", 31, 1 }, + { "LnH_RxStateReq", 30, 1 }, + { "LnH_RxPwrState", 28, 2 }, + { "LnG_RxStateDone", 27, 1 }, + { "LnG_RxStateReq", 26, 1 }, + { "LnG_RxPwrState", 24, 2 }, + { "LnF_RxStateDone", 23, 1 }, + { "LnF_RxStateReq", 22, 1 }, + { "LnF_RxPwrState", 20, 2 }, + { "LnE_RxStateDone", 19, 1 }, + { "LnE_RxStateReq", 18, 1 }, + { "LnE_RxPwrState", 16, 2 }, + { "LnD_RxStateDone", 15, 1 }, + { "LnD_RxStateReq", 14, 1 }, + { "LnD_RxPwrState", 12, 2 }, + { "LnC_RxStateDone", 11, 1 }, + { "LnC_RxStateReq", 10, 1 }, + { "LnC_RxPwrState", 8, 2 }, + { "LnB_RxStateDone", 7, 1 }, + { "LnB_RxStateReq", 6, 1 }, + { "LnB_RxPwrState", 4, 2 }, + { "LnA_RxStateDone", 3, 1 }, + { "LnA_RxStateReq", 2, 1 }, + { "LnA_RxPwrState", 0, 2 }, + { "PCIE_PHY_CURRXPWR", 0x5ba4, 0 }, + { "LnH_RxPwrState", 28, 3 }, + { "LnG_RxPwrState", 24, 3 }, + { "LnF_RxPwrState", 20, 3 }, + { "LnE_RxPwrState", 16, 3 }, + { "LnD_RxPwrState", 12, 3 }, + { "LnC_RxPwrState", 8, 3 }, + { "LnB_RxPwrState", 4, 3 }, + { "LnA_RxPwrState", 0, 3 }, + { "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 }, + { "LnD_STAT", 28, 3 }, + { "LnD_CMD", 24, 3 }, + { "LnC_STAT", 20, 3 }, + { "LnC_CMD", 16, 3 }, + { "LnB_STAT", 12, 3 }, + { "LnB_CMD", 8, 3 }, + { "LnA_STAT", 4, 3 }, + { "LnA_CMD", 0, 3 }, + { "PCIE_PHY_GEN3_AE1", 0x5bac, 0 }, + { "LnH_STAT", 28, 3 }, + { "LnH_CMD", 24, 3 }, + { "LnG_STAT", 20, 3 }, + { "LnG_CMD", 16, 3 }, + { "LnF_STAT", 12, 3 }, + { "LnF_CMD", 8, 3 }, + { "LnE_STAT", 4, 3 }, + { "LnE_CMD", 0, 3 }, + { "PCIE_PHY_FS_LF0", 0x5bb0, 0 }, + { "Lane1LF", 24, 6 }, + { "Lane1FS", 16, 6 }, + { "Lane0LF", 8, 6 }, + { "Lane0FS", 0, 6 }, + { "PCIE_PHY_FS_LF1", 0x5bb4, 0 }, + { "Lane3LF", 24, 6 }, + { "Lane3FS", 16, 6 }, + { "Lane2LF", 8, 6 }, + { "Lane2FS", 0, 6 }, + { "PCIE_PHY_FS_LF2", 0x5bb8, 0 }, + { "Lane5LF", 24, 6 }, + { "Lane5FS", 16, 6 }, + { "Lane4LF", 8, 6 }, + { "Lane4FS", 0, 6 }, + { "PCIE_PHY_FS_LF3", 0x5bbc, 0 }, + { "Lane7LF", 24, 6 }, + { "Lane7FS", 16, 6 }, + { "Lane6LF", 8, 6 }, + { "Lane6FS", 0, 6 }, + { "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 }, + { "CoeffDone", 16, 1 }, + { "CoeffLane", 8, 3 }, + { "CoeffStart", 0, 1 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 }, + { "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 }, + { "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 }, + { "Enable", 31, 1 }, + { "RegAddr", 0, 16 }, + { "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 }, + { "PCIE_STATIC_SPARE1", 0x5bf8, 0 }, + { "PCIE_STATIC_SPARE2", 0x5bfc, 0 }, + { NULL } +}; + +struct reg_info t5_dbg_regs[] = { + { "DBG_DBG0_CFG", 0x6000, 0 }, + { "ModuleSelect", 12, 8 }, + { "RegSelect", 4, 8 }, + { "ClkSelect", 0, 4 }, + { "DBG_DBG0_EN", 0x6004, 0 }, + { "SDRHalfWord0", 8, 1 }, + { "DDREn", 4, 1 }, + { "PortEn", 0, 1 }, + { "DBG_DBG1_CFG", 0x6008, 0 }, + { "ModuleSelect", 12, 8 }, + { "RegSelect", 4, 8 }, + { "ClkSelect", 0, 4 }, + { "DBG_DBG1_EN", 0x600c, 0 }, + { "Clk_en_on_dbg1", 20, 1 }, + { "SDRHalfWord0", 8, 1 }, + { "DDREn", 4, 1 }, + { "PortEn", 0, 1 }, + { "DBG_GPIO_EN", 0x6010, 0 }, + { "GPIO15_OEn", 31, 1 }, + { "GPIO14_OEn", 30, 1 }, + { "GPIO13_OEn", 29, 1 }, + { "GPIO12_OEn", 28, 1 }, + { "GPIO11_OEn", 27, 1 }, + { "GPIO10_OEn", 26, 1 }, + { "GPIO9_OEn", 25, 1 }, + { "GPIO8_OEn", 24, 1 }, + { "GPIO7_OEn", 23, 1 }, + { "GPIO6_OEn", 22, 1 }, + { "GPIO5_OEn", 21, 1 }, + { "GPIO4_OEn", 20, 1 }, + { "GPIO3_OEn", 19, 1 }, + { "GPIO2_OEn", 18, 1 }, + { "GPIO1_OEn", 17, 1 }, + { "GPIO0_OEn", 16, 1 }, + { "GPIO15_Out_Val", 15, 1 }, + { "GPIO14_Out_Val", 14, 1 }, + { "GPIO13_Out_Val", 13, 1 }, + { "GPIO12_Out_Val", 12, 1 }, + { "GPIO11_Out_Val", 11, 1 }, + { "GPIO10_Out_Val", 10, 1 }, + { "GPIO9_Out_Val", 9, 1 }, + { "GPIO8_Out_Val", 8, 1 }, + { "GPIO7_Out_Val", 7, 1 }, + { "GPIO6_Out_Val", 6, 1 }, + { "GPIO5_Out_Val", 5, 1 }, + { "GPIO4_Out_Val", 4, 1 }, + { "GPIO3_Out_Val", 3, 1 }, + { "GPIO2_Out_Val", 2, 1 }, + { "GPIO1_Out_Val", 1, 1 }, + { "GPIO0_Out_Val", 0, 1 }, + { "DBG_GPIO_IN", 0x6014, 0 }, + { "GPIO15_CHG_DET", 31, 1 }, + { "GPIO14_CHG_DET", 30, 1 }, + { "GPIO13_CHG_DET", 29, 1 }, + { "GPIO12_CHG_DET", 28, 1 }, + { "GPIO11_CHG_DET", 27, 1 }, + { "GPIO10_CHG_DET", 26, 1 }, + { "GPIO9_CHG_DET", 25, 1 }, + { "GPIO8_CHG_DET", 24, 1 }, + { "GPIO7_CHG_DET", 23, 1 }, + { "GPIO6_CHG_DET", 22, 1 }, + { "GPIO5_CHG_DET", 21, 1 }, + { "GPIO4_CHG_DET", 20, 1 }, + { "GPIO3_CHG_DET", 19, 1 }, + { "GPIO2_CHG_DET", 18, 1 }, + { "GPIO1_CHG_DET", 17, 1 }, + { "GPIO0_CHG_DET", 16, 1 }, + { "GPIO15_IN", 15, 1 }, + { "GPIO14_IN", 14, 1 }, + { "GPIO13_IN", 13, 1 }, + { "GPIO12_IN", 12, 1 }, + { "GPIO11_IN", 11, 1 }, + { "GPIO10_IN", 10, 1 }, + { "GPIO9_IN", 9, 1 }, + { "GPIO8_IN", 8, 1 }, + { "GPIO7_IN", 7, 1 }, + { "GPIO6_IN", 6, 1 }, + { "GPIO5_IN", 5, 1 }, + { "GPIO4_IN", 4, 1 }, + { "GPIO3_IN", 3, 1 }, + { "GPIO2_IN", 2, 1 }, + { "GPIO1_IN", 1, 1 }, + { "GPIO0_IN", 0, 1 }, + { "DBG_GPIO_EN_NEW", 0x6100, 0 }, + { "GPIO16_OEn", 7, 1 }, + { "GPIO17_OEn", 6, 1 }, + { "GPIO18_OEn", 5, 1 }, + { "GPIO19_OEn", 4, 1 }, + { "GPIO16_Out_Val", 3, 1 }, + { "GPIO17_Out_Val", 2, 1 }, + { "GPIO18_Out_Val", 1, 1 }, + { "GPIO19_Out_Val", 0, 1 }, + { "DBG_GPIO_IN_NEW", 0x6104, 0 }, + { "GPIO16_CHG_DET", 7, 1 }, + { "GPIO17_CHG_DET", 6, 1 }, + { "GPIO18_CHG_DET", 5, 1 }, + { "GPIO19_CHG_DET", 4, 1 }, + { "GPIO16_IN", 3, 1 }, + { "GPIO17_IN", 2, 1 }, + { "GPIO18_IN", 1, 1 }, + { "GPIO19_IN", 0, 1 }, + { "DBG_INT_ENABLE", 0x6018, 0 }, + { "GPIO19", 29, 1 }, + { "GPIO18", 28, 1 }, + { "GPIO17", 27, 1 }, + { "GPIO16", 26, 1 }, + { "IBM_FDL_FAIL_int_enbl", 25, 1 }, + { "pll_lock_lost_int_enbl", 22, 1 }, + { "C_LOCK", 21, 1 }, + { "M_LOCK", 20, 1 }, + { "U_LOCK", 19, 1 }, + { "PCIe_LOCK", 18, 1 }, + { "KX_LOCK", 17, 1 }, + { "KR_LOCK", 16, 1 }, + { "GPIO15", 15, 1 }, + { "GPIO14", 14, 1 }, + { "GPIO13", 13, 1 }, + { "GPIO12", 12, 1 }, + { "GPIO11", 11, 1 }, + { "GPIO10", 10, 1 }, + { "GPIO9", 9, 1 }, + { "GPIO8", 8, 1 }, + { "GPIO7", 7, 1 }, + { "GPIO6", 6, 1 }, + { "GPIO5", 5, 1 }, + { "GPIO4", 4, 1 }, + { "GPIO3", 3, 1 }, + { "GPIO2", 2, 1 }, + { "GPIO1", 1, 1 }, + { "GPIO0", 0, 1 }, + { "DBG_INT_CAUSE", 0x601c, 0 }, + { "GPIO19", 29, 1 }, + { "GPIO18", 28, 1 }, + { "GPIO17", 27, 1 }, + { "GPIO16", 26, 1 }, + { "IBM_FDL_FAIL_int_cause", 25, 1 }, + { "pll_lock_lost_int_cause", 22, 1 }, + { "C_LOCK", 21, 1 }, + { "M_LOCK", 20, 1 }, + { "U_LOCK", 19, 1 }, + { "PCIe_LOCK", 18, 1 }, + { "KX_LOCK", 17, 1 }, + { "KR_LOCK", 16, 1 }, + { "GPIO15", 15, 1 }, + { "GPIO14", 14, 1 }, + { "GPIO13", 13, 1 }, + { "GPIO12", 12, 1 }, + { "GPIO11", 11, 1 }, + { "GPIO10", 10, 1 }, + { "GPIO9", 9, 1 }, + { "GPIO8", 8, 1 }, + { "GPIO7", 7, 1 }, + { "GPIO6", 6, 1 }, + { "GPIO5", 5, 1 }, + { "GPIO4", 4, 1 }, + { "GPIO3", 3, 1 }, + { "GPIO2", 2, 1 }, + { "GPIO1", 1, 1 }, + { "GPIO0", 0, 1 }, + { "DBG_DBG0_RST_VALUE", 0x6020, 0 }, + { "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 }, + { "PCIE_OCLK_En", 20, 1 }, + { "KX_OCLK_En", 16, 1 }, + { "U_OCLK_En", 12, 1 }, + { "KR_OCLK_En", 8, 1 }, + { "M_OCLK_En", 4, 1 }, + { "C_OCLK_En", 0, 1 }, + { "DBG_PLL_LOCK", 0x602c, 0 }, + { "P_LOCK", 20, 1 }, + { "KX_LOCK", 16, 1 }, + { "U_LOCK", 12, 1 }, + { "KR_LOCK", 8, 1 }, + { "M_LOCK", 4, 1 }, + { "C_LOCK", 0, 1 }, + { "DBG_GPIO_ACT_LOW", 0x6030, 0 }, + { "GPIO19_ACT_LOW", 25, 1 }, + { "GPIO18_ACT_LOW", 24, 1 }, + { "GPIO17_ACT_LOW", 23, 1 }, + { "GPIO16_ACT_LOW", 22, 1 }, + { "P_LOCK_ACT_LOW", 21, 1 }, + { "C_LOCK_ACT_LOW", 20, 1 }, + { "M_LOCK_ACT_LOW", 19, 1 }, + { "U_LOCK_ACT_LOW", 18, 1 }, + { "KR_LOCK_ACT_LOW", 17, 1 }, + { "KX_LOCK_ACT_LOW", 16, 1 }, + { "GPIO15_ACT_LOW", 15, 1 }, + { "GPIO14_ACT_LOW", 14, 1 }, + { "GPIO13_ACT_LOW", 13, 1 }, + { "GPIO12_ACT_LOW", 12, 1 }, + { "GPIO11_ACT_LOW", 11, 1 }, + { "GPIO10_ACT_LOW", 10, 1 }, + { "GPIO9_ACT_LOW", 9, 1 }, + { "GPIO8_ACT_LOW", 8, 1 }, + { "GPIO7_ACT_LOW", 7, 1 }, + { "GPIO6_ACT_LOW", 6, 1 }, + { "GPIO5_ACT_LOW", 5, 1 }, + { "GPIO4_ACT_LOW", 4, 1 }, + { "GPIO3_ACT_LOW", 3, 1 }, + { "GPIO2_ACT_LOW", 2, 1 }, + { "GPIO1_ACT_LOW", 1, 1 }, + { "GPIO0_ACT_LOW", 0, 1 }, + { "DBG_EFUSE_BYTE0_3", 0x6034, 0 }, + { "DBG_EFUSE_BYTE4_7", 0x6038, 0 }, + { "DBG_EFUSE_BYTE8_11", 0x603c, 0 }, + { "DBG_EFUSE_BYTE12_15", 0x6040, 0 }, + { "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 }, + { "STATIC_M_PLL_RESET", 30, 1 }, + { "STATIC_M_PLL_SLEEP", 29, 1 }, + { "STATIC_M_PLL_BYPASS", 28, 1 }, + { "STATIC_MPLL_CLK_SEL", 27, 1 }, + { "STATIC_U_PLL_SLEEP", 26, 1 }, + { "STATIC_C_PLL_SLEEP", 25, 1 }, + { "STATIC_LVDS_CLKOUT_SEL", 23, 2 }, + { "STATIC_LVDS_CLKOUT_EN", 22, 1 }, + { "STATIC_CCLK_FREQ_SEL", 20, 2 }, + { "STATIC_UCLK_FREQ_SEL", 18, 2 }, + { "ExPHYClk_sel_en", 17, 1 }, + { "ExPHYClk_sel", 15, 2 }, + { "STATIC_U_PLL_BYPASS", 14, 1 }, + { "STATIC_C_PLL_BYPASS", 13, 1 }, + { "STATIC_KR_PLL_BYPASS", 12, 1 }, + { "STATIC_KX_PLL_BYPASS", 11, 1 }, + { "STATIC_KX_PLL_V", 7, 4 }, + { "STATIC_KR_PLL_V", 3, 4 }, + { "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 }, + { "T5_P_OCLK_MUXSEL", 13, 4 }, + { "M_OCLK_MUXSEL", 12, 1 }, + { "C_OCLK_MUXSEL", 10, 2 }, + { "U_OCLK_MUXSEL", 8, 2 }, + { "P_OCLK_MUXSEL", 6, 2 }, + { "KX_OCLK_MUXSEL", 3, 3 }, + { "KR_OCLK_MUXSEL", 0, 3 }, + { "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 }, + { "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 }, + { "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 }, + { "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 }, + { "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 }, + { "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 }, + { "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 }, + { "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 }, + { "DBG_TRACE_COUNTER", 0x6080, 0 }, + { "Counter1", 16, 16 }, + { "Counter0", 0, 16 }, + { "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 }, + { "DBG_TRACE_CONF", 0x6088, 0 }, + { "dbg_trace_operate_with_trg", 5, 1 }, + { "dbg_trace_operate_en", 4, 1 }, + { "dbg_operate_indv_combined", 3, 1 }, + { "dbg_operate_order_of_trigger", 2, 1 }, + { "dbg_operate_sgl_dbl_trigger", 1, 1 }, + { "dbg_operate0_or_1", 0, 1 }, + { "DBG_TRACE_RDEN", 0x608c, 0 }, + { "RD_ADDR1", 11, 9 }, + { "RD_ADDR0", 2, 9 }, + { "Rd_en1", 1, 1 }, + { "Rd_en0", 0, 1 }, + { "DBG_TRACE_WRADDR", 0x6090, 0 }, + { "Wr_pointer_addr1", 16, 9 }, + { "Wr_pointer_addr0", 0, 9 }, + { "DBG_TRACE0_DATA_OUT", 0x6094, 0 }, + { "DBG_TRACE1_DATA_OUT", 0x6098, 0 }, + { "DBG_FUSE_SENSE_DONE", 0x609c, 0 }, + { "STATIC_JTAG_VersionNr", 5, 4 }, + { "PSRO_sel", 1, 4 }, + { "FUSE_DONE_SENSE", 0, 1 }, + { "DBG_TVSENSE_EN", 0x60a8, 0 }, + { "MCIMPED1_out", 29, 1 }, + { "MCIMPED2_out", 28, 1 }, + { "TVSENSE_SNSOUT", 17, 9 }, + { "TVSENSE_OUTPUTVALID", 16, 1 }, + { "TVSENSE_SLEEP", 10, 1 }, + { "TVSENSE_SENSV", 9, 1 }, + { "TVSENSE_RST", 8, 1 }, + { "TVSENSE_RATIO", 0, 8 }, + { "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 }, + { "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 }, + { "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 }, + { "DBG_FEENABLE", 29, 1 }, + { "DBG_FEF", 23, 6 }, + { "DBG_FEMIMICN", 22, 1 }, + { "DBG_FEGATEC", 21, 1 }, + { "DBG_FEPROGP", 20, 1 }, + { "DBG_FEREADCLK", 19, 1 }, + { "DBG_FERSEL", 3, 16 }, + { "DBG_FETIME", 0, 3 }, + { "DBG_T5_STATIC_M_PLL_CONF1", 0x60b8, 0 }, + { "T5_STATIC_M_PLL_MULTFRAC", 8, 24 }, + { "T5_STATIC_M_PLL_FFSLEWRATE", 0, 8 }, + { "DBG_T5_STATIC_M_PLL_CONF2", 0x60bc, 0 }, + { "T5_STATIC_M_PLL_DCO_BYPASS", 23, 1 }, + { "T5_STATIC_M_PLL_SDORDER", 21, 2 }, + { "T5_STATIC_M_PLL_FFENABLE", 20, 1 }, + { "T5_STATIC_M_PLL_STOPCLKB", 19, 1 }, + { "T5_STATIC_M_PLL_STOPCLKA", 18, 1 }, + { "T5_STATIC_M_PLL_SLEEP", 17, 1 }, + { "T5_STATIC_M_PLL_BYPASS", 16, 1 }, + { "T5_STATIC_M_PLL_LOCKTUNE", 0, 16 }, + { "DBG_T5_STATIC_M_PLL_CONF3", 0x60c0, 0 }, + { "T5_STATIC_M_PLL_MULTPRE", 30, 2 }, + { "T5_STATIC_M_PLL_LOCKSEL", 28, 2 }, + { "T5_STATIC_M_PLL_FFTUNE", 12, 16 }, + { "T5_STATIC_M_PLL_RANGEPRE", 10, 2 }, + { "T5_STATIC_M_PLL_RANGEB", 5, 5 }, + { "T5_STATIC_M_PLL_RANGEA", 0, 5 }, + { "DBG_T5_STATIC_M_PLL_CONF4", 0x60c4, 0 }, + { "DBG_T5_STATIC_M_PLL_CONF5", 0x60c8, 0 }, + { "T5_STATIC_M_PLL_VCVTUNE", 24, 3 }, + { "T5_STATIC_M_PLL_RESET", 23, 1 }, + { "T5_STATIC_MPLL_REFCLK_SEL", 22, 1 }, + { "T5_STATIC_M_PLL_LFTUNE_32_40", 13, 9 }, + { "T5_STATIC_M_PLL_PREDIV", 8, 5 }, + { "T5_STATIC_M_PLL_MULT", 0, 8 }, + { "DBG_T5_STATIC_M_PLL_CONF6", 0x60cc, 0 }, + { "T5_STATIC_PHY0RecRst_", 5, 1 }, + { "T5_STATIC_PHY1RecRst_", 4, 1 }, + { "T5_STATIC_SWMC0Rst_", 3, 1 }, + { "T5_STATIC_SWMC0CfgRst_", 2, 1 }, + { "T5_STATIC_SWMC1Rst_", 1, 1 }, + { "T5_STATIC_SWMC1CfgRst_", 0, 1 }, + { "DBG_T5_STATIC_C_PLL_CONF1", 0x60d0, 0 }, + { "T5_STATIC_C_PLL_MULTFRAC", 8, 24 }, + { "T5_STATIC_C_PLL_FFSLEWRATE", 0, 8 }, + { "DBG_T5_STATIC_C_PLL_CONF2", 0x60d4, 0 }, + { "T5_STATIC_C_PLL_DCO_BYPASS", 23, 1 }, + { "T5_STATIC_C_PLL_SDORDER", 21, 2 }, + { "T5_STATIC_C_PLL_FFENABLE", 20, 1 }, + { "T5_STATIC_C_PLL_STOPCLKB", 19, 1 }, + { "T5_STATIC_C_PLL_STOPCLKA", 18, 1 }, + { "T5_STATIC_C_PLL_SLEEP", 17, 1 }, + { "T5_STATIC_C_PLL_BYPASS", 16, 1 }, + { "T5_STATIC_C_PLL_LOCKTUNE", 0, 16 }, + { "DBG_T5_STATIC_C_PLL_CONF3", 0x60d8, 0 }, + { "T5_STATIC_C_PLL_MULTPRE", 30, 2 }, + { "T5_STATIC_C_PLL_LOCKSEL", 28, 2 }, + { "T5_STATIC_C_PLL_FFTUNE", 12, 16 }, + { "T5_STATIC_C_PLL_RANGEPRE", 10, 2 }, + { "T5_STATIC_C_PLL_RANGEB", 5, 5 }, + { "T5_STATIC_C_PLL_RANGEA", 0, 5 }, + { "DBG_T5_STATIC_C_PLL_CONF4", 0x60dc, 0 }, + { "DBG_T5_STATIC_C_PLL_CONF5", 0x60e0, 0 }, + { "T5_STATIC_C_PLL_VCVTUNE", 22, 3 }, + { "T5_STATIC_C_PLL_LFTUNE_32_40", 13, 9 }, + { "T5_STATIC_C_PLL_PREDIV", 8, 5 }, + { "T5_STATIC_C_PLL_MULT", 0, 8 }, + { "DBG_T5_STATIC_U_PLL_CONF1", 0x60e4, 0 }, + { "T5_STATIC_U_PLL_MULTFRAC", 8, 24 }, + { "T5_STATIC_U_PLL_FFSLEWRATE", 0, 8 }, + { "DBG_T5_STATIC_U_PLL_CONF2", 0x60e8, 0 }, + { "T5_STATIC_U_PLL_DCO_BYPASS", 23, 1 }, + { "T5_STATIC_U_PLL_SDORDER", 21, 2 }, + { "T5_STATIC_U_PLL_FFENABLE", 20, 1 }, + { "T5_STATIC_U_PLL_STOPCLKB", 19, 1 }, + { "T5_STATIC_U_PLL_STOPCLKA", 18, 1 }, + { "T5_STATIC_U_PLL_SLEEP", 17, 1 }, + { "T5_STATIC_U_PLL_BYPASS", 16, 1 }, + { "T5_STATIC_U_PLL_LOCKTUNE", 0, 16 }, + { "DBG_T5_STATIC_U_PLL_CONF3", 0x60ec, 0 }, + { "T5_STATIC_U_PLL_MULTPRE", 30, 2 }, + { "T5_STATIC_U_PLL_LOCKSEL", 28, 2 }, + { "T5_STATIC_U_PLL_FFTUNE", 12, 16 }, + { "T5_STATIC_U_PLL_RANGEPRE", 10, 2 }, + { "T5_STATIC_U_PLL_RANGEB", 5, 5 }, + { "T5_STATIC_U_PLL_RANGEA", 0, 5 }, + { "DBG_T5_STATIC_U_PLL_CONF4", 0x60f0, 0 }, + { "DBG_T5_STATIC_U_PLL_CONF5", 0x60f4, 0 }, + { "T5_STATIC_U_PLL_VCVTUNE", 22, 3 }, + { "T5_STATIC_U_PLL_LFTUNE_32_40", 13, 9 }, + { "T5_STATIC_U_PLL_PREDIV", 8, 5 }, + { "T5_STATIC_U_PLL_MULT", 0, 8 }, + { "DBG_T5_STATIC_KR_PLL_CONF1", 0x60f8, 0 }, + { "T5_STATIC_KR_PLL_BYPASS", 30, 1 }, + { "T5_STATIC_KR_PLL_VBOOSTDIV", 27, 3 }, + { "T5_STATIC_KR_PLL_CPISEL", 24, 3 }, + { "T5_STATIC_KR_PLL_CCALMETHOD", 23, 1 }, + { "T5_STATIC_KR_PLL_CCALLOAD", 22, 1 }, + { "T5_STATIC_KR_PLL_CCALFMIN", 21, 1 }, + { "T5_STATIC_KR_PLL_CCALFMAX", 20, 1 }, + { "T5_STATIC_KR_PLL_CCALCVHOLD", 19, 1 }, + { "T5_STATIC_KR_PLL_CCALBANDSEL", 15, 4 }, + { "T5_STATIC_KR_PLL_BGOFFSET", 11, 4 }, + { "T5_STATIC_KR_PLL_P", 8, 3 }, + { "T5_STATIC_KR_PLL_N2", 4, 4 }, + { "T5_STATIC_KR_PLL_N1", 0, 4 }, + { "DBG_T5_STATIC_KR_PLL_CONF2", 0x60fc, 0 }, + { "T5_STATIC_KR_PLL_M", 11, 9 }, + { "T5_STATIC_KR_PLL_ANALOGTUNE", 0, 11 }, + { "DBG_T5_STATIC_KX_PLL_CONF1", 0x6108, 0 }, + { "T5_STATIC_KX_PLL_BYPASS", 30, 1 }, + { "T5_STATIC_KX_PLL_VBOOSTDIV", 27, 3 }, + { "T5_STATIC_KX_PLL_CPISEL", 24, 3 }, + { "T5_STATIC_KX_PLL_CCALMETHOD", 23, 1 }, + { "T5_STATIC_KX_PLL_CCALLOAD", 22, 1 }, + { "T5_STATIC_KX_PLL_CCALFMIN", 21, 1 }, + { "T5_STATIC_KX_PLL_CCALFMAX", 20, 1 }, + { "T5_STATIC_KX_PLL_CCALCVHOLD", 19, 1 }, + { "T5_STATIC_KX_PLL_CCALBANDSEL", 15, 4 }, + { "T5_STATIC_KX_PLL_BGOFFSET", 11, 4 }, + { "T5_STATIC_KX_PLL_P", 8, 3 }, + { "T5_STATIC_KX_PLL_N2", 4, 4 }, + { "T5_STATIC_KX_PLL_N1", 0, 4 }, + { "DBG_T5_STATIC_KX_PLL_CONF2", 0x610c, 0 }, + { "T5_STATIC_KX_PLL_M", 11, 9 }, + { "T5_STATIC_KX_PLL_ANALOGTUNE", 0, 11 }, + { "DBG_T5_STATIC_C_DFS_CONF", 0x6110, 0 }, + { "STATIC_C_DFS_RANGEA", 8, 5 }, + { "STATIC_C_DFS_RANGEB", 3, 5 }, + { "STATIC_C_DFS_FFTUNE4", 2, 1 }, + { "STATIC_C_DFS_FFTUNE5", 1, 1 }, + { "STATIC_C_DFS_ENABLE", 0, 1 }, + { "DBG_T5_STATIC_U_DFS_CONF", 0x6114, 0 }, + { "STATIC_U_DFS_RANGEA", 8, 5 }, + { "STATIC_U_DFS_RANGEB", 3, 5 }, + { "STATIC_U_DFS_FFTUNE4", 2, 1 }, + { "STATIC_U_DFS_FFTUNE5", 1, 1 }, + { "STATIC_U_DFS_ENABLE", 0, 1 }, + { "DBG_GPIO_PE_EN", 0x6118, 0 }, + { "GPIO19_PE_En", 19, 1 }, + { "GPIO18_PE_En", 18, 1 }, + { "GPIO17_PE_En", 17, 1 }, + { "GPIO16_PE_En", 16, 1 }, + { "GPIO15_PE_En", 15, 1 }, + { "GPIO14_PE_En", 14, 1 }, + { "GPIO13_PE_En", 13, 1 }, + { "GPIO12_PE_En", 12, 1 }, + { "GPIO11_PE_En", 11, 1 }, + { "GPIO10_PE_En", 10, 1 }, + { "GPIO9_PE_En", 9, 1 }, + { "GPIO8_PE_En", 8, 1 }, + { "GPIO7_PE_En", 7, 1 }, + { "GPIO6_PE_En", 6, 1 }, + { "GPIO5_PE_En", 5, 1 }, + { "GPIO4_PE_En", 4, 1 }, + { "GPIO3_PE_En", 3, 1 }, + { "GPIO2_PE_En", 2, 1 }, + { "GPIO1_PE_En", 1, 1 }, + { "GPIO0_PE_En", 0, 1 }, + { "DBG_GPIO_PS_EN", 0x611c, 0 }, + { "GPIO19_PS_En", 19, 1 }, + { "GPIO18_PS_En", 18, 1 }, + { "GPIO17_PS_En", 17, 1 }, + { "GPIO16_PS_En", 16, 1 }, + { "GPIO15_PS_En", 15, 1 }, + { "GPIO14_PS_En", 14, 1 }, + { "GPIO13_PS_En", 13, 1 }, + { "GPIO12_PS_En", 12, 1 }, + { "GPIO11_PS_En", 11, 1 }, + { "GPIO10_PS_En", 10, 1 }, + { "GPIO9_PS_En", 9, 1 }, + { "GPIO8_PS_En", 8, 1 }, + { "GPIO7_PS_En", 7, 1 }, + { "GPIO6_PS_En", 6, 1 }, + { "GPIO5_PS_En", 5, 1 }, + { "GPIO4_PS_En", 4, 1 }, + { "GPIO3_PS_En", 3, 1 }, + { "GPIO2_PS_En", 2, 1 }, + { "GPIO1_PS_En", 1, 1 }, + { "GPIO0_PS_En", 0, 1 }, + { "DBG_EFUSE_BYTE16_19", 0x6120, 0 }, + { "DBG_EFUSE_BYTE20_23", 0x6124, 0 }, + { "DBG_EFUSE_BYTE24_27", 0x6128, 0 }, + { "DBG_EFUSE_BYTE28_31", 0x612c, 0 }, + { "DBG_EFUSE_BYTE32_35", 0x6130, 0 }, + { "DBG_EFUSE_BYTE36_39", 0x6134, 0 }, + { "DBG_EFUSE_BYTE40_43", 0x6138, 0 }, + { "DBG_EFUSE_BYTE44_47", 0x613c, 0 }, + { "DBG_EFUSE_BYTE48_51", 0x6140, 0 }, + { "DBG_EFUSE_BYTE52_55", 0x6144, 0 }, + { "DBG_EFUSE_BYTE56_59", 0x6148, 0 }, + { "DBG_EFUSE_BYTE60_63", 0x614c, 0 }, + { NULL } +}; + +struct reg_info t5_ma_regs[] = { + { "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 }, + { "THRESHOLD1", 17, 15 }, + { "THRESHOLD1_EN", 16, 1 }, + { "THRESHOLD0", 1, 15 }, + { "THRESHOLD0_EN", 0, 1 }, + { "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_ULPTX_DEBUG_CNT", 0x7770, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_ULPRX_DEBUG_CNT", 0x7774, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_LE_DEBUG_CNT", 0x7784, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_CIM_DEBUG_CNT", 0x7788, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_PCIE_DEBUG_CNT", 0x778c, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_PMTX_DEBUG_CNT", 0x7790, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_PMRX_DEBUG_CNT", 0x7794, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_HMA_DEBUG_CNT", 0x7798, 0 }, + { "DBG_READ_DATA_CNT", 24, 8 }, + { "DBG_READ_REQ_CNT", 16, 8 }, + { "DBG_WRITE_DATA_CNT", 8, 8 }, + { "DBG_WRITE_REQ_CNT", 0, 8 }, + { "MA_EDRAM0_BAR", 0x77c0, 0 }, + { "EDRAM0_BASE", 16, 12 }, + { "EDRAM0_SIZE", 0, 12 }, + { "MA_EDRAM1_BAR", 0x77c4, 0 }, + { "EDRAM1_BASE", 16, 12 }, + { "EDRAM1_SIZE", 0, 12 }, + { "MA_EXT_MEMORY0_BAR", 0x77c8, 0 }, + { "EXT_MEM0_BASE", 16, 12 }, + { "EXT_MEM0_SIZE", 0, 12 }, + { "MA_HOST_MEMORY_BAR", 0x77cc, 0 }, + { "HMA_BASE", 16, 12 }, + { "HMA_SIZE", 0, 12 }, + { "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 }, + { "BRC_MODE1", 6, 1 }, + { "EXT_MEM_PAGE_SIZE1", 4, 2 }, + { "BRC_MODE", 2, 1 }, + { "EXT_MEM_PAGE_SIZE", 0, 2 }, + { "MA_ARB_CTRL", 0x77d4, 0 }, + { "DIS_BANK_FAIR", 2, 1 }, + { "DIS_PAGE_HINT", 1, 1 }, + { "DIS_ADV_ARB", 0, 1 }, + { "MA_TARGET_MEM_ENABLE", 0x77d8, 0 }, + { "HMA_MUX", 5, 1 }, + { "EXT_MEM1_ENABLE", 4, 1 }, + { "HMA_ENABLE", 3, 1 }, + { "EXT_MEM0_ENABLE", 2, 1 }, + { "EDRAM1_ENABLE", 1, 1 }, + { "EDRAM0_ENABLE", 0, 1 }, + { "MA_INT_ENABLE", 0x77dc, 0 }, + { "MEM_TO_INT_ENABLE", 2, 1 }, + { "MEM_PERR_INT_ENABLE", 1, 1 }, + { "MEM_WRAP_INT_ENABLE", 0, 1 }, + { "MA_INT_CAUSE", 0x77e0, 0 }, + { "MEM_TO_INT_CAUSE", 2, 1 }, + { "MEM_PERR_INT_CAUSE", 1, 1 }, + { "MEM_WRAP_INT_CAUSE", 0, 1 }, + { "MA_INT_WRAP_STATUS", 0x77e4, 0 }, + { "MEM_WRAP_ADDRESS", 4, 28 }, + { "MEM_WRAP_CLIENT_NUM", 0, 4 }, + { "MA_TP_THREAD1_MAPPER", 0x77e8, 0 }, + { "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 }, + { "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 }, + { "TP_DMARBT_PAR_ERROR_EN", 31, 1 }, + { "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 }, + { "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 }, + { "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 }, + { "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 }, + { "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 }, + { "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 }, + { "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 }, + { "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 }, + { "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 }, + { "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 }, + { "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 }, + { "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 }, + { "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 }, + { "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 }, + { "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 }, + { "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 }, + { "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 }, + { "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 }, + { "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 }, + { "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 }, + { "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 }, + { "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 }, + { "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 }, + { "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 }, + { "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 }, + { "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 }, + { "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 }, + { "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 }, + { "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 }, + { "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 }, + { "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 }, + { "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 }, + { "TP_DMARBT_PAR_ERROR", 31, 1 }, + { "LOGIC_FIFO_PAR_ERROR", 30, 1 }, + { "ARB3_PAR_WRQUEUE_ERROR", 29, 1 }, + { "ARB2_PAR_WRQUEUE_ERROR", 28, 1 }, + { "ARB1_PAR_WRQUEUE_ERROR", 27, 1 }, + { "ARB0_PAR_WRQUEUE_ERROR", 26, 1 }, + { "ARB3_PAR_RDQUEUE_ERROR", 25, 1 }, + { "ARB2_PAR_RDQUEUE_ERROR", 24, 1 }, + { "ARB1_PAR_RDQUEUE_ERROR", 23, 1 }, + { "ARB0_PAR_RDQUEUE_ERROR", 22, 1 }, + { "CL10_PAR_WRQUEUE_ERROR", 21, 1 }, + { "CL9_PAR_WRQUEUE_ERROR", 20, 1 }, + { "CL8_PAR_WRQUEUE_ERROR", 19, 1 }, + { "CL7_PAR_WRQUEUE_ERROR", 18, 1 }, + { "CL6_PAR_WRQUEUE_ERROR", 17, 1 }, + { "CL5_PAR_WRQUEUE_ERROR", 16, 1 }, + { "CL4_PAR_WRQUEUE_ERROR", 15, 1 }, + { "CL3_PAR_WRQUEUE_ERROR", 14, 1 }, + { "CL2_PAR_WRQUEUE_ERROR", 13, 1 }, + { "CL1_PAR_WRQUEUE_ERROR", 12, 1 }, + { "CL0_PAR_WRQUEUE_ERROR", 11, 1 }, + { "CL10_PAR_RDQUEUE_ERROR", 10, 1 }, + { "CL9_PAR_RDQUEUE_ERROR", 9, 1 }, + { "CL8_PAR_RDQUEUE_ERROR", 8, 1 }, + { "CL7_PAR_RDQUEUE_ERROR", 7, 1 }, + { "CL6_PAR_RDQUEUE_ERROR", 6, 1 }, + { "CL5_PAR_RDQUEUE_ERROR", 5, 1 }, + { "CL4_PAR_RDQUEUE_ERROR", 4, 1 }, + { "CL3_PAR_RDQUEUE_ERROR", 3, 1 }, + { "CL2_PAR_RDQUEUE_ERROR", 2, 1 }, + { "CL1_PAR_RDQUEUE_ERROR", 1, 1 }, + { "CL0_PAR_RDQUEUE_ERROR", 0, 1 }, + { "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 }, + { "BONUS_REG", 6, 26 }, + { "COHERANCY_CMD_TYPE", 4, 2 }, + { "COHERANCY_THREAD_NUM", 1, 3 }, + { "COHERANCY_ENABLE", 0, 1 }, + { "MA_ERROR_ENABLE", 0x77fc, 0 }, + { "FUTURE_EXPANSION", 1, 31 }, + { "UE_ENABLE", 0, 1 }, + { "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 }, + { "ARB4_PAR_WRQUEUE_ERROR_EN", 1, 1 }, + { "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 }, + { "MA_PARITY_ERROR_STATUS2", 0x7804, 0 }, + { "ARB4_PAR_WRQUEUE_ERROR", 1, 1 }, + { "ARB4_PAR_RDQUEUE_ERROR", 0, 1 }, + { "MA_EXT_MEMORY1_BAR", 0x7808, 0 }, + { "EXT_MEM1_BASE", 16, 12 }, + { "EXT_MEM1_SIZE", 0, 12 }, + { "MA_PMTX_THROTTLE", 0x780c, 0 }, + { "FL_ENABLE", 31, 1 }, + { "FL_LIMIT", 0, 8 }, + { "MA_PMRX_THROTTLE", 0x7810, 0 }, + { "FL_ENABLE", 31, 1 }, + { "FL_LIMIT", 0, 8 }, + { "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 }, + { "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 }, + { "MA_ULPTX_WRDATA_CNT", 0x781c, 0 }, + { "MA_ULPRX_WRDATA_CNT", 0x7820, 0 }, + { "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 }, + { "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 }, + { "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 }, + { "MA_LE_WRDATA_CNT", 0x7830, 0 }, + { "MA_CIM_WRDATA_CNT", 0x7834, 0 }, + { "MA_PCIE_WRDATA_CNT", 0x7838, 0 }, + { "MA_PMTX_WRDATA_CNT", 0x783c, 0 }, + { "MA_PMRX_WRDATA_CNT", 0x7840, 0 }, + { "MA_HMA_WRDATA_CNT", 0x7844, 0 }, + { "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 }, + { "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 }, + { "MA_ULPTX_RDDATA_CNT", 0x7850, 0 }, + { "MA_ULPRX_RDDATA_CNT", 0x7854, 0 }, + { "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 }, + { "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 }, + { "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 }, + { "MA_LE_RDDATA_CNT", 0x7864, 0 }, + { "MA_CIM_RDDATA_CNT", 0x7868, 0 }, + { "MA_PCIE_RDDATA_CNT", 0x786c, 0 }, + { "MA_PMTX_RDDATA_CNT", 0x7870, 0 }, + { "MA_PMRX_RDDATA_CNT", 0x7874, 0 }, + { "MA_HMA_RDDATA_CNT", 0x7878, 0 }, + { "MA_EDRAM0_WRDATA_CNT1", 0x787c, 0 }, + { "MA_EDRAM0_WRDATA_CNT0", 0x7880, 0 }, + { "MA_EDRAM1_WRDATA_CNT1", 0x7884, 0 }, + { "MA_EDRAM1_WRDATA_CNT0", 0x7888, 0 }, + { "MA_EXT_MEMORY0_WRDATA_CNT1", 0x788c, 0 }, + { "MA_EXT_MEMORY0_WRDATA_CNT0", 0x7890, 0 }, + { "MA_HOST_MEMORY_WRDATA_CNT1", 0x7894, 0 }, + { "MA_HOST_MEMORY_WRDATA_CNT0", 0x7898, 0 }, + { "MA_EXT_MEMORY1_WRDATA_CNT1", 0x789c, 0 }, + { "MA_EXT_MEMORY1_WRDATA_CNT0", 0x78a0, 0 }, + { "MA_EDRAM0_RDDATA_CNT1", 0x78a4, 0 }, + { "MA_EDRAM0_RDDATA_CNT0", 0x78a8, 0 }, + { "MA_EDRAM1_RDDATA_CNT1", 0x78ac, 0 }, + { "MA_EDRAM1_RDDATA_CNT0", 0x78b0, 0 }, + { "MA_EXT_MEMORY0_RDDATA_CNT1", 0x78b4, 0 }, + { "MA_EXT_MEMORY0_RDDATA_CNT0", 0x78b8, 0 }, + { "MA_HOST_MEMORY_RDDATA_CNT1", 0x78bc, 0 }, + { "MA_HOST_MEMORY_RDDATA_CNT0", 0x78c0, 0 }, + { "MA_EXT_MEMORY1_RDDATA_CNT1", 0x78c4, 0 }, + { "MA_EXT_MEMORY1_RDDATA_CNT0", 0x78c8, 0 }, + { "MA_TIMEOUT_CFG", 0x78cc, 0 }, + { "CLR", 31, 1 }, + { "CNT_LOCK", 30, 1 }, + { "WRN", 24, 1 }, + { "DIR", 23, 1 }, + { "TYPE", 22, 1 }, + { "CLIENT", 16, 4 }, + { "DELAY", 0, 16 }, + { "MA_TIMEOUT_CNT", 0x78d0, 0 }, + { "DIR", 23, 1 }, + { "TYPE", 22, 1 }, + { "CLIENT", 16, 4 }, + { "CNT_VAL", 0, 16 }, + { "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 }, + { "FUTURE_CEXPANSION", 29, 3 }, + { "CL12_WR_CMD_TO_EN", 28, 1 }, + { "CL11_WR_CMD_TO_EN", 27, 1 }, + { "CL10_WR_CMD_TO_EN", 26, 1 }, + { "CL9_WR_CMD_TO_EN", 25, 1 }, + { "CL8_WR_CMD_TO_EN", 24, 1 }, + { "CL7_WR_CMD_TO_EN", 23, 1 }, + { "CL6_WR_CMD_TO_EN", 22, 1 }, + { "CL5_WR_CMD_TO_EN", 21, 1 }, + { "CL4_WR_CMD_TO_EN", 20, 1 }, + { "CL3_WR_CMD_TO_EN", 19, 1 }, + { "CL2_WR_CMD_TO_EN", 18, 1 }, + { "CL1_WR_CMD_TO_EN", 17, 1 }, + { "CL0_WR_CMD_TO_EN", 16, 1 }, + { "FUTURE_DEXPANSION", 13, 3 }, + { "CL12_WR_DATA_TO_EN", 12, 1 }, + { "CL11_WR_DATA_TO_EN", 11, 1 }, + { "CL10_WR_DATA_TO_EN", 10, 1 }, + { "CL9_WR_DATA_TO_EN", 9, 1 }, + { "CL8_WR_DATA_TO_EN", 8, 1 }, + { "CL7_WR_DATA_TO_EN", 7, 1 }, + { "CL6_WR_DATA_TO_EN", 6, 1 }, + { "CL5_WR_DATA_TO_EN", 5, 1 }, + { "CL4_WR_DATA_TO_EN", 4, 1 }, + { "CL3_WR_DATA_TO_EN", 3, 1 }, + { "CL2_WR_DATA_TO_EN", 2, 1 }, + { "CL1_WR_DATA_TO_EN", 1, 1 }, + { "CL0_WR_DATA_TO_EN", 0, 1 }, + { "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 }, + { "FUTURE_CEXPANSION", 29, 3 }, + { "CL12_WR_CMD_TO_ERROR", 28, 1 }, + { "CL11_WR_CMD_TO_ERROR", 27, 1 }, + { "CL10_WR_CMD_TO_ERROR", 26, 1 }, + { "CL9_WR_CMD_TO_ERROR", 25, 1 }, + { "CL8_WR_CMD_TO_ERROR", 24, 1 }, + { "CL7_WR_CMD_TO_ERROR", 23, 1 }, + { "CL6_WR_CMD_TO_ERROR", 22, 1 }, + { "CL5_WR_CMD_TO_ERROR", 21, 1 }, + { "CL4_WR_CMD_TO_ERROR", 20, 1 }, + { "CL3_WR_CMD_TO_ERROR", 19, 1 }, + { "CL2_WR_CMD_TO_ERROR", 18, 1 }, + { "CL1_WR_CMD_TO_ERROR", 17, 1 }, + { "CL0_WR_CMD_TO_ERROR", 16, 1 }, + { "FUTURE_DEXPANSION", 13, 3 }, + { "CL12_WR_DATA_TO_ERROR", 12, 1 }, + { "CL11_WR_DATA_TO_ERROR", 11, 1 }, + { "CL10_WR_DATA_TO_ERROR", 10, 1 }, + { "CL9_WR_DATA_TO_ERROR", 9, 1 }, + { "CL8_WR_DATA_TO_ERROR", 8, 1 }, + { "CL7_WR_DATA_TO_ERROR", 7, 1 }, + { "CL6_WR_DATA_TO_ERROR", 6, 1 }, + { "CL5_WR_DATA_TO_ERROR", 5, 1 }, + { "CL4_WR_DATA_TO_ERROR", 4, 1 }, + { "CL3_WR_DATA_TO_ERROR", 3, 1 }, + { "CL2_WR_DATA_TO_ERROR", 2, 1 }, + { "CL1_WR_DATA_TO_ERROR", 1, 1 }, + { "CL0_WR_DATA_TO_ERROR", 0, 1 }, + { "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 }, + { "FUTURE_CEXPANSION", 29, 3 }, + { "CL12_RD_CMD_TO_EN", 28, 1 }, + { "CL11_RD_CMD_TO_EN", 27, 1 }, + { "CL10_RD_CMD_TO_EN", 26, 1 }, + { "CL9_RD_CMD_TO_EN", 25, 1 }, + { "CL8_RD_CMD_TO_EN", 24, 1 }, + { "CL7_RD_CMD_TO_EN", 23, 1 }, + { "CL6_RD_CMD_TO_EN", 22, 1 }, + { "CL5_RD_CMD_TO_EN", 21, 1 }, + { "CL4_RD_CMD_TO_EN", 20, 1 }, + { "CL3_RD_CMD_TO_EN", 19, 1 }, + { "CL2_RD_CMD_TO_EN", 18, 1 }, + { "CL1_RD_CMD_TO_EN", 17, 1 }, + { "CL0_RD_CMD_TO_EN", 16, 1 }, + { "FUTURE_DEXPANSION", 13, 3 }, + { "CL12_RD_DATA_TO_EN", 12, 1 }, + { "CL11_RD_DATA_TO_EN", 11, 1 }, + { "CL10_RD_DATA_TO_EN", 10, 1 }, + { "CL9_RD_DATA_TO_EN", 9, 1 }, + { "CL8_RD_DATA_TO_EN", 8, 1 }, + { "CL7_RD_DATA_TO_EN", 7, 1 }, + { "CL6_RD_DATA_TO_EN", 6, 1 }, + { "CL5_RD_DATA_TO_EN", 5, 1 }, + { "CL4_RD_DATA_TO_EN", 4, 1 }, + { "CL3_RD_DATA_TO_EN", 3, 1 }, + { "CL2_RD_DATA_TO_EN", 2, 1 }, + { "CL1_RD_DATA_TO_EN", 1, 1 }, + { "CL0_RD_DATA_TO_EN", 0, 1 }, + { "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 }, + { "FUTURE_CEXPANSION", 29, 3 }, + { "CL12_RD_CMD_TO_ERROR", 28, 1 }, + { "CL11_RD_CMD_TO_ERROR", 27, 1 }, + { "CL10_RD_CMD_TO_ERROR", 26, 1 }, + { "CL9_RD_CMD_TO_ERROR", 25, 1 }, + { "CL8_RD_CMD_TO_ERROR", 24, 1 }, + { "CL7_RD_CMD_TO_ERROR", 23, 1 }, + { "CL6_RD_CMD_TO_ERROR", 22, 1 }, + { "CL5_RD_CMD_TO_ERROR", 21, 1 }, + { "CL4_RD_CMD_TO_ERROR", 20, 1 }, + { "CL3_RD_CMD_TO_ERROR", 19, 1 }, + { "CL2_RD_CMD_TO_ERROR", 18, 1 }, + { "CL1_RD_CMD_TO_ERROR", 17, 1 }, + { "CL0_RD_CMD_TO_ERROR", 16, 1 }, + { "FUTURE_DEXPANSION", 13, 3 }, + { "CL12_RD_DATA_TO_ERROR", 12, 1 }, + { "CL11_RD_DATA_TO_ERROR", 11, 1 }, + { "CL10_RD_DATA_TO_ERROR", 10, 1 }, + { "CL9_RD_DATA_TO_ERROR", 9, 1 }, + { "CL8_RD_DATA_TO_ERROR", 8, 1 }, + { "CL7_RD_DATA_TO_ERROR", 7, 1 }, + { "CL6_RD_DATA_TO_ERROR", 6, 1 }, + { "CL5_RD_DATA_TO_ERROR", 5, 1 }, + { "CL4_RD_DATA_TO_ERROR", 4, 1 }, + { "CL3_RD_DATA_TO_ERROR", 3, 1 }, + { "CL2_RD_DATA_TO_ERROR", 2, 1 }, + { "CL1_RD_DATA_TO_ERROR", 1, 1 }, + { "CL0_RD_DATA_TO_ERROR", 0, 1 }, + { "MA_BKP_CNT_SEL", 0x78e4, 0 }, + { "TYPE", 30, 2 }, + { "CLIENT", 24, 4 }, + { "MA_BKP_CNT", 0x78e8, 0 }, + { "MA_WRT_ARB", 0x78ec, 0 }, + { "WRT_EN", 31, 1 }, + { "WR_TIM", 16, 8 }, + { "RD_WIN", 8, 8 }, + { "WR_WIN", 0, 8 }, + { "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 }, + { "FUTURE_DEXPANSION", 13, 19 }, + { "CL12_IF_PAR_EN", 12, 1 }, + { "CL11_IF_PAR_EN", 11, 1 }, + { "CL10_IF_PAR_EN", 10, 1 }, + { "CL9_IF_PAR_EN", 9, 1 }, + { "CL8_IF_PAR_EN", 8, 1 }, + { "CL7_IF_PAR_EN", 7, 1 }, + { "CL6_IF_PAR_EN", 6, 1 }, + { "CL5_IF_PAR_EN", 5, 1 }, + { "CL4_IF_PAR_EN", 4, 1 }, + { "CL3_IF_PAR_EN", 3, 1 }, + { "CL2_IF_PAR_EN", 2, 1 }, + { "CL1_IF_PAR_EN", 1, 1 }, + { "CL0_IF_PAR_EN", 0, 1 }, + { "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 }, + { "FUTURE_DEXPANSION", 13, 19 }, + { "CL12_IF_PAR_ERROR", 12, 1 }, + { "CL11_IF_PAR_ERROR", 11, 1 }, + { "CL10_IF_PAR_ERROR", 10, 1 }, + { "CL9_IF_PAR_ERROR", 9, 1 }, + { "CL8_IF_PAR_ERROR", 8, 1 }, + { "CL7_IF_PAR_ERROR", 7, 1 }, + { "CL6_IF_PAR_ERROR", 6, 1 }, + { "CL5_IF_PAR_ERROR", 5, 1 }, + { "CL4_IF_PAR_ERROR", 4, 1 }, + { "CL3_IF_PAR_ERROR", 3, 1 }, + { "CL2_IF_PAR_ERROR", 2, 1 }, + { "CL1_IF_PAR_ERROR", 1, 1 }, + { "CL0_IF_PAR_ERROR", 0, 1 }, + { "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 }, + { "DEBUG_OR", 15, 1 }, + { "DEBUG_HI", 14, 1 }, + { "DEBUG_RPT", 13, 1 }, + { "DEBUGPAGE", 10, 3 }, + { "DEBUGSELH", 5, 5 }, + { "DEBUGSELL", 0, 5 }, + { "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 }, + { NULL } +}; + +struct reg_info t5_cim_regs[] = { + { "CIM_BOOT_CFG", 0x7b00, 0 }, + { "BootAddr", 8, 24 }, + { "uPGen", 2, 6 }, + { "BootSdram", 1, 1 }, + { "uPCRst", 0, 1 }, + { "CIM_BOOT_LEN", 0x7bf0, 0 }, + { "BootLen", 4, 28 }, + { "CIM_FLASH_BASE_ADDR", 0x7b04, 0 }, + { "FlashBaseAddr", 6, 18 }, + { "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 }, + { "FlashAddrSize", 4, 20 }, + { "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 }, + { "EEPROMBaseAddr", 6, 18 }, + { "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 }, + { "EEPROMAddrSize", 4, 20 }, + { "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 }, + { "SdramBaseAddr", 6, 26 }, + { "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 }, + { "SdramAddrSize", 4, 28 }, + { "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 }, + { "ExtMem2BaseAddr", 6, 26 }, + { "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 }, + { "ExtMem2AddrSize", 4, 28 }, + { "CIM_UP_SPARE_INT", 0x7b24, 0 }, + { "TDebugInt", 4, 1 }, + { "BootVecSel", 3, 1 }, + { "uPSpareInt", 0, 3 }, + { "CIM_HOST_INT_ENABLE", 0x7b28, 0 }, + { "ma_cim_IntfPerr", 28, 1 }, + { "PLCIM_MstRspDataParErr", 27, 1 }, + { "NCSI2CIMIntfParErr", 26, 1 }, + { "SGE2CIMIntfParErr", 25, 1 }, + { "ULP2CIMIntfParErr", 24, 1 }, + { "TP2CIMIntfParErr", 23, 1 }, + { "OBQSGERx1ParErr", 22, 1 }, + { "OBQSGERx0ParErr", 21, 1 }, + { "TieQOutParErrIntEn", 20, 1 }, + { "TieQInParErrIntEn", 19, 1 }, + { "MBHostParErr", 18, 1 }, + { "MBuPParErr", 17, 1 }, + { "IBQTP0ParErr", 16, 1 }, + { "IBQTP1ParErr", 15, 1 }, + { "IBQULPParErr", 14, 1 }, + { "IBQSGELOParErr", 13, 1 }, + { "IBQSGEHIParErr", 12, 1 }, + { "IBQNCSIParErr", 11, 1 }, + { "OBQULP0ParErr", 10, 1 }, + { "OBQULP1ParErr", 9, 1 }, + { "OBQULP2ParErr", 8, 1 }, + { "OBQULP3ParErr", 7, 1 }, + { "OBQSGEParErr", 6, 1 }, + { "OBQNCSIParErr", 5, 1 }, + { "Timer1IntEn", 3, 1 }, + { "Timer0IntEn", 2, 1 }, + { "PrefDropIntEn", 1, 1 }, + { "CIM_HOST_INT_CAUSE", 0x7b2c, 0 }, + { "ma_cim_IntfPerr", 28, 1 }, + { "PLCIM_MstRspDataParErr", 27, 1 }, + { "NCSI2CIMIntfParErr", 26, 1 }, + { "SGE2CIMIntfParErr", 25, 1 }, + { "ULP2CIMIntfParErr", 24, 1 }, + { "TP2CIMIntfParErr", 23, 1 }, + { "OBQSGERx1ParErr", 22, 1 }, + { "OBQSGERx0ParErr", 21, 1 }, + { "TieQOutParErrInt", 20, 1 }, + { "TieQInParErrInt", 19, 1 }, + { "MBHostParErr", 18, 1 }, + { "IBQTP0ParErr", 16, 1 }, + { "IBQTP1ParErr", 15, 1 }, + { "IBQULPParErr", 14, 1 }, + { "IBQSGELOParErr", 13, 1 }, + { "IBQSGEHIParErr", 12, 1 }, + { "IBQNCSIParErr", 11, 1 }, + { "OBQULP0ParErr", 10, 1 }, + { "OBQULP1ParErr", 9, 1 }, + { "OBQULP2ParErr", 8, 1 }, + { "OBQULP3ParErr", 7, 1 }, + { "OBQSGEParErr", 6, 1 }, + { "OBQNCSIParErr", 5, 1 }, + { "Timer1Int", 3, 1 }, + { "Timer0Int", 2, 1 }, + { "PrefDropInt", 1, 1 }, + { "uPAccNonZero", 0, 1 }, + { "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 }, + { "EEPROMWRIntEn", 30, 1 }, + { "TimeOutMAIntEn", 29, 1 }, + { "TimeOutIntEn", 28, 1 }, + { "RspOvrLookupIntEn", 27, 1 }, + { "ReqOvrLookupIntEn", 26, 1 }, + { "BlkWrPlIntEn", 25, 1 }, + { "BlkRdPlIntEn", 24, 1 }, + { "SglWrPlIntEn", 23, 1 }, + { "SglRdPlIntEn", 22, 1 }, + { "BlkWrCtlIntEn", 21, 1 }, + { "BlkRdCtlIntEn", 20, 1 }, + { "SglWrCtlIntEn", 19, 1 }, + { "SglRdCtlIntEn", 18, 1 }, + { "BlkWrEEPROMIntEn", 17, 1 }, + { "BlkRdEEPROMIntEn", 16, 1 }, + { "SglWrEEPROMIntEn", 15, 1 }, + { "SglRdEEPROMIntEn", 14, 1 }, + { "BlkWrFlashIntEn", 13, 1 }, + { "BlkRdFlashIntEn", 12, 1 }, + { "SglWrFlashIntEn", 11, 1 }, + { "SglRdFlashIntEn", 10, 1 }, + { "BlkWrBootIntEn", 9, 1 }, + { "BlkRdBootIntEn", 8, 1 }, + { "SglWrBootIntEn", 7, 1 }, + { "SglRdBootIntEn", 6, 1 }, + { "IllWrBEIntEn", 5, 1 }, + { "IllRdBEIntEn", 4, 1 }, + { "IllRdIntEn", 3, 1 }, + { "IllWrIntEn", 2, 1 }, + { "IllTransIntEn", 1, 1 }, + { "RsvdSpaceIntEn", 0, 1 }, + { "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 }, + { "EEPROMWRInt", 30, 1 }, + { "TimeOutMAInt", 29, 1 }, + { "TimeOutInt", 28, 1 }, + { "RspOvrLookupInt", 27, 1 }, + { "ReqOvrLookupInt", 26, 1 }, + { "BlkWrPlInt", 25, 1 }, + { "BlkRdPlInt", 24, 1 }, + { "SglWrPlInt", 23, 1 }, + { "SglRdPlInt", 22, 1 }, + { "BlkWrCtlInt", 21, 1 }, + { "BlkRdCtlInt", 20, 1 }, + { "SglWrCtlInt", 19, 1 }, + { "SglRdCtlInt", 18, 1 }, + { "BlkWrEEPROMInt", 17, 1 }, + { "BlkRdEEPROMInt", 16, 1 }, + { "SglWrEEPROMInt", 15, 1 }, + { "SglRdEEPROMInt", 14, 1 }, + { "BlkWrFlashInt", 13, 1 }, + { "BlkRdFlashInt", 12, 1 }, + { "SglWrFlashInt", 11, 1 }, + { "SglRdFlashInt", 10, 1 }, + { "BlkWrBootInt", 9, 1 }, + { "BlkRdBootInt", 8, 1 }, + { "SglWrBootInt", 7, 1 }, + { "SglRdBootInt", 6, 1 }, + { "IllWrBEInt", 5, 1 }, + { "IllRdBEInt", 4, 1 }, + { "IllRdInt", 3, 1 }, + { "IllWrInt", 2, 1 }, + { "IllTransInt", 1, 1 }, + { "RsvdSpaceInt", 0, 1 }, + { "CIM_UP_INT_ENABLE", 0x7b38, 0 }, + { "ma_cim_IntfPerr", 28, 1 }, + { "PLCIM_MstRspDataParErr", 27, 1 }, + { "NCSI2CIMIntfParErr", 26, 1 }, + { "SGE2CIMIntfParErr", 25, 1 }, + { "ULP2CIMIntfParErr", 24, 1 }, + { "TP2CIMIntfParErr", 23, 1 }, + { "OBQSGERx1ParErr", 22, 1 }, + { "OBQSGERx0ParErr", 21, 1 }, + { "TieQOutParErrIntEn", 20, 1 }, + { "TieQInParErrIntEn", 19, 1 }, + { "MBHostParErr", 18, 1 }, + { "MBuPParErr", 17, 1 }, + { "IBQTP0ParErr", 16, 1 }, + { "IBQTP1ParErr", 15, 1 }, + { "IBQULPParErr", 14, 1 }, + { "IBQSGELOParErr", 13, 1 }, + { "IBQSGEHIParErr", 12, 1 }, + { "IBQNCSIParErr", 11, 1 }, + { "OBQULP0ParErr", 10, 1 }, + { "OBQULP1ParErr", 9, 1 }, + { "OBQULP2ParErr", 8, 1 }, + { "OBQULP3ParErr", 7, 1 }, + { "OBQSGEParErr", 6, 1 }, + { "OBQNCSIParErr", 5, 1 }, + { "MstPlIntEn", 4, 1 }, + { "Timer1IntEn", 3, 1 }, + { "Timer0IntEn", 2, 1 }, + { "PrefDropIntEn", 1, 1 }, + { "CIM_UP_INT_CAUSE", 0x7b3c, 0 }, + { "ma_cim_IntfPerr", 28, 1 }, + { "PLCIM_MstRspDataParErr", 27, 1 }, + { "NCSI2CIMIntfParErr", 26, 1 }, + { "SGE2CIMIntfParErr", 25, 1 }, + { "ULP2CIMIntfParErr", 24, 1 }, + { "TP2CIMIntfParErr", 23, 1 }, + { "OBQSGERx1ParErr", 22, 1 }, + { "OBQSGERx0ParErr", 21, 1 }, + { "TieQOutParErrInt", 20, 1 }, + { "TieQInParErrInt", 19, 1 }, + { "MBHostParErr", 18, 1 }, + { "IBQTP0ParErr", 16, 1 }, + { "IBQTP1ParErr", 15, 1 }, + { "IBQULPParErr", 14, 1 }, + { "IBQSGELOParErr", 13, 1 }, + { "IBQSGEHIParErr", 12, 1 }, + { "IBQNCSIParErr", 11, 1 }, + { "OBQULP0ParErr", 10, 1 }, + { "OBQULP1ParErr", 9, 1 }, + { "OBQULP2ParErr", 8, 1 }, + { "OBQULP3ParErr", 7, 1 }, + { "OBQSGEParErr", 6, 1 }, + { "OBQNCSIParErr", 5, 1 }, + { "MstPlInt", 4, 1 }, + { "Timer1Int", 3, 1 }, + { "Timer0Int", 2, 1 }, + { "PrefDropInt", 1, 1 }, + { "uPAccNonZero", 0, 1 }, + { "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 }, + { "EEPROMWRIntEn", 30, 1 }, + { "TimeOutMAIntEn", 29, 1 }, + { "TimeOutIntEn", 28, 1 }, + { "RspOvrLookupIntEn", 27, 1 }, + { "ReqOvrLookupIntEn", 26, 1 }, + { "BlkWrPlIntEn", 25, 1 }, + { "BlkRdPlIntEn", 24, 1 }, + { "SglWrPlIntEn", 23, 1 }, + { "SglRdPlIntEn", 22, 1 }, + { "BlkWrCtlIntEn", 21, 1 }, + { "BlkRdCtlIntEn", 20, 1 }, + { "SglWrCtlIntEn", 19, 1 }, + { "SglRdCtlIntEn", 18, 1 }, + { "BlkWrEEPROMIntEn", 17, 1 }, + { "BlkRdEEPROMIntEn", 16, 1 }, + { "SglWrEEPROMIntEn", 15, 1 }, + { "SglRdEEPROMIntEn", 14, 1 }, + { "BlkWrFlashIntEn", 13, 1 }, + { "BlkRdFlashIntEn", 12, 1 }, + { "SglWrFlashIntEn", 11, 1 }, + { "SglRdFlashIntEn", 10, 1 }, + { "BlkWrBootIntEn", 9, 1 }, + { "BlkRdBootIntEn", 8, 1 }, + { "SglWrBootIntEn", 7, 1 }, + { "SglRdBootIntEn", 6, 1 }, + { "IllWrBEIntEn", 5, 1 }, + { "IllRdBEIntEn", 4, 1 }, + { "IllRdIntEn", 3, 1 }, + { "IllWrIntEn", 2, 1 }, + { "IllTransIntEn", 1, 1 }, + { "RsvdSpaceIntEn", 0, 1 }, + { "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 }, + { "EEPROMWRInt", 30, 1 }, + { "TimeOutMAInt", 29, 1 }, + { "TimeOutInt", 28, 1 }, + { "RspOvrLookupInt", 27, 1 }, + { "ReqOvrLookupInt", 26, 1 }, + { "BlkWrPlInt", 25, 1 }, + { "BlkRdPlInt", 24, 1 }, + { "SglWrPlInt", 23, 1 }, + { "SglRdPlInt", 22, 1 }, + { "BlkWrCtlInt", 21, 1 }, + { "BlkRdCtlInt", 20, 1 }, + { "SglWrCtlInt", 19, 1 }, + { "SglRdCtlInt", 18, 1 }, + { "BlkWrEEPROMInt", 17, 1 }, + { "BlkRdEEPROMInt", 16, 1 }, + { "SglWrEEPROMInt", 15, 1 }, + { "SglRdEEPROMInt", 14, 1 }, + { "BlkWrFlashInt", 13, 1 }, + { "BlkRdFlashInt", 12, 1 }, + { "SglWrFlashInt", 11, 1 }, + { "SglRdFlashInt", 10, 1 }, + { "BlkWrBootInt", 9, 1 }, + { "BlkRdBootInt", 8, 1 }, + { "SglWrBootInt", 7, 1 }, + { "SglRdBootInt", 6, 1 }, + { "IllWrBEInt", 5, 1 }, + { "IllRdBEInt", 4, 1 }, + { "IllRdInt", 3, 1 }, + { "IllWrInt", 2, 1 }, + { "IllTransInt", 1, 1 }, + { "RsvdSpaceInt", 0, 1 }, + { "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 }, + { "OBQSelect", 4, 1 }, + { "IBQSelect", 3, 1 }, + { "QueNumSelect", 0, 3 }, + { "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 }, + { "QueSize", 24, 6 }, + { "QueBase", 16, 6 }, + { "QueDbg8BEn", 9, 1 }, + { "QueFullThrsh", 0, 9 }, + { "CIM_HOST_ACC_CTRL", 0x7b50, 0 }, + { "HostBusy", 17, 1 }, + { "HostWrite", 16, 1 }, + { "HostAddr", 0, 16 }, + { "CIM_HOST_ACC_DATA", 0x7b54, 0 }, + { "CIM_CDEBUGDATA", 0x7b58, 0 }, + { "CDebugDataH", 16, 16 }, + { "CDebugDataL", 0, 16 }, + { "CIM_IBQ_DBG_CFG", 0x7b60, 0 }, + { "IbqDbgAddr", 16, 12 }, + { "IbqDbgWr", 2, 1 }, + { "IbqDbgBusy", 1, 1 }, + { "IbqDbgEn", 0, 1 }, + { "CIM_OBQ_DBG_CFG", 0x7b64, 0 }, + { "ObqDbgAddr", 16, 12 }, + { "ObqDbgWr", 2, 1 }, + { "ObqDbgBusy", 1, 1 }, + { "ObqDbgEn", 0, 1 }, + { "CIM_IBQ_DBG_DATA", 0x7b68, 0 }, + { "CIM_OBQ_DBG_DATA", 0x7b6c, 0 }, + { "CIM_DEBUGCFG", 0x7b70, 0 }, + { "POLADbgRdPtr", 23, 9 }, + { "PILADbgRdPtr", 14, 9 }, + { "LAMaskTrig", 13, 1 }, + { "LADbgEn", 12, 1 }, + { "LAFillOnce", 11, 1 }, + { "LAMaskStop", 10, 1 }, + { "DebugSelH", 5, 5 }, + { "DebugSelL", 0, 5 }, + { "CIM_DEBUGSTS", 0x7b74, 0 }, + { "LAReset", 31, 1 }, + { "POLADbgWrPtr", 16, 9 }, + { "PILADbgWrPtr", 0, 9 }, + { "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 }, + { "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 }, + { "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 }, + { "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 }, + { "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 }, + { "CIM_MEM_ZONE0_VA", 0x7b90, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE0_BA", 0x7b94, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE0_LEN", 0x7b98, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE1_VA", 0x7b9c, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE1_BA", 0x7ba0, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE2_VA", 0x7ba8, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE2_BA", 0x7bac, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE3_VA", 0x7bb4, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE3_BA", 0x7bb8, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE4_VA", 0x7bc0, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE4_BA", 0x7bc4, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE5_VA", 0x7bcc, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE5_BA", 0x7bd0, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE6_VA", 0x7bd8, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE6_BA", 0x7bdc, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE6_LEN", 0x7be0, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_MEM_ZONE7_VA", 0x7be4, 0 }, + { "MEM_ZONE_VA", 4, 28 }, + { "CIM_MEM_ZONE7_BA", 0x7be8, 0 }, + { "MEM_ZONE_BA", 6, 26 }, + { "PBT_enable", 5, 1 }, + { "ZONE_DST", 0, 2 }, + { "CIM_MEM_ZONE7_LEN", 0x7bec, 0 }, + { "MEM_ZONE_LEN", 4, 28 }, + { "CIM_GLB_TIMER_CTL", 0x7bf4, 0 }, + { "Timer1En", 4, 1 }, + { "Timer0En", 3, 1 }, + { "TimerEn", 1, 1 }, + { "CIM_GLB_TIMER", 0x7bf8, 0 }, + { "CIM_GLB_TIMER_TICK", 0x7bfc, 0 }, + { "CIM_TIMER0", 0x7c00, 0 }, + { "CIM_TIMER1", 0x7c04, 0 }, + { "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 }, + { "DAddrTimeOut", 2, 30 }, + { "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 }, + { "DAddrIllegal", 2, 30 }, + { "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 }, + { "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 }, + { "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 }, + { "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 }, + { "CIM_PERR_INJECT", 0x7c20, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "CIM_PERR_ENABLE", 0x7c24, 0 }, + { "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 }, + { "CIM_MA_TIMER_EN", 0x7c2c, 0 }, + { "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 }, + { "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 }, + { "CIM_UP_OPERATION_FREQ", 0x7c38, 0 }, + { "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 }, + { "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 }, + { "CIM_SGE1_PKT_ERR_CODE", 8, 8 }, + { "CIM_SGE0_PKT_ERR_CODE", 0, 8 }, + { "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 }, + { "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 }, + { "CIM_CGEN", 0x7c48, 0 }, + { "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 }, + { "obq_throuttle_on_eop", 4, 1 }, + { "obq_read_ctl_perf_mode_disable", 3, 1 }, + { "obq_wait_for_eop_flush_disable", 2, 1 }, + { "ibq_rra_dsbl", 1, 1 }, + { "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 }, + { "CIM_CGEN_GLOBAL", 0x7c50, 0 }, + { "CIM_DPSLP_EN", 0x7c54, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e240, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e244, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e248, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e250, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e254, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e258, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e260, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e264, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e268, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e270, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e274, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e278, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1e640, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e644, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e648, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e650, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e654, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e658, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e660, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e664, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e668, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e670, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e674, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e678, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1f240, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f244, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f248, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f250, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f254, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f258, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f260, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f264, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f268, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f270, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f274, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f278, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1f640, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f644, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f648, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f650, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f654, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f658, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f660, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f664, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f668, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f670, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f674, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f678, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 }, + { "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 }, + { "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 }, + { "MBWrBusy", 31, 1 }, + { "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 }, + { "MBMsgRdyIntEn", 19, 1 }, + { "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 }, + { "MBMsgRdyInt", 19, 1 }, + { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 }, + { "MBGeneric", 4, 28 }, + { "MBMsgValid", 3, 1 }, + { "MBIntReq", 2, 1 }, + { "MBOwner", 0, 2 }, + { NULL } +}; + +struct reg_info t5_tp_regs[] = { + { "TP_IN_CONFIG", 0x7d00, 0 }, + { "VLANExtEnPort3", 31, 1 }, + { "VLANExtEnPort2", 30, 1 }, + { "VLANExtEnPort1", 29, 1 }, + { "VLANExtEnPort0", 28, 1 }, + { "TcpOptParserDisCh3", 27, 1 }, + { "TcpOptParserDisCh2", 26, 1 }, + { "TcpOptParserDisCh1", 25, 1 }, + { "TcpOptParserDisCh0", 24, 1 }, + { "CrcPassPrt3", 23, 1 }, + { "CrcPassPrt2", 22, 1 }, + { "CrcPassPrt1", 21, 1 }, + { "CrcPassPrt0", 20, 1 }, + { "VepaMode", 19, 1 }, + { "FipUpEn", 18, 1 }, + { "FcoeUpEn", 17, 1 }, + { "FcoeEnable", 16, 1 }, + { "IPv6Enable", 15, 1 }, + { "NICMode", 14, 1 }, + { "VnTagDefaultVal", 13, 1 }, + { "ECheckUDPLen", 12, 1 }, + { "EReportUdpHdrLen", 11, 1 }, + { "FcoeFPMA", 10, 1 }, + { "VnTagEnable", 9, 1 }, + { "VnTagEthEnable", 8, 1 }, + { "CChecksumCheckIP", 7, 1 }, + { "CChecksumCheckUDP", 6, 1 }, + { "CChecksumCheckTCP", 5, 1 }, + { "CTag", 4, 1 }, + { "CDemux", 3, 1 }, + { "EthUpEn", 2, 1 }, + { "CEthernet", 1, 1 }, + { "CTunnel", 0, 1 }, + { "TP_OUT_CONFIG", 0x7d04, 0 }, + { "PortQfcEn", 28, 4 }, + { "EPktDistChn3", 23, 1 }, + { "EPktDistChn2", 22, 1 }, + { "EPktDistChn1", 21, 1 }, + { "EPktDistChn0", 20, 1 }, + { "TtlMode", 19, 1 }, + { "EQfcDmac", 18, 1 }, + { "ELpbkIncMpsStat", 17, 1 }, + { "IPIDSplitMode", 16, 1 }, + { "EChecksumInsertTCP", 11, 1 }, + { "EChecksumInsertIP", 10, 1 }, + { "EVnTagEn", 9, 1 }, + { "ECPL", 8, 1 }, + { "EPriority", 7, 1 }, + { "EEthernet", 6, 1 }, + { "CChecksumInsertTCP", 5, 1 }, + { "CChecksumInsertIP", 4, 1 }, + { "CCPL", 2, 1 }, + { "CEthernet", 0, 1 }, + { "TP_GLOBAL_CONFIG", 0x7d08, 0 }, + { "SYNCookieParams", 26, 6 }, + { "RXFlowControlDisable", 25, 1 }, + { "TXPacingEnable", 24, 1 }, + { "AttackFilterEnable", 23, 1 }, + { "SYNCookieNoOptions", 22, 1 }, + { "ProtectedMode", 21, 1 }, + { "PingDrop", 20, 1 }, + { "FragmentDrop", 19, 1 }, + { "FiveTupleLookup", 17, 2 }, + { "OfdMpsStats", 16, 1 }, + { "DontFragment", 15, 1 }, + { "IPIdentSplit", 14, 1 }, + { "RssSynSteerEnable", 12, 1 }, + { "IssFromCplEnable", 11, 1 }, + { "RssLoopbackEnable", 10, 1 }, + { "TCAMServerUse", 8, 2 }, + { "IPTTL", 0, 8 }, + { "TP_DB_CONFIG", 0x7d0c, 0 }, + { "DBMaxOpCnt", 24, 8 }, + { "CxMaxOpCntDisable", 23, 1 }, + { "CxMaxOpCnt", 16, 7 }, + { "TxMaxOpCntDisable", 15, 1 }, + { "TxMaxOpCnt", 8, 7 }, + { "RxMaxOpCntDisable", 7, 1 }, + { "RxMaxOpCnt", 0, 7 }, + { "TP_CMM_TCB_BASE", 0x7d10, 0 }, + { "TP_CMM_MM_BASE", 0x7d14, 0 }, + { "TP_CMM_TIMER_BASE", 0x7d18, 0 }, + { "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 }, + { "RxPoolSize", 16, 16 }, + { "TxPoolSize", 0, 16 }, + { "TP_PMM_TX_BASE", 0x7d20, 0 }, + { "TP_PMM_DEFRAG_BASE", 0x7d24, 0 }, + { "TP_PMM_RX_BASE", 0x7d28, 0 }, + { "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 }, + { "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 }, + { "PMRxNumChn", 31, 1 }, + { "PMRxMaxPage", 0, 21 }, + { "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 }, + { "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 }, + { "PMTxNumChn", 30, 2 }, + { "PMTxMaxPage", 0, 21 }, + { "TP_TCP_OPTIONS", 0x7d40, 0 }, + { "MTUDefault", 16, 16 }, + { "MTUEnable", 10, 1 }, + { "SACKTx", 9, 1 }, + { "SACKRx", 8, 1 }, + { "SACKMode", 4, 2 }, + { "WindowScaleMode", 2, 2 }, + { "TimestampsMode", 0, 2 }, + { "TP_DACK_CONFIG", 0x7d44, 0 }, + { "AutoState3", 30, 2 }, + { "AutoState2", 28, 2 }, + { "AutoState1", 26, 2 }, + { "ByteThreshold", 8, 18 }, + { "MSSThreshold", 4, 3 }, + { "AutoCareful", 2, 1 }, + { "AutoEnable", 1, 1 }, + { "Mode", 0, 1 }, + { "TP_PC_CONFIG", 0x7d48, 0 }, + { "CMCacheDisable", 31, 1 }, + { "EnableOcspiFull", 30, 1 }, + { "EnableFLMErrorDDP", 29, 1 }, + { "LockTid", 28, 1 }, + { "DisableInvPend", 27, 1 }, + { "EnableFilterCount", 26, 1 }, + { "RddpCongEn", 25, 1 }, + { "EnableOnFlyPDU", 24, 1 }, + { "EnableMinRcvWnd", 23, 1 }, + { "EnableMaxRcvWnd", 22, 1 }, + { "TxDataAckRateEnable", 21, 1 }, + { "TxDeferEnable", 20, 1 }, + { "RxCongestionMode", 19, 1 }, + { "HearbeatOnceDACK", 18, 1 }, + { "HearbeatOnceHeap", 17, 1 }, + { "HearbeatDACK", 16, 1 }, + { "TxCongestionMode", 15, 1 }, + { "AcceptLatestRcvAdv", 14, 1 }, + { "DisableSYNData", 13, 1 }, + { "DisableWindowPSH", 12, 1 }, + { "DisableFINOldData", 11, 1 }, + { "EnableFLMError", 10, 1 }, + { "EnableOptMtu", 9, 1 }, + { "FilterPeerFIN", 8, 1 }, + { "EnableFeedbackSend", 7, 1 }, + { "EnableRDMAError", 6, 1 }, + { "EnableFilterNat", 5, 1 }, + { "DisableHeldFIN", 4, 1 }, + { "EnableOfdoVLAN", 3, 1 }, + { "DisableTimeWait", 2, 1 }, + { "EnableVlanCheck", 1, 1 }, + { "TxDataAckPageEnable", 0, 1 }, + { "TP_PC_CONFIG2", 0x7d4c, 0 }, + { "EnableMtuVfMode", 31, 1 }, + { "EnableMibVfMode", 30, 1 }, + { "DisableLbkCheck", 29, 1 }, + { "EnableUrgDdpOff", 28, 1 }, + { "EnableFilterLpbk", 27, 1 }, + { "DisableTblMmgr", 26, 1 }, + { "CngRecSndNxt", 25, 1 }, + { "EnableLbkChn", 24, 1 }, + { "EnableLroEcn", 23, 1 }, + { "EnablePcmdCheck", 22, 1 }, + { "EnableELbkAFull", 21, 1 }, + { "EnableCLbkAFull", 20, 1 }, + { "EnableOespiFull", 19, 1 }, + { "DisableHitCheck", 18, 1 }, + { "EnableRssErrCheck", 17, 1 }, + { "DisableNewPshFlag", 16, 1 }, + { "EnableRddpRcvAdvClr", 15, 1 }, + { "EnableFinDdpOff", 14, 1 }, + { "EnableArpMiss", 13, 1 }, + { "EnableRstPaws", 12, 1 }, + { "EnableIPv6RSS", 11, 1 }, + { "EnableNonOfdHybRss", 10, 1 }, + { "EnableUDP4TupRss", 9, 1 }, + { "EnableRxPktTmstpRss", 8, 1 }, + { "EnableEPCMDAFull", 7, 1 }, + { "EnableCPCMDAFull", 6, 1 }, + { "EnableEHdrAFull", 5, 1 }, + { "EnableCHdrAFull", 4, 1 }, + { "EnableEMacAFull", 3, 1 }, + { "EnableNonOfdTidRss", 2, 1 }, + { "EnableNonOfdTcbRss", 1, 1 }, + { "EnableTnlOfdClosed", 0, 1 }, + { "TP_TCP_BACKOFF_REG0", 0x7d50, 0 }, + { "TimerBackoffIndex3", 24, 8 }, + { "TimerBackoffIndex2", 16, 8 }, + { "TimerBackoffIndex1", 8, 8 }, + { "TimerBackoffIndex0", 0, 8 }, + { "TP_TCP_BACKOFF_REG1", 0x7d54, 0 }, + { "TimerBackoffIndex7", 24, 8 }, + { "TimerBackoffIndex6", 16, 8 }, + { "TimerBackoffIndex5", 8, 8 }, + { "TimerBackoffIndex4", 0, 8 }, + { "TP_TCP_BACKOFF_REG2", 0x7d58, 0 }, + { "TimerBackoffIndex11", 24, 8 }, + { "TimerBackoffIndex10", 16, 8 }, + { "TimerBackoffIndex9", 8, 8 }, + { "TimerBackoffIndex8", 0, 8 }, + { "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 }, + { "TimerBackoffIndex15", 24, 8 }, + { "TimerBackoffIndex14", 16, 8 }, + { "TimerBackoffIndex13", 8, 8 }, + { "TimerBackoffIndex12", 0, 8 }, + { "TP_PARA_REG0", 0x7d60, 0 }, + { "LimTxThresh", 28, 4 }, + { "InitCwndIdle", 27, 1 }, + { "InitCwnd", 24, 3 }, + { "DupAckThresh", 20, 4 }, + { "ChnErrEnable", 14, 1 }, + { "SetTimeEnable", 13, 1 }, + { "CplErrEnable", 12, 1 }, + { "FastTnlCnt", 11, 1 }, + { "FastTblCnt", 10, 1 }, + { "TpTcamKey", 9, 1 }, + { "SwsMode", 8, 1 }, + { "TsmpMode", 6, 2 }, + { "ByteCountLimit", 4, 2 }, + { "SwsShove", 3, 1 }, + { "TblTimer", 2, 1 }, + { "RxtPace", 1, 1 }, + { "SwsTimer", 0, 1 }, + { "TP_PARA_REG1", 0x7d64, 0 }, + { "InitRwnd", 16, 16 }, + { "InitialSSThresh", 0, 16 }, + { "TP_PARA_REG2", 0x7d68, 0 }, + { "MaxRxData", 16, 16 }, + { "RxCoalesceSize", 0, 16 }, + { "TP_PARA_REG3", 0x7d6c, 0 }, + { "EnableTnlCngLpbk", 31, 1 }, + { "EnableTnlCngFifo", 30, 1 }, + { "EnableTnlCngHdr", 29, 1 }, + { "EnableTnlCngSge", 28, 1 }, + { "RxMacCheck", 27, 1 }, + { "RxSynFilter", 26, 1 }, + { "CngCtrlECN", 25, 1 }, + { "RxDdpOffInit", 24, 1 }, + { "TunnelCngDrop3", 23, 1 }, + { "TunnelCngDrop2", 22, 1 }, + { "TunnelCngDrop1", 21, 1 }, + { "TunnelCngDrop0", 20, 1 }, + { "TxDataAckIdx", 16, 4 }, + { "RxFragEnable", 12, 3 }, + { "TxPaceFixedStrict", 11, 1 }, + { "TxPaceAutoStrict", 10, 1 }, + { "TxPaceFixed", 9, 1 }, + { "TxPaceAuto", 8, 1 }, + { "RxChnTunnel", 7, 1 }, + { "RxUrgTunnel", 6, 1 }, + { "RxUrgMode", 5, 1 }, + { "TxUrgMode", 4, 1 }, + { "CngCtrlMode", 2, 2 }, + { "RxCoalesceEnable", 1, 1 }, + { "RxCoalescePshEn", 0, 1 }, + { "TP_PARA_REG4", 0x7d70, 0 }, + { "IdleCwndHighSpeed", 28, 1 }, + { "RxmtCwndHighSpeed", 27, 1 }, + { "OverdriveHighSpeed", 25, 2 }, + { "ByteCountHighSpeed", 24, 1 }, + { "IdleCwndNewReno", 20, 1 }, + { "RxmtCwndNewReno", 19, 1 }, + { "OverdriveNewReno", 17, 2 }, + { "ByteCountNewReno", 16, 1 }, + { "IdleCwndTahoe", 12, 1 }, + { "RxmtCwndTahoe", 11, 1 }, + { "OverdriveTahoe", 9, 2 }, + { "ByteCountTahoe", 8, 1 }, + { "IdleCwndReno", 4, 1 }, + { "RxmtCwndReno", 3, 1 }, + { "OverdriveReno", 1, 2 }, + { "ByteCountReno", 0, 1 }, + { "TP_PARA_REG5", 0x7d74, 0 }, + { "IndicateSize", 16, 16 }, + { "MaxProxySize", 12, 4 }, + { "EnableReadPdu", 11, 1 }, + { "EnableReadAhead", 10, 1 }, + { "EmptyRqEnable", 9, 1 }, + { "SchdEnable", 8, 1 }, + { "EnableXoffPdu", 7, 1 }, + { "EnableNewFar", 6, 1 }, + { "EnableFragCheck", 5, 1 }, + { "RearmDdpOffset", 4, 1 }, + { "ResetDdpOffset", 3, 1 }, + { "OnFlyDDPEnable", 2, 1 }, + { "DackTimerSpin", 1, 1 }, + { "PushTimerEnable", 0, 1 }, + { "TP_PARA_REG6", 0x7d78, 0 }, + { "TxPDUSizeAdj", 24, 8 }, + { "DisablePDUAck", 20, 1 }, + { "EnableCSav", 19, 1 }, + { "EnableDeferPDU", 18, 1 }, + { "EnableFlush", 17, 1 }, + { "EnableBytePersist", 16, 1 }, + { "DisableTmoCng", 15, 1 }, + { "EnableReadAhead", 14, 1 }, + { "AllowExeption", 13, 1 }, + { "EnableDeferACK", 12, 1 }, + { "EnableESnd", 11, 1 }, + { "EnableCSnd", 10, 1 }, + { "EnablePDUE", 9, 1 }, + { "EnablePDUC", 8, 1 }, + { "EnableBUFI", 7, 1 }, + { "EnableBUFE", 6, 1 }, + { "EnableDefer", 5, 1 }, + { "EnableClearRxmtOos", 4, 1 }, + { "DisablePDUCng", 3, 1 }, + { "DisablePDUTimeout", 2, 1 }, + { "DisablePDURxmt", 1, 1 }, + { "DisablePDUxmt", 0, 1 }, + { "TP_PARA_REG7", 0x7d7c, 0 }, + { "PMMaxXferLen1", 16, 16 }, + { "PMMaxXferLen0", 0, 16 }, + { "TP_ENG_CONFIG", 0x7d80, 0 }, + { "TableLatencyDone", 28, 4 }, + { "TableLatencyStart", 24, 4 }, + { "EngineLatencyDelta", 16, 4 }, + { "EngineLatencyMmgr", 12, 4 }, + { "EngineLatencyWireIp6", 8, 4 }, + { "EngineLatencyWire", 4, 4 }, + { "EngineLatencyBase", 0, 4 }, + { "TP_ERR_CONFIG", 0x7d8c, 0 }, + { "TnlErrorFPMA", 31, 1 }, + { "TnlErrorPing", 30, 1 }, + { "TnlErrorCsum", 29, 1 }, + { "TnlErrorCsumIP", 28, 1 }, + { "TnlErrorTcpOpt", 25, 1 }, + { "TnlErrorPktLen", 24, 1 }, + { "TnlErrorTcpHdrLen", 23, 1 }, + { "TnlErrorIpHdrLen", 22, 1 }, + { "TnlErrorEthHdrLen", 21, 1 }, + { "TnlErrorAttack", 20, 1 }, + { "TnlErrorFrag", 19, 1 }, + { "TnlErrorIpVer", 18, 1 }, + { "TnlErrorMac", 17, 1 }, + { "TnlErrorAny", 16, 1 }, + { "DropErrorFPMA", 15, 1 }, + { "DropErrorPing", 14, 1 }, + { "DropErrorCsum", 13, 1 }, + { "DropErrorCsumIP", 12, 1 }, + { "DropErrorTcpOpt", 9, 1 }, + { "DropErrorPktLen", 8, 1 }, + { "DropErrorTcpHdrLen", 7, 1 }, + { "DropErrorIpHdrLen", 6, 1 }, + { "DropErrorEthHdrLen", 5, 1 }, + { "DropErrorAttack", 4, 1 }, + { "DropErrorFrag", 3, 1 }, + { "DropErrorIpVer", 2, 1 }, + { "DropErrorMac", 1, 1 }, + { "DropErrorAny", 0, 1 }, + { "TP_TIMER_RESOLUTION", 0x7d90, 0 }, + { "TimerResolution", 16, 8 }, + { "TimestampResolution", 8, 8 }, + { "DelayedACKResolution", 0, 8 }, + { "TP_MSL", 0x7d94, 0 }, + { "TP_RXT_MIN", 0x7d98, 0 }, + { "TP_RXT_MAX", 0x7d9c, 0 }, + { "TP_PERS_MIN", 0x7da0, 0 }, + { "TP_PERS_MAX", 0x7da4, 0 }, + { "TP_KEEP_IDLE", 0x7da8, 0 }, + { "TP_KEEP_INTVL", 0x7dac, 0 }, + { "TP_INIT_SRTT", 0x7db0, 0 }, + { "MaxRtt", 16, 16 }, + { "InitSrtt", 0, 16 }, + { "TP_DACK_TIMER", 0x7db4, 0 }, + { "TP_FINWAIT2_TIMER", 0x7db8, 0 }, + { "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 }, + { "TP_SHIFT_CNT", 0x7dc0, 0 }, + { "SynShiftMax", 24, 8 }, + { "RxtShiftMaxR1", 20, 4 }, + { "RxtShiftMaxR2", 16, 4 }, + { "PerShiftBackoffMax", 12, 4 }, + { "PerShiftMax", 8, 4 }, + { "KeepaliveMaxR1", 4, 4 }, + { "KeepaliveMaxR2", 0, 4 }, + { "TP_TM_CONFIG", 0x7dc4, 0 }, + { "TP_TIME_LO", 0x7dc8, 0 }, + { "TP_TIME_HI", 0x7dcc, 0 }, + { "TP_PORT_MTU_0", 0x7dd0, 0 }, + { "Port1MTUValue", 16, 16 }, + { "Port0MTUValue", 0, 16 }, + { "TP_PORT_MTU_1", 0x7dd4, 0 }, + { "Port3MTUValue", 16, 16 }, + { "Port2MTUValue", 0, 16 }, + { "TP_PACE_TABLE", 0x7dd8, 0 }, + { "TP_CCTRL_TABLE", 0x7ddc, 0 }, + { "RowIndex", 16, 16 }, + { "RowValue", 0, 16 }, + { "TP_MTU_TABLE", 0x7de4, 0 }, + { "MTUIndex", 24, 8 }, + { "MTUWidth", 16, 4 }, + { "MTUValue", 0, 14 }, + { "TP_ULP_TABLE", 0x7de8, 0 }, + { "ULPType7Field", 28, 4 }, + { "ULPType6Field", 24, 4 }, + { "ULPType5Field", 20, 4 }, + { "ULPType4Field", 16, 4 }, + { "ULPType3Field", 12, 4 }, + { "ULPType2Field", 8, 4 }, + { "ULPType1Field", 4, 4 }, + { "ULPType0Field", 0, 4 }, + { "TP_RSS_LKP_TABLE", 0x7dec, 0 }, + { "LkpTblRowVld", 31, 1 }, + { "LkpTblRowIdx", 20, 10 }, + { "LkpTblQueue1", 10, 10 }, + { "LkpTblQueue0", 0, 10 }, + { "TP_RSS_CONFIG", 0x7df0, 0 }, + { "TNL4tupEnIpv6", 31, 1 }, + { "TNL2tupEnIpv6", 30, 1 }, + { "TNL4tupEnIpv4", 29, 1 }, + { "TNL2tupEnIpv4", 28, 1 }, + { "TNLTcpSel", 27, 1 }, + { "TNLIp6Sel", 26, 1 }, + { "TNLVrtSel", 25, 1 }, + { "TNLMapEn", 24, 1 }, + { "TNLFcoeMode", 23, 1 }, + { "TNLFcoeEn", 21, 1 }, + { "HashXor", 20, 1 }, + { "OFDHashSave", 19, 1 }, + { "OFDVrtSel", 18, 1 }, + { "OFDMapEn", 17, 1 }, + { "OFDLkpEn", 16, 1 }, + { "SYN4tupEnIpv6", 15, 1 }, + { "SYN2tupEnIpv6", 14, 1 }, + { "SYN4tupEnIpv4", 13, 1 }, + { "SYN2tupEnIpv4", 12, 1 }, + { "SYNIp6Sel", 11, 1 }, + { "SYNVrtSel", 10, 1 }, + { "SYNMapEn", 9, 1 }, + { "SYNLkpEn", 8, 1 }, + { "ChannelEnable", 7, 1 }, + { "PortEnable", 6, 1 }, + { "TNLAllLookup", 5, 1 }, + { "VirtEnable", 4, 1 }, + { "CongestionEnable", 3, 1 }, + { "HashToeplitz", 2, 1 }, + { "UdpEnable", 1, 1 }, + { "Disable", 0, 1 }, + { "TP_RSS_CONFIG_TNL", 0x7df4, 0 }, + { "MaskSize", 28, 4 }, + { "MaskFilter", 16, 11 }, + { "UseWireCh", 0, 1 }, + { "TP_RSS_CONFIG_OFD", 0x7df8, 0 }, + { "MaskSize", 28, 4 }, + { "RRCPLMapEn", 20, 1 }, + { "RRCPLQueWidth", 16, 4 }, + { "FrmwrQueMask", 12, 4 }, + { "TP_RSS_CONFIG_SYN", 0x7dfc, 0 }, + { "MaskSize", 28, 4 }, + { "UseWireCh", 0, 1 }, + { "TP_RSS_CONFIG_VRT", 0x7e00, 0 }, + { "VfRdRg", 25, 1 }, + { "VfRdEn", 24, 1 }, + { "VfPerrEn", 23, 1 }, + { "KeyPerrEn", 22, 1 }, + { "VfVlanEn", 21, 1 }, + { "VfFwEn", 20, 1 }, + { "HashDelay", 16, 4 }, + { "VfWrAddr", 8, 7 }, + { "KeyMode", 6, 2 }, + { "VfWrEn", 5, 1 }, + { "KeyWrEn", 4, 1 }, + { "KeyWrAddr", 0, 4 }, + { "TP_RSS_CONFIG_CNG", 0x7e04, 0 }, + { "ChnCount3", 31, 1 }, + { "ChnCount2", 30, 1 }, + { "ChnCount1", 29, 1 }, + { "ChnCount0", 28, 1 }, + { "ChnUndFlow3", 27, 1 }, + { "ChnUndFlow2", 26, 1 }, + { "ChnUndFlow1", 25, 1 }, + { "ChnUndFlow0", 24, 1 }, + { "ChnOvrFlow3", 23, 1 }, + { "ChnOvrFlow2", 22, 1 }, + { "ChnOvrFlow1", 21, 1 }, + { "ChnOvrFlow0", 20, 1 }, + { "RstChn3", 19, 1 }, + { "RstChn2", 18, 1 }, + { "RstChn1", 17, 1 }, + { "RstChn0", 16, 1 }, + { "UpdVld", 15, 1 }, + { "Xoff", 14, 1 }, + { "UpdChn3", 13, 1 }, + { "UpdChn2", 12, 1 }, + { "UpdChn1", 11, 1 }, + { "UpdChn0", 10, 1 }, + { "Queue", 0, 10 }, + { "TP_LA_TABLE_0", 0x7e10, 0 }, + { "VirtPort1Table", 16, 16 }, + { "VirtPort0Table", 0, 16 }, + { "TP_LA_TABLE_1", 0x7e14, 0 }, + { "VirtPort3Table", 16, 16 }, + { "VirtPort2Table", 0, 16 }, + { "TP_TM_PIO_ADDR", 0x7e18, 0 }, + { "TP_TM_PIO_DATA", 0x7e1c, 0 }, + { "TP_MOD_CONFIG", 0x7e24, 0 }, + { "RxChannelWeight1", 24, 8 }, + { "RXChannelWeight0", 16, 8 }, + { "TimerMode", 8, 8 }, + { "TxChannelXoffEn", 0, 4 }, + { "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 }, + { "RX_MOD_WEIGHT", 24, 8 }, + { "TX_MOD_WEIGHT", 16, 8 }, + { "TX_MOD_QUEUE_REQ_MAP", 0, 16 }, + { "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 }, + { "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 }, + { "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 }, + { "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 }, + { "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 }, + { "CH3", 24, 8 }, + { "CH2", 16, 8 }, + { "CH1", 8, 8 }, + { "CH0", 0, 8 }, + { "TP_MOD_RATE_LIMIT", 0x7e38, 0 }, + { "RX_MOD_RATE_LIMIT_INC", 24, 8 }, + { "RX_MOD_RATE_LIMIT_TICK", 16, 8 }, + { "TX_MOD_RATE_LIMIT_INC", 8, 8 }, + { "TX_MOD_RATE_LIMIT_TICK", 0, 8 }, + { "TP_PIO_ADDR", 0x7e40, 0 }, + { "TP_PIO_DATA", 0x7e44, 0 }, + { "TP_RESET", 0x7e4c, 0 }, + { "FlstInitEnable", 1, 1 }, + { "TPReset", 0, 1 }, + { "TP_MIB_INDEX", 0x7e50, 0 }, + { "TP_MIB_DATA", 0x7e54, 0 }, + { "TP_SYNC_TIME_HI", 0x7e58, 0 }, + { "TP_SYNC_TIME_LO", 0x7e5c, 0 }, + { "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 }, + { "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 }, + { "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 }, + { "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 }, + { "TP_INT_ENABLE", 0x7e70, 0 }, + { "FlmTxFlstEmpty", 30, 1 }, + { "RssLkpPerr", 29, 1 }, + { "FlmPerrSet", 28, 1 }, + { "ProtocolSramPerr", 27, 1 }, + { "ArpLutPerr", 26, 1 }, + { "CmRcfOpPerr", 25, 1 }, + { "CmCachePerr", 24, 1 }, + { "CmRcfDataPerr", 23, 1 }, + { "DbL2tLutPerr", 22, 1 }, + { "DbTxTidPerr", 21, 1 }, + { "DbExtPerr", 20, 1 }, + { "DbOpPerr", 19, 1 }, + { "TmCachePerr", 18, 1 }, + { "ETpOutCplFifoPerr", 17, 1 }, + { "ETpOutTcpFifoPerr", 16, 1 }, + { "ETpOutIpFifoPerr", 15, 1 }, + { "ETpOutEthFifoPerr", 14, 1 }, + { "ETpInCplFifoPerr", 13, 1 }, + { "ETpInTcpOptFifoPerr", 12, 1 }, + { "ETpInTcpFifoPerr", 11, 1 }, + { "ETpInIpFifoPerr", 10, 1 }, + { "ETpInEthFifoPerr", 9, 1 }, + { "CTpOutCplFifoPerr", 8, 1 }, + { "CTpOutPldFifoPerr", 7, 1 }, + { "CTpOutIpFifoPerr", 6, 1 }, + { "CTpOutEthFifoPerr", 5, 1 }, + { "CTpInCplFifoPerr", 4, 1 }, + { "CTpInTcpOpFifoPerr", 3, 1 }, + { "PduFbkFifoPerr", 2, 1 }, + { "CmOpExtFifoPerr", 1, 1 }, + { "DelInvFifoPerr", 0, 1 }, + { "TP_INT_CAUSE", 0x7e74, 0 }, + { "FlmTxFlstEmpty", 30, 1 }, + { "RssLkpPerr", 29, 1 }, + { "FlmPerrSet", 28, 1 }, + { "ProtocolSramPerr", 27, 1 }, + { "ArpLutPerr", 26, 1 }, + { "CmRcfOpPerr", 25, 1 }, + { "CmCachePerr", 24, 1 }, + { "CmRcfDataPerr", 23, 1 }, + { "DbL2tLutPerr", 22, 1 }, + { "DbTxTidPerr", 21, 1 }, + { "DbExtPerr", 20, 1 }, + { "DbOpPerr", 19, 1 }, + { "TmCachePerr", 18, 1 }, + { "ETpOutCplFifoPerr", 17, 1 }, + { "ETpOutTcpFifoPerr", 16, 1 }, + { "ETpOutIpFifoPerr", 15, 1 }, + { "ETpOutEthFifoPerr", 14, 1 }, + { "ETpInCplFifoPerr", 13, 1 }, + { "ETpInTcpOptFifoPerr", 12, 1 }, + { "ETpInTcpFifoPerr", 11, 1 }, + { "ETpInIpFifoPerr", 10, 1 }, + { "ETpInEthFifoPerr", 9, 1 }, + { "CTpOutCplFifoPerr", 8, 1 }, + { "CTpOutPldFifoPerr", 7, 1 }, + { "CTpOutIpFifoPerr", 6, 1 }, + { "CTpOutEthFifoPerr", 5, 1 }, + { "CTpInCplFifoPerr", 4, 1 }, + { "CTpInTcpOpFifoPerr", 3, 1 }, + { "PduFbkFifoPerr", 2, 1 }, + { "CmOpExtFifoPerr", 1, 1 }, + { "DelInvFifoPerr", 0, 1 }, + { "TP_PER_ENABLE", 0x7e78, 0 }, + { "FlmTxFlstEmpty", 30, 1 }, + { "RssLkpPerr", 29, 1 }, + { "FlmPerrSet", 28, 1 }, + { "ProtocolSramPerr", 27, 1 }, + { "ArpLutPerr", 26, 1 }, + { "CmRcfOpPerr", 25, 1 }, + { "CmCachePerr", 24, 1 }, + { "CmRcfDataPerr", 23, 1 }, + { "DbL2tLutPerr", 22, 1 }, + { "DbTxTidPerr", 21, 1 }, + { "DbExtPerr", 20, 1 }, + { "DbOpPerr", 19, 1 }, + { "TmCachePerr", 18, 1 }, + { "ETpOutCplFifoPerr", 17, 1 }, + { "ETpOutTcpFifoPerr", 16, 1 }, + { "ETpOutIpFifoPerr", 15, 1 }, + { "ETpOutEthFifoPerr", 14, 1 }, + { "ETpInCplFifoPerr", 13, 1 }, + { "ETpInTcpOptFifoPerr", 12, 1 }, + { "ETpInTcpFifoPerr", 11, 1 }, + { "ETpInIpFifoPerr", 10, 1 }, + { "ETpInEthFifoPerr", 9, 1 }, + { "CTpOutCplFifoPerr", 8, 1 }, + { "CTpOutPldFifoPerr", 7, 1 }, + { "CTpOutIpFifoPerr", 6, 1 }, + { "CTpOutEthFifoPerr", 5, 1 }, + { "CTpInCplFifoPerr", 4, 1 }, + { "CTpInTcpOpFifoPerr", 3, 1 }, + { "PduFbkFifoPerr", 2, 1 }, + { "CmOpExtFifoPerr", 1, 1 }, + { "DelInvFifoPerr", 0, 1 }, + { "TP_FLM_FREE_PS_CNT", 0x7e80, 0 }, + { "TP_FLM_FREE_RX_CNT", 0x7e84, 0 }, + { "FreeRxPageChn", 28, 1 }, + { "FreeRxPageCount", 0, 21 }, + { "TP_FLM_FREE_TX_CNT", 0x7e88, 0 }, + { "FreeTxPageChn", 28, 2 }, + { "FreeTxPageCount", 0, 21 }, + { "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 }, + { "TP_TM_HEAP_POP_CNT", 0x7e90, 0 }, + { "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 }, + { "TP_TM_DACK_POP_CNT", 0x7e98, 0 }, + { "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 }, + { "TP_MOD_POP_CNT", 0x7ea0, 0 }, + { "TP_TIMER_SEPARATOR", 0x7ea4, 0 }, + { "TimerSeparator", 16, 16 }, + { "DisableTimeFreeze", 0, 1 }, + { "TP_STAMP_TIME", 0x7ea8, 0 }, + { "TP_DEBUG_FLAGS", 0x7eac, 0 }, + { "RxTimerCompBuffer", 27, 1 }, + { "RxTimerDackFirst", 26, 1 }, + { "RxTimerDack", 25, 1 }, + { "RxTimerHeartbeat", 24, 1 }, + { "RxPawsDrop", 23, 1 }, + { "RxUrgDataDrop", 22, 1 }, + { "RxFutureData", 21, 1 }, + { "RxRcvRxmData", 20, 1 }, + { "RxRcvOooDataFin", 19, 1 }, + { "RxRcvOooData", 18, 1 }, + { "RxRcvWndZero", 17, 1 }, + { "RxRcvWndLtMss", 16, 1 }, + { "TxDfrFast", 13, 1 }, + { "TxRxmMisc", 12, 1 }, + { "TxDupAckInc", 11, 1 }, + { "TxRxmUrg", 10, 1 }, + { "TxRxmFin", 9, 1 }, + { "TxRxmSyn", 8, 1 }, + { "TxRxmNewReno", 7, 1 }, + { "TxRxmFast", 6, 1 }, + { "TxRxmTimer", 5, 1 }, + { "TxRxmTimerKeepalive", 4, 1 }, + { "TxRxmTimerPersist", 3, 1 }, + { "TxRcvAdvShrunk", 2, 1 }, + { "TxRcvAdvZero", 1, 1 }, + { "TxRcvAdvLtMss", 0, 1 }, + { "TP_RX_SCHED", 0x7eb0, 0 }, + { "CommitReset1", 31, 1 }, + { "CommitReset0", 30, 1 }, + { "ForceCong1", 29, 1 }, + { "ForceCong0", 28, 1 }, + { "EnableLpbkFull1", 26, 2 }, + { "EnableLpbkFull0", 24, 2 }, + { "EnableFifoFull1", 22, 2 }, + { "EnablePcmdFull1", 20, 2 }, + { "EnableHdrFull1", 18, 2 }, + { "EnableFifoFull0", 16, 2 }, + { "EnablePcmdFull0", 14, 2 }, + { "EnableHdrFull0", 12, 2 }, + { "TP_TX_SCHED", 0x7eb4, 0 }, + { "CommitReset3", 31, 1 }, + { "CommitReset2", 30, 1 }, + { "CommitReset1", 29, 1 }, + { "CommitReset0", 28, 1 }, + { "ForceCong3", 27, 1 }, + { "ForceCong2", 26, 1 }, + { "ForceCong1", 25, 1 }, + { "ForceCong0", 24, 1 }, + { "CommitLimit3", 18, 6 }, + { "CommitLimit2", 12, 6 }, + { "CommitLimit1", 6, 6 }, + { "CommitLimit0", 0, 6 }, + { "TP_FX_SCHED", 0x7eb8, 0 }, + { "TxChnXoff3", 19, 1 }, + { "TxChnXoff2", 18, 1 }, + { "TxChnXoff1", 17, 1 }, + { "TxChnXoff0", 16, 1 }, + { "TxModXoff7", 15, 1 }, + { "TxModXoff6", 14, 1 }, + { "TxModXoff5", 13, 1 }, + { "TxModXoff4", 12, 1 }, + { "TxModXoff3", 11, 1 }, + { "TxModXoff2", 10, 1 }, + { "TxModXoff1", 9, 1 }, + { "TxModXoff0", 8, 1 }, + { "RxChnXoff3", 7, 1 }, + { "RxChnXoff2", 6, 1 }, + { "RxChnXoff1", 5, 1 }, + { "RxChnXoff0", 4, 1 }, + { "RxModXoff1", 1, 1 }, + { "RxModXoff0", 0, 1 }, + { "TP_TX_ORATE", 0x7ebc, 0 }, + { "OfdRate3", 24, 8 }, + { "OfdRate2", 16, 8 }, + { "OfdRate1", 8, 8 }, + { "OfdRate0", 0, 8 }, + { "TP_IX_SCHED0", 0x7ec0, 0 }, + { "TP_IX_SCHED1", 0x7ec4, 0 }, + { "TP_IX_SCHED2", 0x7ec8, 0 }, + { "TP_IX_SCHED3", 0x7ecc, 0 }, + { "TP_TX_TRATE", 0x7ed0, 0 }, + { "TnlRate3", 24, 8 }, + { "TnlRate2", 16, 8 }, + { "TnlRate1", 8, 8 }, + { "TnlRate0", 0, 8 }, + { "TP_DBG_LA_CONFIG", 0x7ed4, 0 }, + { "DbgLaOpcEnable", 24, 8 }, + { "DbgLaWhlf", 23, 1 }, + { "DbgLaWptr", 16, 7 }, + { "DbgLaMode", 14, 2 }, + { "DbgLaFatalFreeze", 13, 1 }, + { "DbgLaEnable", 12, 1 }, + { "DbgLaRptr", 0, 7 }, + { "TP_DBG_LA_DATAL", 0x7ed8, 0 }, + { "TP_DBG_LA_DATAH", 0x7edc, 0 }, + { "TP_PROTOCOL_CNTRL", 0x7ee8, 0 }, + { "WriteEnable", 31, 1 }, + { "TcamEnable", 10, 1 }, + { "BlockSelect", 8, 2 }, + { "LineAddress", 1, 7 }, + { "RequestDone", 0, 1 }, + { "TP_PROTOCOL_DATA0", 0x7eec, 0 }, + { "TP_PROTOCOL_DATA1", 0x7ef0, 0 }, + { "TP_PROTOCOL_DATA2", 0x7ef4, 0 }, + { "TP_PROTOCOL_DATA3", 0x7ef8, 0 }, + { "TP_PROTOCOL_DATA4", 0x7efc, 0 }, + { NULL } +}; + +struct reg_info t5_ulp_tx_regs[] = { + { "ULP_TX_CONFIG", 0x8dc0, 0 }, + { "PHYS_ADDR_RESP_EN", 6, 1 }, + { "ENDIANESS_CHANGE", 5, 1 }, + { "ERR_RTAG_EN", 4, 1 }, + { "TSO_ETHLEN_EN", 3, 1 }, + { "emsg_more_info", 2, 1 }, + { "LOSDR", 1, 1 }, + { "extra_tag_insertion_enable", 0, 1 }, + { "ULP_TX_PERR_INJECT", 0x8dc4, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "ULP_TX_INT_ENABLE", 0x8dc8, 0 }, + { "Pbl_bound_err_ch3", 31, 1 }, + { "Pbl_bound_err_ch2", 30, 1 }, + { "Pbl_bound_err_ch1", 29, 1 }, + { "Pbl_bound_err_ch0", 28, 1 }, + { "sge2ulp_fifo_perr_set3", 27, 1 }, + { "sge2ulp_fifo_perr_set2", 26, 1 }, + { "sge2ulp_fifo_perr_set1", 25, 1 }, + { "sge2ulp_fifo_perr_set0", 24, 1 }, + { "cim2ulp_fifo_perr_set3", 23, 1 }, + { "cim2ulp_fifo_perr_set2", 22, 1 }, + { "cim2ulp_fifo_perr_set1", 21, 1 }, + { "cim2ulp_fifo_perr_set0", 20, 1 }, + { "CQE_fifo_perr_set3", 19, 1 }, + { "CQE_fifo_perr_set2", 18, 1 }, + { "CQE_fifo_perr_set1", 17, 1 }, + { "CQE_fifo_perr_set0", 16, 1 }, + { "pbl_fifo_perr_set3", 15, 1 }, + { "pbl_fifo_perr_set2", 14, 1 }, + { "pbl_fifo_perr_set1", 13, 1 }, + { "pbl_fifo_perr_set0", 12, 1 }, + { "cmd_fifo_perr_set3", 11, 1 }, + { "cmd_fifo_perr_set2", 10, 1 }, + { "cmd_fifo_perr_set1", 9, 1 }, + { "cmd_fifo_perr_set0", 8, 1 }, + { "lso_hdr_sram_perr_set3", 7, 1 }, + { "lso_hdr_sram_perr_set2", 6, 1 }, + { "lso_hdr_sram_perr_set1", 5, 1 }, + { "lso_hdr_sram_perr_set0", 4, 1 }, + { "ULP_TX_INT_CAUSE", 0x8dcc, 0 }, + { "Pbl_bound_err_ch3", 31, 1 }, + { "Pbl_bound_err_ch2", 30, 1 }, + { "Pbl_bound_err_ch1", 29, 1 }, + { "Pbl_bound_err_ch0", 28, 1 }, + { "sge2ulp_fifo_perr_set3", 27, 1 }, + { "sge2ulp_fifo_perr_set2", 26, 1 }, + { "sge2ulp_fifo_perr_set1", 25, 1 }, + { "sge2ulp_fifo_perr_set0", 24, 1 }, + { "cim2ulp_fifo_perr_set3", 23, 1 }, + { "cim2ulp_fifo_perr_set2", 22, 1 }, + { "cim2ulp_fifo_perr_set1", 21, 1 }, + { "cim2ulp_fifo_perr_set0", 20, 1 }, + { "CQE_fifo_perr_set3", 19, 1 }, + { "CQE_fifo_perr_set2", 18, 1 }, + { "CQE_fifo_perr_set1", 17, 1 }, + { "CQE_fifo_perr_set0", 16, 1 }, + { "pbl_fifo_perr_set3", 15, 1 }, + { "pbl_fifo_perr_set2", 14, 1 }, + { "pbl_fifo_perr_set1", 13, 1 }, + { "pbl_fifo_perr_set0", 12, 1 }, + { "cmd_fifo_perr_set3", 11, 1 }, + { "cmd_fifo_perr_set2", 10, 1 }, + { "cmd_fifo_perr_set1", 9, 1 }, + { "cmd_fifo_perr_set0", 8, 1 }, + { "lso_hdr_sram_perr_set3", 7, 1 }, + { "lso_hdr_sram_perr_set2", 6, 1 }, + { "lso_hdr_sram_perr_set1", 5, 1 }, + { "lso_hdr_sram_perr_set0", 4, 1 }, + { "ULP_TX_PERR_ENABLE", 0x8dd0, 0 }, + { "sge2ulp_fifo_perr_set3", 27, 1 }, + { "sge2ulp_fifo_perr_set2", 26, 1 }, + { "sge2ulp_fifo_perr_set1", 25, 1 }, + { "sge2ulp_fifo_perr_set0", 24, 1 }, + { "cim2ulp_fifo_perr_set3", 23, 1 }, + { "cim2ulp_fifo_perr_set2", 22, 1 }, + { "cim2ulp_fifo_perr_set1", 21, 1 }, + { "cim2ulp_fifo_perr_set0", 20, 1 }, + { "CQE_fifo_perr_set3", 19, 1 }, + { "CQE_fifo_perr_set2", 18, 1 }, + { "CQE_fifo_perr_set1", 17, 1 }, + { "CQE_fifo_perr_set0", 16, 1 }, + { "pbl_fifo_perr_set3", 15, 1 }, + { "pbl_fifo_perr_set2", 14, 1 }, + { "pbl_fifo_perr_set1", 13, 1 }, + { "pbl_fifo_perr_set0", 12, 1 }, + { "cmd_fifo_perr_set3", 11, 1 }, + { "cmd_fifo_perr_set2", 10, 1 }, + { "cmd_fifo_perr_set1", 9, 1 }, + { "cmd_fifo_perr_set0", 8, 1 }, + { "lso_hdr_sram_perr_set3", 7, 1 }, + { "lso_hdr_sram_perr_set2", 6, 1 }, + { "lso_hdr_sram_perr_set1", 5, 1 }, + { "lso_hdr_sram_perr_set0", 4, 1 }, + { "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 }, + { "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 }, + { "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 }, + { "ULP_TX_PBL_ULIMIT", 0x8de0, 0 }, + { "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 }, + { "Ch3Size1", 24, 8 }, + { "Ch2Size1", 16, 8 }, + { "Ch1Size1", 8, 8 }, + { "Ch0Size1", 0, 8 }, + { "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 }, + { "Ch3Size2", 24, 8 }, + { "Ch2Size2", 16, 8 }, + { "Ch1Size2", 8, 8 }, + { "Ch0Size2", 0, 8 }, + { "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 }, + { "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 }, + { "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 }, + { "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 }, + { "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 }, + { "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 }, + { "ULP_TX_FC_SOF", 0x8e20, 0 }, + { "SOF_FS3", 24, 8 }, + { "SOF_FS2", 16, 8 }, + { "SOF_3", 8, 8 }, + { "SOF_2", 0, 8 }, + { "ULP_TX_FC_EOF", 0x8e24, 0 }, + { "EOF_LS3", 24, 8 }, + { "EOF_LS2", 16, 8 }, + { "EOF_3", 8, 8 }, + { "EOF_2", 0, 8 }, + { "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 }, + { "ULP_TX_CGEN", 0x8e2c, 0 }, + { "ULP_TX_CGEN_Storage", 8, 4 }, + { "ULP_TX_CGEN_RDMA", 4, 4 }, + { "ULP_TX_CGEN_Channel", 0, 4 }, + { "ULP_TX_MEM_CFG", 0x8e30, 0 }, + { "ULP_TX_PERR_INJECT_2", 0x8e34, 0 }, + { "MemSel", 1, 3 }, + { "InjectDataErr", 0, 1 }, + { "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 }, + { "smarbt2ulp_data_perr_set", 12, 1 }, + { "ulp2tp_data_perr_set", 11, 1 }, + { "ma2ulp_data_perr_set", 10, 1 }, + { "sge2ulp_data_perr_set", 9, 1 }, + { "cim2ulp_data_perr_set", 8, 1 }, + { "fso_hdr_sram_perr_set3", 7, 1 }, + { "fso_hdr_sram_perr_set2", 6, 1 }, + { "fso_hdr_sram_perr_set1", 5, 1 }, + { "fso_hdr_sram_perr_set0", 4, 1 }, + { "t10_pi_sram_perr_set3", 3, 1 }, + { "t10_pi_sram_perr_set2", 2, 1 }, + { "t10_pi_sram_perr_set1", 1, 1 }, + { "t10_pi_sram_perr_set0", 0, 1 }, + { "ULP_TX_INT_CAUSE_2", 0x8e80, 0 }, + { "smarbt2ulp_data_perr_set", 12, 1 }, + { "ulp2tp_data_perr_set", 11, 1 }, + { "ma2ulp_data_perr_set", 10, 1 }, + { "sge2ulp_data_perr_set", 9, 1 }, + { "cim2ulp_data_perr_set", 8, 1 }, + { "fso_hdr_sram_perr_set3", 7, 1 }, + { "fso_hdr_sram_perr_set2", 6, 1 }, + { "fso_hdr_sram_perr_set1", 5, 1 }, + { "fso_hdr_sram_perr_set0", 4, 1 }, + { "t10_pi_sram_perr_set3", 3, 1 }, + { "t10_pi_sram_perr_set2", 2, 1 }, + { "t10_pi_sram_perr_set1", 1, 1 }, + { "t10_pi_sram_perr_set0", 0, 1 }, + { "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 }, + { "smarbt2ulp_data_perr_set", 12, 1 }, + { "ulp2tp_data_perr_set", 11, 1 }, + { "ma2ulp_data_perr_set", 10, 1 }, + { "sge2ulp_data_perr_set", 9, 1 }, + { "cim2ulp_data_perr_set", 8, 1 }, + { "fso_hdr_sram_perr_set3", 7, 1 }, + { "fso_hdr_sram_perr_set2", 6, 1 }, + { "fso_hdr_sram_perr_set1", 5, 1 }, + { "fso_hdr_sram_perr_set0", 4, 1 }, + { "t10_pi_sram_perr_set3", 3, 1 }, + { "t10_pi_sram_perr_set2", 2, 1 }, + { "t10_pi_sram_perr_set1", 1, 1 }, + { "t10_pi_sram_perr_set0", 0, 1 }, + { "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 }, + { "ERR_CH3", 12, 4 }, + { "ERR_CH2", 8, 4 }, + { "ERR_CH1", 4, 4 }, + { "ERR_CH0", 0, 4 }, + { "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 }, + { "CLR_DROP", 16, 4 }, + { "CLR_CH3", 12, 4 }, + { "CLR_CH2", 8, 4 }, + { "CLR_CH1", 4, 4 }, + { "CLR_CH0", 0, 4 }, + { "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 }, + { "SOP_CNT_ULP2TP", 28, 4 }, + { "EOP_CNT_ULP2TP", 24, 4 }, + { "SOP_CNT_LSO_IN", 20, 4 }, + { "EOP_CNT_LSO_IN", 16, 4 }, + { "SOP_CNT_ALG_IN", 12, 4 }, + { "EOP_CNT_ALG_IN", 8, 4 }, + { "SOP_CNT_CIM2ULP", 4, 4 }, + { "EOP_CNT_CIM2ULP", 0, 4 }, + { "ULP_TX_SE_CNT_CH1", 0x8eac, 0 }, + { "SOP_CNT_ULP2TP", 28, 4 }, + { "EOP_CNT_ULP2TP", 24, 4 }, + { "SOP_CNT_LSO_IN", 20, 4 }, + { "EOP_CNT_LSO_IN", 16, 4 }, + { "SOP_CNT_ALG_IN", 12, 4 }, + { "EOP_CNT_ALG_IN", 8, 4 }, + { "SOP_CNT_CIM2ULP", 4, 4 }, + { "EOP_CNT_CIM2ULP", 0, 4 }, + { "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 }, + { "SOP_CNT_ULP2TP", 28, 4 }, + { "EOP_CNT_ULP2TP", 24, 4 }, + { "SOP_CNT_LSO_IN", 20, 4 }, + { "EOP_CNT_LSO_IN", 16, 4 }, + { "SOP_CNT_ALG_IN", 12, 4 }, + { "EOP_CNT_ALG_IN", 8, 4 }, + { "SOP_CNT_CIM2ULP", 4, 4 }, + { "EOP_CNT_CIM2ULP", 0, 4 }, + { "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 }, + { "SOP_CNT_ULP2TP", 28, 4 }, + { "EOP_CNT_ULP2TP", 24, 4 }, + { "SOP_CNT_LSO_IN", 20, 4 }, + { "EOP_CNT_LSO_IN", 16, 4 }, + { "SOP_CNT_ALG_IN", 12, 4 }, + { "EOP_CNT_ALG_IN", 8, 4 }, + { "SOP_CNT_CIM2ULP", 4, 4 }, + { "EOP_CNT_CIM2ULP", 0, 4 }, + { "ULP_TX_DROP_CNT", 0x8eb8, 0 }, + { "DROP_CH3", 12, 4 }, + { "DROP_CH2", 8, 4 }, + { "DROP_CH1", 4, 4 }, + { "DROP_CH0", 0, 4 }, + { "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 }, + { "channel_sel", 12, 2 }, + { "intf_sel", 4, 4 }, + { "num_flits", 1, 3 }, + { "cmd_gen_en", 0, 1 }, + { "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 }, + { "ULP_TX_FPGA_CMD_1", 0x8e40, 0 }, + { "ULP_TX_FPGA_CMD_2", 0x8e44, 0 }, + { "ULP_TX_FPGA_CMD_3", 0x8e48, 0 }, + { "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 }, + { "ULP_TX_FPGA_CMD_5", 0x8e50, 0 }, + { "ULP_TX_FPGA_CMD_6", 0x8e54, 0 }, + { "ULP_TX_FPGA_CMD_7", 0x8e58, 0 }, + { "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 }, + { "ULP_TX_FPGA_CMD_9", 0x8e60, 0 }, + { "ULP_TX_FPGA_CMD_10", 0x8e64, 0 }, + { "ULP_TX_FPGA_CMD_11", 0x8e68, 0 }, + { "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 }, + { "ULP_TX_FPGA_CMD_13", 0x8e70, 0 }, + { "ULP_TX_FPGA_CMD_14", 0x8e74, 0 }, + { "ULP_TX_FPGA_CMD_15", 0x8e78, 0 }, + { "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 }, + { "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 }, + { "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 }, + { "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 }, + { "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 }, + { "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 }, + { "ULP_TX_CSU_REVISION", 0x8ebc, 0 }, + { "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 }, + { "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 }, + { "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 }, + { "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 }, + { "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 }, + { "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 }, + { "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 }, + { "ULP_TX_LA_RESERVED_1", 0x8edc, 0 }, + { "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 }, + { "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 }, + { "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 }, + { "ULP_TX_LA_RESERVED_2", 0x8eec, 0 }, + { "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 }, + { "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 }, + { "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 }, + { "ULP_TX_LA_RESERVED_3", 0x8efc, 0 }, + { "ULP_TX_LA_RDPTR_4", 0x8f00, 0 }, + { "ULP_TX_LA_RDDATA_4", 0x8f04, 0 }, + { "ULP_TX_LA_WRPTR_4", 0x8f08, 0 }, + { "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 }, + { "ULP_TX_LA_RDPTR_5", 0x8f10, 0 }, + { "ULP_TX_LA_RDDATA_5", 0x8f14, 0 }, + { "ULP_TX_LA_WRPTR_5", 0x8f18, 0 }, + { "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 }, + { "ULP_TX_LA_RDPTR_6", 0x8f20, 0 }, + { "ULP_TX_LA_RDDATA_6", 0x8f24, 0 }, + { "ULP_TX_LA_WRPTR_6", 0x8f28, 0 }, + { "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 }, + { "ULP_TX_LA_RDPTR_7", 0x8f30, 0 }, + { "ULP_TX_LA_RDDATA_7", 0x8f34, 0 }, + { "ULP_TX_LA_WRPTR_7", 0x8f38, 0 }, + { "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 }, + { "ULP_TX_LA_RDPTR_8", 0x8f40, 0 }, + { "ULP_TX_LA_RDDATA_8", 0x8f44, 0 }, + { "ULP_TX_LA_WRPTR_8", 0x8f48, 0 }, + { "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 }, + { "ULP_TX_LA_RDPTR_9", 0x8f50, 0 }, + { "ULP_TX_LA_RDDATA_9", 0x8f54, 0 }, + { "ULP_TX_LA_WRPTR_9", 0x8f58, 0 }, + { "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 }, + { "ULP_TX_LA_RDPTR_10", 0x8f60, 0 }, + { "ULP_TX_LA_RDDATA_10", 0x8f64, 0 }, + { "ULP_TX_LA_WRPTR_10", 0x8f68, 0 }, + { "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 }, + { NULL } +}; + +struct reg_info t5_pm_rx_regs[] = { + { "PM_RX_CFG", 0x8fc0, 0 }, + { "ch1_output", 27, 5 }, + { "strobe1", 16, 1 }, + { "ch1_input", 11, 5 }, + { "ch2_input", 6, 5 }, + { "ch3_input", 1, 5 }, + { "strobe0", 0, 1 }, + { "PM_RX_MODE", 0x8fc4, 0 }, + { "use_bundle_len", 4, 1 }, + { "stat_to_ch", 3, 1 }, + { "stat_from_ch", 1, 2 }, + { "prefetch_enable", 0, 1 }, + { "PM_RX_STAT_CONFIG", 0x8fc8, 0 }, + { "PM_RX_STAT_COUNT", 0x8fcc, 0 }, + { "PM_RX_DBG_CTRL", 0x8fd0, 0 }, + { "OspiWrBusy", 21, 2 }, + { "IspiWrBusy", 17, 4 }, + { "PMDbgAddr", 0, 17 }, + { "PM_RX_DBG_DATA", 0x8fd4, 0 }, + { "PM_RX_INT_ENABLE", 0x8fd8, 0 }, + { "ospi_overflow1", 28, 1 }, + { "ospi_overflow0", 27, 1 }, + { "ma_intf_sdc_err", 26, 1 }, + { "bundle_len_ParErr", 25, 1 }, + { "bundle_len_ovfl", 24, 1 }, + { "sdc_err", 23, 1 }, + { "zero_e_cmd_error", 22, 1 }, + { "iespi0_fifo2x_Rx_framing_error", 21, 1 }, + { "iespi1_fifo2x_Rx_framing_error", 20, 1 }, + { "iespi2_fifo2x_Rx_framing_error", 19, 1 }, + { "iespi3_fifo2x_Rx_framing_error", 18, 1 }, + { "iespi0_Rx_framing_error", 17, 1 }, + { "iespi1_Rx_framing_error", 16, 1 }, + { "iespi2_Rx_framing_error", 15, 1 }, + { "iespi3_Rx_framing_error", 14, 1 }, + { "iespi0_Tx_framing_error", 13, 1 }, + { "iespi1_Tx_framing_error", 12, 1 }, + { "iespi2_Tx_framing_error", 11, 1 }, + { "iespi3_Tx_framing_error", 10, 1 }, + { "ocspi0_Rx_framing_error", 9, 1 }, + { "ocspi1_Rx_framing_error", 8, 1 }, + { "ocspi0_Tx_framing_error", 7, 1 }, + { "ocspi1_Tx_framing_error", 6, 1 }, + { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 }, + { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 }, + { "ocspi_par_error", 3, 1 }, + { "db_options_par_error", 2, 1 }, + { "iespi_par_error", 1, 1 }, + { "e_pcmd_par_error", 0, 1 }, + { "PM_RX_INT_CAUSE", 0x8fdc, 0 }, + { "ospi_overflow1", 28, 1 }, + { "ospi_overflow0", 27, 1 }, + { "ma_intf_sdc_err", 26, 1 }, + { "bundle_len_ParErr", 25, 1 }, + { "bundle_len_ovfl", 24, 1 }, + { "sdc_err", 23, 1 }, + { "zero_e_cmd_error", 22, 1 }, + { "iespi0_fifo2x_Rx_framing_error", 21, 1 }, + { "iespi1_fifo2x_Rx_framing_error", 20, 1 }, + { "iespi2_fifo2x_Rx_framing_error", 19, 1 }, + { "iespi3_fifo2x_Rx_framing_error", 18, 1 }, + { "iespi0_Rx_framing_error", 17, 1 }, + { "iespi1_Rx_framing_error", 16, 1 }, + { "iespi2_Rx_framing_error", 15, 1 }, + { "iespi3_Rx_framing_error", 14, 1 }, + { "iespi0_Tx_framing_error", 13, 1 }, + { "iespi1_Tx_framing_error", 12, 1 }, + { "iespi2_Tx_framing_error", 11, 1 }, + { "iespi3_Tx_framing_error", 10, 1 }, + { "ocspi0_Rx_framing_error", 9, 1 }, + { "ocspi1_Rx_framing_error", 8, 1 }, + { "ocspi0_Tx_framing_error", 7, 1 }, + { "ocspi1_Tx_framing_error", 6, 1 }, + { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 }, + { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 }, + { "ocspi_par_error", 3, 1 }, + { "db_options_par_error", 2, 1 }, + { "iespi_par_error", 1, 1 }, + { "e_pcmd_par_error", 0, 1 }, + { NULL } +}; + +struct reg_info t5_pm_tx_regs[] = { + { "PM_TX_CFG", 0x8fe0, 0 }, + { "ch1_output", 27, 5 }, + { "ch2_output", 22, 5 }, + { "ch3_output", 17, 5 }, + { "strobe1", 16, 1 }, + { "ch1_input", 11, 5 }, + { "ch2_input", 6, 5 }, + { "ch3_input", 1, 5 }, + { "strobe0", 0, 1 }, + { "PM_TX_MODE", 0x8fe4, 0 }, + { "cong_thresh3", 25, 7 }, + { "cong_thresh2", 18, 7 }, + { "cong_thresh1", 11, 7 }, + { "cong_thresh0", 4, 7 }, + { "use_bundle_len", 3, 1 }, + { "stat_channel", 1, 2 }, + { "prefetch_enable", 0, 1 }, + { "PM_TX_STAT_CONFIG", 0x8fe8, 0 }, + { "PM_TX_STAT_COUNT", 0x8fec, 0 }, + { "PM_TX_DBG_CTRL", 0x8ff0, 0 }, + { "OspiWrBusy", 21, 4 }, + { "IspiWrBusy", 17, 4 }, + { "PMDbgAddr", 0, 17 }, + { "PM_TX_DBG_DATA", 0x8ff4, 0 }, + { "PM_TX_INT_ENABLE", 0x8ff8, 0 }, + { "pcmd_len_ovfl0", 31, 1 }, + { "pcmd_len_ovfl1", 30, 1 }, + { "pcmd_len_ovfl2", 29, 1 }, + { "zero_c_cmd_error", 28, 1 }, + { "icspi0_fifo2x_Rx_framing_error", 27, 1 }, + { "icspi1_fifo2x_Rx_framing_error", 26, 1 }, + { "icspi2_fifo2x_Rx_framing_error", 25, 1 }, + { "icspi3_fifo2x_Rx_framing_error", 24, 1 }, + { "icspi0_Rx_framing_error", 23, 1 }, + { "icspi1_Rx_framing_error", 22, 1 }, + { "icspi2_Rx_framing_error", 21, 1 }, + { "icspi3_Rx_framing_error", 20, 1 }, + { "icspi0_Tx_framing_error", 19, 1 }, + { "icspi1_Tx_framing_error", 18, 1 }, + { "icspi2_Tx_framing_error", 17, 1 }, + { "icspi3_Tx_framing_error", 16, 1 }, + { "oespi0_Rx_framing_error", 15, 1 }, + { "oespi1_Rx_framing_error", 14, 1 }, + { "oespi2_Rx_framing_error", 13, 1 }, + { "oespi3_Rx_framing_error", 12, 1 }, + { "oespi0_Tx_framing_error", 11, 1 }, + { "oespi1_Tx_framing_error", 10, 1 }, + { "oespi2_Tx_framing_error", 9, 1 }, + { "oespi3_Tx_framing_error", 8, 1 }, + { "oespi0_ofifo2x_Tx_framing_error", 7, 1 }, + { "oespi1_ofifo2x_Tx_framing_error", 6, 1 }, + { "oespi2_ofifo2x_Tx_framing_error", 5, 1 }, + { "oespi3_ofifo2x_Tx_framing_error", 4, 1 }, + { "oespi_par_error", 3, 1 }, + { "db_options_par_error", 2, 1 }, + { "icspi_par_error", 1, 1 }, + { "c_pcmd_par_error", 0, 1 }, + { "PM_TX_INT_CAUSE", 0x8ffc, 0 }, + { "pcmd_len_ovfl0", 31, 1 }, + { "pcmd_len_ovfl1", 30, 1 }, + { "pcmd_len_ovfl2", 29, 1 }, + { "zero_c_cmd_error", 28, 1 }, + { "icspi0_fifo2x_Rx_framing_error", 27, 1 }, + { "icspi1_fifo2x_Rx_framing_error", 26, 1 }, + { "icspi2_fifo2x_Rx_framing_error", 25, 1 }, + { "icspi3_fifo2x_Rx_framing_error", 24, 1 }, + { "icspi0_Rx_framing_error", 23, 1 }, + { "icspi1_Rx_framing_error", 22, 1 }, + { "icspi2_Rx_framing_error", 21, 1 }, + { "icspi3_Rx_framing_error", 20, 1 }, + { "icspi0_Tx_framing_error", 19, 1 }, + { "icspi1_Tx_framing_error", 18, 1 }, + { "icspi2_Tx_framing_error", 17, 1 }, + { "icspi3_Tx_framing_error", 16, 1 }, + { "oespi0_Rx_framing_error", 15, 1 }, + { "oespi1_Rx_framing_error", 14, 1 }, + { "oespi2_Rx_framing_error", 13, 1 }, + { "oespi3_Rx_framing_error", 12, 1 }, + { "oespi0_Tx_framing_error", 11, 1 }, + { "oespi1_Tx_framing_error", 10, 1 }, + { "oespi2_Tx_framing_error", 9, 1 }, + { "oespi3_Tx_framing_error", 8, 1 }, + { "oespi0_ofifo2x_Tx_framing_error", 7, 1 }, + { "oespi1_ofifo2x_Tx_framing_error", 6, 1 }, + { "oespi2_ofifo2x_Tx_framing_error", 5, 1 }, + { "oespi3_ofifo2x_Tx_framing_error", 4, 1 }, + { "ospi_or_bundle_len_par_err", 3, 1 }, + { "db_options_par_error", 2, 1 }, + { "icspi_par_error", 1, 1 }, + { "c_pcmd_par_error", 0, 1 }, + { NULL } +}; + +struct reg_info t5_mps_regs[] = { + { "MPS_CMN_CTL", 0x9000, 0 }, + { "LpbkCrdtCtrl", 4, 1 }, + { "Detect8023", 3, 1 }, + { "VFDirectAccess", 2, 1 }, + { "NumPorts", 0, 2 }, + { "MPS_INT_ENABLE", 0x9004, 0 }, + { "StatIntEnb", 5, 1 }, + { "TxIntEnb", 4, 1 }, + { "RxIntEnb", 3, 1 }, + { "TrcIntEnb", 2, 1 }, + { "ClsIntEnb", 1, 1 }, + { "PLIntEnb", 0, 1 }, + { "MPS_INT_CAUSE", 0x9008, 0 }, + { "StatInt", 5, 1 }, + { "TxInt", 4, 1 }, + { "RxInt", 3, 1 }, + { "TrcInt", 2, 1 }, + { "ClsInt", 1, 1 }, + { "PLInt", 0, 1 }, + { "MPS_CGEN_GLOBAL", 0x900c, 0 }, + { "MPS_VF_TX_CTL_31_0", 0x9010, 0 }, + { "MPS_VF_TX_CTL_63_32", 0x9014, 0 }, + { "MPS_VF_TX_CTL_95_64", 0x9018, 0 }, + { "MPS_VF_TX_CTL_127_96", 0x901c, 0 }, + { "MPS_VF_RX_CTL_31_0", 0x9020, 0 }, + { "MPS_VF_RX_CTL_63_32", 0x9024, 0 }, + { "MPS_VF_RX_CTL_95_64", 0x9028, 0 }, + { "MPS_VF_RX_CTL_127_96", 0x902c, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 }, + { "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 }, + { "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 }, + { "MPS_WOL_CTL_MODE", 0x9058, 0 }, + { "MPS_FPGA_DEBUG", 0x9060, 0 }, + { "FPGA_PTP_PORT", 9, 2 }, + { "LPBK_EN", 8, 1 }, + { "CH_MAP3", 6, 2 }, + { "CH_MAP2", 4, 2 }, + { "CH_MAP1", 2, 2 }, + { "CH_MAP0", 0, 2 }, + { "MPS_DEBUG_CTL", 0x9068, 0 }, + { "DbgModeCtl_H", 11, 1 }, + { "DbgSel_H", 6, 5 }, + { "DbgModeCtl_L", 5, 1 }, + { "DbgSel_L", 0, 5 }, + { "MPS_DEBUG_DATA_REG_L", 0x906c, 0 }, + { "MPS_DEBUG_DATA_REG_H", 0x9070, 0 }, + { "MPS_TOP_SPARE", 0x9074, 0 }, + { "TopSpare", 8, 24 }, + { "oVlanSelLpbk3", 7, 1 }, + { "oVlanSelLpbk2", 6, 1 }, + { "oVlanSelLpbk1", 5, 1 }, + { "oVlanSelLpbk0", 4, 1 }, + { "oVlanSelMac3", 3, 1 }, + { "oVlanSelMac2", 2, 1 }, + { "oVlanSelMac1", 1, 1 }, + { "oVlanSelMac0", 0, 1 }, + { "MPS_BUILD_REVISION", 0x9078, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 }, + { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 }, + { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 }, + { "MPS_PORT_CTL", 0x30000, 0 }, + { "LpbkEn", 31, 1 }, + { "TxEn", 30, 1 }, + { "RxEn", 29, 1 }, + { "PPPEn", 28, 1 }, + { "FCSStripEn", 27, 1 }, + { "PPPAndPause", 26, 1 }, + { "PrioPPPEnMap", 16, 8 }, + { "MPS_PORT_PAUSE_CTL", 0x30004, 0 }, + { "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 }, + { "RegSendOff", 24, 8 }, + { "RegSendOn", 16, 8 }, + { "SgeSendEn", 8, 8 }, + { "RxSendEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 }, + { "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 }, + { "RegHaltOn", 8, 8 }, + { "RxHaltEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 }, + { "RegSending", 16, 8 }, + { "SgeSending", 8, 8 }, + { "RxSending", 0, 8 }, + { "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 }, + { "RegHalted", 8, 8 }, + { "RxHalted", 0, 8 }, + { "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 }, + { "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 }, + { "Prty7", 14, 2 }, + { "Prty6", 12, 2 }, + { "Prty5", 10, 2 }, + { "Prty4", 8, 2 }, + { "Prty3", 6, 2 }, + { "Prty2", 4, 2 }, + { "Prty1", 2, 2 }, + { "Prty0", 0, 2 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 }, + { "Prty7", 28, 4 }, + { "Prty6", 24, 4 }, + { "Prty5", 20, 4 }, + { "Prty4", 16, 4 }, + { "Prty3", 12, 4 }, + { "Prty2", 8, 4 }, + { "Prty1", 4, 4 }, + { "Prty0", 0, 4 }, + { "MPS_PORT_CTL", 0x34000, 0 }, + { "LpbkEn", 31, 1 }, + { "TxEn", 30, 1 }, + { "RxEn", 29, 1 }, + { "PPPEn", 28, 1 }, + { "FCSStripEn", 27, 1 }, + { "PPPAndPause", 26, 1 }, + { "PrioPPPEnMap", 16, 8 }, + { "MPS_PORT_PAUSE_CTL", 0x34004, 0 }, + { "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 }, + { "RegSendOff", 24, 8 }, + { "RegSendOn", 16, 8 }, + { "SgeSendEn", 8, 8 }, + { "RxSendEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 }, + { "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 }, + { "RegHaltOn", 8, 8 }, + { "RxHaltEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 }, + { "RegSending", 16, 8 }, + { "SgeSending", 8, 8 }, + { "RxSending", 0, 8 }, + { "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 }, + { "RegHalted", 8, 8 }, + { "RxHalted", 0, 8 }, + { "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 }, + { "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 }, + { "Prty7", 14, 2 }, + { "Prty6", 12, 2 }, + { "Prty5", 10, 2 }, + { "Prty4", 8, 2 }, + { "Prty3", 6, 2 }, + { "Prty2", 4, 2 }, + { "Prty1", 2, 2 }, + { "Prty0", 0, 2 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 }, + { "Prty7", 28, 4 }, + { "Prty6", 24, 4 }, + { "Prty5", 20, 4 }, + { "Prty4", 16, 4 }, + { "Prty3", 12, 4 }, + { "Prty2", 8, 4 }, + { "Prty1", 4, 4 }, + { "Prty0", 0, 4 }, + { "MPS_PORT_CTL", 0x38000, 0 }, + { "LpbkEn", 31, 1 }, + { "TxEn", 30, 1 }, + { "RxEn", 29, 1 }, + { "PPPEn", 28, 1 }, + { "FCSStripEn", 27, 1 }, + { "PPPAndPause", 26, 1 }, + { "PrioPPPEnMap", 16, 8 }, + { "MPS_PORT_PAUSE_CTL", 0x38004, 0 }, + { "MPS_PORT_TX_PAUSE_CTL", 0x38008, 0 }, + { "RegSendOff", 24, 8 }, + { "RegSendOn", 16, 8 }, + { "SgeSendEn", 8, 8 }, + { "RxSendEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_CTL2", 0x3800c, 0 }, + { "MPS_PORT_RX_PAUSE_CTL", 0x38010, 0 }, + { "RegHaltOn", 8, 8 }, + { "RxHaltEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_STATUS", 0x38014, 0 }, + { "RegSending", 16, 8 }, + { "SgeSending", 8, 8 }, + { "RxSending", 0, 8 }, + { "MPS_PORT_RX_PAUSE_STATUS", 0x38018, 0 }, + { "RegHalted", 8, 8 }, + { "RxHalted", 0, 8 }, + { "MPS_PORT_TX_PAUSE_DEST_L", 0x3801c, 0 }, + { "MPS_PORT_TX_PAUSE_DEST_H", 0x38020, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x38024, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x38028, 0 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3802c, 0 }, + { "Prty7", 14, 2 }, + { "Prty6", 12, 2 }, + { "Prty5", 10, 2 }, + { "Prty4", 8, 2 }, + { "Prty3", 6, 2 }, + { "Prty2", 4, 2 }, + { "Prty1", 2, 2 }, + { "Prty0", 0, 2 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x38030, 0 }, + { "Prty7", 28, 4 }, + { "Prty6", 24, 4 }, + { "Prty5", 20, 4 }, + { "Prty4", 16, 4 }, + { "Prty3", 12, 4 }, + { "Prty2", 8, 4 }, + { "Prty1", 4, 4 }, + { "Prty0", 0, 4 }, + { "MPS_PORT_CTL", 0x3c000, 0 }, + { "LpbkEn", 31, 1 }, + { "TxEn", 30, 1 }, + { "RxEn", 29, 1 }, + { "PPPEn", 28, 1 }, + { "FCSStripEn", 27, 1 }, + { "PPPAndPause", 26, 1 }, + { "PrioPPPEnMap", 16, 8 }, + { "MPS_PORT_PAUSE_CTL", 0x3c004, 0 }, + { "MPS_PORT_TX_PAUSE_CTL", 0x3c008, 0 }, + { "RegSendOff", 24, 8 }, + { "RegSendOn", 16, 8 }, + { "SgeSendEn", 8, 8 }, + { "RxSendEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_CTL2", 0x3c00c, 0 }, + { "MPS_PORT_RX_PAUSE_CTL", 0x3c010, 0 }, + { "RegHaltOn", 8, 8 }, + { "RxHaltEn", 0, 8 }, + { "MPS_PORT_TX_PAUSE_STATUS", 0x3c014, 0 }, + { "RegSending", 16, 8 }, + { "SgeSending", 8, 8 }, + { "RxSending", 0, 8 }, + { "MPS_PORT_RX_PAUSE_STATUS", 0x3c018, 0 }, + { "RegHalted", 8, 8 }, + { "RxHalted", 0, 8 }, + { "MPS_PORT_TX_PAUSE_DEST_L", 0x3c01c, 0 }, + { "MPS_PORT_TX_PAUSE_DEST_H", 0x3c020, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x3c024, 0 }, + { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x3c028, 0 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3c02c, 0 }, + { "Prty7", 14, 2 }, + { "Prty6", 12, 2 }, + { "Prty5", 10, 2 }, + { "Prty4", 8, 2 }, + { "Prty3", 6, 2 }, + { "Prty2", 4, 2 }, + { "Prty1", 2, 2 }, + { "Prty0", 0, 2 }, + { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x3c030, 0 }, + { "Prty7", 28, 4 }, + { "Prty6", 24, 4 }, + { "Prty5", 20, 4 }, + { "Prty4", 16, 4 }, + { "Prty3", 12, 4 }, + { "Prty2", 8, 4 }, + { "Prty1", 4, 4 }, + { "Prty0", 0, 4 }, + { "MPS_PF_CTL", 0x1e2c0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1e6c0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1eac0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1eec0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1f2c0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1f6c0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1fac0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_PF_CTL", 0x1fec0, 0 }, + { "TxEn", 1, 1 }, + { "RxEn", 0, 1 }, + { "MPS_RX_CTL", 0x11000, 0 }, + { "FILT_VLAN_SEL", 17, 1 }, + { "CBA_EN", 16, 1 }, + { "BLK_SNDR", 12, 4 }, + { "CMPRS", 8, 4 }, + { "SNF", 0, 8 }, + { "MPS_RX_PORT_MUX_CTL", 0x11004, 0 }, + { "CTL_P3", 12, 4 }, + { "CTL_P2", 8, 4 }, + { "CTL_P1", 4, 4 }, + { "CTL_P0", 0, 4 }, + { "MPS_RX_PG_FL", 0x11008, 0 }, + { "RST", 16, 1 }, + { "CNT", 0, 16 }, + { "MPS_RX_PKT_FL", 0x1100c, 0 }, + { "RST", 16, 1 }, + { "CNT", 0, 16 }, + { "MPS_RX_PG_RSV0", 0x11010, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV1", 0x11014, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV2", 0x11018, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV3", 0x1101c, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV4", 0x11020, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV5", 0x11024, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV6", 0x11028, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_RSV7", 0x1102c, 0 }, + { "CLR_INTR", 31, 1 }, + { "SET_INTR", 30, 1 }, + { "USED", 16, 12 }, + { "ALLOC", 0, 12 }, + { "MPS_RX_PG_SHR_BG0", 0x11030, 0 }, + { "EN", 31, 1 }, + { "SEL", 30, 1 }, + { "MAX", 16, 12 }, + { "BORW", 0, 12 }, + { "MPS_RX_PG_SHR_BG1", 0x11034, 0 }, + { "EN", 31, 1 }, + { "SEL", 30, 1 }, + { "MAX", 16, 12 }, + { "BORW", 0, 12 }, + { "MPS_RX_PG_SHR_BG2", 0x11038, 0 }, + { "EN", 31, 1 }, + { "SEL", 30, 1 }, + { "MAX", 16, 12 }, + { "BORW", 0, 12 }, + { "MPS_RX_PG_SHR_BG3", 0x1103c, 0 }, + { "EN", 31, 1 }, + { "SEL", 30, 1 }, + { "MAX", 16, 12 }, + { "BORW", 0, 12 }, + { "MPS_RX_PG_SHR0", 0x11040, 0 }, + { "QUOTA", 16, 12 }, + { "USED", 0, 12 }, + { "MPS_RX_PG_SHR1", 0x11044, 0 }, + { "QUOTA", 16, 12 }, + { "USED", 0, 12 }, + { "MPS_RX_PG_HYST_BG0", 0x11048, 0 }, + { "EN", 31, 1 }, + { "TH", 0, 12 }, + { "MPS_RX_PG_HYST_BG1", 0x1104c, 0 }, + { "EN", 31, 1 }, + { "TH", 0, 12 }, + { "MPS_RX_PG_HYST_BG2", 0x11050, 0 }, + { "EN", 31, 1 }, + { "TH", 0, 12 }, + { "MPS_RX_PG_HYST_BG3", 0x11054, 0 }, + { "EN", 31, 1 }, + { "TH", 0, 12 }, + { "MPS_RX_OCH_CTL", 0x11058, 0 }, + { "DROP_WT", 27, 5 }, + { "TRUNC_WT", 22, 5 }, + { "DRAIN", 13, 5 }, + { "DROP", 8, 5 }, + { "STOP", 0, 5 }, + { "MPS_RX_LPBK_BP0", 0x1105c, 0 }, + { "MPS_RX_LPBK_BP1", 0x11060, 0 }, + { "MPS_RX_LPBK_BP2", 0x11064, 0 }, + { "MPS_RX_LPBK_BP3", 0x11068, 0 }, + { "MPS_RX_PORT_GAP", 0x1106c, 0 }, + { "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 }, + { "FF", 23, 1 }, + { "PGMO", 22, 1 }, + { "PGME", 21, 1 }, + { "CHMN", 20, 1 }, + { "RPLC", 19, 1 }, + { "ATRB", 18, 1 }, + { "PSMX", 17, 1 }, + { "PGLL", 16, 1 }, + { "PGFL", 15, 1 }, + { "PKTQ", 14, 1 }, + { "PKFL", 13, 1 }, + { "PPM3", 12, 1 }, + { "PPM2", 11, 1 }, + { "PPM1", 10, 1 }, + { "PPM0", 9, 1 }, + { "SPMX", 8, 1 }, + { "CDL3", 7, 1 }, + { "CDL2", 6, 1 }, + { "CDL1", 5, 1 }, + { "CDL0", 4, 1 }, + { "CDM3", 3, 1 }, + { "CDM2", 2, 1 }, + { "CDM1", 1, 1 }, + { "CDM0", 0, 1 }, + { "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 }, + { "FF", 23, 1 }, + { "PGMO", 22, 1 }, + { "PGME", 21, 1 }, + { "CHMN", 20, 1 }, + { "RPLC", 19, 1 }, + { "ATRB", 18, 1 }, + { "PSMX", 17, 1 }, + { "PGLL", 16, 1 }, + { "PGFL", 15, 1 }, + { "PKTQ", 14, 1 }, + { "PKFL", 13, 1 }, + { "PPM3", 12, 1 }, + { "PPM2", 11, 1 }, + { "PPM1", 10, 1 }, + { "PPM0", 9, 1 }, + { "SPMX", 8, 1 }, + { "CDL3", 7, 1 }, + { "CDL2", 6, 1 }, + { "CDL1", 5, 1 }, + { "CDL0", 4, 1 }, + { "CDM3", 3, 1 }, + { "CDM2", 2, 1 }, + { "CDM1", 1, 1 }, + { "CDM0", 0, 1 }, + { "MPS_RX_PERR_ENABLE", 0x1107c, 0 }, + { "FF", 23, 1 }, + { "PGMO", 22, 1 }, + { "PGME", 21, 1 }, + { "CHMN", 20, 1 }, + { "RPLC", 19, 1 }, + { "ATRB", 18, 1 }, + { "PSMX", 17, 1 }, + { "PGLL", 16, 1 }, + { "PGFL", 15, 1 }, + { "PKTQ", 14, 1 }, + { "PKFL", 13, 1 }, + { "PPM3", 12, 1 }, + { "PPM2", 11, 1 }, + { "PPM1", 10, 1 }, + { "PPM0", 9, 1 }, + { "SPMX", 8, 1 }, + { "CDL3", 7, 1 }, + { "CDL2", 6, 1 }, + { "CDL1", 5, 1 }, + { "CDL0", 4, 1 }, + { "CDM3", 3, 1 }, + { "CDM2", 2, 1 }, + { "CDM1", 1, 1 }, + { "CDM0", 0, 1 }, + { "MPS_RX_PERR_INJECT", 0x11080, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 }, + { "MTU_ERR_INT3", 19, 1 }, + { "MTU_ERR_INT2", 18, 1 }, + { "MTU_ERR_INT1", 17, 1 }, + { "MTU_ERR_INT0", 16, 1 }, + { "SE_CNT_ERR_INT", 15, 1 }, + { "FRM_ERR_INT", 14, 1 }, + { "LEN_ERR_INT", 13, 1 }, + { "INT_ERR_INT", 8, 5 }, + { "PG_TH_INT7", 7, 1 }, + { "PG_TH_INT6", 6, 1 }, + { "PG_TH_INT5", 5, 1 }, + { "PG_TH_INT4", 4, 1 }, + { "PG_TH_INT3", 3, 1 }, + { "PG_TH_INT2", 2, 1 }, + { "PG_TH_INT1", 1, 1 }, + { "PG_TH_INT0", 0, 1 }, + { "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 }, + { "MTU_ERR_INT3", 19, 1 }, + { "MTU_ERR_INT2", 18, 1 }, + { "MTU_ERR_INT1", 17, 1 }, + { "MTU_ERR_INT0", 16, 1 }, + { "SE_CNT_ERR_INT", 15, 1 }, + { "FRM_ERR_INT", 14, 1 }, + { "LEN_ERR_INT", 13, 1 }, + { "INT_ERR_INT", 8, 5 }, + { "PG_TH_INT7", 7, 1 }, + { "PG_TH_INT6", 6, 1 }, + { "PG_TH_INT5", 5, 1 }, + { "PG_TH_INT4", 4, 1 }, + { "PG_TH_INT3", 3, 1 }, + { "PG_TH_INT2", 2, 1 }, + { "PG_TH_INT1", 1, 1 }, + { "PG_TH_INT0", 0, 1 }, + { "MPS_RX_PPP_ATRB", 0x1109c, 0 }, + { "ETYPE", 16, 16 }, + { "OPCODE", 0, 16 }, + { "MPS_RX_QFC0_ATRB", 0x110a0, 0 }, + { "ETYPE", 16, 16 }, + { "DA", 0, 16 }, + { "MPS_RX_QFC1_ATRB", 0x110a4, 0 }, + { "MPS_RX_PT_ARB0", 0x110a8, 0 }, + { "LPBK_WT", 16, 14 }, + { "MAC_WT", 0, 14 }, + { "MPS_RX_PT_ARB1", 0x110ac, 0 }, + { "LPBK_WT", 16, 14 }, + { "MAC_WT", 0, 14 }, + { "MPS_RX_PT_ARB2", 0x110b0, 0 }, + { "LPBK_WT", 16, 14 }, + { "MAC_WT", 0, 14 }, + { "MPS_RX_PT_ARB3", 0x110b4, 0 }, + { "LPBK_WT", 16, 14 }, + { "MAC_WT", 0, 14 }, + { "MPS_RX_PT_ARB4", 0x110b8, 0 }, + { "LPBK_WT", 16, 14 }, + { "MAC_WT", 0, 14 }, + { "MPS_PF_OUT_EN", 0x110bc, 0 }, + { "MPS_BMC_MTU", 0x110c0, 0 }, + { "MPS_BMC_PKT_CNT", 0x110c4, 0 }, + { "MPS_BMC_BYTE_CNT", 0x110c8, 0 }, + { "MPS_PFVF_ATRB_CTL", 0x110cc, 0 }, + { "RD_WRN", 31, 1 }, + { "PFVF", 0, 8 }, + { "MPS_PFVF_ATRB", 0x110d0, 0 }, + { "PF", 28, 3 }, + { "OFF", 18, 1 }, + { "NV_DROP", 17, 1 }, + { "MODE", 16, 1 }, + { "MTU", 0, 14 }, + { "MPS_PFVF_ATRB_FLTR0", 0x110d4, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR1", 0x110d8, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR2", 0x110dc, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR3", 0x110e0, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR4", 0x110e4, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR5", 0x110e8, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR6", 0x110ec, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR7", 0x110f0, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR8", 0x110f4, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR9", 0x110f8, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR10", 0x110fc, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR11", 0x11100, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR12", 0x11104, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR13", 0x11108, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR14", 0x1110c, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PFVF_ATRB_FLTR15", 0x11110, 0 }, + { "VLAN_EN", 16, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_RPLC_MAP_CTL", 0x11114, 0 }, + { "RD_WRN", 31, 1 }, + { "ADDR", 0, 10 }, + { "MPS_PF_RPLCT_MAP", 0x11118, 0 }, + { "MPS_VF_RPLCT_MAP0", 0x1111c, 0 }, + { "MPS_VF_RPLCT_MAP1", 0x11120, 0 }, + { "MPS_VF_RPLCT_MAP2", 0x11124, 0 }, + { "MPS_VF_RPLCT_MAP3", 0x11128, 0 }, + { "MPS_MEM_DBG_CTL", 0x1112c, 0 }, + { "PKD", 17, 1 }, + { "PGD", 16, 1 }, + { "ADDR", 0, 16 }, + { "MPS_PKD_MEM_DATA0", 0x11130, 0 }, + { "MPS_PKD_MEM_DATA1", 0x11134, 0 }, + { "MPS_PKD_MEM_DATA2", 0x11138, 0 }, + { "MPS_PGD_MEM_DATA", 0x1113c, 0 }, + { "MPS_RX_SE_CNT_ERR", 0x11140, 0 }, + { "MPS_RX_SE_CNT_CLR", 0x11144, 0 }, + { "MPS_RX_SE_CNT_IN0", 0x11148, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN1", 0x1114c, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN2", 0x11150, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN3", 0x11154, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN4", 0x11158, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN5", 0x1115c, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN6", 0x11160, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_IN7", 0x11164, 0 }, + { "SOP_CNT_PM", 24, 8 }, + { "EOP_CNT_PM", 16, 8 }, + { "SOP_CNT_IN", 8, 8 }, + { "EOP_CNT_IN", 0, 8 }, + { "MPS_RX_SE_CNT_OUT01", 0x11168, 0 }, + { "SOP_CNT_1", 24, 8 }, + { "EOP_CNT_1", 16, 8 }, + { "SOP_CNT_0", 8, 8 }, + { "EOP_CNT_0", 0, 8 }, + { "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 }, + { "SOP_CNT_3", 24, 8 }, + { "EOP_CNT_3", 16, 8 }, + { "SOP_CNT_2", 8, 8 }, + { "EOP_CNT_2", 0, 8 }, + { "MPS_RX_SPI_ERR", 0x11170, 0 }, + { "LEN_ERR", 21, 4 }, + { "ERR", 0, 21 }, + { "MPS_RX_IN_BUS_STATE", 0x11174, 0 }, + { "ST3", 24, 8 }, + { "ST2", 16, 8 }, + { "ST1", 8, 8 }, + { "ST0", 0, 8 }, + { "MPS_RX_OUT_BUS_STATE", 0x11178, 0 }, + { "ST_NCSI", 23, 9 }, + { "ST_TP", 0, 23 }, + { "MPS_RX_DBG_CTL", 0x1117c, 0 }, + { "OUT_DBG_CHNL", 8, 3 }, + { "DBG_PKD_QSEL", 7, 1 }, + { "DBG_CDS_INV", 6, 1 }, + { "IN_DBG_PORT", 3, 3 }, + { "IN_DBG_CHNL", 0, 3 }, + { "MPS_RX_SPARE", 0x11190, 0 }, + { "MPS_RX_PTP_ETYPE", 0x11194, 0 }, + { "PETYPE2", 16, 16 }, + { "PETYPE1", 0, 16 }, + { "MPS_RX_PTP_TCP", 0x11198, 0 }, + { "PTCPORT2", 16, 16 }, + { "PTCPORT1", 0, 16 }, + { "MPS_RX_PTP_UDP", 0x1119c, 0 }, + { "PUDPORT2", 16, 16 }, + { "PUDPORT1", 0, 16 }, + { "MPS_RX_PTP_CTL", 0x111a0, 0 }, + { "MIN_PTP_SPACE", 24, 7 }, + { "PUDP2EN", 20, 4 }, + { "PUDP1EN", 16, 4 }, + { "PTCP2EN", 12, 4 }, + { "PTCP1EN", 8, 4 }, + { "PETYPE2EN", 4, 4 }, + { "PETYPE1EN", 0, 4 }, + { "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 }, + { "TH_HIGH", 16, 16 }, + { "TH_LOW", 0, 16 }, + { "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 }, + { "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 }, + { "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 }, + { "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 }, + { "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 }, + { "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 }, + { "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 }, + { "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 }, + { "MPS_RX_CGEN", 0x11204, 0 }, + { "MPS_RX_CGEN_NCSI", 12, 1 }, + { "MPS_RX_CGEN_OUT", 8, 4 }, + { "MPS_RX_CGEN_LPBK_IN", 4, 4 }, + { "MPS_RX_CGEN_MAC_IN", 0, 4 }, + { "MPS_PORT_RX_CTL", 0x30100, 0 }, + { "PTP_FWD_UP", 21, 1 }, + { "NO_RPLCT_M", 20, 1 }, + { "RPLCT_SEL_L", 18, 2 }, + { "FLTR_VLAN_SEL", 17, 1 }, + { "PRIO_VLAN_SEL", 16, 1 }, + { "CHK_8023_LEN_M", 15, 1 }, + { "CHK_8023_LEN_L", 14, 1 }, + { "NIV_DROP", 13, 1 }, + { "NOV_DROP", 12, 1 }, + { "CLS_PRT", 11, 1 }, + { "RX_QFC_EN", 10, 1 }, + { "QFC_FWD_UP", 9, 1 }, + { "PPP_FWD_UP", 8, 1 }, + { "PAUSE_FWD_UP", 7, 1 }, + { "LPBK_BP", 6, 1 }, + { "PASS_NO_MATCH", 5, 1 }, + { "IVLAN_EN", 4, 1 }, + { "OVLAN_EN3", 3, 1 }, + { "OVLAN_EN2", 2, 1 }, + { "OVLAN_EN1", 1, 1 }, + { "OVLAN_EN0", 0, 1 }, + { "MPS_PORT_RX_MTU", 0x30104, 0 }, + { "MPS_PORT_RX_PF_MAP", 0x30108, 0 }, + { "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 }, + { "MPS_PORT_RX_VF_MAP1", 0x30110, 0 }, + { "MPS_PORT_RX_VF_MAP2", 0x30114, 0 }, + { "MPS_PORT_RX_VF_MAP3", 0x30118, 0 }, + { "MPS_PORT_RX_IVLAN", 0x3011c, 0 }, + { "MPS_PORT_RX_OVLAN0", 0x30120, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN1", 0x30124, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN2", 0x30128, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN3", 0x3012c, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_RSS_HASH", 0x30130, 0 }, + { "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL1", 0x30138, 0 }, + { "FIXED_PFVF_MAC", 13, 1 }, + { "FIXED_PFVF_LPBK", 12, 1 }, + { "FIXED_PFVF_LPBK_OV", 11, 1 }, + { "FIXED_PF", 8, 3 }, + { "FIXED_VF_VLD", 7, 1 }, + { "FIXED_VF", 0, 7 }, + { "MPS_PORT_RX_SPARE", 0x3013c, 0 }, + { "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 }, + { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL", 0x34100, 0 }, + { "PTP_FWD_UP", 21, 1 }, + { "NO_RPLCT_M", 20, 1 }, + { "RPLCT_SEL_L", 18, 2 }, + { "FLTR_VLAN_SEL", 17, 1 }, + { "PRIO_VLAN_SEL", 16, 1 }, + { "CHK_8023_LEN_M", 15, 1 }, + { "CHK_8023_LEN_L", 14, 1 }, + { "NIV_DROP", 13, 1 }, + { "NOV_DROP", 12, 1 }, + { "CLS_PRT", 11, 1 }, + { "RX_QFC_EN", 10, 1 }, + { "QFC_FWD_UP", 9, 1 }, + { "PPP_FWD_UP", 8, 1 }, + { "PAUSE_FWD_UP", 7, 1 }, + { "LPBK_BP", 6, 1 }, + { "PASS_NO_MATCH", 5, 1 }, + { "IVLAN_EN", 4, 1 }, + { "OVLAN_EN3", 3, 1 }, + { "OVLAN_EN2", 2, 1 }, + { "OVLAN_EN1", 1, 1 }, + { "OVLAN_EN0", 0, 1 }, + { "MPS_PORT_RX_MTU", 0x34104, 0 }, + { "MPS_PORT_RX_PF_MAP", 0x34108, 0 }, + { "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 }, + { "MPS_PORT_RX_VF_MAP1", 0x34110, 0 }, + { "MPS_PORT_RX_VF_MAP2", 0x34114, 0 }, + { "MPS_PORT_RX_VF_MAP3", 0x34118, 0 }, + { "MPS_PORT_RX_IVLAN", 0x3411c, 0 }, + { "MPS_PORT_RX_OVLAN0", 0x34120, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN1", 0x34124, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN2", 0x34128, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN3", 0x3412c, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_RSS_HASH", 0x34130, 0 }, + { "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL1", 0x34138, 0 }, + { "FIXED_PFVF_MAC", 13, 1 }, + { "FIXED_PFVF_LPBK", 12, 1 }, + { "FIXED_PFVF_LPBK_OV", 11, 1 }, + { "FIXED_PF", 8, 3 }, + { "FIXED_VF_VLD", 7, 1 }, + { "FIXED_VF", 0, 7 }, + { "MPS_PORT_RX_SPARE", 0x3413c, 0 }, + { "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 }, + { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL", 0x38100, 0 }, + { "PTP_FWD_UP", 21, 1 }, + { "NO_RPLCT_M", 20, 1 }, + { "RPLCT_SEL_L", 18, 2 }, + { "FLTR_VLAN_SEL", 17, 1 }, + { "PRIO_VLAN_SEL", 16, 1 }, + { "CHK_8023_LEN_M", 15, 1 }, + { "CHK_8023_LEN_L", 14, 1 }, + { "NIV_DROP", 13, 1 }, + { "NOV_DROP", 12, 1 }, + { "CLS_PRT", 11, 1 }, + { "RX_QFC_EN", 10, 1 }, + { "QFC_FWD_UP", 9, 1 }, + { "PPP_FWD_UP", 8, 1 }, + { "PAUSE_FWD_UP", 7, 1 }, + { "LPBK_BP", 6, 1 }, + { "PASS_NO_MATCH", 5, 1 }, + { "IVLAN_EN", 4, 1 }, + { "OVLAN_EN3", 3, 1 }, + { "OVLAN_EN2", 2, 1 }, + { "OVLAN_EN1", 1, 1 }, + { "OVLAN_EN0", 0, 1 }, + { "MPS_PORT_RX_MTU", 0x38104, 0 }, + { "MPS_PORT_RX_PF_MAP", 0x38108, 0 }, + { "MPS_PORT_RX_VF_MAP0", 0x3810c, 0 }, + { "MPS_PORT_RX_VF_MAP1", 0x38110, 0 }, + { "MPS_PORT_RX_VF_MAP2", 0x38114, 0 }, + { "MPS_PORT_RX_VF_MAP3", 0x38118, 0 }, + { "MPS_PORT_RX_IVLAN", 0x3811c, 0 }, + { "MPS_PORT_RX_OVLAN0", 0x38120, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN1", 0x38124, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN2", 0x38128, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN3", 0x3812c, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_RSS_HASH", 0x38130, 0 }, + { "MPS_PORT_RX_RSS_CONTROL", 0x38134, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL1", 0x38138, 0 }, + { "FIXED_PFVF_MAC", 13, 1 }, + { "FIXED_PFVF_LPBK", 12, 1 }, + { "FIXED_PFVF_LPBK_OV", 11, 1 }, + { "FIXED_PF", 8, 3 }, + { "FIXED_VF_VLD", 7, 1 }, + { "FIXED_VF", 0, 7 }, + { "MPS_PORT_RX_SPARE", 0x3813c, 0 }, + { "MPS_PORT_RX_PTP_RSS_HASH", 0x38140, 0 }, + { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x38144, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL", 0x3c100, 0 }, + { "PTP_FWD_UP", 21, 1 }, + { "NO_RPLCT_M", 20, 1 }, + { "RPLCT_SEL_L", 18, 2 }, + { "FLTR_VLAN_SEL", 17, 1 }, + { "PRIO_VLAN_SEL", 16, 1 }, + { "CHK_8023_LEN_M", 15, 1 }, + { "CHK_8023_LEN_L", 14, 1 }, + { "NIV_DROP", 13, 1 }, + { "NOV_DROP", 12, 1 }, + { "CLS_PRT", 11, 1 }, + { "RX_QFC_EN", 10, 1 }, + { "QFC_FWD_UP", 9, 1 }, + { "PPP_FWD_UP", 8, 1 }, + { "PAUSE_FWD_UP", 7, 1 }, + { "LPBK_BP", 6, 1 }, + { "PASS_NO_MATCH", 5, 1 }, + { "IVLAN_EN", 4, 1 }, + { "OVLAN_EN3", 3, 1 }, + { "OVLAN_EN2", 2, 1 }, + { "OVLAN_EN1", 1, 1 }, + { "OVLAN_EN0", 0, 1 }, + { "MPS_PORT_RX_MTU", 0x3c104, 0 }, + { "MPS_PORT_RX_PF_MAP", 0x3c108, 0 }, + { "MPS_PORT_RX_VF_MAP0", 0x3c10c, 0 }, + { "MPS_PORT_RX_VF_MAP1", 0x3c110, 0 }, + { "MPS_PORT_RX_VF_MAP2", 0x3c114, 0 }, + { "MPS_PORT_RX_VF_MAP3", 0x3c118, 0 }, + { "MPS_PORT_RX_IVLAN", 0x3c11c, 0 }, + { "MPS_PORT_RX_OVLAN0", 0x3c120, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN1", 0x3c124, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN2", 0x3c128, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_OVLAN3", 0x3c12c, 0 }, + { "OVLAN_MASK", 16, 16 }, + { "OVLAN_ETYPE", 0, 16 }, + { "MPS_PORT_RX_RSS_HASH", 0x3c130, 0 }, + { "MPS_PORT_RX_RSS_CONTROL", 0x3c134, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_PORT_RX_CTL1", 0x3c138, 0 }, + { "FIXED_PFVF_MAC", 13, 1 }, + { "FIXED_PFVF_LPBK", 12, 1 }, + { "FIXED_PFVF_LPBK_OV", 11, 1 }, + { "FIXED_PF", 8, 3 }, + { "FIXED_VF_VLD", 7, 1 }, + { "FIXED_VF", 0, 7 }, + { "MPS_PORT_RX_SPARE", 0x3c13c, 0 }, + { "MPS_PORT_RX_PTP_RSS_HASH", 0x3c140, 0 }, + { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x3c144, 0 }, + { "RSS_CTRL", 16, 8 }, + { "QUE_NUM", 0, 16 }, + { "MPS_TX_PRTY_SEL", 0x9400, 0 }, + { "Ch4_Prty", 20, 3 }, + { "Ch3_Prty", 16, 3 }, + { "Ch2_Prty", 12, 3 }, + { "Ch1_Prty", 8, 3 }, + { "Ch0_Prty", 4, 3 }, + { "TP_Source", 2, 2 }, + { "NCSI_Source", 0, 2 }, + { "MPS_TX_INT_ENABLE", 0x9404, 0 }, + { "PortErr", 16, 1 }, + { "FRMERR", 15, 1 }, + { "SECNTERR", 14, 1 }, + { "BUBBLE", 13, 1 }, + { "TxDescFifo", 9, 4 }, + { "TxDataFifo", 5, 4 }, + { "Ncsi", 4, 1 }, + { "TP", 0, 4 }, + { "MPS_TX_INT_CAUSE", 0x9408, 0 }, + { "PortErr", 16, 1 }, + { "FRMERR", 15, 1 }, + { "SECNTERR", 14, 1 }, + { "BUBBLE", 13, 1 }, + { "TxDescFifo", 9, 4 }, + { "TxDataFifo", 5, 4 }, + { "Ncsi", 4, 1 }, + { "TP", 0, 4 }, + { "MPS_TX_PERR_ENABLE", 0x9410, 0 }, + { "TxDescFifo", 9, 4 }, + { "TxDataFifo", 5, 4 }, + { "Ncsi", 4, 1 }, + { "TP", 0, 4 }, + { "MPS_TX_PERR_INJECT", 0x9414, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MPS_TX_SE_CNT_TP01", 0x9418, 0 }, + { "SOP_CNT_1", 24, 8 }, + { "EOP_CNT_1", 16, 8 }, + { "SOP_CNT_0", 8, 8 }, + { "EOP_CNT_0", 0, 8 }, + { "MPS_TX_SE_CNT_TP23", 0x941c, 0 }, + { "SOP_CNT_3", 24, 8 }, + { "EOP_CNT_3", 16, 8 }, + { "SOP_CNT_2", 8, 8 }, + { "EOP_CNT_2", 0, 8 }, + { "MPS_TX_SE_CNT_MAC01", 0x9420, 0 }, + { "SOP_CNT_1", 24, 8 }, + { "EOP_CNT_1", 16, 8 }, + { "SOP_CNT_0", 8, 8 }, + { "EOP_CNT_0", 0, 8 }, + { "MPS_TX_SE_CNT_MAC23", 0x9424, 0 }, + { "SOP_CNT_3", 24, 8 }, + { "EOP_CNT_3", 16, 8 }, + { "SOP_CNT_2", 8, 8 }, + { "EOP_CNT_2", 0, 8 }, + { "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 }, + { "Bubble", 16, 8 }, + { "Spi", 8, 8 }, + { "SeCnt", 0, 8 }, + { "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 }, + { "NcsiSeCnt", 20, 1 }, + { "LpbkSeCnt", 16, 4 }, + { "Bubble", 8, 8 }, + { "SeCnt", 0, 8 }, + { "MPS_TX_PORT_ERR", 0x9430, 0 }, + { "Lpbkpt3", 7, 1 }, + { "Lpbkpt2", 6, 1 }, + { "Lpbkpt1", 5, 1 }, + { "Lpbkpt0", 4, 1 }, + { "pt3", 3, 1 }, + { "pt2", 2, 1 }, + { "pt1", 1, 1 }, + { "pt0", 0, 1 }, + { "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 }, + { "BpEn", 1, 1 }, + { "DropEn", 0, 1 }, + { "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 }, + { "BpEn", 1, 1 }, + { "DropEn", 0, 1 }, + { "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 }, + { "BpEn", 1, 1 }, + { "DropEn", 0, 1 }, + { "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 }, + { "BpEn", 1, 1 }, + { "DropEn", 0, 1 }, + { "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 }, + { "SOPCh1", 31, 1 }, + { "EOPCh1", 30, 1 }, + { "SizeCh1", 27, 3 }, + { "ErrCh1", 26, 1 }, + { "FullCh1", 25, 1 }, + { "ValidCh1", 24, 1 }, + { "DataCh1", 16, 8 }, + { "SOPCh0", 15, 1 }, + { "EOPCh0", 14, 1 }, + { "SizeCh0", 11, 3 }, + { "ErrCh0", 10, 1 }, + { "FullCh0", 9, 1 }, + { "ValidCh0", 8, 1 }, + { "DataCh0", 0, 8 }, + { "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 }, + { "SOPCh3", 31, 1 }, + { "EOPCh3", 30, 1 }, + { "SizeCh3", 27, 3 }, + { "ErrCh3", 26, 1 }, + { "FullCh3", 25, 1 }, + { "ValidCh3", 24, 1 }, + { "DataCh3", 16, 8 }, + { "SOPCh2", 15, 1 }, + { "EOPCh2", 14, 1 }, + { "SizeCh2", 11, 3 }, + { "ErrCh2", 10, 1 }, + { "FullCh2", 9, 1 }, + { "ValidCh2", 8, 1 }, + { "DataCh2", 0, 8 }, + { "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 }, + { "SOPPt1", 31, 1 }, + { "EOPPt1", 30, 1 }, + { "SizePt1", 27, 3 }, + { "ErrPt1", 26, 1 }, + { "FullPt1", 25, 1 }, + { "ValidPt1", 24, 1 }, + { "DataPt1", 16, 8 }, + { "SOPPt0", 15, 1 }, + { "EOPPt0", 14, 1 }, + { "SizePt0", 11, 3 }, + { "ErrPt0", 10, 1 }, + { "FullPt0", 9, 1 }, + { "ValidPt0", 8, 1 }, + { "DataPt0", 0, 8 }, + { "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 }, + { "SOPPt3", 31, 1 }, + { "EOPPt3", 30, 1 }, + { "SizePt3", 27, 3 }, + { "ErrPt3", 26, 1 }, + { "FullPt3", 25, 1 }, + { "ValidPt3", 24, 1 }, + { "DataPt3", 16, 8 }, + { "SOPPt2", 15, 1 }, + { "EOPPt2", 14, 1 }, + { "SizePt2", 11, 3 }, + { "ErrPt2", 10, 1 }, + { "FullPt2", 9, 1 }, + { "ValidPt2", 8, 1 }, + { "DataPt2", 0, 8 }, + { "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 }, + { "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 }, + { "SubPrtH", 11, 5 }, + { "PortH", 8, 3 }, + { "SubPrtL", 3, 5 }, + { "PortL", 0, 3 }, + { "MPS_TX_PAD_CTL", 0x945c, 0 }, + { "LpbkPadEnPt3", 7, 1 }, + { "LpbkPadEnPt2", 6, 1 }, + { "LpbkPadEnPt1", 5, 1 }, + { "LpbkPadEnPt0", 4, 1 }, + { "MacPadEnPt3", 3, 1 }, + { "MacPadEnPt2", 2, 1 }, + { "MacPadEnPt1", 1, 1 }, + { "MacPadEnPt0", 0, 1 }, + { "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 }, + { "TP2MPS_Ch3", 24, 8 }, + { "TP2MPS_Ch2", 16, 8 }, + { "TP2MPS_Ch1", 8, 8 }, + { "TP2MPS_Ch0", 0, 8 }, + { "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 }, + { "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 }, + { "PFNOVFDROP", 5, 1 }, + { "NCSI_Ch4_CLR", 4, 1 }, + { "TP2MPS_Ch3_CLR", 3, 1 }, + { "TP2MPS_Ch2_CLR", 2, 1 }, + { "TP2MPS_Ch1_CLR", 1, 1 }, + { "TP2MPS_Ch0_CLR", 0, 1 }, + { "MPS_TX_CGEN", 0x946c, 0 }, + { "TxOutLpbk3_CGEN", 31, 1 }, + { "TxOutLpbk2_CGEN", 30, 1 }, + { "TxOutLpbk1_CGEN", 29, 1 }, + { "TxOutLpbk0_CGEN", 28, 1 }, + { "TxOutMAC3_CGEN", 27, 1 }, + { "TxOutMAC2_CGEN", 26, 1 }, + { "TxOutMAC1_CGEN", 25, 1 }, + { "TxOutMAC0_CGEN", 24, 1 }, + { "TxSchLpbk3_CGEN", 23, 1 }, + { "TxSchLpbk2_CGEN", 22, 1 }, + { "TxSchLpbk1_CGEN", 21, 1 }, + { "TxSchLpbk0_CGEN", 20, 1 }, + { "TxSchMAC3_CGEN", 19, 1 }, + { "TxSchMAC2_CGEN", 18, 1 }, + { "TxSchMAC1_CGEN", 17, 1 }, + { "TxSchMAC0_CGEN", 16, 1 }, + { "TxInCh4_CGEN", 15, 1 }, + { "TxInCh3_CGEN", 14, 1 }, + { "TxInCh2_CGEN", 13, 1 }, + { "TxInCh1_CGEN", 12, 1 }, + { "TxInCh0_CGEN", 11, 1 }, + { "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 }, + { "TxOutLpbk3_CGEN", 31, 1 }, + { "TxOutLpbk2_CGEN", 30, 1 }, + { "TxOutLpbk1_CGEN", 29, 1 }, + { "TxOutLpbk0_CGEN", 28, 1 }, + { "TxOutMAC3_CGEN", 27, 1 }, + { "TxOutMAC2_CGEN", 26, 1 }, + { "TxOutMAC1_CGEN", 25, 1 }, + { "TxOutMAC0_CGEN", 24, 1 }, + { "TxSchLpbk3_CGEN", 23, 1 }, + { "TxSchLpbk2_CGEN", 22, 1 }, + { "TxSchLpbk1_CGEN", 21, 1 }, + { "TxSchLpbk0_CGEN", 20, 1 }, + { "TxSchMAC3_CGEN", 19, 1 }, + { "TxSchMAC2_CGEN", 18, 1 }, + { "TxSchMAC1_CGEN", 17, 1 }, + { "TxSchMAC0_CGEN", 16, 1 }, + { "TxInCh4_CGEN", 15, 1 }, + { "TxInCh3_CGEN", 14, 1 }, + { "TxInCh2_CGEN", 13, 1 }, + { "TxInCh1_CGEN", 12, 1 }, + { "TxInCh0_CGEN", 11, 1 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 }, + { "ProtocolID", 16, 16 }, + { "Priority", 13, 3 }, + { "CFI", 12, 1 }, + { "Tag", 0, 12 }, + { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 }, + { "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 }, + { "FifoTh", 5, 9 }, + { "FifoEn", 4, 1 }, + { "MaxPktCnt", 0, 4 }, + { "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 }, + { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 }, + { "off_pending", 8, 8 }, + { "on_pending", 0, 8 }, + { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 }, + { "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 }, + { "FifoTh", 5, 9 }, + { "FifoEn", 4, 1 }, + { "MaxPktCnt", 0, 4 }, + { "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 }, + { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 }, + { "off_pending", 8, 8 }, + { "on_pending", 0, 8 }, + { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x38190, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x38194, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x38198, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3819c, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x381a0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x381a8, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x381ac, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x381b0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x381b4, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x381b8, 0 }, + { "MPS_PORT_TX_FIFO_CTL", 0x381c4, 0 }, + { "FifoTh", 5, 9 }, + { "FifoEn", 4, 1 }, + { "MaxPktCnt", 0, 4 }, + { "MPS_PORT_FPGA_PAUSE_CTL", 0x381c8, 0 }, + { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x381d0, 0 }, + { "off_pending", 8, 8 }, + { "on_pending", 0, 8 }, + { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x3c190, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x3c194, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x3c198, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3c19c, 0 }, + { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x3c1a0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x3c1a8, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x3c1ac, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x3c1b0, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x3c1b4, 0 }, + { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x3c1b8, 0 }, + { "MPS_PORT_TX_FIFO_CTL", 0x3c1c4, 0 }, + { "FifoTh", 5, 9 }, + { "FifoEn", 4, 1 }, + { "MaxPktCnt", 0, 4 }, + { "MPS_PORT_FPGA_PAUSE_CTL", 0x3c1c8, 0 }, + { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x3c1d0, 0 }, + { "off_pending", 8, 8 }, + { "on_pending", 0, 8 }, + { "MPS_TRC_CFG", 0x9800, 0 }, + { "TrcMultiRSSFilter", 5, 1 }, + { "TrcFifoEmpty", 4, 1 }, + { "TrcIgnoreDropInput", 3, 1 }, + { "TrcKeepDuplicates", 2, 1 }, + { "TrcEn", 1, 1 }, + { "TrcMultiFilter", 0, 1 }, + { "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 }, + { "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 }, + { "RssControl", 16, 8 }, + { "QueueNumber", 0, 16 }, + { "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 }, + { "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 }, + { "RssControl", 16, 8 }, + { "QueueNumber", 0, 16 }, + { "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 }, + { "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 }, + { "RssControl", 16, 8 }, + { "QueueNumber", 0, 16 }, + { "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 }, + { "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 }, + { "RssControl", 16, 8 }, + { "QueueNumber", 0, 16 }, + { "MPS_TRC_RSS_HASH", 0xa008, 0 }, + { "MPS_TRC_RSS_CONTROL", 0xa00c, 0 }, + { "RssControl", 16, 8 }, + { "QueueNumber", 0, 16 }, + { "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 }, + { "TrcMPS2TP_MacOnly", 20, 1 }, + { "TrcAllMPS2TP", 19, 1 }, + { "TrcAllTP2MPS", 18, 1 }, + { "TrcAllVf", 17, 1 }, + { "OffEn", 16, 1 }, + { "VfFiltEn", 15, 1 }, + { "VfFiltMask", 8, 7 }, + { "VfFiltValid", 7, 1 }, + { "VfFiltData", 0, 7 }, + { "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 }, + { "TrcMPS2TP_MacOnly", 20, 1 }, + { "TrcAllMPS2TP", 19, 1 }, + { "TrcAllTP2MPS", 18, 1 }, + { "TrcAllVf", 17, 1 }, + { "OffEn", 16, 1 }, + { "VfFiltEn", 15, 1 }, + { "VfFiltMask", 8, 7 }, + { "VfFiltValid", 7, 1 }, + { "VfFiltData", 0, 7 }, + { "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 }, + { "TrcMPS2TP_MacOnly", 20, 1 }, + { "TrcAllMPS2TP", 19, 1 }, + { "TrcAllTP2MPS", 18, 1 }, + { "TrcAllVf", 17, 1 }, + { "OffEn", 16, 1 }, + { "VfFiltEn", 15, 1 }, + { "VfFiltMask", 8, 7 }, + { "VfFiltValid", 7, 1 }, + { "VfFiltData", 0, 7 }, + { "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 }, + { "TrcMPS2TP_MacOnly", 20, 1 }, + { "TrcAllMPS2TP", 19, 1 }, + { "TrcAllTP2MPS", 18, 1 }, + { "TrcAllVf", 17, 1 }, + { "OffEn", 16, 1 }, + { "VfFiltEn", 15, 1 }, + { "VfFiltMask", 8, 7 }, + { "VfFiltValid", 7, 1 }, + { "VfFiltData", 0, 7 }, + { "MPS_TRC_CGEN", 0xa020, 0 }, + { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 }, + { "TfInsertActLen", 27, 1 }, + { "TfInsertTimer", 26, 1 }, + { "TfInvertMatch", 25, 1 }, + { "TfPktTooLarge", 24, 1 }, + { "TfEn", 23, 1 }, + { "TfPort", 18, 5 }, + { "TfDrop", 17, 1 }, + { "TfSopEopErr", 16, 1 }, + { "TfLength", 8, 5 }, + { "TfOffset", 0, 5 }, + { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 }, + { "TfInsertActLen", 27, 1 }, + { "TfInsertTimer", 26, 1 }, + { "TfInvertMatch", 25, 1 }, + { "TfPktTooLarge", 24, 1 }, + { "TfEn", 23, 1 }, + { "TfPort", 18, 5 }, + { "TfDrop", 17, 1 }, + { "TfSopEopErr", 16, 1 }, + { "TfLength", 8, 5 }, + { "TfOffset", 0, 5 }, + { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 }, + { "TfInsertActLen", 27, 1 }, + { "TfInsertTimer", 26, 1 }, + { "TfInvertMatch", 25, 1 }, + { "TfPktTooLarge", 24, 1 }, + { "TfEn", 23, 1 }, + { "TfPort", 18, 5 }, + { "TfDrop", 17, 1 }, + { "TfSopEopErr", 16, 1 }, + { "TfLength", 8, 5 }, + { "TfOffset", 0, 5 }, + { "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 }, + { "TfInsertActLen", 27, 1 }, + { "TfInsertTimer", 26, 1 }, + { "TfInvertMatch", 25, 1 }, + { "TfPktTooLarge", 24, 1 }, + { "TfEn", 23, 1 }, + { "TfPort", 18, 5 }, + { "TfDrop", 17, 1 }, + { "TfSopEopErr", 16, 1 }, + { "TfLength", 8, 5 }, + { "TfOffset", 0, 5 }, + { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 }, + { "TfMinPktSize", 16, 9 }, + { "TfCaptureMax", 0, 14 }, + { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 }, + { "TfMinPktSize", 16, 9 }, + { "TfCaptureMax", 0, 14 }, + { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 }, + { "TfMinPktSize", 16, 9 }, + { "TfCaptureMax", 0, 14 }, + { "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 }, + { "TfMinPktSize", 16, 9 }, + { "TfCaptureMax", 0, 14 }, + { "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 }, + { "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 }, + { "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 }, + { "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 }, + { "MPS_TRC_FILTER_DROP", 0x9840, 0 }, + { "TfDropInpCount", 16, 16 }, + { "TfDropBufferCount", 0, 16 }, + { "MPS_TRC_FILTER_DROP", 0x9844, 0 }, + { "TfDropInpCount", 16, 16 }, + { "TfDropBufferCount", 0, 16 }, + { "MPS_TRC_FILTER_DROP", 0x9848, 0 }, + { "TfDropInpCount", 16, 16 }, + { "TfDropBufferCount", 0, 16 }, + { "MPS_TRC_FILTER_DROP", 0x984c, 0 }, + { "TfDropInpCount", 16, 16 }, + { "TfDropBufferCount", 0, 16 }, + { "MPS_TRC_PERR_INJECT", 0x9850, 0 }, + { "MemSel", 1, 4 }, + { "InjectDataErr", 0, 1 }, + { "MPS_TRC_PERR_ENABLE", 0x9854, 0 }, + { "MiscPerr", 8, 1 }, + { "PktFifo", 4, 4 }, + { "FiltMem", 0, 4 }, + { "MPS_TRC_INT_ENABLE", 0x9858, 0 }, + { "PLErrEnb", 9, 1 }, + { "MiscPerr", 8, 1 }, + { "PktFifo", 4, 4 }, + { "FiltMem", 0, 4 }, + { "MPS_TRC_INT_CAUSE", 0x985c, 0 }, + { "PLErrEnb", 9, 1 }, + { "MiscPerr", 8, 1 }, + { "PktFifo", 4, 4 }, + { "FiltMem", 0, 4 }, + { "MPS_TRC_TIMESTAMP_L", 0x9860, 0 }, + { "MPS_TRC_TIMESTAMP_H", 0x9864, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 }, + { "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 }, + { "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 }, + { "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 }, + { "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 }, + { "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 }, + { "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 }, + { "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 }, + { "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 }, + { "MPS_STAT_CTL", 0x9600, 0 }, + { "StatStopCtrl", 10, 1 }, + { "StopStat", 9, 1 }, + { "StatWriteCtrl", 8, 1 }, + { "CountLbPF", 7, 1 }, + { "CountLbVF", 6, 1 }, + { "CountPauseMCRx", 5, 1 }, + { "CountPauseStatRx", 4, 1 }, + { "CountPauseMCTx", 3, 1 }, + { "CountPauseStatTx", 2, 1 }, + { "CountVFinPF", 1, 1 }, + { "LpbkErrStat", 0, 1 }, + { "MPS_STAT_INT_ENABLE", 0x9608, 0 }, + { "MPS_STAT_INT_CAUSE", 0x960c, 0 }, + { "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 }, + { "Rxbg", 27, 2 }, + { "Rxpf", 22, 5 }, + { "Txpf", 18, 4 }, + { "Rxport", 11, 7 }, + { "Lbport", 6, 5 }, + { "Txport", 0, 6 }, + { "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 }, + { "Rxbg", 27, 2 }, + { "Rxpf", 22, 5 }, + { "Txpf", 18, 4 }, + { "Rxport", 11, 7 }, + { "Lbport", 6, 5 }, + { "Txport", 0, 6 }, + { "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 }, + { "Rxbg", 27, 2 }, + { "Rxpf", 22, 5 }, + { "Txpf", 18, 4 }, + { "Rxport", 11, 7 }, + { "Lbport", 6, 5 }, + { "Txport", 0, 6 }, + { "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 }, + { "TxCh", 20, 4 }, + { "Tx", 12, 8 }, + { "Pause", 8, 4 }, + { "Drop", 0, 8 }, + { "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 }, + { "TxCh", 20, 4 }, + { "Tx", 12, 8 }, + { "Pause", 8, 4 }, + { "Drop", 0, 8 }, + { "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 }, + { "TxCh", 20, 4 }, + { "Tx", 12, 8 }, + { "Pause", 8, 4 }, + { "Drop", 0, 8 }, + { "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 }, + { "Pause", 20, 4 }, + { "Lpbk", 16, 4 }, + { "Nq", 8, 8 }, + { "PV", 4, 4 }, + { "Mac", 0, 4 }, + { "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 }, + { "Pause", 20, 4 }, + { "Lpbk", 16, 4 }, + { "Nq", 8, 8 }, + { "PV", 4, 4 }, + { "Mac", 0, 4 }, + { "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 }, + { "Pause", 20, 4 }, + { "Lpbk", 16, 4 }, + { "Nq", 8, 8 }, + { "PV", 4, 4 }, + { "Mac", 0, 4 }, + { "MPS_STAT_PERR_INJECT", 0x9634, 0 }, + { "MemSel", 1, 7 }, + { "InjectDataErr", 0, 1 }, + { "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 }, + { "SubPrtH", 5, 5 }, + { "SubPrtL", 0, 5 }, + { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 }, + { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 }, + { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 }, + { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 }, + { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 }, + { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 }, + { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 }, + { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 }, + { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 }, + { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 }, + { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 }, + { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 }, + { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 }, + { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 }, + { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 }, + { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 }, + { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 }, + { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 }, + { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 }, + { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 }, + { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 }, + { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 }, + { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 }, + { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 }, + { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 }, + { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 }, + { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 }, + { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 }, + { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 }, + { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 }, + { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 }, + { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 }, + { "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 }, + { "Rxvf", 5, 3 }, + { "Txvf", 0, 5 }, + { "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 }, + { "Rxvf", 5, 3 }, + { "Txvf", 0, 5 }, + { "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 }, + { "Rxvf", 5, 3 }, + { "Txvf", 0, 5 }, + { "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 }, + { "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 }, + { "PtLpbk", 8, 4 }, + { "PtTx", 4, 4 }, + { "PtRx", 0, 4 }, + { "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 }, + { "PFTx", 8, 8 }, + { "PFRx", 0, 8 }, + { "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 }, + { "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 }, + { "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 }, + { "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 }, + { "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 }, + { "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 }, + { "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 }, + { "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x38400, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x38404, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x38408, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3840c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x38410, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x38414, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x38418, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3841c, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x38420, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x38424, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x38428, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3842c, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_L", 0x38430, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_H", 0x38434, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x38438, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3843c, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x38440, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x38444, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x38448, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3844c, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x38450, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x38454, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x38458, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3845c, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x38460, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x38464, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x38468, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3846c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x38470, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x38474, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x38478, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3847c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x38480, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x38484, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x38488, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3848c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x38490, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x38494, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x38498, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3849c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x384a0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x384a4, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x384a8, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x384ac, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x384b0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x384b4, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x384c0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x384c4, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x384c8, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x384cc, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x384d0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x384d4, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x384d8, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x384dc, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x384e0, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x384e4, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x384e8, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x384ec, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_L", 0x384f0, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_H", 0x384f4, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x384f8, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x384fc, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x38500, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x38504, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x38508, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3850c, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x38510, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x38514, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x38518, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3851c, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x38520, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x38524, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x38528, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3852c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x38540, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x38544, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x38548, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3854c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x38550, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x38554, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x38558, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3855c, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x38560, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x38564, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x38568, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3856c, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x38570, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x38574, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x38578, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3857c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x38580, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x38584, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x38588, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3858c, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_L", 0x38590, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_H", 0x38594, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x38598, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3859c, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x385a0, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x385a4, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x385a8, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x385ac, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x385b0, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x385b4, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x385b8, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x385bc, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x385c0, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x385c4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x385c8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x385cc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x385d0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x385d4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x385d8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x385dc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x385e0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x385e4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x385e8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x385ec, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x385f0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x385f4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x385f8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x385fc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x38600, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x38604, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x38608, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3860c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x38610, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x38614, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x38618, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3861c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x3c400, 0 }, + { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x3c404, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x3c408, 0 }, + { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3c40c, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x3c410, 0 }, + { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x3c414, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x3c418, 0 }, + { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3c41c, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x3c420, 0 }, + { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x3c424, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x3c428, 0 }, + { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3c42c, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_L", 0x3c430, 0 }, + { "MPS_PORT_STAT_TX_PORT_64B_H", 0x3c434, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x3c438, 0 }, + { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3c43c, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x3c440, 0 }, + { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x3c444, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x3c448, 0 }, + { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3c44c, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x3c450, 0 }, + { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x3c454, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x3c458, 0 }, + { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3c45c, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x3c460, 0 }, + { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x3c464, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x3c468, 0 }, + { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3c46c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x3c470, 0 }, + { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x3c474, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x3c478, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3c47c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x3c480, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x3c484, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x3c488, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3c48c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x3c490, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x3c494, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x3c498, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3c49c, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x3c4a0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x3c4a4, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x3c4a8, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x3c4ac, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x3c4b0, 0 }, + { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x3c4b4, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x3c4c0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x3c4c4, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x3c4c8, 0 }, + { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x3c4cc, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x3c4d0, 0 }, + { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x3c4d4, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x3c4d8, 0 }, + { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x3c4dc, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x3c4e0, 0 }, + { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x3c4e4, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x3c4e8, 0 }, + { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x3c4ec, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_L", 0x3c4f0, 0 }, + { "MPS_PORT_STAT_LB_PORT_64B_H", 0x3c4f4, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x3c4f8, 0 }, + { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x3c4fc, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x3c500, 0 }, + { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x3c504, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x3c508, 0 }, + { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3c50c, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x3c510, 0 }, + { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x3c514, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x3c518, 0 }, + { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3c51c, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x3c520, 0 }, + { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x3c524, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x3c528, 0 }, + { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3c52c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x3c540, 0 }, + { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x3c544, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x3c548, 0 }, + { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3c54c, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x3c550, 0 }, + { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x3c554, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x3c558, 0 }, + { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3c55c, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x3c560, 0 }, + { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x3c564, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x3c568, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3c56c, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x3c570, 0 }, + { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x3c574, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x3c578, 0 }, + { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3c57c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x3c580, 0 }, + { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x3c584, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x3c588, 0 }, + { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3c58c, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_L", 0x3c590, 0 }, + { "MPS_PORT_STAT_RX_PORT_64B_H", 0x3c594, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x3c598, 0 }, + { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3c59c, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x3c5a0, 0 }, + { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x3c5a4, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x3c5a8, 0 }, + { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x3c5ac, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x3c5b0, 0 }, + { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x3c5b4, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x3c5b8, 0 }, + { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x3c5bc, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x3c5c0, 0 }, + { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x3c5c4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x3c5c8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x3c5cc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x3c5d0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x3c5d4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x3c5d8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x3c5dc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x3c5e0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x3c5e4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x3c5e8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x3c5ec, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x3c5f0, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x3c5f4, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x3c5f8, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x3c5fc, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x3c600, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x3c604, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x3c608, 0 }, + { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3c60c, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x3c610, 0 }, + { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x3c614, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x3c618, 0 }, + { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3c61c, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 }, + { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 }, + { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 }, + { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 }, + { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 }, + { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 }, + { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 }, + { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 }, + { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 }, + { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 }, + { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 }, + { "Valid", 20, 1 }, + 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{ "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 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"MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30290, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30294, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x30298, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3029c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302a0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302a4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302a8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302ac, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302b0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302b4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + 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"MPS_PORT_CLS_HASH_SRAM", 0x302c8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302cc, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302d0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302d4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x302d8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 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{ "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c21c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c220, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c224, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c228, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c22c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c230, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c234, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c238, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c23c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c240, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c244, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c248, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c24c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c250, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c254, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c258, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c25c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c260, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c264, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c268, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c26c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c270, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c274, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c278, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c27c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c280, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c284, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c288, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c28c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c290, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c294, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c298, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c29c, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2a0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2a4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2a8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2ac, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2b0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2b4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2b8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2bc, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2c0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2c4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2c8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2cc, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2d0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2d4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2d8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2dc, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2ec, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f0, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f4, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f8, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c2fc, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_SRAM", 0x3c300, 0 }, + { "Valid", 20, 1 }, + { "PortMap", 16, 4 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 }, + { "UnicastEnable", 31, 1 }, + { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 }, + { "Enable", 31, 1 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 }, + { "MatchBoth", 17, 1 }, + { "Valid", 16, 1 }, + { "DA", 0, 16 }, + { "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 }, + { "BMC_VLAN_SEL", 13, 1 }, + { "Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PORT_CLS_CTL", 0x30318, 0 }, + { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 }, + { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 }, + { "LPBK_TCAM_PRIORITY", 12, 1 }, + { "LPBK_SMAC_TCAM_SEL", 10, 2 }, + { "LPBK_DMAC_TCAM_SEL", 8, 2 }, + { "TCAM1_HIT_PRIORITY", 7, 1 }, + { "TCAM0_HIT_PRIORITY", 6, 1 }, + { "TCAM_PRIORITY", 5, 1 }, + { "SMAC_TCAM_SEL", 3, 2 }, + { "DMAC_TCAM_SEL", 1, 2 }, + { "PF_VLAN_SEL", 0, 1 }, + { "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 }, + { "UnicastEnable", 31, 1 }, + { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 }, + { "Enable", 31, 1 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 }, + { "MatchBoth", 17, 1 }, + { "Valid", 16, 1 }, + { "DA", 0, 16 }, + { "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 }, + { "BMC_VLAN_SEL", 13, 1 }, + { "Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PORT_CLS_CTL", 0x34318, 0 }, + { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 }, + { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 }, + { "LPBK_TCAM_PRIORITY", 12, 1 }, + { "LPBK_SMAC_TCAM_SEL", 10, 2 }, + { "LPBK_DMAC_TCAM_SEL", 8, 2 }, + { "TCAM1_HIT_PRIORITY", 7, 1 }, + { "TCAM0_HIT_PRIORITY", 6, 1 }, + { "TCAM_PRIORITY", 5, 1 }, + { "SMAC_TCAM_SEL", 3, 2 }, + { "DMAC_TCAM_SEL", 1, 2 }, + { "PF_VLAN_SEL", 0, 1 }, + { "MPS_PORT_CLS_HASH_CTL", 0x38304, 0 }, + { "UnicastEnable", 31, 1 }, + { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x38308, 0 }, + { "Enable", 31, 1 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3830c, 0 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x38310, 0 }, + { "MatchBoth", 17, 1 }, + { "Valid", 16, 1 }, + { "DA", 0, 16 }, + { "MPS_PORT_CLS_BMC_VLAN", 0x38314, 0 }, + { "BMC_VLAN_SEL", 13, 1 }, + { "Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PORT_CLS_CTL", 0x38318, 0 }, + { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 }, + { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 }, + { "LPBK_TCAM_PRIORITY", 12, 1 }, + { "LPBK_SMAC_TCAM_SEL", 10, 2 }, + { "LPBK_DMAC_TCAM_SEL", 8, 2 }, + { "TCAM1_HIT_PRIORITY", 7, 1 }, + { "TCAM0_HIT_PRIORITY", 6, 1 }, + { "TCAM_PRIORITY", 5, 1 }, + { "SMAC_TCAM_SEL", 3, 2 }, + { "DMAC_TCAM_SEL", 1, 2 }, + { "PF_VLAN_SEL", 0, 1 }, + { "MPS_PORT_CLS_HASH_CTL", 0x3c304, 0 }, + { "UnicastEnable", 31, 1 }, + { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x3c308, 0 }, + { "Enable", 31, 1 }, + { "MultiListen", 15, 1 }, + { "Priority", 12, 3 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3c30c, 0 }, + { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x3c310, 0 }, + { "MatchBoth", 17, 1 }, + { "Valid", 16, 1 }, + { "DA", 0, 16 }, + { "MPS_PORT_CLS_BMC_VLAN", 0x3c314, 0 }, + { "BMC_VLAN_SEL", 13, 1 }, + { "Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_PORT_CLS_CTL", 0x3c318, 0 }, + { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 }, + { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 }, + { "LPBK_TCAM_PRIORITY", 12, 1 }, + { "LPBK_SMAC_TCAM_SEL", 10, 2 }, + { "LPBK_DMAC_TCAM_SEL", 8, 2 }, + { "TCAM1_HIT_PRIORITY", 7, 1 }, + { "TCAM0_HIT_PRIORITY", 6, 1 }, + { "TCAM_PRIORITY", 5, 1 }, + { "SMAC_TCAM_SEL", 3, 2 }, + { "DMAC_TCAM_SEL", 1, 2 }, + { "PF_VLAN_SEL", 0, 1 }, + { "MPS_CLS_CTL", 0xd000, 0 }, + { "MemWriteFault", 4, 1 }, + { "MemWriteWaiting", 3, 1 }, + { "CimNoPromiscuous", 2, 1 }, + { "HypervisorOnly", 1, 1 }, + { "VlanClsEn", 0, 1 }, + { "MPS_CLS_ARB_WEIGHT", 0xd004, 0 }, + { "PlWeight", 16, 5 }, + { "CimWeight", 8, 5 }, + { "LpbkWeight", 0, 5 }, + { "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 }, + { "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 }, + { "MatchBoth", 17, 1 }, + { "Valid", 16, 1 }, + { "DA", 0, 16 }, + { "MPS_CLS_BMC_VLAN", 0xd018, 0 }, + { "Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_PERR_INJECT", 0xd01c, 0 }, + { "MemSel", 1, 2 }, + { "InjectDataErr", 0, 1 }, + { "MPS_CLS_PERR_ENABLE", 0xd020, 0 }, + { "HashSRAM", 2, 1 }, + { "MatchTCAM", 1, 1 }, + { "MatchSRAM", 0, 1 }, + { "MPS_CLS_INT_ENABLE", 0xd024, 0 }, + { "PLErrEnb", 3, 1 }, + { "HashSRAM", 2, 1 }, + { "MatchTCAM", 1, 1 }, + { "MatchSRAM", 0, 1 }, + { "MPS_CLS_INT_CAUSE", 0xd028, 0 }, + { "PLErrEnb", 3, 1 }, + { "HashSRAM", 2, 1 }, + { "MatchTCAM", 1, 1 }, + { "MatchSRAM", 0, 1 }, + { "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 }, + { "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 }, + { "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 }, + { "Cls_Priority", 24, 3 }, + { "Cls_Replicate", 23, 1 }, + { "Cls_Index", 14, 9 }, + { "Cls_VF", 7, 7 }, + { "Cls_VF_Vld", 6, 1 }, + { "Cls_PF", 3, 3 }, + { "Cls_Match", 0, 3 }, + { "MPS_CLS_PL_TEST_CTL", 0xd038, 0 }, + { "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 }, + { "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 }, + { "VLAN_Mask", 16, 12 }, + { "PF", 13, 3 }, + { "VLAN_Valid", 12, 1 }, + { "VLAN_ID", 0, 12 }, + { "MPS_CLS_SRAM_L", 0xe000, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe008, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe010, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe018, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe020, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe028, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe030, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe038, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe040, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe048, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe050, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe058, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe060, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe068, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe070, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe078, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe080, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe088, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe090, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe098, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0a0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0a8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0b0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0b8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0c0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0c8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0d0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0d8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0e0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0e8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0f0, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe0f8, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { "MPS_CLS_SRAM_L", 0xe100, 0 }, + { "MultiListen3", 28, 1 }, + { "MultiListen2", 27, 1 }, + { "MultiListen1", 26, 1 }, + { "MultiListen0", 25, 1 }, + { "Priority3", 22, 3 }, + { "Priority2", 19, 3 }, + { "Priority1", 16, 3 }, + { "Priority0", 13, 3 }, + { "Valid", 12, 1 }, + { "Replicate", 11, 1 }, + { "PF", 8, 3 }, + { "VF_Valid", 7, 1 }, + { "VF", 0, 7 }, + { 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"MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef14, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef1c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef24, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef2c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef34, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef3c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef44, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef4c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef54, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef5c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef64, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef6c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef74, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef7c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef84, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef8c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef94, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xef9c, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefa4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefac, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefb4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefbc, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefc4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefcc, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefd4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefdc, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefe4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xefec, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xeff4, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_SRAM_H", 0xeffc, 0 }, + { "MacParity1", 9, 1 }, + { "MacParity0", 8, 1 }, + { "MacParityMaskSize", 4, 4 }, + { "PortMap", 0, 4 }, + { "MPS_CLS_TCAM_Y_L", 0xf000, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf010, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf020, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf030, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf040, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf050, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf060, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf070, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf080, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf090, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf0f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf100, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf110, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf120, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf130, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf140, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf150, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf160, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf170, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf180, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf190, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf1f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf200, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf210, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf220, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf230, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf240, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf250, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf260, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf270, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf280, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf290, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf2f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf300, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf310, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf320, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf330, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf340, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf350, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf360, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf370, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf380, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf390, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf3f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf400, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf410, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf420, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf430, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf440, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf450, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf460, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf470, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf480, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf490, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf4f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf500, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf510, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf520, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf530, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf540, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf550, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf560, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf570, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf580, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf590, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf5f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf600, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf610, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf620, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf630, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf640, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf650, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf660, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf670, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf680, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf690, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf6f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf700, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf710, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf720, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf730, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf740, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf750, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf760, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf770, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf780, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf790, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf7f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf800, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf810, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf820, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf830, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf840, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf850, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf860, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf870, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf880, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf890, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf8f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf900, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf910, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf920, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf930, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf940, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf950, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf960, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf970, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf980, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf990, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9a0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9b0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9c0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9d0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9e0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xf9f0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa00, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa10, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa20, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa30, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa40, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa50, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa60, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa70, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa80, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfa90, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfaa0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfab0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfac0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfad0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfae0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfaf0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb00, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb10, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb20, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb30, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb40, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb50, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb60, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb70, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb80, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfb90, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfba0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfbb0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfbc0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfbd0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfbe0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfbf0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc00, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc10, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc20, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc30, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc40, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc50, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc60, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc70, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc80, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfc90, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfca0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfcb0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfcc0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfcd0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfce0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfcf0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd00, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd10, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd20, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd30, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd40, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd50, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd60, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd70, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd80, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfd90, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfda0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfdb0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfdc0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfdd0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfde0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfdf0, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe00, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe10, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe20, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe30, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe40, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe50, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe60, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe70, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe80, 0 }, + { "MPS_CLS_TCAM_Y_L", 0xfe90, 0 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{ "MPS_CLS_TCAM_Y_H", 0x10174, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10184, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10194, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101a4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101b4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101c4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101d4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101e4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x101f4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10204, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10214, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10224, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10234, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10244, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10254, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10264, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10274, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10284, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10294, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102a4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102b4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102c4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102d4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102e4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x102f4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10304, 0 }, + { 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"MPS_CLS_TCAM_Y_H", 0x10cd4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ce4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10cf4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d04, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d14, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d24, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d34, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d44, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d54, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d64, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d74, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d84, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10d94, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10da4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10db4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10dc4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10dd4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10de4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10df4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e04, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e14, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e24, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e34, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e44, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e54, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e64, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e74, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e84, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10e94, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ea4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10eb4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ec4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ed4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ee4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ef4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f04, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f14, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f24, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f34, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f44, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f54, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f64, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f74, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f84, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10f94, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10fa4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10fb4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10fc4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10fd4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10fe4, 0 }, + { "MPS_CLS_TCAM_Y_H", 0x10ff4, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf008, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf018, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf028, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf038, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf048, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf058, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf068, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf078, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf088, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf098, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf0f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf108, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf118, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf128, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf138, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf148, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf158, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf168, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf178, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf188, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf198, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf1a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf1b8, 0 }, + { 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"MPS_CLS_TCAM_X_L", 0xf378, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf388, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf398, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf3f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf408, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf418, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf428, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf438, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf448, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf458, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf468, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf478, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf488, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf498, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf4f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf508, 0 }, + { "MPS_CLS_TCAM_X_L", 0xf518, 0 }, + { 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0x100e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x100f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10108, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10118, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10128, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10138, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10148, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10158, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10168, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10178, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10188, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10198, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x101f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10208, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10218, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10228, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10238, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10248, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10258, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10268, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10278, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10288, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10298, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x102f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10308, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10318, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10328, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10338, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10348, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10358, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10368, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10378, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10388, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10398, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103a8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103b8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103c8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103d8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103e8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x103f8, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10408, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10418, 0 }, + { "MPS_CLS_TCAM_X_L", 0x10428, 0 }, + { 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"MPS_CLS_TCAM_X_H", 0x10a3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10a9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10aac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10abc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10acc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10adc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10aec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10afc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b0c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b1c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b2c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10b9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bbc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bcc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bdc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10bfc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c0c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c1c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c2c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10c9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10cac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10cbc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10ccc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10cdc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10cec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10cfc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d0c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d1c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d2c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10d9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10dac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10dbc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10dcc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10ddc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10dec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10dfc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e0c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e1c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e2c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10e9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10eac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10ebc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10ecc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10edc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10eec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10efc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f0c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f1c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f2c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f3c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f4c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f5c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f6c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f7c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f8c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10f9c, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10fac, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10fbc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10fcc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10fdc, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10fec, 0 }, + { "MPS_CLS_TCAM_X_H", 0x10ffc, 0 }, + { NULL } +}; + +struct reg_info t5_cpl_switch_regs[] = { + { "CPL_SWITCH_CNTRL", 0x19040, 0 }, + { "cpl_pkt_tid", 8, 24 }, + { "cim_split_enable", 6, 1 }, + { "cim_truncate_enable", 5, 1 }, + { "cim_to_up_full_size", 4, 1 }, + { "cpu_no_enable", 3, 1 }, + { "switch_table_enable", 2, 1 }, + { "sge_enable", 1, 1 }, + { "cim_enable", 0, 1 }, + { "CPL_SWITCH_TBL_IDX", 0x19044, 0 }, + { "CPL_SWITCH_TBL_DATA", 0x19048, 0 }, + { "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 }, + { "zero_cmd_ch1", 8, 8 }, + { "zero_cmd_ch0", 0, 8 }, + { "CPL_INTR_ENABLE", 0x19050, 0 }, + { "perr_cpl_128to128_1", 7, 1 }, + { "perr_cpl_128to128_0", 6, 1 }, + { "cim_op_map_perr", 5, 1 }, + { "cim_ovfl_error", 4, 1 }, + { "tp_framing_error", 3, 1 }, + { "sge_framing_error", 2, 1 }, + { "cim_framing_error", 1, 1 }, + { "zero_switch_error", 0, 1 }, + { "CPL_INTR_CAUSE", 0x19054, 0 }, + { "perr_cpl_128to128_1", 7, 1 }, + { "perr_cpl_128to128_0", 6, 1 }, + { "cim_op_map_perr", 5, 1 }, + { "cim_ovfl_error", 4, 1 }, + { "tp_framing_error", 3, 1 }, + { "sge_framing_error", 2, 1 }, + { "cim_framing_error", 1, 1 }, + { "zero_switch_error", 0, 1 }, + { "CPL_MAP_TBL_IDX", 0x19058, 0 }, + { "cim_split_opcode_program", 8, 1 }, + { "cpl_map_tbl_idx", 0, 8 }, + { "CPL_MAP_TBL_DATA", 0x1905c, 0 }, + { NULL } +}; + +struct reg_info t5_smb_regs[] = { + { "SMB_GLOBAL_TIME_CFG", 0x19060, 0 }, + { "MacroCntCfg", 8, 5 }, + { "MicroCntCfg", 0, 8 }, + { "SMB_MST_TIMEOUT_CFG", 0x19064, 0 }, + { "SMB_MST_CTL_CFG", 0x19068, 0 }, + { "MstFifoDbg", 31, 1 }, + { "MstFifoDbgClr", 30, 1 }, + { "MstRxByteCfg", 12, 6 }, + { "MstTxByteCfg", 6, 6 }, + { "MstReset", 1, 1 }, + { "MstCtlEn", 0, 1 }, + { "SMB_MST_CTL_STS", 0x1906c, 0 }, + { "MstRxByteCnt", 12, 6 }, + { "MstTxByteCnt", 6, 6 }, + { "MstBusySts", 0, 1 }, + { "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 }, + { "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 }, + { "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 }, + { "SMB_SLV_CTL_CFG", 0x1907c, 0 }, + { "SlvFifoDbg", 31, 1 }, + { "SlvFifoDbgClr", 30, 1 }, + { "SlvCrcOutBitInv", 21, 1 }, + { "SlvCrcOutBitRev", 20, 1 }, + { "SlvCrcInBitRev", 19, 1 }, + { "SlvCrcPreset", 11, 8 }, + { "SlvAddrCfg", 4, 7 }, + { "SlvAlrtSet", 2, 1 }, + { "SlvReset", 1, 1 }, + { "SlvCtlEn", 0, 1 }, + { "SMB_SLV_CTL_STS", 0x19080, 0 }, + { "SlvFifoTxCnt", 12, 6 }, + { "SlvFifoCnt", 6, 6 }, + { "SlvAlrtSts", 2, 1 }, + { "SlvBusySts", 0, 1 }, + { "SMB_SLV_FIFO_RDWR", 0x19084, 0 }, + { "SMB_INT_ENABLE", 0x1908c, 0 }, + { "MstTxFifoParEn", 21, 1 }, + { "MstRxFifoParEn", 20, 1 }, + { "SlvFifoParEn", 19, 1 }, + { "SlvUnExpBusStopEn", 18, 1 }, + { "SlvUnExpBusStartEn", 17, 1 }, + { "SlvCommandCodeInvEn", 16, 1 }, + { "SlvByteCntErrEn", 15, 1 }, + { "SlvUnExpAckMstEn", 14, 1 }, + { "SlvUnExpNackMstEn", 13, 1 }, + { "SlvNoBusStopEn", 12, 1 }, + { "SlvNoRepStartEn", 11, 1 }, + { "SlvRxAddrIntEn", 10, 1 }, + { "SlvRxPecErrIntEn", 9, 1 }, + { "SlvPrepToArpIntEn", 8, 1 }, + { "SlvTimeOutIntEn", 7, 1 }, + { "SlvErrIntEn", 6, 1 }, + { "SlvDoneIntEn", 5, 1 }, + { "SlvRxRdyIntEn", 4, 1 }, + { "MstTimeOutIntEn", 3, 1 }, + { "MstNAckIntEn", 2, 1 }, + { "MstLostArbIntEn", 1, 1 }, + { "MstDoneIntEn", 0, 1 }, + { "SMB_INT_CAUSE", 0x19090, 0 }, + { "MstTxFifoParInt", 21, 1 }, + { "MstRxFifoParInt", 20, 1 }, + { "SlvFifoParInt", 19, 1 }, + { "SlvUnExpBusStopInt", 18, 1 }, + { "SlvUnExpBusStartInt", 17, 1 }, + { "SlvCommandCodeInvInt", 16, 1 }, + { "SlvByteCntErrInt", 15, 1 }, + { "SlvUnExpAckMstInt", 14, 1 }, + { "SlvUnExpNackMstInt", 13, 1 }, + { "SlvNoBusStopInt", 12, 1 }, + { "SlvNoRepStartInt", 11, 1 }, + { "SlvRxAddrInt", 10, 1 }, + { "SlvRxPecErrInt", 9, 1 }, + { "SlvPrepToArpInt", 8, 1 }, + { "SlvTimeOutInt", 7, 1 }, + { "SlvErrInt", 6, 1 }, + { "SlvDoneInt", 5, 1 }, + { "SlvRxRdyInt", 4, 1 }, + { "MstTimeOutInt", 3, 1 }, + { "MstNAckInt", 2, 1 }, + { "MstLostArbInt", 1, 1 }, + { "MstDoneInt", 0, 1 }, + { "SMB_DEBUG_DATA", 0x19094, 0 }, + { "DebugDataH", 16, 16 }, + { "DebugDataL", 0, 16 }, + { "SMB_PERR_EN", 0x19098, 0 }, + { "MstTxFifo", 21, 1 }, + { "MstRxFifo", 19, 1 }, + { "SlvFifo", 18, 1 }, + { "MstTxFifoPerrEn", 2, 1 }, + { "MstRxFifoPerrEn", 1, 1 }, + { "SlvFifoPerrEn", 0, 1 }, + { "SMB_PERR_INJ", 0x1909c, 0 }, + { "MstTxInjDataErr", 3, 1 }, + { "MstRxInjDataErr", 2, 1 }, + { "SlvInjDataErr", 1, 1 }, + { "FifoInjDataErrEn", 0, 1 }, + { "SMB_SLV_ARP_CTL", 0x190a0, 0 }, + { "ArpCommandCode", 2, 8 }, + { "ArpAddrRes", 1, 1 }, + { "ArpAddrVal", 0, 1 }, + { "SMB_ARP_UDID0", 0x190a4, 0 }, + { "SMB_ARP_UDID1", 0x190a8, 0 }, + { "SubsystemVendorID", 16, 16 }, + { "SubsystemDeviceID", 0, 16 }, + { "SMB_ARP_UDID2", 0x190ac, 0 }, + { "DeviceID", 16, 16 }, + { "Interface", 0, 16 }, + { "SMB_ARP_UDID3", 0x190b0, 0 }, + { "DeviceCap", 24, 8 }, + { "VersionID", 16, 8 }, + { "VendorID", 0, 16 }, + { "SMB_SLV_AUX_ADDR0", 0x190b4, 0 }, + { "AuxAddr0Val", 6, 1 }, + { "AuxAddr0", 0, 6 }, + { "SMB_SLV_AUX_ADDR1", 0x190b8, 0 }, + { "AuxAddr1Val", 6, 1 }, + { "AuxAddr1", 0, 6 }, + { "SMB_SLV_AUX_ADDR2", 0x190bc, 0 }, + { "AuxAddr2Val", 6, 1 }, + { "AuxAddr2", 0, 6 }, + { "SMB_SLV_AUX_ADDR3", 0x190c0, 0 }, + { "AuxAddr3Val", 6, 1 }, + { "AuxAddr3", 0, 6 }, + { "SMB_COMMAND_CODE0", 0x190c4, 0 }, + { "SMB_COMMAND_CODE1", 0x190c8, 0 }, + { "SMB_COMMAND_CODE2", 0x190cc, 0 }, + { "SMB_COMMAND_CODE3", 0x190d0, 0 }, + { "SMB_COMMAND_CODE4", 0x190d4, 0 }, + { "SMB_COMMAND_CODE5", 0x190d8, 0 }, + { "SMB_COMMAND_CODE6", 0x190dc, 0 }, + { "SMB_COMMAND_CODE7", 0x190e0, 0 }, + { "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 }, + { "MacroCntClkCfg", 8, 5 }, + { "MicroCntClkCfg", 0, 8 }, + { "SMB_CTL_STATUS", 0x190e8, 0 }, + { "MstBusBusy", 2, 1 }, + { "SlvBusBusy", 1, 1 }, + { "BusBusy", 0, 1 }, + { NULL } +}; + +struct reg_info t5_i2cm_regs[] = { + { "I2CM_CFG", 0x190f0, 0 }, + { "I2CM_DATA", 0x190f4, 0 }, + { "I2CM_OP", 0x190f8, 0 }, + { "Busy", 31, 1 }, + { "Ack", 30, 1 }, + { "Cont", 1, 1 }, + { "Op", 0, 1 }, + { NULL } +}; + +struct reg_info t5_mi_regs[] = { + { "MI_CFG", 0x19100, 0 }, + { "T4_St", 14, 1 }, + { "ClkDiv", 5, 8 }, + { "St", 3, 2 }, + { "PreEn", 2, 1 }, + { "MDIInv", 1, 1 }, + { "MDIO_1P2V_Sel", 0, 1 }, + { "MI_ADDR", 0x19104, 0 }, + { "PhyAddr", 5, 5 }, + { "RegAddr", 0, 5 }, + { "MI_DATA", 0x19108, 0 }, + { "MI_OP", 0x1910c, 0 }, + { "Busy", 31, 1 }, + { "St", 3, 2 }, + { "Inc", 2, 1 }, + { "Op", 0, 2 }, + { NULL } +}; + +struct reg_info t5_uart_regs[] = { + { "UART_CONFIG", 0x19110, 0 }, + { "StopBits", 22, 2 }, + { "Parity", 20, 2 }, + { "DataBits", 16, 4 }, + { "ClkDiv", 0, 12 }, + { NULL } +}; + +struct reg_info t5_pmu_regs[] = { + { "PMU_PART_CG_PWRMODE", 0x19120, 0 }, + { "SGE_Part_CGEn", 19, 1 }, + { "PDP_Part_CGEn", 18, 1 }, + { "TP_Part_CGEn", 17, 1 }, + { "EDC0_Part_CGEn", 16, 1 }, + { "EDC1_Part_CGEn", 15, 1 }, + { "LE_Part_CGEn", 14, 1 }, + { "MA_Part_CGEn", 13, 1 }, + { "MC0_Part_CGEn", 12, 1 }, + { "MC1_Part_CGEn", 11, 1 }, + { "PCIE_Part_CGEn", 10, 1 }, + { "InitPowerMode", 0, 2 }, + { "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 }, + { "GlobalDeepSleepEn", 6, 1 }, + { "HWWakeUpEn", 5, 1 }, + { "Port3SleepMode", 4, 1 }, + { "Port2SleepMode", 3, 1 }, + { "Port1SleepMode", 2, 1 }, + { "Port0SleepMode", 1, 1 }, + { "WakeUp", 0, 1 }, + { NULL } +}; + +struct reg_info t5_ulp_rx_regs[] = { + { "ULP_RX_CTL", 0x19150, 0 }, + { "PCMD1Threshold", 24, 8 }, + { "PCMD0Threshold", 16, 8 }, + { "disable_0B_STAG_ERR", 14, 1 }, + { "RDMA_0b_wr_opcode", 10, 4 }, + { "RDMA_0b_wr_pass", 9, 1 }, + { "STAG_RQE", 8, 1 }, + { "RDMA_State_En", 7, 1 }, + { "Crc1_En", 6, 1 }, + { "RDMA_0b_wr_cqe", 5, 1 }, + { "PCIE_Atrb_En", 4, 1 }, + { "RDMA_permissive_mode", 3, 1 }, + { "PagePodME", 2, 1 }, + { "IscsiTagTcb", 1, 1 }, + { "TddpTagTcb", 0, 1 }, + { "ULP_RX_INT_ENABLE", 0x19154, 0 }, + { "SE_CNT_MISMATCH_1", 26, 1 }, + { "SE_CNT_MISMATCH_0", 25, 1 }, + { "ENABLE_CTX_1", 24, 1 }, + { "ENABLE_CTX_0", 23, 1 }, + { "ENABLE_FF", 22, 1 }, + { "ENABLE_APF_1", 21, 1 }, + { "ENABLE_APF_0", 20, 1 }, + { "ENABLE_AF_1", 19, 1 }, + { "ENABLE_AF_0", 18, 1 }, + { "ENABLE_DDPDF_1", 17, 1 }, + { "ENABLE_DDPMF_1", 16, 1 }, + { "ENABLE_MEMRF_1", 15, 1 }, + { "ENABLE_PRSDF_1", 14, 1 }, + { "ENABLE_DDPDF_0", 13, 1 }, + { "ENABLE_DDPMF_0", 12, 1 }, + { "ENABLE_MEMRF_0", 11, 1 }, + { "ENABLE_PRSDF_0", 10, 1 }, + { "ENABLE_PCMDF_1", 9, 1 }, + { "ENABLE_TPTCF_1", 8, 1 }, + { "ENABLE_DDPCF_1", 7, 1 }, + { "ENABLE_MPARF_1", 6, 1 }, + { "ENABLE_MPARC_1", 5, 1 }, + { "ENABLE_PCMDF_0", 4, 1 }, + { "ENABLE_TPTCF_0", 3, 1 }, + { "ENABLE_DDPCF_0", 2, 1 }, + { "ENABLE_MPARF_0", 1, 1 }, + { "ENABLE_MPARC_0", 0, 1 }, + { "ULP_RX_INT_CAUSE", 0x19158, 0 }, + { "SE_CNT_MISMATCH_1", 26, 1 }, + { "SE_CNT_MISMATCH_0", 25, 1 }, + { "CAUSE_CTX_1", 24, 1 }, + { "CAUSE_CTX_0", 23, 1 }, + { "CAUSE_FF", 22, 1 }, + { "CAUSE_APF_1", 21, 1 }, + { "CAUSE_APF_0", 20, 1 }, + { "CAUSE_AF_1", 19, 1 }, + { "CAUSE_AF_0", 18, 1 }, + { "CAUSE_DDPDF_1", 17, 1 }, + { "CAUSE_DDPMF_1", 16, 1 }, + { "CAUSE_MEMRF_1", 15, 1 }, + { "CAUSE_PRSDF_1", 14, 1 }, + { "CAUSE_DDPDF_0", 13, 1 }, + { "CAUSE_DDPMF_0", 12, 1 }, + { "CAUSE_MEMRF_0", 11, 1 }, + { "CAUSE_PRSDF_0", 10, 1 }, + { "CAUSE_PCMDF_1", 9, 1 }, + { "CAUSE_TPTCF_1", 8, 1 }, + { "CAUSE_DDPCF_1", 7, 1 }, + { "CAUSE_MPARF_1", 6, 1 }, + { "CAUSE_MPARC_1", 5, 1 }, + { "CAUSE_PCMDF_0", 4, 1 }, + { "CAUSE_TPTCF_0", 3, 1 }, + { "CAUSE_DDPCF_0", 2, 1 }, + { "CAUSE_MPARF_0", 1, 1 }, + { "CAUSE_MPARC_0", 0, 1 }, + { "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 }, + { "IscsiLlimit", 6, 26 }, + { "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 }, + { "IscsiUlimit", 6, 26 }, + { "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 }, + { "IscsiTagMask", 6, 26 }, + { "ULP_RX_ISCSI_PSZ", 0x19168, 0 }, + { "Hpz3", 24, 4 }, + { "Hpz2", 16, 4 }, + { "Hpz1", 8, 4 }, + { "Hpz0", 0, 4 }, + { "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 }, + { "TddpLlimit", 6, 26 }, + { "ULP_RX_TDDP_ULIMIT", 0x19170, 0 }, + { "TddpUlimit", 6, 26 }, + { "ULP_RX_TDDP_TAGMASK", 0x19174, 0 }, + { "TddpTagMask", 6, 26 }, + { "ULP_RX_TDDP_PSZ", 0x19178, 0 }, + { "Hpz3", 24, 4 }, + { "Hpz2", 16, 4 }, + { "Hpz1", 8, 4 }, + { "Hpz0", 0, 4 }, + { "ULP_RX_STAG_LLIMIT", 0x1917c, 0 }, + { "ULP_RX_STAG_ULIMIT", 0x19180, 0 }, + { "ULP_RX_RQ_LLIMIT", 0x19184, 0 }, + { "ULP_RX_RQ_ULIMIT", 0x19188, 0 }, + { "ULP_RX_PBL_LLIMIT", 0x1918c, 0 }, + { "ULP_RX_PBL_ULIMIT", 0x19190, 0 }, + { "ULP_RX_CTX_BASE", 0x19194, 0 }, + { "ULP_RX_PERR_ENABLE", 0x1919c, 0 }, + { "PERR_SE_CNT_MISMATCH_1", 26, 1 }, + { "PERR_SE_CNT_MISMATCH_0", 25, 1 }, + { "PERR_RSVD0", 24, 1 }, + { "PERR_RSVD1", 23, 1 }, + { "PERR_ENABLE_FF", 22, 1 }, + { "PERR_ENABLE_APF_1", 21, 1 }, + { "PERR_ENABLE_APF_0", 20, 1 }, + { "PERR_ENABLE_AF_1", 19, 1 }, + { "PERR_ENABLE_AF_0", 18, 1 }, + { "PERR_ENABLE_DDPDF_1", 17, 1 }, + { "PERR_ENABLE_DDPMF_1", 16, 1 }, + { "PERR_ENABLE_MEMRF_1", 15, 1 }, + { "PERR_ENABLE_PRSDF_1", 14, 1 }, + { "PERR_ENABLE_DDPDF_0", 13, 1 }, + { "PERR_ENABLE_DDPMF_0", 12, 1 }, + { "PERR_ENABLE_MEMRF_0", 11, 1 }, + { "PERR_ENABLE_PRSDF_0", 10, 1 }, + { "PERR_ENABLE_PCMDF_1", 9, 1 }, + { "PERR_ENABLE_TPTCF_1", 8, 1 }, + { "PERR_ENABLE_DDPCF_1", 7, 1 }, + { "PERR_ENABLE_MPARF_1", 6, 1 }, + { "PERR_ENABLE_MPARC_1", 5, 1 }, + { "PERR_ENABLE_PCMDF_0", 4, 1 }, + { "PERR_ENABLE_TPTCF_0", 3, 1 }, + { "PERR_ENABLE_DDPCF_0", 2, 1 }, + { "PERR_ENABLE_MPARF_0", 1, 1 }, + { "PERR_ENABLE_MPARC_0", 0, 1 }, + { "ULP_RX_PERR_INJECT", 0x191a0, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 }, + { "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 }, + { "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 }, + { "REQ", 21, 1 }, + { "WB", 20, 1 }, + { "TID", 0, 20 }, + { "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 }, + { "REQ", 21, 1 }, + { "WB", 20, 1 }, + { "TID", 0, 20 }, + { "ULP_RX_SE_CNT_ERR", 0x191d0, 0 }, + { "ERR_CH1", 4, 4 }, + { "ERR_CH0", 0, 4 }, + { "ULP_RX_SE_CNT_CLR", 0x191d4, 0 }, + { "CLR_CH0", 4, 4 }, + { "CLR_CH1", 0, 4 }, + { "ULP_RX_SE_CNT_CH0", 0x191d8, 0 }, + { "SOP_CNT_OUT0", 28, 4 }, + { "EOP_CNT_OUT0", 24, 4 }, + { "SOP_CNT_AL0", 20, 4 }, + { "EOP_CNT_AL0", 16, 4 }, + { "SOP_CNT_MR0", 12, 4 }, + { "EOP_CNT_MR0", 8, 4 }, + { "SOP_CNT_IN0", 4, 4 }, + { "EOP_CNT_IN0", 0, 4 }, + { "ULP_RX_SE_CNT_CH1", 0x191dc, 0 }, + { "SOP_CNT_OUT1", 28, 4 }, + { "EOP_CNT_OUT1", 24, 4 }, + { "SOP_CNT_AL1", 20, 4 }, + { "EOP_CNT_AL1", 16, 4 }, + { "SOP_CNT_MR1", 12, 4 }, + { "EOP_CNT_MR1", 8, 4 }, + { "SOP_CNT_IN1", 4, 4 }, + { "EOP_CNT_IN1", 0, 4 }, + { "ULP_RX_DBG_CTL", 0x191e0, 0 }, + { "EN_DBG_H", 17, 1 }, + { "EN_DBG_L", 16, 1 }, + { "SEL_H", 8, 8 }, + { "SEL_L", 0, 8 }, + { "ULP_RX_DBG_DATAH", 0x191e4, 0 }, + { "ULP_RX_DBG_DATAL", 0x191e8, 0 }, + { "ULP_RX_LA_CHNL", 0x19238, 0 }, + { "ULP_RX_LA_CTL", 0x1923c, 0 }, + { "ULP_RX_LA_RDPTR", 0x19240, 0 }, + { "ULP_RX_LA_RDDATA", 0x19244, 0 }, + { "ULP_RX_LA_WRPTR", 0x19248, 0 }, + { "ULP_RX_LA_RESERVED", 0x1924c, 0 }, + { "ULP_RX_CQE_GEN_EN", 0x19250, 0 }, + { "Termimate_msg", 1, 1 }, + { "Terminate_with_err", 0, 1 }, + { "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 }, + { "atomic_req_qno", 22, 2 }, + { "atomic_rsp_qno", 20, 2 }, + { "immediate_qno", 18, 2 }, + { "immediate_with_se_qno", 16, 2 }, + { "atomic_wr_opcode", 12, 4 }, + { "atomic_rd_opcode", 8, 4 }, + { "immediate_opcode", 4, 4 }, + { "immediate_with_se_opcode", 0, 4 }, + { "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 }, + { "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 }, + { "terminate_status_en", 4, 1 }, + { "multiple_pref_enable", 3, 1 }, + { "umudp_pbl_pref_enable", 2, 1 }, + { "rdma_pbl_pref_en", 1, 1 }, + { "sdc_crc_prot_en", 0, 1 }, + { "ULP_RX_CH0_CGEN", 0x19260, 0 }, + { "BYPASS_CGEN", 7, 1 }, + { "TDDP_CGEN", 6, 1 }, + { "ISCSI_CGEN", 5, 1 }, + { "RDMA_CGEN", 4, 1 }, + { "CHANNEL_CGEN", 3, 1 }, + { "All_DataPath_CGEN", 2, 1 }, + { "T10Diff_DataPath_CGEN", 1, 1 }, + { "Rdma_DataPath_CGEN", 0, 1 }, + { "ULP_RX_CH1_CGEN", 0x19264, 0 }, + { "BYPASS_CGEN", 7, 1 }, + { "TDDP_CGEN", 6, 1 }, + { "ISCSI_CGEN", 5, 1 }, + { "RDMA_CGEN", 4, 1 }, + { "CHANNEL_CGEN", 3, 1 }, + { "All_DataPath_CGEN", 2, 1 }, + { "T10Diff_DataPath_CGEN", 1, 1 }, + { "Rdma_DataPath_CGEN", 0, 1 }, + { "ULP_RX_RFE_DISABLE", 0x19268, 0 }, + { "ULP_RX_INT_ENABLE_2", 0x1926c, 0 }, + { "ULPRX2MA_IntfPerr", 8, 1 }, + { "ALN_SDC_ERR_1", 7, 1 }, + { "ALN_SDC_ERR_0", 6, 1 }, + { "PF_UNTAGGED_TPT_1", 5, 1 }, + { "PF_UNTAGGED_TPT_0", 4, 1 }, + { "PF_PBL_1", 3, 1 }, + { "PF_PBL_0", 2, 1 }, + { "DDP_HINT_1", 1, 1 }, + { "DDP_HINT_0", 0, 1 }, + { "ULP_RX_INT_CAUSE_2", 0x19270, 0 }, + { "ULPRX2MA_IntfPerr", 8, 1 }, + { "ALN_SDC_ERR_1", 7, 1 }, + { "ALN_SDC_ERR_0", 6, 1 }, + { "PF_UNTAGGED_TPT_1", 5, 1 }, + { "PF_UNTAGGED_TPT_0", 4, 1 }, + { "PF_PBL_1", 3, 1 }, + { "PF_PBL_0", 2, 1 }, + { "DDP_HINT_1", 1, 1 }, + { "DDP_HINT_0", 0, 1 }, + { "ULP_RX_PERR_ENABLE_2", 0x19274, 0 }, + { "ENABLE_ULPRX2MA_IntfPerr", 8, 1 }, + { "ENABLE_ALN_SDC_ERR_1", 7, 1 }, + { "ENABLE_ALN_SDC_ERR_0", 6, 1 }, + { "ENABLE_PF_UNTAGGED_TPT_1", 5, 1 }, + { "ENABLE_PF_UNTAGGED_TPT_0", 4, 1 }, + { "ENABLE_PF_PBL_1", 3, 1 }, + { "ENABLE_PF_PBL_0", 2, 1 }, + { "ENABLE_DDP_HINT_1", 1, 1 }, + { "ENABLE_DDP_HINT_0", 0, 1 }, + { "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 }, + { "ULP_RX_ATOMIC_LEN", 0x1927c, 0 }, + { "atomic_rpl_len", 16, 8 }, + { "atomic_req_len", 8, 8 }, + { "atomic_immediate_len", 0, 8 }, + { "ULP_RX_CGEN_GLOBAL", 0x19280, 0 }, + { "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 }, + { "clear_ctx_err_cnt1", 3, 1 }, + { "clear_ctx_err_cnt0", 2, 1 }, + { "skip_ma_req_en1", 1, 1 }, + { "skip_ma_req_en0", 0, 1 }, + { "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 }, + { "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 }, + { "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 }, + { "Rd_or_Term_msn_check_enable", 2, 1 }, + { "atomic_op_msn_check_enable", 1, 1 }, + { "send_msn_check_enable", 0, 1 }, + { NULL } +}; + +struct reg_info t5_sf_regs[] = { + { "SF_DATA", 0x193f8, 0 }, + { "SF_OP", 0x193fc, 0 }, + { "Busy", 31, 1 }, + { "Lock", 4, 1 }, + { "Cont", 3, 1 }, + { "ByteCnt", 1, 2 }, + { "Op", 0, 1 }, + { NULL } +}; + +struct reg_info t5_pl_regs[] = { + { "PL_PF_INT_CAUSE", 0x1e3c0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1e3c4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1e3c8, 0 }, + { "PL_PF_INT_CAUSE", 0x1e7c0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1e7c4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1e7c8, 0 }, + { "PL_PF_INT_CAUSE", 0x1ebc0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1ebc4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1ebc8, 0 }, + { "PL_PF_INT_CAUSE", 0x1efc0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1efc4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1efc8, 0 }, + { "PL_PF_INT_CAUSE", 0x1f3c0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1f3c4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1f3c8, 0 }, + { "PL_PF_INT_CAUSE", 0x1f7c0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1f7c4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1f7c8, 0 }, + { "PL_PF_INT_CAUSE", 0x1fbc0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1fbc4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1fbc8, 0 }, + { "PL_PF_INT_CAUSE", 0x1ffc0, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_INT_ENABLE", 0x1ffc4, 0 }, + { "SW", 3, 1 }, + { "CIM", 1, 1 }, + { "MPS", 0, 1 }, + { "PL_PF_CTL", 0x1ffc8, 0 }, + { "PL_WHOAMI", 0x19400, 0 }, + { "PortxMap", 24, 3 }, + { "SourceBus", 16, 2 }, + { "SourcePF", 8, 3 }, + { "IsVF", 7, 1 }, + { "VFID", 0, 7 }, + { "PL_PERR_CAUSE", 0x19404, 0 }, + { "MC1", 31, 1 }, + { "UART", 28, 1 }, + { "ULP_TX", 27, 1 }, + { "SGE", 26, 1 }, + { "HMA", 25, 1 }, + { "CPL_SWITCH", 24, 1 }, + { "ULP_RX", 23, 1 }, + { "PM_RX", 22, 1 }, + { "PM_TX", 21, 1 }, + { "MA", 20, 1 }, + { "TP", 19, 1 }, + { "LE", 18, 1 }, + { "EDC1", 17, 1 }, + { "EDC0", 16, 1 }, + { "MC0", 15, 1 }, + { "PCIE", 14, 1 }, + { "PMU", 13, 1 }, + { "MAC", 9, 1 }, + { "SMB", 8, 1 }, + { "SF", 7, 1 }, + { "PL", 6, 1 }, + { "NCSI", 5, 1 }, + { "MPS", 4, 1 }, + { "MI", 3, 1 }, + { "DBG", 2, 1 }, + { "I2CM", 1, 1 }, + { "CIM", 0, 1 }, + { "PL_PERR_ENABLE", 0x19408, 0 }, + { "MC1", 31, 1 }, + { "UART", 28, 1 }, + { "ULP_TX", 27, 1 }, + { "SGE", 26, 1 }, + { "HMA", 25, 1 }, + { "CPL_SWITCH", 24, 1 }, + { "ULP_RX", 23, 1 }, + { "PM_RX", 22, 1 }, + { "PM_TX", 21, 1 }, + { "MA", 20, 1 }, + { "TP", 19, 1 }, + { "LE", 18, 1 }, + { "EDC1", 17, 1 }, + { "EDC0", 16, 1 }, + { "MC0", 15, 1 }, + { "PCIE", 14, 1 }, + { "PMU", 13, 1 }, + { "MAC", 9, 1 }, + { "SMB", 8, 1 }, + { "SF", 7, 1 }, + { "PL", 6, 1 }, + { "NCSI", 5, 1 }, + { "MPS", 4, 1 }, + { "MI", 3, 1 }, + { "DBG", 2, 1 }, + { "I2CM", 1, 1 }, + { "CIM", 0, 1 }, + { "PL_INT_CAUSE", 0x1940c, 0 }, + { "MC1", 31, 1 }, + { "FLR", 30, 1 }, + { "SW_CIM", 29, 1 }, + { "UART", 28, 1 }, + { "ULP_TX", 27, 1 }, + { "SGE", 26, 1 }, + { "HMA", 25, 1 }, + { "CPL_SWITCH", 24, 1 }, + { "ULP_RX", 23, 1 }, + { "PM_RX", 22, 1 }, + { "PM_TX", 21, 1 }, + { "MA", 20, 1 }, + { "TP", 19, 1 }, + { "LE", 18, 1 }, + { "EDC1", 17, 1 }, + { "EDC0", 16, 1 }, + { "MC0", 15, 1 }, + { "PCIE", 14, 1 }, + { "PMU", 13, 1 }, + { "MAC3", 12, 1 }, + { "MAC2", 11, 1 }, + { "MAC1", 10, 1 }, + { "MAC0", 9, 1 }, + { "SMB", 8, 1 }, + { "SF", 7, 1 }, + { "PL", 6, 1 }, + { "NCSI", 5, 1 }, + { "MPS", 4, 1 }, + { "MI", 3, 1 }, + { "DBG", 2, 1 }, + { "I2CM", 1, 1 }, + { "CIM", 0, 1 }, + { "PL_INT_ENABLE", 0x19410, 0 }, + { "MC1", 31, 1 }, + { "FLR", 30, 1 }, + { "SW_CIM", 29, 1 }, + { "UART", 28, 1 }, + { "ULP_TX", 27, 1 }, + { "SGE", 26, 1 }, + { "HMA", 25, 1 }, + { "CPL_SWITCH", 24, 1 }, + { "ULP_RX", 23, 1 }, + { "PM_RX", 22, 1 }, + { "PM_TX", 21, 1 }, + { "MA", 20, 1 }, + { "TP", 19, 1 }, + { "LE", 18, 1 }, + { "EDC1", 17, 1 }, + { "EDC0", 16, 1 }, + { "MC0", 15, 1 }, + { "PCIE", 14, 1 }, + { "PMU", 13, 1 }, + { "MAC3", 12, 1 }, + { "MAC2", 11, 1 }, + { "MAC1", 10, 1 }, + { "MAC0", 9, 1 }, + { "SMB", 8, 1 }, + { "SF", 7, 1 }, + { "PL", 6, 1 }, + { "NCSI", 5, 1 }, + { "MPS", 4, 1 }, + { "MI", 3, 1 }, + { "DBG", 2, 1 }, + { "I2CM", 1, 1 }, + { "CIM", 0, 1 }, + { "PL_INT_MAP0", 0x19414, 0 }, + { "MapNCSI", 16, 9 }, + { "MapDefault", 0, 9 }, + { "PL_INT_MAP1", 0x19418, 0 }, + { "MapMAC1", 16, 9 }, + { "MapMAC0", 0, 9 }, + { "PL_INT_MAP2", 0x1941c, 0 }, + { "MapMAC3", 16, 9 }, + { "MapMAC2", 0, 9 }, + { "PL_INT_MAP3", 0x19420, 0 }, + { "MapMI", 16, 9 }, + { "MapSMB", 0, 9 }, + { "PL_INT_MAP4", 0x19424, 0 }, + { "MapDBG", 16, 9 }, + { "MapI2CM", 0, 9 }, + { "PL_RST", 0x19428, 0 }, + { "AutoPciePause", 4, 1 }, + { "FatalPerrEn", 3, 1 }, + { "SWIntCIM", 2, 1 }, + { "PIORst", 1, 1 }, + { "PIORstMode", 0, 1 }, + { "PL_PL_INT_CAUSE", 0x19430, 0 }, + { "PL_BusPerr", 6, 1 }, + { "FatalPerr", 4, 1 }, + { "InvalidAccess", 3, 1 }, + { "Timeout", 2, 1 }, + { "PLErr", 1, 1 }, + { "PL_PL_INT_ENABLE", 0x19434, 0 }, + { "PL_BusPerr", 6, 1 }, + { "FatalPerr", 4, 1 }, + { "InvalidAccess", 3, 1 }, + { "Timeout", 2, 1 }, + { "PLErr", 1, 1 }, + { "PL_PL_PERR_ENABLE", 0x19438, 0 }, + { "PL_BusPerr", 6, 1 }, + { "PL_REV", 0x1943c, 0 }, + { "ChipID", 4, 4 }, + { "Rev", 0, 4 }, + { "PL_PCIE_LINK", 0x19440, 0 }, + { "LN0_AESTAT", 26, 3 }, + { "LN0_AECMD", 23, 3 }, + { "StateCfgInitF", 16, 7 }, + { "StateCfgInit", 12, 4 }, + { "SPEED", 8, 2 }, + { "PERstTimeout", 7, 1 }, + { "LTSSMEnable", 6, 1 }, + { "LTSSM", 0, 6 }, + { "PL_PCIE_CTL_STAT", 0x19444, 0 }, + { "Status", 16, 16 }, + { "Control", 0, 16 }, + { "PL_SEMAPHORE_CTL", 0x1944c, 0 }, + { "LockStatus", 16, 8 }, + { "OwnerOverride", 8, 1 }, + { "EnablePF", 0, 8 }, + { "PL_SEMAPHORE_LOCK", 0x19450, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x19454, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x19458, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x1945c, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x19460, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x19464, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x19468, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_SEMAPHORE_LOCK", 0x1946c, 0 }, + { "Lock", 31, 1 }, + { "SourceBus", 3, 2 }, + { "SourcePF", 0, 3 }, + { "PL_PORTX_MAP", 0x19474, 0 }, + { "MAP7", 28, 3 }, + { "MAP6", 24, 3 }, + { "MAP5", 20, 3 }, + { "MAP4", 16, 3 }, + { "MAP3", 12, 3 }, + { "MAP2", 8, 3 }, + { "MAP1", 4, 3 }, + { "MAP0", 0, 3 }, + { "PL_VF_SLICE_L", 0x19490, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x19498, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194a0, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194a8, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194b0, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194b8, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194c0, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_L", 0x194c8, 0 }, + { "LimitAddr", 16, 10 }, + { "BaseAddr", 0, 10 }, + { "PL_VF_SLICE_H", 0x19494, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x1949c, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194a4, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194ac, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194b4, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194bc, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194c4, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_VF_SLICE_H", 0x194cc, 0 }, + { "ModIndx", 16, 3 }, + { "ModOffset", 0, 10 }, + { "PL_TIMEOUT_CTL", 0x194f0, 0 }, + { "PerrCapture", 16, 1 }, + { "Timeout", 0, 16 }, + { "PL_TIMEOUT_STATUS0", 0x194f4, 0 }, + { "Addr", 2, 28 }, + { "PL_TIMEOUT_STATUS1", 0x194f8, 0 }, + { "Valid", 31, 1 }, + { "ValidPerr", 30, 1 }, + { "Write", 22, 1 }, + { "Bus", 20, 2 }, + { "PF", 16, 3 }, + { "VFID", 0, 8 }, + { NULL } +}; + +struct reg_info t5_le_regs[] = { + { "LE_BUF_CONFIG", 0x19c00, 0 }, + { "LE_DB_CONFIG", 0x19c04, 0 }, + { "MASKCMDOLAPDIS", 26, 1 }, + { "IPv4HASHSIZEEN", 25, 1 }, + { "PROTOCOLMASKEN", 24, 1 }, + { "TUPLESIZEEN", 23, 1 }, + { "SRVRSRAMEN", 22, 1 }, + { "TCAMCMDOVLAPEN", 21, 1 }, + { "HASHEN", 20, 1 }, + { "ASBOTHSRCHENPR", 19, 1 }, + { "ASBOTHSRCHEN", 18, 1 }, + { "ASLIPCOMPEN", 17, 1 }, + { "BUILD", 16, 1 }, + { "POCLIPTID0", 15, 1 }, + { "TCAMARBOFF", 14, 1 }, + { "ACCNTFULLEN", 13, 1 }, + { "FilterRWnoCLIP", 12, 1 }, + { "FilterEn", 11, 1 }, + { "CRCHASH", 10, 1 }, + { "COMPTID", 9, 1 }, + { "SYNMode", 7, 2 }, + { "SINGLETHREAD", 6, 1 }, + { "LEBUSEN", 5, 1 }, + { "ELOOKDUMEN", 4, 1 }, + { "IPv4ONLYEN", 3, 1 }, + { "MOSTCMDOEN", 2, 1 }, + { "DELACTSYNOEN", 1, 1 }, + { "CMDOVERLAPDIS", 0, 1 }, + { "LE_MISC", 0x19c08, 0 }, + { "SRAMDEEPSLEEP_STAT", 11, 1 }, + { "TCAMDEEPSLEEP1_STAT", 10, 1 }, + { "TCAMDEEPSLEEP0_STAT", 9, 1 }, + { "SRAMDEEPSLEEP", 8, 1 }, + { "TCAMDEEPSLEEP1", 7, 1 }, + { "TCAMDEEPSLEEP0", 6, 1 }, + { "SRVRAMCLKOFF", 5, 1 }, + { "HASHCLKOFF", 4, 1 }, + { "CMPUNVAIL", 0, 4 }, + { "LE_DB_ROUTING_TABLE_INDEX", 0x19c10, 0 }, + { "RTINDX", 7, 6 }, + { "LE_DB_FILTER_TABLE_INDEX", 0x19c14, 0 }, + { "FTINDX", 7, 6 }, + { "LE_DB_SERVER_INDEX", 0x19c18, 0 }, + { "SRINDX", 7, 6 }, + { "LE_DB_CLIP_TABLE_INDEX", 0x19c1c, 0 }, + { "CLIPTINDX", 7, 6 }, + { "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 }, + { "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 }, + { "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 }, + { "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 }, + { "LE_ACT_CNT_THRSH", 0x19c9c, 0 }, + { "LE_DB_HASH_CONFIG", 0x19c28, 0 }, + { "HASHTIDSIZE", 16, 6 }, + { "HASHSIZE", 0, 6 }, + { "LE_DB_HASH_TABLE_BASE", 0x19c2c, 0 }, + { "LE_DB_HASH_TID_BASE", 0x19c30, 0 }, + { "LE_DB_SIZE", 0x19c34, 0 }, + { "LE_DB_INT_ENABLE", 0x19c38, 0 }, + { "MsgSel", 27, 5 }, + { "ActCntIPv6Tzero", 21, 1 }, + { "ActCntIPv4Tzero", 20, 1 }, + { "ActCntIPv6zero", 19, 1 }, + { "ActCntIPv4zero", 18, 1 }, + { "MARspParErr", 17, 1 }, + { "ReqQParErr", 16, 1 }, + { "UnknownCmd", 15, 1 }, + { "VfParErr", 14, 1 }, + { "DropFilterHit", 13, 1 }, + { "FilterHit", 12, 1 }, + { "SYNCookieOff", 11, 1 }, + { "SYNCookieBad", 10, 1 }, + { "SYNCookie", 9, 1 }, + { "NFASrchFail", 8, 1 }, + { "ActRgnFull", 7, 1 }, + { "ParityErr", 6, 1 }, + { "LIPMiss", 5, 1 }, + { "LIP0", 4, 1 }, + { "Miss", 3, 1 }, + { "RoutingHit", 2, 1 }, + { "ActiveHit", 1, 1 }, + { "ServerHit", 0, 1 }, + { "LE_DB_INT_CAUSE", 0x19c3c, 0 }, + { "ActCntIPv6Tzero", 21, 1 }, + { "ActCntIPv4Tzero", 20, 1 }, + { "ActCntIPv6zero", 19, 1 }, + { "ActCntIPv4zero", 18, 1 }, + { "MARspParErr", 17, 1 }, + { "ReqQParErr", 16, 1 }, + { "UnknownCmd", 15, 1 }, + { "VfParErr", 14, 1 }, + { "DropFilterHit", 13, 1 }, + { "FilterHit", 12, 1 }, + { "SYNCookieOff", 11, 1 }, + { "SYNCookieBad", 10, 1 }, + { "SYNCookie", 9, 1 }, + { "NFASrchFail", 8, 1 }, + { "ActRgnFull", 7, 1 }, + { "ParityErr", 6, 1 }, + { "LIPMiss", 5, 1 }, + { "LIP0", 4, 1 }, + { "Miss", 3, 1 }, + { "RoutingHit", 2, 1 }, + { "ActiveHit", 1, 1 }, + { "ServerHit", 0, 1 }, + { "LE_DB_INT_TID", 0x19c40, 0 }, + { "LE_DB_INT_PTID", 0x19c44, 0 }, + { "LE_DB_INT_INDEX", 0x19c48, 0 }, + { "LE_DB_INT_CMD", 0x19c4c, 0 }, + { "LE_DB_MASK_IPV4", 0x19c50, 0 }, + { "LE_DB_MASK_IPV4", 0x19c54, 0 }, + { "LE_DB_MASK_IPV4", 0x19c58, 0 }, + { "LE_DB_MASK_IPV4", 0x19c5c, 0 }, + { "LE_DB_MASK_IPV4", 0x19c60, 0 }, + { "LE_DB_MASK_IPV6", 0x19ca0, 0 }, + { "LE_DB_MASK_IPV6", 0x19ca4, 0 }, + { "LE_DB_MASK_IPV6", 0x19ca8, 0 }, + { "LE_DB_MASK_IPV6", 0x19cac, 0 }, + { "LE_DB_MASK_IPV6", 0x19cb0, 0 }, + { "LE_DB_MASK_IPV6", 0x19cb4, 0 }, + { "LE_DB_MASK_IPV6", 0x19cb8, 0 }, + { "LE_DB_MASK_IPV6", 0x19cbc, 0 }, + { "LE_DB_MASK_IPV6", 0x19cc0, 0 }, + { "LE_DB_MASK_IPV6", 0x19cc4, 0 }, + { "LE_DB_MASK_IPV6", 0x19cc8, 0 }, + { "LE_DB_MASK_IPV6", 0x19ccc, 0 }, + { "LE_DB_MASK_IPV6", 0x19cd0, 0 }, + { "LE_DB_MASK_IPV6", 0x19cd4, 0 }, + { "LE_DB_MASK_IPV6", 0x19cd8, 0 }, + { "LE_DB_MASK_IPV6", 0x19cdc, 0 }, + { "LE_DB_MASK_IPV6", 0x19ce0, 0 }, + { "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 }, + { "RspCnt", 16, 16 }, + { "ReqCnt", 0, 16 }, + { "LE_DB_DBGI_CONFIG", 0x19cf0, 0 }, + { "DBGICMDPERR", 31, 1 }, + { "DBGICMDRANGE", 22, 3 }, + { "DBGICMDMSKTYPE", 21, 1 }, + { "DBGICMDSEARCH", 20, 1 }, + { "DBGICMDREAD", 19, 1 }, + { "DBGICMDLEARN", 18, 1 }, + { "DBGICMDERASE", 17, 1 }, + { "DBGICMDIPv6", 16, 1 }, + { "DBGICMDTYPE", 13, 3 }, + { "DBGICMDACKERR", 12, 1 }, + { "DBGICMDBUSY", 3, 1 }, + { "DBGICMDSTRT", 2, 1 }, + { "DBGICMDMODE", 0, 2 }, + { "LE_DB_DBGI_REQ_TCAM_CMD", 0x19cf4, 0 }, + { "DBGICMD", 20, 4 }, + { "DBGITINDEX", 0, 20 }, + { "LE_PERR_ENABLE", 0x19cf8, 0 }, + { "MARspParErr", 17, 1 }, + { "ReqQueue", 16, 1 }, + { "VfParErr", 14, 1 }, + { "TCAM", 6, 1 }, + { "LE_SPARE", 0x19cfc, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d2c, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d30, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d34, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d38, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d3c, 0 }, + { "LE_DB_DBGI_REQ_DATA", 0x19d40, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d7c, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d80, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d84, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d88, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d8c, 0 }, + { "LE_DB_DBGI_REQ_MASK", 0x19d90, 0 }, + { "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 }, + { "DBGIRspIndex", 12, 20 }, + { "DBGIRspMsg", 8, 4 }, + { "DBGIRspMsgVld", 7, 1 }, + { "DBGIRspMHit", 2, 1 }, + { "DBGIRspHit", 1, 1 }, + { "DBGIRspValid", 0, 1 }, + { "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 }, + { "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 }, + { "LE_DB_DBGI_RSP_LAST_CMD", 0x19de4, 0 }, + { "LastCmdB", 16, 11 }, + { "LastCmdA", 0, 11 }, + { "LE_DB_DROP_FILTER_ENTRY", 0x19de8, 0 }, + { "DropFilterEn", 31, 1 }, + { "DropFilterClear", 17, 1 }, + { "DropFilterSet", 16, 1 }, + { "DropFilterFIDX", 0, 13 }, + { "LE_DB_PTID_SVRBASE", 0x19df0, 0 }, + { "SVRBASE_ADDR", 2, 18 }, + { "LE_DB_FTID_FLTRBASE", 0x19df4, 0 }, + { "FLTRBASE_ADDR", 2, 18 }, + { "LE_DB_TID_HASHBASE", 0x19df8, 0 }, + { "HASHBASE_ADDR", 2, 20 }, + { "LE_PERR_INJECT", 0x19dfc, 0 }, + { "MemSel", 1, 3 }, + { "InjectDataErr", 0, 1 }, + { "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 }, + { "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 }, + { "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 }, + { "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 }, + { "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e70, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e74, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e78, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e7c, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e80, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e84, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e88, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e8c, 0 }, + { "LE_DB_ACTIVE_MASK_IPV6", 0x19e90, 0 }, + { "LE_HASH_MASK_GEN_IPV4", 0x19ea0, 0 }, + { "LE_HASH_MASK_GEN_IPV4", 0x19ea4, 0 }, + { "LE_HASH_MASK_GEN_IPV4", 0x19ea8, 0 }, + { "LE_HASH_MASK_GEN_IPV4", 0x19eac, 0 }, + { "LE_HASH_MASK_GEN_IPV4", 0x19eb0, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19eb4, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19eb8, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ebc, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ec0, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ec4, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ec8, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ecc, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ed0, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ed4, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ed8, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19edc, 0 }, + { "LE_HASH_MASK_GEN_IPV6", 0x19ee0, 0 }, + { "LE_HASH_MASK_CMP_IPV4", 0x19ee4, 0 }, + { "LE_HASH_MASK_CMP_IPV4", 0x19ee8, 0 }, + { "LE_HASH_MASK_CMP_IPV4", 0x19eec, 0 }, + { "LE_HASH_MASK_CMP_IPV4", 0x19ef0, 0 }, + { "LE_HASH_MASK_CMP_IPV4", 0x19ef4, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19ef8, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19efc, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f00, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f04, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f08, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f0c, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f10, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f14, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f18, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f1c, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f20, 0 }, + { "LE_HASH_MASK_CMP_IPV6", 0x19f24, 0 }, + { "LE_SRVR_SRAM_INIT", 0x19f34, 0 }, + { "SRVRSRAMBASE", 2, 20 }, + { "SRVRINITBUSY", 1, 1 }, + { "SRVRINIT", 0, 1 }, + { "LE_SRVR_VF_SRCH_TABLE", 0x19f38, 0 }, + { "RDWR", 21, 1 }, + { "VFINDEX", 14, 7 }, + { "SRCHHADDR", 7, 7 }, + { "SRCHLADDR", 0, 7 }, + { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 }, + { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 }, + { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 }, + { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 }, + { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 }, + { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 }, + { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 }, + { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 }, + { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 }, + { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 }, + { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa4, 0 }, + { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa8, 0 }, + { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fac, 0 }, + { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb0, 0 }, + { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb4, 0 }, + { "LE_HASH_COLLISION", 0x19fc4, 0 }, + { "LE_GLOBAL_COLLISION", 0x19fc8, 0 }, + { "LE_FULL_CNT_COLLISION", 0x19fcc, 0 }, + { "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 }, + { "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 }, + { "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 }, + { "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 }, + { "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 }, + { "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 }, + { NULL } +}; + +struct reg_info t5_ncsi_regs[] = { + { "NCSI_PORT_CFGREG", 0x1a000, 0 }, + { "WireEn", 28, 4 }, + { "strp_crc", 24, 4 }, + { "rx_halt", 22, 1 }, + { "flush_rx_fifo", 21, 1 }, + { "hw_arb_en", 20, 1 }, + { "soft_pkg_sel", 19, 1 }, + { "err_discard_en", 18, 1 }, + { "max_pkt_size", 4, 14 }, + { "rx_byte_swap", 3, 1 }, + { "tx_byte_swap", 2, 1 }, + { "NCSI_RST_CTRL", 0x1a004, 0 }, + { "mac_ref_rst", 2, 1 }, + { "mac_rx_rst", 1, 1 }, + { "mac_tx_rst", 0, 1 }, + { "NCSI_CH0_SADDR_LOW", 0x1a010, 0 }, + { "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 }, + { "CHO_SADDR_EN", 31, 1 }, + { "CH0_SADDR_HIGH", 0, 16 }, + { "NCSI_CH1_SADDR_LOW", 0x1a018, 0 }, + { "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 }, + { "CH1_SADDR_EN", 31, 1 }, + { "CH1_SADDR_HIGH", 0, 16 }, + { "NCSI_CH2_SADDR_LOW", 0x1a020, 0 }, + { "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 }, + { "CH2_SADDR_EN", 31, 1 }, + { "CH2_SADDR_HIGH", 0, 16 }, + { "NCSI_CH3_SADDR_LOW", 0x1a028, 0 }, + { "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 }, + { "CH3_SADDR_EN", 31, 1 }, + { "CH3_SADDR_HIGH", 0, 16 }, + { "NCSI_WORK_REQHDR_0", 0x1a030, 0 }, + { "NCSI_WORK_REQHDR_1", 0x1a034, 0 }, + { "NCSI_WORK_REQHDR_2", 0x1a038, 0 }, + { "NCSI_WORK_REQHDR_3", 0x1a03c, 0 }, + { "NCSI_MPS_HDR_LO", 0x1a040, 0 }, + { "NCSI_MPS_HDR_HI", 0x1a044, 0 }, + { "NCSI_CTL", 0x1a048, 0 }, + { "STRIP_OVLAN", 3, 1 }, + { "bmc_drop_non_bc", 2, 1 }, + { "bmc_rx_fwd_all", 1, 1 }, + { "FWD_BMC", 0, 1 }, + { "NCSI_NCSI_ETYPE", 0x1a04c, 0 }, + { "NCSI_RX_FIFO_CNT", 0x1a050, 0 }, + { "NCSI_RX_ERR_CNT", 0x1a054, 0 }, + { "NCSI_RX_OF_CNT", 0x1a058, 0 }, + { "NCSI_RX_MS_CNT", 0x1a05c, 0 }, + { "NCSI_RX_IE_CNT", 0x1a060, 0 }, + { "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 }, + { "MPS2CIM_CNT", 16, 9 }, + { "MPS2BMC_CNT", 0, 9 }, + { "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 }, + { "CIM2MPS_CNT", 16, 9 }, + { "CIM2BMC_CNT", 0, 9 }, + { "NCSI_TX_FIFO_CNT", 0x1a06c, 0 }, + { "NCSI_SE_CNT_CTL", 0x1a0b0, 0 }, + { "NCSI_SE_CNT_MPS", 0x1a0b4, 0 }, + { "NCSI_SE_CNT_CIM", 0x1a0b8, 0 }, + { "NCSI_BUS_DEBUG", 0x1a0bc, 0 }, + { "NCSI_LA_RDPTR", 0x1a0c0, 0 }, + { "NCSI_LA_RDDATA", 0x1a0c4, 0 }, + { "NCSI_LA_WRPTR", 0x1a0c8, 0 }, + { "NCSI_LA_RESERVED", 0x1a0cc, 0 }, + { "NCSI_LA_CTL", 0x1a0d0, 0 }, + { "NCSI_INT_ENABLE", 0x1a0d4, 0 }, + { "CIM_DM_prty_err", 8, 1 }, + { "MPS_DM_prty_err", 7, 1 }, + { "token", 6, 1 }, + { "arb_done", 5, 1 }, + { "arb_started", 4, 1 }, + { "WOL", 3, 1 }, + { "MACInt", 2, 1 }, + { "TXFIFO_prty_err", 1, 1 }, + { "RXFIFO_prty_err", 0, 1 }, + { "NCSI_INT_CAUSE", 0x1a0d8, 0 }, + { "CIM_DM_prty_err", 8, 1 }, + { "MPS_DM_prty_err", 7, 1 }, + { "token", 6, 1 }, + { "arb_done", 5, 1 }, + { "arb_started", 4, 1 }, + { "WOL", 3, 1 }, + { "MACInt", 2, 1 }, + { "TXFIFO_prty_err", 1, 1 }, + { "RXFIFO_prty_err", 0, 1 }, + { "NCSI_STATUS", 0x1a0dc, 0 }, + { "Master", 1, 1 }, + { "arb_status", 0, 1 }, + { "NCSI_PAUSE_CTRL", 0x1a0e0, 0 }, + { "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 }, + { "NCSI_PAUSE_WM", 0x1a0ec, 0 }, + { "PauseHWM", 16, 11 }, + { "PauseLWM", 0, 11 }, + { "NCSI_DEBUG", 0x1a0f0, 0 }, + { "TxFIFO_empty", 4, 1 }, + { "TxFIFO_full", 3, 1 }, + { "PKG_ID", 0, 3 }, + { "NCSI_PERR_INJECT", 0x1a0f4, 0 }, + { "MemSel", 1, 1 }, + { "InjectDataErr", 0, 1 }, + { "NCSI_PERR_ENABLE", 0x1a0f8, 0 }, + { "CIM_DM_prty_err", 8, 1 }, + { "MPS_DM_prty_err", 7, 1 }, + { "TXFIFO_prty_err", 1, 1 }, + { "RXFIFO_prty_err", 0, 1 }, + { "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 }, + { "TxSndZeroPause", 12, 1 }, + { "TxSndPause", 11, 1 }, + { "TxStop", 10, 1 }, + { "TxStart", 9, 1 }, + { "BackPress", 8, 1 }, + { "StatWrEn", 7, 1 }, + { "IncrStat", 6, 1 }, + { "ClearStat", 5, 1 }, + { "EnMgmtPort", 4, 1 }, + { "TxEn", 3, 1 }, + { "RxEn", 2, 1 }, + { "LoopLocal", 1, 1 }, + { "LoopPHY", 0, 1 }, + { "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 }, + { "PClkDiv128", 22, 1 }, + { "CopyPause", 21, 1 }, + { "NonStdPreOK", 20, 1 }, + { "NoFCS", 19, 1 }, + { "RxEnHalfDup", 18, 1 }, + { "NoCopyFCS", 17, 1 }, + { "LenChkEn", 16, 1 }, + { "RxBufOffset", 14, 2 }, + { "PauseEn", 13, 1 }, + { "RetryTest", 12, 1 }, + { "PClkDiv", 10, 2 }, + { "ExtClass", 9, 1 }, + { "En1536Frame", 8, 1 }, + { "UCastHashEn", 7, 1 }, + { "MCastHashEn", 6, 1 }, + { "RxBCastDis", 5, 1 }, + { "CopyAllFrames", 4, 1 }, + { "JumboEn", 3, 1 }, + { "SerEn", 2, 1 }, + { "FullDuplex", 1, 1 }, + { "Speed", 0, 1 }, + { "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 }, + { "PHYMgmtStatus", 2, 1 }, + { "MDIStatus", 1, 1 }, + { "LinkStatus", 0, 1 }, + { "NCSI_MACB_TX_STATUS", 0x1a114, 0 }, + { "UnderrunErr", 6, 1 }, + { "TxComplete", 5, 1 }, + { "BufferExhausted", 4, 1 }, + { "TxProgress", 3, 1 }, + { "RetryLimit", 2, 1 }, + { "ColEvent", 1, 1 }, + { "UsedBitRead", 0, 1 }, + { "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 }, + { "RxBufQPtr", 2, 30 }, + { "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 }, + { "TxBufQPtr", 2, 30 }, + { "NCSI_MACB_RX_STATUS", 0x1a120, 0 }, + { "RxOverrunErr", 2, 1 }, + { "FrameRcvd", 1, 1 }, + { "NoRxBuf", 0, 1 }, + { "NCSI_MACB_INT_STATUS", 0x1a124, 0 }, + { "PauseTimeZero", 13, 1 }, + { "PauseRcvd", 12, 1 }, + { "HRespNotOK", 11, 1 }, + { "RxOverrun", 10, 1 }, + { "LinkChange", 9, 1 }, + { "TxComplete", 7, 1 }, + { "TxBufErr", 6, 1 }, + { "RetryLimitErr", 5, 1 }, + { "TxBufUnderrun", 4, 1 }, + { "TxUsedBitRead", 3, 1 }, + { "RxUsedBitRead", 2, 1 }, + { "RxComplete", 1, 1 }, + { "MgmtFrameSent", 0, 1 }, + { "NCSI_MACB_INT_EN", 0x1a128, 0 }, + { "PauseTimeZero", 13, 1 }, + { "PauseRcvd", 12, 1 }, + { "HRespNotOK", 11, 1 }, + { "RxOverrun", 10, 1 }, + { "LinkChange", 9, 1 }, + { "TxComplete", 7, 1 }, + { "TxBufErr", 6, 1 }, + { "RetryLimitErr", 5, 1 }, + { "TxBufUnderrun", 4, 1 }, + { "TxUsedBitRead", 3, 1 }, + { "RxUsedBitRead", 2, 1 }, + { "RxComplete", 1, 1 }, + { "MgmtFrameSent", 0, 1 }, + { "NCSI_MACB_INT_DIS", 0x1a12c, 0 }, + { "PauseTimeZero", 13, 1 }, + { "PauseRcvd", 12, 1 }, + { "HRespNotOK", 11, 1 }, + { "RxOverrun", 10, 1 }, + { "LinkChange", 9, 1 }, + { "TxComplete", 7, 1 }, + { "TxBufErr", 6, 1 }, + { "RetryLimitErr", 5, 1 }, + { "TxBufUnderrun", 4, 1 }, + { "TxUsedBitRead", 3, 1 }, + { "RxUsedBitRead", 2, 1 }, + { "RxComplete", 1, 1 }, + { "MgmtFrameSent", 0, 1 }, + { "NCSI_MACB_INT_MASK", 0x1a130, 0 }, + { "PauseTimeZero", 13, 1 }, + { "PauseRcvd", 12, 1 }, + { "HRespNotOK", 11, 1 }, + { "RxOverrun", 10, 1 }, + { "LinkChange", 9, 1 }, + { "TxComplete", 7, 1 }, + { "TxBufErr", 6, 1 }, + { "RetryLimitErr", 5, 1 }, + { "TxBufUnderrun", 4, 1 }, + { "TxUsedBitRead", 3, 1 }, + { "RxUsedBitRead", 2, 1 }, + { "RxComplete", 1, 1 }, + { "MgmtFrameSent", 0, 1 }, + { "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 }, + { "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 }, + { "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 }, + { "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 }, + { "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 }, + { "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 }, + { "NCSI_MACB_FCS_ERR", 0x1a150, 0 }, + { "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 }, + { "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 }, + { "NCSI_MACB_LATE_COL", 0x1a15c, 0 }, + { "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 }, + { "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 }, + { "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 }, + { "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 }, + { "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 }, + { "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 }, + { "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 }, + { "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 }, + { "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 }, + { "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 }, + { "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 }, + { "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 }, + { "NCSI_MACB_HASH_LOW", 0x1a190, 0 }, + { "NCSI_MACB_HASH_HIGH", 0x1a194, 0 }, + { "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 }, + { "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 }, + { "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 }, + { "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 }, + { "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 }, + { "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 }, + { "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 }, + { "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 }, + { "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 }, + { "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 }, + { "NCSI_MACB_USER_IO", 0x1a1c0, 0 }, + { "UserProgInput", 16, 16 }, + { "UserProgOutput", 0, 16 }, + { "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 }, + { "MCHashEn", 19, 1 }, + { "Specific1En", 18, 1 }, + { "ARPEn", 17, 1 }, + { "MagicPktEn", 16, 1 }, + { "ARPIPAddr", 0, 16 }, + { "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 }, + { "PartRef", 16, 16 }, + { "DesRev", 0, 16 }, + { NULL } +}; + +struct reg_info t5_mac_regs[] = { + { "MAC_PORT_CFG", 0x30800, 0 }, + { "MAC_Clk_Sel", 29, 3 }, + { "SinkTx", 27, 1 }, + { "SinkTxOnLinkDown", 26, 1 }, + { "LoopNoFwd", 24, 1 }, + { "Smux_Rx_Loop", 19, 1 }, + { "Rx_Lane_Swap", 18, 1 }, + { "Tx_Lane_Swap", 17, 1 }, + { "Signal_Det", 14, 1 }, + { "SmuxTxSel", 9, 1 }, + { "SmuxRxSel", 8, 1 }, + { "PortSpeed", 4, 2 }, + { "Rx_Byte_Swap", 3, 1 }, + { "Tx_Byte_Swap", 2, 1 }, + { "Port_Sel", 0, 1 }, + { "MAC_PORT_RESET_CTRL", 0x30804, 0 }, + { "TWGDSK_HSSC16B", 31, 1 }, + { "EEE_RESET", 30, 1 }, + { "PTP_TIMER", 29, 1 }, + { "MtipRefReset", 28, 1 }, + { "MtipTxffReset", 27, 1 }, + { "MtipRxffReset", 26, 1 }, + { "MtipRegReset", 25, 1 }, + { "AEC3Reset", 23, 1 }, + { "AEC2Reset", 22, 1 }, + { "AEC1Reset", 21, 1 }, + { "AEC0Reset", 20, 1 }, + { "AET3Reset", 19, 1 }, + { "AET2Reset", 18, 1 }, + { "AET1Reset", 17, 1 }, + { "AET0Reset", 16, 1 }, + { "TXIF_Reset", 12, 1 }, + { "RXIF_Reset", 11, 1 }, + { "AuxExt_Reset", 10, 1 }, + { "MtipSd3TxRst", 9, 1 }, + { "MtipSd2TxRst", 8, 1 }, + { "MtipSd1TxRst", 7, 1 }, + { "MtipSd0TxRst", 6, 1 }, + { "MtipSd3RxRst", 5, 1 }, + { "MtipSd2RxRst", 4, 1 }, + { "MtipSd1RxRst", 3, 1 }, + { "WOL_Reset", 2, 1 }, + { "MtipSd0RxRst", 1, 1 }, + { "HSS_Reset", 0, 1 }, + { "MAC_PORT_LED_CFG", 0x30808, 0 }, + { "Led1_Cfg", 5, 3 }, + { "Led1_Polarity_Inv", 4, 1 }, + { "Led0_Cfg", 1, 3 }, + { "Led0_Polarity_Inv", 0, 1 }, + { "MAC_PORT_LED_COUNTHI", 0x3080c, 0 }, + { "MAC_PORT_LED_COUNTLO", 0x30810, 0 }, + { "MAC_PORT_CFG3", 0x30814, 0 }, + { "FPGA_PTP_PORT", 26, 2 }, + { "FCSDisCtrl", 25, 1 }, + { "SigDetCtrl", 24, 1 }, + { "tx_lane", 23, 1 }, + { "rx_lane", 22, 1 }, + { "se_clr", 21, 1 }, + { "an_ena", 17, 4 }, + { "sd_rx_clk_ena", 13, 4 }, + { "sd_tx_clk_ena", 9, 4 }, + { "SGMIISEL", 8, 1 }, + { "HSSPLLSEL", 4, 4 }, + { "HSSC16C20SEL", 0, 4 }, + { "MAC_PORT_CFG2", 0x30818, 0 }, + { "Rx_Polarity_Inv", 28, 4 }, + { "Tx_Polarity_Inv", 24, 4 }, + { "InstanceNum", 22, 2 }, + { "StopOnPerr", 21, 1 }, + { "PatEn", 18, 1 }, + { "MagicEn", 17, 1 }, + { "T5_AEC_PMA_TX_READY", 4, 4 }, + { "T5_AEC_PMA_RX_READY", 0, 4 }, + { "MAC_PORT_PKT_COUNT", 0x3081c, 0 }, + { "tx_sop_count", 24, 8 }, + { "tx_eop_count", 16, 8 }, + { "rx_sop_count", 8, 8 }, + { "rx_eop_count", 0, 8 }, + { "MAC_PORT_CFG4", 0x30820, 0 }, + { "AEC3_RX_WIDTH", 14, 2 }, + { "AEC2_RX_WIDTH", 12, 2 }, + { "AEC1_RX_WIDTH", 10, 2 }, + { "AEC0_RX_WIDTH", 8, 2 }, + { "AEC3_TX_WIDTH", 6, 2 }, + { "AEC2_TX_WIDTH", 4, 2 }, + { "AEC1_TX_WIDTH", 2, 2 }, + { "AEC0_TX_WIDTH", 0, 2 }, + { "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 }, + { "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 }, + { "MAC_PORT_LINK_STATUS", 0x30834, 0 }, + { "an_done", 6, 1 }, + { "align_done", 5, 1 }, + { "block_lock", 4, 1 }, + { "remflt", 3, 1 }, + { "locflt", 2, 1 }, + { "linkup", 1, 1 }, + { "linkdn", 0, 1 }, + { "MAC_PORT_EPIO_DATA0", 0x308c0, 0 }, + { "MAC_PORT_EPIO_DATA1", 0x308c4, 0 }, + { "MAC_PORT_EPIO_DATA2", 0x308c8, 0 }, + { "MAC_PORT_EPIO_DATA3", 0x308cc, 0 }, + { "MAC_PORT_EPIO_OP", 0x308d0, 0 }, + { "Busy", 31, 1 }, + { "Write", 8, 1 }, + { "Address", 0, 8 }, + { "MAC_PORT_WOL_STATUS", 0x308d4, 0 }, + { "MagicDetected", 31, 1 }, + { "PatDetected", 30, 1 }, + { "ClearMagic", 4, 1 }, + { "ClearMatch", 3, 1 }, + { "MatchedFilter", 0, 3 }, + { "MAC_PORT_INT_EN", 0x308d8, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_INT_CAUSE", 0x308dc, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_PERR_INT_EN", 0x308e0, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_ENABLE", 0x308e8, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INJECT", 0x308ec, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MAC_PORT_HSS_CFG0", 0x308f0, 0 }, + { "TXDTS", 31, 1 }, + { "TXCTS", 30, 1 }, + { "TXBTS", 29, 1 }, + { "TXATS", 28, 1 }, + { "TXDOBS", 27, 1 }, + { "TXCOBS", 26, 1 }, + { "TXBOBS", 25, 1 }, + { "TXAOBS", 24, 1 }, + { "HSSREFCLKVALIDA", 20, 1 }, + { "HSSREFCLKVALIDB", 19, 1 }, + { "HSSRESYNCA", 18, 1 }, + { "HSSAVDHI", 17, 1 }, + { "HSSRESYNCB", 16, 1 }, + { "HSSRECCALA", 15, 1 }, + { "HSSRXACMODE", 14, 1 }, + { "HSSRECCALB", 13, 1 }, + { "HSSPLLBYPA", 12, 1 }, + { "HSSPLLBYPB", 11, 1 }, + { "HSSPDWNPLLA", 10, 1 }, + { "HSSPDWNPLLB", 9, 1 }, + { "HSSVCOSELA", 8, 1 }, + { "HSSVCOSELB", 7, 1 }, + { "HSSCALCOMP", 6, 1 }, + { "HSSCALENAB", 5, 1 }, + { "HSSEXTC16SEL", 4, 1 }, + { "MAC_PORT_HSS_CFG1", 0x308f4, 0 }, + { "RXACONFIGSEL", 30, 2 }, + { "RXAQUIET", 29, 1 }, + { "RXAREFRESH", 28, 1 }, + { "RXBCONFIGSEL", 26, 2 }, + { "RXBQUIET", 25, 1 }, + { "RXBREFRESH", 24, 1 }, + { "RXCCONFIGSEL", 22, 2 }, + { "RXCQUIET", 21, 1 }, + { "RXCREFRESH", 20, 1 }, + { "RXDCONFIGSEL", 18, 2 }, + { "RXDQUIET", 17, 1 }, + { "RXDREFRESH", 16, 1 }, + { "TXACONFIGSEL", 14, 2 }, + { "TXAQUIET", 13, 1 }, + { "TXAREFRESH", 12, 1 }, + { "TXBCONFIGSEL", 10, 2 }, + { "TXBQUIET", 9, 1 }, + { "TXBREFRESH", 8, 1 }, + { "TXCCONFIGSEL", 6, 2 }, + { "TXCQUIET", 5, 1 }, + { "TXCREFRESH", 4, 1 }, + { "TXDCONFIGSEL", 2, 2 }, + { "TXDQUIET", 1, 1 }, + { "TXDREFRESH", 0, 1 }, + { "MAC_PORT_HSS_CFG2", 0x308f8, 0 }, + { "RXAASSTCLK", 31, 1 }, + { "T5RXAPRBSRST", 30, 1 }, + { "RXBASSTCLK", 29, 1 }, + { "T5RXBPRBSRST", 28, 1 }, + { "RXCASSTCLK", 27, 1 }, + { "T5RXCPRBSRST", 26, 1 }, + { "RXDASSTCLK", 25, 1 }, + { "T5RXDPRBSRST", 24, 1 }, + { "RXDDATASYNC", 23, 1 }, + { "RXCDATASYNC", 22, 1 }, + { "RXBDATASYNC", 21, 1 }, + { "RXADATASYNC", 20, 1 }, + { "RXDEARLYIN", 19, 1 }, + { "RXDLATEIN", 18, 1 }, + { "RXDPHSLOCK", 17, 1 }, + { "RXDPHSDNIN", 16, 1 }, + { "RXDPHSUPIN", 15, 1 }, + { "RXCEARLYIN", 14, 1 }, + { "RXCLATEIN", 13, 1 }, + { "RXCPHSLOCK", 12, 1 }, + { "RXCPHSDNIN", 11, 1 }, + { "RXCPHSUPIN", 10, 1 }, + { "RXBEARLYIN", 9, 1 }, + { "RXBLATEIN", 8, 1 }, + { "RXBPHSLOCK", 7, 1 }, + { "RXBPHSDNIN", 6, 1 }, + { "RXBPHSUPIN", 5, 1 }, + { "RXAEARLYIN", 4, 1 }, + { "RXALATEIN", 3, 1 }, + { "RXAPHSLOCK", 2, 1 }, + { "RXAPHSDNIN", 1, 1 }, + { "RXAPHSUPIN", 0, 1 }, + { "MAC_PORT_HSS_CFG3", 0x308fc, 0 }, + { "HSSCALSSTN", 25, 3 }, + { "HSSCALSSTP", 22, 3 }, + { "HSSVBOOSTDIVB", 19, 3 }, + { "HSSVBOOSTDIVA", 16, 3 }, + { "HSSPLLCONFIGB", 8, 8 }, + { "HSSPLLCONFIGA", 0, 8 }, + { "MAC_PORT_HSS_CFG4", 0x30900, 0 }, + { "HSSDIVSELA", 9, 9 }, + { "HSSDIVSELB", 0, 9 }, + { "MAC_PORT_HSS_STATUS", 0x30904, 0 }, + { "RXDPRBSSYNC", 15, 1 }, + { "RXCPRBSSYNC", 14, 1 }, + { "RXBPRBSSYNC", 13, 1 }, + { "RXAPRBSSYNC", 12, 1 }, + { "RXDPRBSERR", 11, 1 }, + { "RXCPRBSERR", 10, 1 }, + { "RXBPRBSERR", 9, 1 }, + { "RXAPRBSERR", 8, 1 }, + { "RXDSIGDET", 7, 1 }, + { "RXCSIGDET", 6, 1 }, + { "RXBSIGDET", 5, 1 }, + { "RXASIGDET", 4, 1 }, + { "HSSPLLLOCKB", 3, 1 }, + { "HSSPLLLOCKA", 2, 1 }, + { "HSSPRTREADYB", 1, 1 }, + { "HSSPRTREADYA", 0, 1 }, + { "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 }, + { "RXAQUIET_STATUS", 15, 1 }, + { "RXAREFRESH_STATUS", 14, 1 }, + { "RXBQUIET_STATUS", 13, 1 }, + { "RXBREFRESH_STATUS", 12, 1 }, + { "RXCQUIET_STATUS", 11, 1 }, + { "RXCREFRESH_STATUS", 10, 1 }, + { "RXDQUIET_STATUS", 9, 1 }, + { "RXDREFRESH_STATUS", 8, 1 }, + { "TXAQUIET_STATUS", 7, 1 }, + { "TXAREFRESH_STATUS", 6, 1 }, + { "TXBQUIET_STATUS", 5, 1 }, + { "TXBREFRESH_STATUS", 4, 1 }, + { "TXCQUIET_STATUS", 3, 1 }, + { "TXCREFRESH_STATUS", 2, 1 }, + { "TXDQUIET_STATUS", 1, 1 }, + { "TXDREFRESH_STATUS", 0, 1 }, + { "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 }, + { "MAC_PORT_HSS_PL_CTL", 0x30910, 0 }, + { "TOV", 16, 8 }, + { "TSU", 8, 8 }, + { "IPW", 0, 8 }, + { "MAC_PORT_RUNT_FRAME", 0x30914, 0 }, + { "runtclear", 16, 1 }, + { "runt", 0, 16 }, + { "MAC_PORT_EEE_STATUS", 0x30918, 0 }, + { "eee_tx_10g_state", 10, 2 }, + { "eee_rx_10g_state", 8, 2 }, + { "eee_tx_1g_state", 6, 2 }, + { "eee_rx_1g_state", 4, 2 }, + { "pma_rx_refresh", 3, 1 }, + { "pma_rx_quiet", 2, 1 }, + { "pma_tx_refresh", 1, 1 }, + { "pma_tx_quiet", 0, 1 }, + { "MAC_PORT_CGEN", 0x3091c, 0 }, + { "CGEN", 8, 1 }, + { "sd7_CGEN", 7, 1 }, + { "sd6_CGEN", 6, 1 }, + { "sd5_CGEN", 5, 1 }, + { "sd4_CGEN", 4, 1 }, + { "sd3_CGEN", 3, 1 }, + { "sd2_CGEN", 2, 1 }, + { "sd1_CGEN", 1, 1 }, + { "sd0_CGEN", 0, 1 }, + { "MAC_PORT_CGEN_MTIP", 0x30920, 0 }, + { "MACSEG5_CGEN", 11, 1 }, + { "PCSSEG5_CGEN", 10, 1 }, + { "MACSEG4_CGEN", 9, 1 }, + { "PCSSEG4_CGEN", 8, 1 }, + { "MACSEG3_CGEN", 7, 1 }, + { "PCSSEG3_CGEN", 6, 1 }, + { "MACSEG2_CGEN", 5, 1 }, + { "PCSSEG2_CGEN", 4, 1 }, + { "MACSEG1_CGEN", 3, 1 }, + { "PCSSEG1_CGEN", 2, 1 }, + { "MACSEG0_CGEN", 1, 1 }, + { "PCSSEG0_CGEN", 0, 1 }, + { "MAC_PORT_TX_TS_ID", 0x30924, 0 }, + { "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 }, + { "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 }, + { "MAC_PORT_EEE_CTL", 0x30930, 0 }, + { "EEE_CTRL", 2, 30 }, + { "TICK_START", 1, 1 }, + { "En", 0, 1 }, + { "MAC_PORT_EEE_TX_CTL", 0x30934, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_ACTIVE", 3, 1 }, + { "LPI_TXHOLD", 2, 1 }, + { "LPI_REQ", 1, 1 }, + { "EEE_TX_RESET", 0, 1 }, + { "MAC_PORT_EEE_RX_CTL", 0x30938, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_IND", 1, 1 }, + { "EEE_RX_RESET", 0, 1 }, + { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 }, + { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 }, + { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 }, + { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 }, + { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 }, + { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 }, + { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 }, + { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 }, + { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 }, + { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 }, + { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 }, + { "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 }, + { "wake_cnt_clr", 16, 1 }, + { "wake_cnt", 0, 16 }, + { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 }, + { "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 }, + { "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 }, + { "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 }, + { "MAC_PORT_PTP_SUM_LO", 0x30990, 0 }, + { "MAC_PORT_PTP_SUM_HI", 0x30994, 0 }, + { "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 }, + { "Y", 16, 16 }, + { "X", 0, 16 }, + { "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 }, + { "Y_TICK", 16, 16 }, + { "X_TICK", 0, 16 }, + { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 }, + { "B", 16, 16 }, + { "A", 0, 16 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 }, + { "MAC_PORT_PTP_CFG", 0x309ac, 0 }, + { "FRZ", 18, 1 }, + { "OFFSER_ADJUST_SIGN", 17, 1 }, + { "ADD_OFFSET", 16, 1 }, + { "CYCLE1", 8, 8 }, + { "Q", 0, 8 }, + { "MAC_PORT_MTIP_REVISION", 0x30a00, 0 }, + { "CUSTREV", 16, 16 }, + { "VER", 8, 8 }, + { "REV", 0, 8 }, + { "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 }, + { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 }, + { "TX_FLUSH", 22, 1 }, + { "RX_SFD_ANY", 21, 1 }, + { "PAUSE_PFC_COMP", 20, 1 }, + { "PFC_MODE", 19, 1 }, + { "RS_COL_CNT_EXT", 18, 1 }, + { "NO_LGTH_CHECK", 17, 1 }, + { "SEND_IDLE", 16, 1 }, + { "PHY_TXENA", 15, 1 }, + { "RX_ERR_DISC", 14, 1 }, + { "CMD_FRAME_ENA", 13, 1 }, + { "SW_RESET", 12, 1 }, + { "TX_PAD_EN", 11, 1 }, + { "LOOPBACK_EN", 10, 1 }, + { "TX_ADDR_INS", 9, 1 }, + { "PAUSE_IGNORE", 8, 1 }, + { "PAUSE_FWD", 7, 1 }, + { "CRC_FWD", 6, 1 }, + { "PAD_EN", 5, 1 }, + { "PROMIS_EN", 4, 1 }, + { "WAN_MODE", 3, 1 }, + { "RX_ENA", 1, 1 }, + { "TX_ENA", 0, 1 }, + { "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 }, + { "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 }, + { "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 }, + { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 }, + { "ENABLE", 8, 1 }, + { "ADDR", 0, 6 }, + { "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 }, + { "TS_AVAIL", 3, 1 }, + { "PHY_LOS", 2, 1 }, + { "RX_REM_FAULT", 1, 1 }, + { "RX_LOC_FAULT", 0, 1 }, + { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 }, + { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 }, + { "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 }, + { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 }, + { "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 }, + { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 }, + { "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 }, + { "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 }, + { "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 }, + { "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 }, + { "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 }, + { "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 }, + { "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 }, + { "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 }, + { "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 }, + { "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 }, + { "MAC_PORT_IFOUTERRORS", 0x30af8, 0 }, + { "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 }, + { "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 }, + { "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 }, + { "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 }, + { "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 }, + { "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 }, + { "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 }, + { "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 }, + { "MAC_PORT_IFINERRORS", 0x30b90, 0 }, + { "MAC_PORT_IFINERRORSHI", 0x30b94, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 }, + { "MAC_PORT_MTIP_SGMII_CONTROL", 0x30d00, 0 }, + { "Reset", 15, 1 }, + { "Loopback", 14, 1 }, + { "sppedsel1", 13, 1 }, + { "AN_EN", 12, 1 }, + { "PWRDWN", 11, 1 }, + { "Isolate", 10, 1 }, + { "AN_RESTART", 9, 1 }, + { "DPLX", 8, 1 }, + { "CollisionTest", 7, 1 }, + { "SpeedSel0", 6, 1 }, + { "MAC_PORT_MTIP_SGMII_STATUS", 0x30d04, 0 }, + { "100BaseT4", 15, 1 }, + { "100BaseXFullDplx", 14, 1 }, + { "100BaseXHalfDplx", 13, 1 }, + { "10MbpsFullDplx", 12, 1 }, + { "10MbpsHalfDplx", 11, 1 }, + { "100BaseT2FullDplx", 10, 1 }, + { "100BaseT2HalfDplx", 9, 1 }, + { "ExtdStatus", 8, 1 }, + { "AN_Complete", 5, 1 }, + { "SGMII_REM_FAULT", 4, 1 }, + { "AN_Ability", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "JabberDetect", 1, 1 }, + { "ExtdCapability", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x30d08, 0 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x30d0c, 0 }, + { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x30d10, 0 }, + { "NP", 15, 1 }, + { "ACK", 14, 1 }, + { "RF2", 13, 1 }, + { "RF1", 12, 1 }, + { "PS2", 8, 1 }, + { "PS1", 7, 1 }, + { "HD", 6, 1 }, + { "FD", 5, 1 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x30d14, 0 }, + { "CuLinkStatus", 15, 1 }, + { "ACK", 14, 1 }, + { "CuDplxStatus", 12, 1 }, + { "CuSpeed", 10, 2 }, + { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x30d18, 0 }, + { "PgRcvd", 1, 1 }, + { "RealTimePgRcvd", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x30d1c, 0 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x30d20, 0 }, + { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x30d3c, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x30d48, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x30d4c, 0 }, + { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x30d50, 0 }, + { "SGMII_PCS_ENABLE", 5, 1 }, + { "SGMII_HDUPLEX", 4, 1 }, + { "SGMII_SPEED", 2, 2 }, + { "USE_SGMII_AN", 1, 1 }, + { "SGMII_ENA", 0, 1 }, + { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x31200, 0 }, + { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x31204, 0 }, + { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x31208, 0 }, + { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3120c, 0 }, + { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x31220, 0 }, + { "MAC_PORT_MTIP_VL_INTVL", 0x31240, 0 }, + { "VL_INTVL", 1, 1 }, + { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x31600, 0 }, + { "CLK_DIV", 7, 9 }, + { "CL45_EN", 6, 1 }, + { "disable_preamble", 5, 1 }, + { "mdio_hold_time", 2, 3 }, + { "mdio_read_err", 1, 1 }, + { "mdio_busy", 0, 1 }, + { "MAC_PORT_MTIP_MDIO_COMMAND", 0x31604, 0 }, + { "read", 15, 1 }, + { "read_incr", 14, 1 }, + { "port_addr", 5, 5 }, + { "dev_addr", 0, 5 }, + { "MAC_PORT_MTIP_MDIO_DATA", 0x31608, 0 }, + { "readbusy", 31, 1 }, + { "data_word", 0, 16 }, + { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3160c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_0", 0x31a00, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_1", 0x31a04, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_2", 0x31a08, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_3", 0x31a0c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_4", 0x31a10, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_5", 0x31a14, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_6", 0x31a18, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_7", 0x31a1c, 0 }, + { "MAC_PORT_MTIP_PCS_CTL", 0x31e00, 0 }, + { "RESET", 15, 1 }, + { "LPBK", 14, 1 }, + { "SPEED_SEL1", 13, 1 }, + { "LP_MODE", 11, 1 }, + { "SPEED_SEL0", 6, 1 }, + { "SPEED", 2, 4 }, + { "MAC_PORT_MTIP_PCS_STATUS1", 0x31e04, 0 }, + { "FaultDet", 7, 1 }, + { "rx_link_status", 2, 1 }, + { "LoPwrAbl", 1, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x31e08, 0 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x31e0c, 0 }, + { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x31e10, 0 }, + { "100G", 8, 1 }, + { "40G", 7, 1 }, + { "10BASE_TL", 1, 1 }, + { "10G", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x31e14, 0 }, + { "TC", 6, 1 }, + { "DTEXS", 5, 1 }, + { "PHYXS", 4, 1 }, + { "PCS", 3, 1 }, + { "WIS", 2, 1 }, + { "PMD_PMA", 1, 1 }, + { "CL22", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x31e18, 0 }, + { "VendDev2", 15, 1 }, + { "VendDev1", 14, 1 }, + { "CL22EXT", 13, 1 }, + { "MAC_PORT_MTIP_PCS_CTL2", 0x31e1c, 0 }, + { "MAC_PORT_MTIP_PCS_STATUS2", 0x31e20, 0 }, + { "Device", 15, 1 }, + { "TxFault", 7, 1 }, + { "RxFault", 6, 1 }, + { "100BASE_R", 5, 1 }, + { "40GBASE_R", 4, 1 }, + { "10GBASE_T", 3, 1 }, + { "10GBASE_W", 2, 1 }, + { "10GBASE_X", 1, 1 }, + { "10GBASE_R", 0, 1 }, + { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x31e38, 0 }, + { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x31e3c, 0 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x31e80, 0 }, + { "RxLinkStatus", 12, 1 }, + { "RESEREVED", 4, 8 }, + { "10GPRBS9", 3, 1 }, + { "10GPRBS31", 2, 1 }, + { "HiBER", 1, 1 }, + { "blocklock", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x31e84, 0 }, + { "blocklockLL", 15, 1 }, + { "HiBERLH", 14, 1 }, + { "HiBERCount", 8, 6 }, + { "ErrBlkCnt", 0, 8 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x31e88, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x31e8c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x31e90, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x31e94, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x31e98, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x31e9c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x31ea0, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x31ea4, 0 }, + { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x31ea8, 0 }, + { "TXPRBS9", 6, 1 }, + { "RXPRBS31", 5, 1 }, + { "TXPRBS31", 4, 1 }, + { "TxTestPatEn", 3, 1 }, + { "RxTestPatEn", 2, 1 }, + { "TestPatSel", 1, 1 }, + { "DataPatSel", 0, 1 }, + { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x31eac, 0 }, + { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x31eb0, 0 }, + { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x31eb4, 0 }, + { "HiCountPrsnt", 15, 1 }, + { "BLOCK_CNT_HI", 0, 14 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x31ec8, 0 }, + { "alignstatus", 12, 1 }, + { "Lane7", 7, 1 }, + { "Lane6", 6, 1 }, + { "Lane5", 5, 1 }, + { "Lane4", 4, 1 }, + { "Lane3", 3, 1 }, + { "Lane2", 2, 1 }, + { "Lane1", 1, 1 }, + { "Lane0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x31ecc, 0 }, + { "Lane19", 11, 1 }, + { "Lane18", 10, 1 }, + { "Lane17", 9, 1 }, + { "Lane16", 8, 1 }, + { "Lane15", 7, 1 }, + { "Lane14", 6, 1 }, + { "Lane13", 5, 1 }, + { "Lane12", 4, 1 }, + { "Lane11", 3, 1 }, + { "Lane10", 2, 1 }, + { "Lane9", 1, 1 }, + { "Lane8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x31ed0, 0 }, + { "AMLOCK7", 7, 1 }, + { "AMLOCK6", 6, 1 }, + { "AMLOCK5", 5, 1 }, + { "AMLOCK4", 4, 1 }, + { "AMLOCK3", 3, 1 }, + { "AMLOCK2", 2, 1 }, + { "AMLOCK1", 1, 1 }, + { "AMLOCK0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x31ed4, 0 }, + { "AMLOCK19", 11, 1 }, + { "AMLOCK18", 10, 1 }, + { "AMLOCK17", 9, 1 }, + { "AMLOCK16", 8, 1 }, + { "AMLOCK15", 7, 1 }, + { "AMLOCK14", 6, 1 }, + { "AMLOCK13", 5, 1 }, + { "AMLOCK12", 4, 1 }, + { "AMLOCK11", 3, 1 }, + { "AMLOCK10", 2, 1 }, + { "AMLOCK9", 1, 1 }, + { "AMLOCK8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x31f68, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x31f6c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x31f70, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x31f74, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x31f78, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x31f7c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x31f80, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x31f84, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x31f88, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x31f8c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x31f90, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x31f94, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x31f98, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x31f9c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x31fa0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x31fa4, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x31fa8, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x31fac, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x31fb0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x31fb4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x31fb8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x31fbc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x31fc0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x31fc4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x31fc8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x31fcc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x31fd0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x31fd4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x31fd8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x31fdc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x31fe0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x31fe4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x31fe8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x31fec, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x31ff0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x31ff4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x31ff8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x31ffc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x32000, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x32004, 0 }, + { "MAC_PORT_BEAN_CTL", 0x32200, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS", 0x32204, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0", 0x32208, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1", 0x3220c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2", 0x32210, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0", 0x32214, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1", 0x32218, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3221c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT", 0x32220, 0 }, + { "MAC_PORT_BEAN_XNP_0", 0x32224, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1", 0x32228, 0 }, + { "MAC_PORT_BEAN_XNP_2", 0x3222c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0", 0x32230, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1", 0x32234, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2", 0x32238, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS", 0x3223c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE1", 0x32240, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE1", 0x32244, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x32248, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3224c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x32250, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x32254, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x32258, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3225c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x32260, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE1", 0x32264, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE1", 0x32268, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3226c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x32270, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x32274, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x32278, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3227c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE2", 0x32280, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE2", 0x32284, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x32288, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3228c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x32290, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x32294, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x32298, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3229c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x322a0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE2", 0x322a4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE2", 0x322a8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE2", 0x322ac, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x322b0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x322b4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x322b8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x322bc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE3", 0x322c0, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE3", 0x322c4, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x322c8, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x322cc, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x322d0, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x322d4, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x322d8, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x322dc, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x322e0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE3", 0x322e4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE3", 0x322e8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE3", 0x322ec, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x322f0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x322f4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x322f8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x322fc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_FEC_KR_CONTROL", 0x32600, 0 }, + { "enable_tr", 1, 1 }, + { "restart_tr", 0, 1 }, + { "MAC_PORT_FEC_KR_STATUS", 0x32604, 0 }, + { "fecKRsigdet", 15, 1 }, + { "train_fail", 3, 1 }, + { "startup_status", 2, 1 }, + { "frame_lock", 1, 1 }, + { "rx_status", 0, 1 }, + { "MAC_PORT_FEC_KR_LP_COEFF", 0x32608, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LP_STAT", 0x3260c, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_COEFF", 0x32610, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_STAT", 0x32614, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_ABILITY", 0x32618, 0 }, + { "fec_ind_ability", 1, 1 }, + { "ability", 0, 1 }, + { "MAC_PORT_FEC_CONTROL", 0x3261c, 0 }, + { "fec_en_err_ind", 1, 1 }, + { "fec_en", 0, 1 }, + { "MAC_PORT_FEC_STATUS", 0x32620, 0 }, + { "FEC_LOCKED_100", 1, 1 }, + { "FEC_LOCKED", 0, 1 }, + { "MAC_PORT_FEC_CERR_CNT_0", 0x32624, 0 }, + { "MAC_PORT_FEC_CERR_CNT_1", 0x32628, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_0", 0x3262c, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_1", 0x32630, 0 }, + { "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 }, + { "T5_AE0_RXSTAT_RDY", 15, 1 }, + { "T5_AE0_RXSTAT_C2", 4, 2 }, + { "T5_AE0_RXSTAT_C1", 2, 2 }, + { "T5_AE0_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE", 0x32a10, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 }, + { "T5_AE1_RXSTAT_RDY", 15, 1 }, + { "T5_AE1_RXSTAT_C2", 4, 2 }, + { "T5_AE1_RXSTAT_C1", 2, 2 }, + { "T5_AE1_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 }, + { "T5_AE2_RXSTAT_RDY", 15, 1 }, + { "T5_AE2_RXSTAT_C2", 4, 2 }, + { "T5_AE2_RXSTAT_C1", 2, 2 }, + { "T5_AE2_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 }, + { "T5_AE3_RXSTAT_RDY", 15, 1 }, + { "T5_AE3_RXSTAT_C2", 4, 2 }, + { "T5_AE3_RXSTAT_C1", 2, 2 }, + { "T5_AE3_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_TX_DIS", 0x32a80, 0 }, + { "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 }, + { "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 }, + { "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 }, + { "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 }, + { "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 }, + { "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 }, + { "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 }, + { "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_0", 0x32b10, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_1", 0x32b30, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_2", 0x32b50, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_3", 0x32b70, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 }, + { "MAC_PORT_BANDGAP_CONTROL", 0x3382c, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x33880, 0 }, + { "RCCTL1", 5, 1 }, + { "RCCTL0", 4, 1 }, + { "RCAMP1", 3, 1 }, + { "RCAMP0", 2, 1 }, + { "RCAMPEN", 1, 1 }, + { "RCRST", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x33884, 0 }, + { "RCERR", 1, 1 }, + { "RCCOMP", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x33888, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3388c, 0 }, + { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 }, + { "LBIST", 7, 1 }, + { "LOGICTEST", 6, 1 }, + { "MAVDHI", 5, 1 }, + { "AUXEN", 4, 1 }, + { "JTAGMD", 3, 1 }, + { "RXACMODE", 2, 1 }, + { "HSSACJPC", 1, 1 }, + { "HSSACJAC", 0, 1 }, + { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 }, + { "REFVALIDD", 6, 1 }, + { "REFVALIDC", 5, 1 }, + { "REFVALIDB", 4, 1 }, + { "REFVALIDA", 3, 1 }, + { "REFSELRESET", 2, 1 }, + { "SOFTRESET", 1, 1 }, + { "MACROTEST", 0, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 }, + { "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 }, + { "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x33030, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33060, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33064, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33068, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33070, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33074, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33088, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3308c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x33090, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x33094, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x33098, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x33130, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33160, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33164, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33168, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33170, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33174, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33188, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3318c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x33190, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x33194, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x33198, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x33430, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33460, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33464, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33468, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33470, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33474, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33488, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3348c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x33490, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x33494, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x33498, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x33530, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33560, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33564, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33568, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33570, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33574, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33588, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3358c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x33590, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x33594, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x33598, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x33930, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33960, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33964, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33968, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33970, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33974, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33988, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3398c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x33990, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x33994, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x33998, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 }, + { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x33238, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x33240, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3324c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3325c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33260, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33264, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x33284, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x33288, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3328c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x33290, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x33294, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x33298, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 }, + { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x332c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKA_DFE_H1", 0x332c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H2", 0x332c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_H3", 0x332cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H4", 0x332d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H5", 0x332d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x332d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x332dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x332e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H12", 0x332e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x332f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x33338, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x33340, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3334c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3335c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33360, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33364, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x33384, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x33388, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3338c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x33390, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x33394, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x33398, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 }, + { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x333c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKB_DFE_H1", 0x333c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H2", 0x333c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_H3", 0x333cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H4", 0x333d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H5", 0x333d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x333d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x333dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x333e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H12", 0x333e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x333f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x33638, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x33640, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3364c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3365c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33660, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33664, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x33684, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x33688, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3368c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x33690, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x33694, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x33698, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 }, + { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x336c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKC_DFE_H1", 0x336c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H2", 0x336c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_H3", 0x336cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H4", 0x336d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H5", 0x336d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x336d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x336dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x336e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H12", 0x336e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x336f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x33738, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x33740, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3374c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3375c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33760, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33764, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x33784, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x33788, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3378c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x33790, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x33794, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x33798, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 }, + { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x337c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKD_DFE_H1", 0x337c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H2", 0x337c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_H3", 0x337cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H4", 0x337d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H5", 0x337d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x337d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x337dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x337e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H12", 0x337e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x337f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x33a38, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x33a40, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x33a4c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x33a5c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33a60, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33a64, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x33a84, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x33a88, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x33a8c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x33a90, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x33a94, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x33a98, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 }, + { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x33ac0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x33ac4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x33ac8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x33acc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x33ad0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x33ad4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x33ad8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x33adc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x33ae0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x33ae4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x33af8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_CFG", 0x34800, 0 }, + { "MAC_Clk_Sel", 29, 3 }, + { "SinkTx", 27, 1 }, + { "SinkTxOnLinkDown", 26, 1 }, + { "LoopNoFwd", 24, 1 }, + { "Smux_Rx_Loop", 19, 1 }, + { "Rx_Lane_Swap", 18, 1 }, + { "Tx_Lane_Swap", 17, 1 }, + { "Signal_Det", 14, 1 }, + { "SmuxTxSel", 9, 1 }, + { "SmuxRxSel", 8, 1 }, + { "PortSpeed", 4, 2 }, + { "Rx_Byte_Swap", 3, 1 }, + { "Tx_Byte_Swap", 2, 1 }, + { "Port_Sel", 0, 1 }, + { "MAC_PORT_RESET_CTRL", 0x34804, 0 }, + { "TWGDSK_HSSC16B", 31, 1 }, + { "EEE_RESET", 30, 1 }, + { "PTP_TIMER", 29, 1 }, + { "MtipRefReset", 28, 1 }, + { "MtipTxffReset", 27, 1 }, + { "MtipRxffReset", 26, 1 }, + { "MtipRegReset", 25, 1 }, + { "AEC3Reset", 23, 1 }, + { "AEC2Reset", 22, 1 }, + { "AEC1Reset", 21, 1 }, + { "AEC0Reset", 20, 1 }, + { "AET3Reset", 19, 1 }, + { "AET2Reset", 18, 1 }, + { "AET1Reset", 17, 1 }, + { "AET0Reset", 16, 1 }, + { "TXIF_Reset", 12, 1 }, + { "RXIF_Reset", 11, 1 }, + { "AuxExt_Reset", 10, 1 }, + { "MtipSd3TxRst", 9, 1 }, + { "MtipSd2TxRst", 8, 1 }, + { "MtipSd1TxRst", 7, 1 }, + { "MtipSd0TxRst", 6, 1 }, + { "MtipSd3RxRst", 5, 1 }, + { "MtipSd2RxRst", 4, 1 }, + { "MtipSd1RxRst", 3, 1 }, + { "WOL_Reset", 2, 1 }, + { "MtipSd0RxRst", 1, 1 }, + { "HSS_Reset", 0, 1 }, + { "MAC_PORT_LED_CFG", 0x34808, 0 }, + { "Led1_Cfg", 5, 3 }, + { "Led1_Polarity_Inv", 4, 1 }, + { "Led0_Cfg", 1, 3 }, + { "Led0_Polarity_Inv", 0, 1 }, + { "MAC_PORT_LED_COUNTHI", 0x3480c, 0 }, + { "MAC_PORT_LED_COUNTLO", 0x34810, 0 }, + { "MAC_PORT_CFG3", 0x34814, 0 }, + { "FPGA_PTP_PORT", 26, 2 }, + { "FCSDisCtrl", 25, 1 }, + { "SigDetCtrl", 24, 1 }, + { "tx_lane", 23, 1 }, + { "rx_lane", 22, 1 }, + { "se_clr", 21, 1 }, + { "an_ena", 17, 4 }, + { "sd_rx_clk_ena", 13, 4 }, + { "sd_tx_clk_ena", 9, 4 }, + { "SGMIISEL", 8, 1 }, + { "HSSPLLSEL", 4, 4 }, + { "HSSC16C20SEL", 0, 4 }, + { "MAC_PORT_CFG2", 0x34818, 0 }, + { "Rx_Polarity_Inv", 28, 4 }, + { "Tx_Polarity_Inv", 24, 4 }, + { "InstanceNum", 22, 2 }, + { "StopOnPerr", 21, 1 }, + { "PatEn", 18, 1 }, + { "MagicEn", 17, 1 }, + { "T5_AEC_PMA_TX_READY", 4, 4 }, + { "T5_AEC_PMA_RX_READY", 0, 4 }, + { "MAC_PORT_PKT_COUNT", 0x3481c, 0 }, + { "tx_sop_count", 24, 8 }, + { "tx_eop_count", 16, 8 }, + { "rx_sop_count", 8, 8 }, + { "rx_eop_count", 0, 8 }, + { "MAC_PORT_CFG4", 0x34820, 0 }, + { "AEC3_RX_WIDTH", 14, 2 }, + { "AEC2_RX_WIDTH", 12, 2 }, + { "AEC1_RX_WIDTH", 10, 2 }, + { "AEC0_RX_WIDTH", 8, 2 }, + { "AEC3_TX_WIDTH", 6, 2 }, + { "AEC2_TX_WIDTH", 4, 2 }, + { "AEC1_TX_WIDTH", 2, 2 }, + { "AEC0_TX_WIDTH", 0, 2 }, + { "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 }, + { "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 }, + { "MAC_PORT_LINK_STATUS", 0x34834, 0 }, + { "an_done", 6, 1 }, + { "align_done", 5, 1 }, + { "block_lock", 4, 1 }, + { "remflt", 3, 1 }, + { "locflt", 2, 1 }, + { "linkup", 1, 1 }, + { "linkdn", 0, 1 }, + { "MAC_PORT_EPIO_DATA0", 0x348c0, 0 }, + { "MAC_PORT_EPIO_DATA1", 0x348c4, 0 }, + { "MAC_PORT_EPIO_DATA2", 0x348c8, 0 }, + { "MAC_PORT_EPIO_DATA3", 0x348cc, 0 }, + { "MAC_PORT_EPIO_OP", 0x348d0, 0 }, + { "Busy", 31, 1 }, + { "Write", 8, 1 }, + { "Address", 0, 8 }, + { "MAC_PORT_WOL_STATUS", 0x348d4, 0 }, + { "MagicDetected", 31, 1 }, + { "PatDetected", 30, 1 }, + { "ClearMagic", 4, 1 }, + { "ClearMatch", 3, 1 }, + { "MatchedFilter", 0, 3 }, + { "MAC_PORT_INT_EN", 0x348d8, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_INT_CAUSE", 0x348dc, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_PERR_INT_EN", 0x348e0, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_ENABLE", 0x348e8, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INJECT", 0x348ec, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MAC_PORT_HSS_CFG0", 0x348f0, 0 }, + { "TXDTS", 31, 1 }, + { "TXCTS", 30, 1 }, + { "TXBTS", 29, 1 }, + { "TXATS", 28, 1 }, + { "TXDOBS", 27, 1 }, + { "TXCOBS", 26, 1 }, + { "TXBOBS", 25, 1 }, + { "TXAOBS", 24, 1 }, + { "HSSREFCLKVALIDA", 20, 1 }, + { "HSSREFCLKVALIDB", 19, 1 }, + { "HSSRESYNCA", 18, 1 }, + { "HSSAVDHI", 17, 1 }, + { "HSSRESYNCB", 16, 1 }, + { "HSSRECCALA", 15, 1 }, + { "HSSRXACMODE", 14, 1 }, + { "HSSRECCALB", 13, 1 }, + { "HSSPLLBYPA", 12, 1 }, + { "HSSPLLBYPB", 11, 1 }, + { "HSSPDWNPLLA", 10, 1 }, + { "HSSPDWNPLLB", 9, 1 }, + { "HSSVCOSELA", 8, 1 }, + { "HSSVCOSELB", 7, 1 }, + { "HSSCALCOMP", 6, 1 }, + { "HSSCALENAB", 5, 1 }, + { "HSSEXTC16SEL", 4, 1 }, + { "MAC_PORT_HSS_CFG1", 0x348f4, 0 }, + { "RXACONFIGSEL", 30, 2 }, + { "RXAQUIET", 29, 1 }, + { "RXAREFRESH", 28, 1 }, + { "RXBCONFIGSEL", 26, 2 }, + { "RXBQUIET", 25, 1 }, + { "RXBREFRESH", 24, 1 }, + { "RXCCONFIGSEL", 22, 2 }, + { "RXCQUIET", 21, 1 }, + { "RXCREFRESH", 20, 1 }, + { "RXDCONFIGSEL", 18, 2 }, + { "RXDQUIET", 17, 1 }, + { "RXDREFRESH", 16, 1 }, + { "TXACONFIGSEL", 14, 2 }, + { "TXAQUIET", 13, 1 }, + { "TXAREFRESH", 12, 1 }, + { "TXBCONFIGSEL", 10, 2 }, + { "TXBQUIET", 9, 1 }, + { "TXBREFRESH", 8, 1 }, + { "TXCCONFIGSEL", 6, 2 }, + { "TXCQUIET", 5, 1 }, + { "TXCREFRESH", 4, 1 }, + { "TXDCONFIGSEL", 2, 2 }, + { "TXDQUIET", 1, 1 }, + { "TXDREFRESH", 0, 1 }, + { "MAC_PORT_HSS_CFG2", 0x348f8, 0 }, + { "RXAASSTCLK", 31, 1 }, + { "T5RXAPRBSRST", 30, 1 }, + { "RXBASSTCLK", 29, 1 }, + { "T5RXBPRBSRST", 28, 1 }, + { "RXCASSTCLK", 27, 1 }, + { "T5RXCPRBSRST", 26, 1 }, + { "RXDASSTCLK", 25, 1 }, + { "T5RXDPRBSRST", 24, 1 }, + { "RXDDATASYNC", 23, 1 }, + { "RXCDATASYNC", 22, 1 }, + { "RXBDATASYNC", 21, 1 }, + { "RXADATASYNC", 20, 1 }, + { "RXDEARLYIN", 19, 1 }, + { "RXDLATEIN", 18, 1 }, + { "RXDPHSLOCK", 17, 1 }, + { "RXDPHSDNIN", 16, 1 }, + { "RXDPHSUPIN", 15, 1 }, + { "RXCEARLYIN", 14, 1 }, + { "RXCLATEIN", 13, 1 }, + { "RXCPHSLOCK", 12, 1 }, + { "RXCPHSDNIN", 11, 1 }, + { "RXCPHSUPIN", 10, 1 }, + { "RXBEARLYIN", 9, 1 }, + { "RXBLATEIN", 8, 1 }, + { "RXBPHSLOCK", 7, 1 }, + { "RXBPHSDNIN", 6, 1 }, + { "RXBPHSUPIN", 5, 1 }, + { "RXAEARLYIN", 4, 1 }, + { "RXALATEIN", 3, 1 }, + { "RXAPHSLOCK", 2, 1 }, + { "RXAPHSDNIN", 1, 1 }, + { "RXAPHSUPIN", 0, 1 }, + { "MAC_PORT_HSS_CFG3", 0x348fc, 0 }, + { "HSSCALSSTN", 25, 3 }, + { "HSSCALSSTP", 22, 3 }, + { "HSSVBOOSTDIVB", 19, 3 }, + { "HSSVBOOSTDIVA", 16, 3 }, + { "HSSPLLCONFIGB", 8, 8 }, + { "HSSPLLCONFIGA", 0, 8 }, + { "MAC_PORT_HSS_CFG4", 0x34900, 0 }, + { "HSSDIVSELA", 9, 9 }, + { "HSSDIVSELB", 0, 9 }, + { "MAC_PORT_HSS_STATUS", 0x34904, 0 }, + { "RXDPRBSSYNC", 15, 1 }, + { "RXCPRBSSYNC", 14, 1 }, + { "RXBPRBSSYNC", 13, 1 }, + { "RXAPRBSSYNC", 12, 1 }, + { "RXDPRBSERR", 11, 1 }, + { "RXCPRBSERR", 10, 1 }, + { "RXBPRBSERR", 9, 1 }, + { "RXAPRBSERR", 8, 1 }, + { "RXDSIGDET", 7, 1 }, + { "RXCSIGDET", 6, 1 }, + { "RXBSIGDET", 5, 1 }, + { "RXASIGDET", 4, 1 }, + { "HSSPLLLOCKB", 3, 1 }, + { "HSSPLLLOCKA", 2, 1 }, + { "HSSPRTREADYB", 1, 1 }, + { "HSSPRTREADYA", 0, 1 }, + { "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 }, + { "RXAQUIET_STATUS", 15, 1 }, + { "RXAREFRESH_STATUS", 14, 1 }, + { "RXBQUIET_STATUS", 13, 1 }, + { "RXBREFRESH_STATUS", 12, 1 }, + { "RXCQUIET_STATUS", 11, 1 }, + { "RXCREFRESH_STATUS", 10, 1 }, + { "RXDQUIET_STATUS", 9, 1 }, + { "RXDREFRESH_STATUS", 8, 1 }, + { "TXAQUIET_STATUS", 7, 1 }, + { "TXAREFRESH_STATUS", 6, 1 }, + { "TXBQUIET_STATUS", 5, 1 }, + { "TXBREFRESH_STATUS", 4, 1 }, + { "TXCQUIET_STATUS", 3, 1 }, + { "TXCREFRESH_STATUS", 2, 1 }, + { "TXDQUIET_STATUS", 1, 1 }, + { "TXDREFRESH_STATUS", 0, 1 }, + { "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 }, + { "MAC_PORT_HSS_PL_CTL", 0x34910, 0 }, + { "TOV", 16, 8 }, + { "TSU", 8, 8 }, + { "IPW", 0, 8 }, + { "MAC_PORT_RUNT_FRAME", 0x34914, 0 }, + { "runtclear", 16, 1 }, + { "runt", 0, 16 }, + { "MAC_PORT_EEE_STATUS", 0x34918, 0 }, + { "eee_tx_10g_state", 10, 2 }, + { "eee_rx_10g_state", 8, 2 }, + { "eee_tx_1g_state", 6, 2 }, + { "eee_rx_1g_state", 4, 2 }, + { "pma_rx_refresh", 3, 1 }, + { "pma_rx_quiet", 2, 1 }, + { "pma_tx_refresh", 1, 1 }, + { "pma_tx_quiet", 0, 1 }, + { "MAC_PORT_CGEN", 0x3491c, 0 }, + { "CGEN", 8, 1 }, + { "sd7_CGEN", 7, 1 }, + { "sd6_CGEN", 6, 1 }, + { "sd5_CGEN", 5, 1 }, + { "sd4_CGEN", 4, 1 }, + { "sd3_CGEN", 3, 1 }, + { "sd2_CGEN", 2, 1 }, + { "sd1_CGEN", 1, 1 }, + { "sd0_CGEN", 0, 1 }, + { "MAC_PORT_CGEN_MTIP", 0x34920, 0 }, + { "MACSEG5_CGEN", 11, 1 }, + { "PCSSEG5_CGEN", 10, 1 }, + { "MACSEG4_CGEN", 9, 1 }, + { "PCSSEG4_CGEN", 8, 1 }, + { "MACSEG3_CGEN", 7, 1 }, + { "PCSSEG3_CGEN", 6, 1 }, + { "MACSEG2_CGEN", 5, 1 }, + { "PCSSEG2_CGEN", 4, 1 }, + { "MACSEG1_CGEN", 3, 1 }, + { "PCSSEG1_CGEN", 2, 1 }, + { "MACSEG0_CGEN", 1, 1 }, + { "PCSSEG0_CGEN", 0, 1 }, + { "MAC_PORT_TX_TS_ID", 0x34924, 0 }, + { "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 }, + { "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 }, + { "MAC_PORT_EEE_CTL", 0x34930, 0 }, + { "EEE_CTRL", 2, 30 }, + { "TICK_START", 1, 1 }, + { "En", 0, 1 }, + { "MAC_PORT_EEE_TX_CTL", 0x34934, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_ACTIVE", 3, 1 }, + { "LPI_TXHOLD", 2, 1 }, + { "LPI_REQ", 1, 1 }, + { "EEE_TX_RESET", 0, 1 }, + { "MAC_PORT_EEE_RX_CTL", 0x34938, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_IND", 1, 1 }, + { "EEE_RX_RESET", 0, 1 }, + { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 }, + { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 }, + { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 }, + { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 }, + { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 }, + { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 }, + { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 }, + { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 }, + { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 }, + { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 }, + { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 }, + { "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 }, + { "wake_cnt_clr", 16, 1 }, + { "wake_cnt", 0, 16 }, + { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 }, + { "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 }, + { "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 }, + { "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 }, + { "MAC_PORT_PTP_SUM_LO", 0x34990, 0 }, + { "MAC_PORT_PTP_SUM_HI", 0x34994, 0 }, + { "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 }, + { "Y", 16, 16 }, + { "X", 0, 16 }, + { "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 }, + { "Y_TICK", 16, 16 }, + { "X_TICK", 0, 16 }, + { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 }, + { "B", 16, 16 }, + { "A", 0, 16 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 }, + { "MAC_PORT_PTP_CFG", 0x349ac, 0 }, + { "FRZ", 18, 1 }, + { "OFFSER_ADJUST_SIGN", 17, 1 }, + { "ADD_OFFSET", 16, 1 }, + { "CYCLE1", 8, 8 }, + { "Q", 0, 8 }, + { "MAC_PORT_MTIP_REVISION", 0x34a00, 0 }, + { "CUSTREV", 16, 16 }, + { "VER", 8, 8 }, + { "REV", 0, 8 }, + { "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 }, + { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 }, + { "TX_FLUSH", 22, 1 }, + { "RX_SFD_ANY", 21, 1 }, + { "PAUSE_PFC_COMP", 20, 1 }, + { "PFC_MODE", 19, 1 }, + { "RS_COL_CNT_EXT", 18, 1 }, + { "NO_LGTH_CHECK", 17, 1 }, + { "SEND_IDLE", 16, 1 }, + { "PHY_TXENA", 15, 1 }, + { "RX_ERR_DISC", 14, 1 }, + { "CMD_FRAME_ENA", 13, 1 }, + { "SW_RESET", 12, 1 }, + { "TX_PAD_EN", 11, 1 }, + { "LOOPBACK_EN", 10, 1 }, + { "TX_ADDR_INS", 9, 1 }, + { "PAUSE_IGNORE", 8, 1 }, + { "PAUSE_FWD", 7, 1 }, + { "CRC_FWD", 6, 1 }, + { "PAD_EN", 5, 1 }, + { "PROMIS_EN", 4, 1 }, + { "WAN_MODE", 3, 1 }, + { "RX_ENA", 1, 1 }, + { "TX_ENA", 0, 1 }, + { "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 }, + { "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 }, + { "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 }, + { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 }, + { "ENABLE", 8, 1 }, + { "ADDR", 0, 6 }, + { "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 }, + { "TS_AVAIL", 3, 1 }, + { "PHY_LOS", 2, 1 }, + { "RX_REM_FAULT", 1, 1 }, + { "RX_LOC_FAULT", 0, 1 }, + { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 }, + { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 }, + { "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 }, + { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 }, + { "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 }, + { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 }, + { "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 }, + { "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 }, + { "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 }, + { "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 }, + { "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 }, + { "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 }, + { "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 }, + { "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 }, + { "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 }, + { "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 }, + { "MAC_PORT_IFOUTERRORS", 0x34af8, 0 }, + { "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 }, + { "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 }, + { "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 }, + { "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 }, + { "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 }, + { "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 }, + { "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 }, + { "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 }, + { "MAC_PORT_IFINERRORS", 0x34b90, 0 }, + { "MAC_PORT_IFINERRORSHI", 0x34b94, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 }, + { "MAC_PORT_MTIP_SGMII_CONTROL", 0x34d00, 0 }, + { "Reset", 15, 1 }, + { "Loopback", 14, 1 }, + { "sppedsel1", 13, 1 }, + { "AN_EN", 12, 1 }, + { "PWRDWN", 11, 1 }, + { "Isolate", 10, 1 }, + { "AN_RESTART", 9, 1 }, + { "DPLX", 8, 1 }, + { "CollisionTest", 7, 1 }, + { "SpeedSel0", 6, 1 }, + { "MAC_PORT_MTIP_SGMII_STATUS", 0x34d04, 0 }, + { "100BaseT4", 15, 1 }, + { "100BaseXFullDplx", 14, 1 }, + { "100BaseXHalfDplx", 13, 1 }, + { "10MbpsFullDplx", 12, 1 }, + { "10MbpsHalfDplx", 11, 1 }, + { "100BaseT2FullDplx", 10, 1 }, + { "100BaseT2HalfDplx", 9, 1 }, + { "ExtdStatus", 8, 1 }, + { "AN_Complete", 5, 1 }, + { "SGMII_REM_FAULT", 4, 1 }, + { "AN_Ability", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "JabberDetect", 1, 1 }, + { "ExtdCapability", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x34d08, 0 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x34d0c, 0 }, + { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x34d10, 0 }, + { "NP", 15, 1 }, + { "ACK", 14, 1 }, + { "RF2", 13, 1 }, + { "RF1", 12, 1 }, + { "PS2", 8, 1 }, + { "PS1", 7, 1 }, + { "HD", 6, 1 }, + { "FD", 5, 1 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x34d14, 0 }, + { "CuLinkStatus", 15, 1 }, + { "ACK", 14, 1 }, + { "CuDplxStatus", 12, 1 }, + { "CuSpeed", 10, 2 }, + { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x34d18, 0 }, + { "PgRcvd", 1, 1 }, + { "RealTimePgRcvd", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x34d1c, 0 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x34d20, 0 }, + { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x34d3c, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x34d48, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x34d4c, 0 }, + { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x34d50, 0 }, + { "SGMII_PCS_ENABLE", 5, 1 }, + { "SGMII_HDUPLEX", 4, 1 }, + { "SGMII_SPEED", 2, 2 }, + { "USE_SGMII_AN", 1, 1 }, + { "SGMII_ENA", 0, 1 }, + { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x35200, 0 }, + { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x35204, 0 }, + { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x35208, 0 }, + { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3520c, 0 }, + { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x35220, 0 }, + { "MAC_PORT_MTIP_VL_INTVL", 0x35240, 0 }, + { "VL_INTVL", 1, 1 }, + { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x35600, 0 }, + { "CLK_DIV", 7, 9 }, + { "CL45_EN", 6, 1 }, + { "disable_preamble", 5, 1 }, + { "mdio_hold_time", 2, 3 }, + { "mdio_read_err", 1, 1 }, + { "mdio_busy", 0, 1 }, + { "MAC_PORT_MTIP_MDIO_COMMAND", 0x35604, 0 }, + { "read", 15, 1 }, + { "read_incr", 14, 1 }, + { "port_addr", 5, 5 }, + { "dev_addr", 0, 5 }, + { "MAC_PORT_MTIP_MDIO_DATA", 0x35608, 0 }, + { "readbusy", 31, 1 }, + { "data_word", 0, 16 }, + { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3560c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_0", 0x35a00, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_1", 0x35a04, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_2", 0x35a08, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_3", 0x35a0c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_4", 0x35a10, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_5", 0x35a14, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_6", 0x35a18, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_7", 0x35a1c, 0 }, + { "MAC_PORT_MTIP_PCS_CTL", 0x35e00, 0 }, + { "RESET", 15, 1 }, + { "LPBK", 14, 1 }, + { "SPEED_SEL1", 13, 1 }, + { "LP_MODE", 11, 1 }, + { "SPEED_SEL0", 6, 1 }, + { "SPEED", 2, 4 }, + { "MAC_PORT_MTIP_PCS_STATUS1", 0x35e04, 0 }, + { "FaultDet", 7, 1 }, + { "rx_link_status", 2, 1 }, + { "LoPwrAbl", 1, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x35e08, 0 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x35e0c, 0 }, + { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x35e10, 0 }, + { "100G", 8, 1 }, + { "40G", 7, 1 }, + { "10BASE_TL", 1, 1 }, + { "10G", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x35e14, 0 }, + { "TC", 6, 1 }, + { "DTEXS", 5, 1 }, + { "PHYXS", 4, 1 }, + { "PCS", 3, 1 }, + { "WIS", 2, 1 }, + { "PMD_PMA", 1, 1 }, + { "CL22", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x35e18, 0 }, + { "VendDev2", 15, 1 }, + { "VendDev1", 14, 1 }, + { "CL22EXT", 13, 1 }, + { "MAC_PORT_MTIP_PCS_CTL2", 0x35e1c, 0 }, + { "MAC_PORT_MTIP_PCS_STATUS2", 0x35e20, 0 }, + { "Device", 15, 1 }, + { "TxFault", 7, 1 }, + { "RxFault", 6, 1 }, + { "100BASE_R", 5, 1 }, + { "40GBASE_R", 4, 1 }, + { "10GBASE_T", 3, 1 }, + { "10GBASE_W", 2, 1 }, + { "10GBASE_X", 1, 1 }, + { "10GBASE_R", 0, 1 }, + { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x35e38, 0 }, + { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x35e3c, 0 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x35e80, 0 }, + { "RxLinkStatus", 12, 1 }, + { "RESEREVED", 4, 8 }, + { "10GPRBS9", 3, 1 }, + { "10GPRBS31", 2, 1 }, + { "HiBER", 1, 1 }, + { "blocklock", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x35e84, 0 }, + { "blocklockLL", 15, 1 }, + { "HiBERLH", 14, 1 }, + { "HiBERCount", 8, 6 }, + { "ErrBlkCnt", 0, 8 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x35e88, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x35e8c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x35e90, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x35e94, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x35e98, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x35e9c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x35ea0, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x35ea4, 0 }, + { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x35ea8, 0 }, + { "TXPRBS9", 6, 1 }, + { "RXPRBS31", 5, 1 }, + { "TXPRBS31", 4, 1 }, + { "TxTestPatEn", 3, 1 }, + { "RxTestPatEn", 2, 1 }, + { "TestPatSel", 1, 1 }, + { "DataPatSel", 0, 1 }, + { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x35eac, 0 }, + { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x35eb0, 0 }, + { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x35eb4, 0 }, + { "HiCountPrsnt", 15, 1 }, + { "BLOCK_CNT_HI", 0, 14 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x35ec8, 0 }, + { "alignstatus", 12, 1 }, + { "Lane7", 7, 1 }, + { "Lane6", 6, 1 }, + { "Lane5", 5, 1 }, + { "Lane4", 4, 1 }, + { "Lane3", 3, 1 }, + { "Lane2", 2, 1 }, + { "Lane1", 1, 1 }, + { "Lane0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x35ecc, 0 }, + { "Lane19", 11, 1 }, + { "Lane18", 10, 1 }, + { "Lane17", 9, 1 }, + { "Lane16", 8, 1 }, + { "Lane15", 7, 1 }, + { "Lane14", 6, 1 }, + { "Lane13", 5, 1 }, + { "Lane12", 4, 1 }, + { "Lane11", 3, 1 }, + { "Lane10", 2, 1 }, + { "Lane9", 1, 1 }, + { "Lane8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x35ed0, 0 }, + { "AMLOCK7", 7, 1 }, + { "AMLOCK6", 6, 1 }, + { "AMLOCK5", 5, 1 }, + { "AMLOCK4", 4, 1 }, + { "AMLOCK3", 3, 1 }, + { "AMLOCK2", 2, 1 }, + { "AMLOCK1", 1, 1 }, + { "AMLOCK0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x35ed4, 0 }, + { "AMLOCK19", 11, 1 }, + { "AMLOCK18", 10, 1 }, + { "AMLOCK17", 9, 1 }, + { "AMLOCK16", 8, 1 }, + { "AMLOCK15", 7, 1 }, + { "AMLOCK14", 6, 1 }, + { "AMLOCK13", 5, 1 }, + { "AMLOCK12", 4, 1 }, + { "AMLOCK11", 3, 1 }, + { "AMLOCK10", 2, 1 }, + { "AMLOCK9", 1, 1 }, + { "AMLOCK8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x35f68, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x35f6c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x35f70, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x35f74, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x35f78, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x35f7c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x35f80, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x35f84, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x35f88, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x35f8c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x35f90, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x35f94, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x35f98, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x35f9c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x35fa0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x35fa4, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x35fa8, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x35fac, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x35fb0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x35fb4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x35fb8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x35fbc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x35fc0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x35fc4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x35fc8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x35fcc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x35fd0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x35fd4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x35fd8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x35fdc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x35fe0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x35fe4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x35fe8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x35fec, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x35ff0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x35ff4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x35ff8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x35ffc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x36000, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x36004, 0 }, + { "MAC_PORT_BEAN_CTL", 0x36200, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS", 0x36204, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0", 0x36208, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1", 0x3620c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2", 0x36210, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0", 0x36214, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1", 0x36218, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3621c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT", 0x36220, 0 }, + { "MAC_PORT_BEAN_XNP_0", 0x36224, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1", 0x36228, 0 }, + { "MAC_PORT_BEAN_XNP_2", 0x3622c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0", 0x36230, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1", 0x36234, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2", 0x36238, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS", 0x3623c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE1", 0x36240, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE1", 0x36244, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x36248, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3624c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x36250, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x36254, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x36258, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3625c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x36260, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE1", 0x36264, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE1", 0x36268, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3626c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x36270, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x36274, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x36278, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3627c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE2", 0x36280, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE2", 0x36284, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x36288, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3628c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x36290, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x36294, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x36298, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3629c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x362a0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE2", 0x362a4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE2", 0x362a8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE2", 0x362ac, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x362b0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x362b4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x362b8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x362bc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE3", 0x362c0, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE3", 0x362c4, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x362c8, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x362cc, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x362d0, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x362d4, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x362d8, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x362dc, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x362e0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE3", 0x362e4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE3", 0x362e8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE3", 0x362ec, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x362f0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x362f4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x362f8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x362fc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_FEC_KR_CONTROL", 0x36600, 0 }, + { "enable_tr", 1, 1 }, + { "restart_tr", 0, 1 }, + { "MAC_PORT_FEC_KR_STATUS", 0x36604, 0 }, + { "fecKRsigdet", 15, 1 }, + { "train_fail", 3, 1 }, + { "startup_status", 2, 1 }, + { "frame_lock", 1, 1 }, + { "rx_status", 0, 1 }, + { "MAC_PORT_FEC_KR_LP_COEFF", 0x36608, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LP_STAT", 0x3660c, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_COEFF", 0x36610, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_STAT", 0x36614, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_ABILITY", 0x36618, 0 }, + { "fec_ind_ability", 1, 1 }, + { "ability", 0, 1 }, + { "MAC_PORT_FEC_CONTROL", 0x3661c, 0 }, + { "fec_en_err_ind", 1, 1 }, + { "fec_en", 0, 1 }, + { "MAC_PORT_FEC_STATUS", 0x36620, 0 }, + { "FEC_LOCKED_100", 1, 1 }, + { "FEC_LOCKED", 0, 1 }, + { "MAC_PORT_FEC_CERR_CNT_0", 0x36624, 0 }, + { "MAC_PORT_FEC_CERR_CNT_1", 0x36628, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_0", 0x3662c, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_1", 0x36630, 0 }, + { "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 }, + { "T5_AE0_RXSTAT_RDY", 15, 1 }, + { "T5_AE0_RXSTAT_C2", 4, 2 }, + { "T5_AE0_RXSTAT_C1", 2, 2 }, + { "T5_AE0_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE", 0x36a10, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 }, + { "T5_AE1_RXSTAT_RDY", 15, 1 }, + { "T5_AE1_RXSTAT_C2", 4, 2 }, + { "T5_AE1_RXSTAT_C1", 2, 2 }, + { "T5_AE1_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 }, + { "T5_AE2_RXSTAT_RDY", 15, 1 }, + { "T5_AE2_RXSTAT_C2", 4, 2 }, + { "T5_AE2_RXSTAT_C1", 2, 2 }, + { "T5_AE2_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 }, + { "T5_AE3_RXSTAT_RDY", 15, 1 }, + { "T5_AE3_RXSTAT_C2", 4, 2 }, + { "T5_AE3_RXSTAT_C1", 2, 2 }, + { "T5_AE3_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_TX_DIS", 0x36a80, 0 }, + { "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 }, + { "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 }, + { "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 }, + { "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 }, + { "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 }, + { "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 }, + { "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 }, + { "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_0", 0x36b10, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_1", 0x36b30, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_2", 0x36b50, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_3", 0x36b70, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 }, + { "MAC_PORT_BANDGAP_CONTROL", 0x3782c, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x37880, 0 }, + { "RCCTL1", 5, 1 }, + { "RCCTL0", 4, 1 }, + { "RCAMP1", 3, 1 }, + { "RCAMP0", 2, 1 }, + { "RCAMPEN", 1, 1 }, + { "RCRST", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x37884, 0 }, + { "RCERR", 1, 1 }, + { "RCCOMP", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x37888, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3788c, 0 }, + { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 }, + { "LBIST", 7, 1 }, + { "LOGICTEST", 6, 1 }, + { "MAVDHI", 5, 1 }, + { "AUXEN", 4, 1 }, + { "JTAGMD", 3, 1 }, + { "RXACMODE", 2, 1 }, + { "HSSACJPC", 1, 1 }, + { "HSSACJAC", 0, 1 }, + { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 }, + { "REFVALIDD", 6, 1 }, + { "REFVALIDC", 5, 1 }, + { "REFVALIDB", 4, 1 }, + { "REFVALIDA", 3, 1 }, + { "REFSELRESET", 2, 1 }, + { "SOFTRESET", 1, 1 }, + { "MACROTEST", 0, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 }, + { "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 }, + { "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x37030, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37060, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37064, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37068, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37070, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37074, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37088, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3708c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x37090, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x37094, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x37098, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x37130, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37160, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37164, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37168, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37170, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37174, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37188, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3718c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x37190, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x37194, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x37198, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x37430, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37460, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37464, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37468, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37470, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37474, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37488, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3748c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x37490, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x37494, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x37498, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x37530, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37560, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37564, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37568, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37570, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37574, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37588, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3758c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x37590, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x37594, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x37598, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x37930, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37960, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37964, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37968, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37970, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37974, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37988, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3798c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x37990, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x37994, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x37998, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 }, + { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x37238, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x37240, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3724c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3725c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37260, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37264, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x37284, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x37288, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3728c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x37290, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x37294, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x37298, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 }, + { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x372c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKA_DFE_H1", 0x372c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H2", 0x372c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_H3", 0x372cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H4", 0x372d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H5", 0x372d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x372d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x372dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x372e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H12", 0x372e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x372f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x37338, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x37340, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3734c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3735c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37360, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37364, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x37384, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x37388, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3738c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x37390, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x37394, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x37398, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 }, + { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x373c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKB_DFE_H1", 0x373c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H2", 0x373c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_H3", 0x373cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H4", 0x373d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H5", 0x373d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x373d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x373dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x373e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H12", 0x373e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x373f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x37638, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x37640, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3764c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3765c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37660, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37664, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x37684, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x37688, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3768c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x37690, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x37694, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x37698, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 }, + { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x376c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKC_DFE_H1", 0x376c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H2", 0x376c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_H3", 0x376cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H4", 0x376d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H5", 0x376d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x376d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x376dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x376e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H12", 0x376e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x376f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x37738, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x37740, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3774c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3775c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37760, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37764, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x37784, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x37788, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3778c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x37790, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x37794, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x37798, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 }, + { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x377c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKD_DFE_H1", 0x377c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H2", 0x377c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_H3", 0x377cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H4", 0x377d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H5", 0x377d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x377d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x377dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x377e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H12", 0x377e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x377f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x37a38, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x37a40, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x37a4c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x37a5c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37a60, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37a64, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x37a84, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x37a88, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x37a8c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x37a90, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x37a94, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x37a98, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 }, + { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x37ac0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x37ac4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x37ac8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x37acc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x37ad0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x37ad4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x37ad8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x37adc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x37ae0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x37ae4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x37af8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_CFG", 0x38800, 0 }, + { "MAC_Clk_Sel", 29, 3 }, + { "SinkTx", 27, 1 }, + { "SinkTxOnLinkDown", 26, 1 }, + { "LoopNoFwd", 24, 1 }, + { "Smux_Rx_Loop", 19, 1 }, + { "Rx_Lane_Swap", 18, 1 }, + { "Tx_Lane_Swap", 17, 1 }, + { "Signal_Det", 14, 1 }, + { "SmuxTxSel", 9, 1 }, + { "SmuxRxSel", 8, 1 }, + { "PortSpeed", 4, 2 }, + { "Rx_Byte_Swap", 3, 1 }, + { "Tx_Byte_Swap", 2, 1 }, + { "Port_Sel", 0, 1 }, + { "MAC_PORT_RESET_CTRL", 0x38804, 0 }, + { "TWGDSK_HSSC16B", 31, 1 }, + { "EEE_RESET", 30, 1 }, + { "PTP_TIMER", 29, 1 }, + { "MtipRefReset", 28, 1 }, + { "MtipTxffReset", 27, 1 }, + { "MtipRxffReset", 26, 1 }, + { "MtipRegReset", 25, 1 }, + { "AEC3Reset", 23, 1 }, + { "AEC2Reset", 22, 1 }, + { "AEC1Reset", 21, 1 }, + { "AEC0Reset", 20, 1 }, + { "AET3Reset", 19, 1 }, + { "AET2Reset", 18, 1 }, + { "AET1Reset", 17, 1 }, + { "AET0Reset", 16, 1 }, + { "TXIF_Reset", 12, 1 }, + { "RXIF_Reset", 11, 1 }, + { "AuxExt_Reset", 10, 1 }, + { "MtipSd3TxRst", 9, 1 }, + { "MtipSd2TxRst", 8, 1 }, + { "MtipSd1TxRst", 7, 1 }, + { "MtipSd0TxRst", 6, 1 }, + { "MtipSd3RxRst", 5, 1 }, + { "MtipSd2RxRst", 4, 1 }, + { "MtipSd1RxRst", 3, 1 }, + { "WOL_Reset", 2, 1 }, + { "MtipSd0RxRst", 1, 1 }, + { "HSS_Reset", 0, 1 }, + { "MAC_PORT_LED_CFG", 0x38808, 0 }, + { "Led1_Cfg", 5, 3 }, + { "Led1_Polarity_Inv", 4, 1 }, + { "Led0_Cfg", 1, 3 }, + { "Led0_Polarity_Inv", 0, 1 }, + { "MAC_PORT_LED_COUNTHI", 0x3880c, 0 }, + { "MAC_PORT_LED_COUNTLO", 0x38810, 0 }, + { "MAC_PORT_CFG3", 0x38814, 0 }, + { "FPGA_PTP_PORT", 26, 2 }, + { "FCSDisCtrl", 25, 1 }, + { "SigDetCtrl", 24, 1 }, + { "tx_lane", 23, 1 }, + { "rx_lane", 22, 1 }, + { "se_clr", 21, 1 }, + { "an_ena", 17, 4 }, + { "sd_rx_clk_ena", 13, 4 }, + { "sd_tx_clk_ena", 9, 4 }, + { "SGMIISEL", 8, 1 }, + { "HSSPLLSEL", 4, 4 }, + { "HSSC16C20SEL", 0, 4 }, + { "MAC_PORT_CFG2", 0x38818, 0 }, + { "Rx_Polarity_Inv", 28, 4 }, + { "Tx_Polarity_Inv", 24, 4 }, + { "InstanceNum", 22, 2 }, + { "StopOnPerr", 21, 1 }, + { "PatEn", 18, 1 }, + { "MagicEn", 17, 1 }, + { "T5_AEC_PMA_TX_READY", 4, 4 }, + { "T5_AEC_PMA_RX_READY", 0, 4 }, + { "MAC_PORT_PKT_COUNT", 0x3881c, 0 }, + { "tx_sop_count", 24, 8 }, + { "tx_eop_count", 16, 8 }, + { "rx_sop_count", 8, 8 }, + { "rx_eop_count", 0, 8 }, + { "MAC_PORT_CFG4", 0x38820, 0 }, + { "AEC3_RX_WIDTH", 14, 2 }, + { "AEC2_RX_WIDTH", 12, 2 }, + { "AEC1_RX_WIDTH", 10, 2 }, + { "AEC0_RX_WIDTH", 8, 2 }, + { "AEC3_TX_WIDTH", 6, 2 }, + { "AEC2_TX_WIDTH", 4, 2 }, + { "AEC1_TX_WIDTH", 2, 2 }, + { "AEC0_TX_WIDTH", 0, 2 }, + { "MAC_PORT_MAGIC_MACID_LO", 0x38824, 0 }, + { "MAC_PORT_MAGIC_MACID_HI", 0x38828, 0 }, + { "MAC_PORT_LINK_STATUS", 0x38834, 0 }, + { "an_done", 6, 1 }, + { "align_done", 5, 1 }, + { "block_lock", 4, 1 }, + { "remflt", 3, 1 }, + { "locflt", 2, 1 }, + { "linkup", 1, 1 }, + { "linkdn", 0, 1 }, + { "MAC_PORT_EPIO_DATA0", 0x388c0, 0 }, + { "MAC_PORT_EPIO_DATA1", 0x388c4, 0 }, + { "MAC_PORT_EPIO_DATA2", 0x388c8, 0 }, + { "MAC_PORT_EPIO_DATA3", 0x388cc, 0 }, + { "MAC_PORT_EPIO_OP", 0x388d0, 0 }, + { "Busy", 31, 1 }, + { "Write", 8, 1 }, + { "Address", 0, 8 }, + { "MAC_PORT_WOL_STATUS", 0x388d4, 0 }, + { "MagicDetected", 31, 1 }, + { "PatDetected", 30, 1 }, + { "ClearMagic", 4, 1 }, + { "ClearMatch", 3, 1 }, + { "MatchedFilter", 0, 3 }, + { "MAC_PORT_INT_EN", 0x388d8, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_INT_CAUSE", 0x388dc, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_PERR_INT_EN", 0x388e0, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INT_CAUSE", 0x388e4, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_ENABLE", 0x388e8, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INJECT", 0x388ec, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MAC_PORT_HSS_CFG0", 0x388f0, 0 }, + { "TXDTS", 31, 1 }, + { "TXCTS", 30, 1 }, + { "TXBTS", 29, 1 }, + { "TXATS", 28, 1 }, + { "TXDOBS", 27, 1 }, + { "TXCOBS", 26, 1 }, + { "TXBOBS", 25, 1 }, + { "TXAOBS", 24, 1 }, + { "HSSREFCLKVALIDA", 20, 1 }, + { "HSSREFCLKVALIDB", 19, 1 }, + { "HSSRESYNCA", 18, 1 }, + { "HSSAVDHI", 17, 1 }, + { "HSSRESYNCB", 16, 1 }, + { "HSSRECCALA", 15, 1 }, + { "HSSRXACMODE", 14, 1 }, + { "HSSRECCALB", 13, 1 }, + { "HSSPLLBYPA", 12, 1 }, + { "HSSPLLBYPB", 11, 1 }, + { "HSSPDWNPLLA", 10, 1 }, + { "HSSPDWNPLLB", 9, 1 }, + { "HSSVCOSELA", 8, 1 }, + { "HSSVCOSELB", 7, 1 }, + { "HSSCALCOMP", 6, 1 }, + { "HSSCALENAB", 5, 1 }, + { "HSSEXTC16SEL", 4, 1 }, + { "MAC_PORT_HSS_CFG1", 0x388f4, 0 }, + { "RXACONFIGSEL", 30, 2 }, + { "RXAQUIET", 29, 1 }, + { "RXAREFRESH", 28, 1 }, + { "RXBCONFIGSEL", 26, 2 }, + { "RXBQUIET", 25, 1 }, + { "RXBREFRESH", 24, 1 }, + { "RXCCONFIGSEL", 22, 2 }, + { "RXCQUIET", 21, 1 }, + { "RXCREFRESH", 20, 1 }, + { "RXDCONFIGSEL", 18, 2 }, + { "RXDQUIET", 17, 1 }, + { "RXDREFRESH", 16, 1 }, + { "TXACONFIGSEL", 14, 2 }, + { "TXAQUIET", 13, 1 }, + { "TXAREFRESH", 12, 1 }, + { "TXBCONFIGSEL", 10, 2 }, + { "TXBQUIET", 9, 1 }, + { "TXBREFRESH", 8, 1 }, + { "TXCCONFIGSEL", 6, 2 }, + { "TXCQUIET", 5, 1 }, + { "TXCREFRESH", 4, 1 }, + { "TXDCONFIGSEL", 2, 2 }, + { "TXDQUIET", 1, 1 }, + { "TXDREFRESH", 0, 1 }, + { "MAC_PORT_HSS_CFG2", 0x388f8, 0 }, + { "RXAASSTCLK", 31, 1 }, + { "T5RXAPRBSRST", 30, 1 }, + { "RXBASSTCLK", 29, 1 }, + { "T5RXBPRBSRST", 28, 1 }, + { "RXCASSTCLK", 27, 1 }, + { "T5RXCPRBSRST", 26, 1 }, + { "RXDASSTCLK", 25, 1 }, + { "T5RXDPRBSRST", 24, 1 }, + { "RXDDATASYNC", 23, 1 }, + { "RXCDATASYNC", 22, 1 }, + { "RXBDATASYNC", 21, 1 }, + { "RXADATASYNC", 20, 1 }, + { "RXDEARLYIN", 19, 1 }, + { "RXDLATEIN", 18, 1 }, + { "RXDPHSLOCK", 17, 1 }, + { "RXDPHSDNIN", 16, 1 }, + { "RXDPHSUPIN", 15, 1 }, + { "RXCEARLYIN", 14, 1 }, + { "RXCLATEIN", 13, 1 }, + { "RXCPHSLOCK", 12, 1 }, + { "RXCPHSDNIN", 11, 1 }, + { "RXCPHSUPIN", 10, 1 }, + { "RXBEARLYIN", 9, 1 }, + { "RXBLATEIN", 8, 1 }, + { "RXBPHSLOCK", 7, 1 }, + { "RXBPHSDNIN", 6, 1 }, + { "RXBPHSUPIN", 5, 1 }, + { "RXAEARLYIN", 4, 1 }, + { "RXALATEIN", 3, 1 }, + { "RXAPHSLOCK", 2, 1 }, + { "RXAPHSDNIN", 1, 1 }, + { "RXAPHSUPIN", 0, 1 }, + { "MAC_PORT_HSS_CFG3", 0x388fc, 0 }, + { "HSSCALSSTN", 25, 3 }, + { "HSSCALSSTP", 22, 3 }, + { "HSSVBOOSTDIVB", 19, 3 }, + { "HSSVBOOSTDIVA", 16, 3 }, + { "HSSPLLCONFIGB", 8, 8 }, + { "HSSPLLCONFIGA", 0, 8 }, + { "MAC_PORT_HSS_CFG4", 0x38900, 0 }, + { "HSSDIVSELA", 9, 9 }, + { "HSSDIVSELB", 0, 9 }, + { "MAC_PORT_HSS_STATUS", 0x38904, 0 }, + { "RXDPRBSSYNC", 15, 1 }, + { "RXCPRBSSYNC", 14, 1 }, + { "RXBPRBSSYNC", 13, 1 }, + { "RXAPRBSSYNC", 12, 1 }, + { "RXDPRBSERR", 11, 1 }, + { "RXCPRBSERR", 10, 1 }, + { "RXBPRBSERR", 9, 1 }, + { "RXAPRBSERR", 8, 1 }, + { "RXDSIGDET", 7, 1 }, + { "RXCSIGDET", 6, 1 }, + { "RXBSIGDET", 5, 1 }, + { "RXASIGDET", 4, 1 }, + { "HSSPLLLOCKB", 3, 1 }, + { "HSSPLLLOCKA", 2, 1 }, + { "HSSPRTREADYB", 1, 1 }, + { "HSSPRTREADYA", 0, 1 }, + { "MAC_PORT_HSS_EEE_STATUS", 0x38908, 0 }, + { "RXAQUIET_STATUS", 15, 1 }, + { "RXAREFRESH_STATUS", 14, 1 }, + { "RXBQUIET_STATUS", 13, 1 }, + { "RXBREFRESH_STATUS", 12, 1 }, + { "RXCQUIET_STATUS", 11, 1 }, + { "RXCREFRESH_STATUS", 10, 1 }, + { "RXDQUIET_STATUS", 9, 1 }, + { "RXDREFRESH_STATUS", 8, 1 }, + { "TXAQUIET_STATUS", 7, 1 }, + { "TXAREFRESH_STATUS", 6, 1 }, + { "TXBQUIET_STATUS", 5, 1 }, + { "TXBREFRESH_STATUS", 4, 1 }, + { "TXCQUIET_STATUS", 3, 1 }, + { "TXCREFRESH_STATUS", 2, 1 }, + { "TXDQUIET_STATUS", 1, 1 }, + { "TXDREFRESH_STATUS", 0, 1 }, + { "MAC_PORT_HSS_SIGDET_STATUS", 0x3890c, 0 }, + { "MAC_PORT_HSS_PL_CTL", 0x38910, 0 }, + { "TOV", 16, 8 }, + { "TSU", 8, 8 }, + { "IPW", 0, 8 }, + { "MAC_PORT_RUNT_FRAME", 0x38914, 0 }, + { "runtclear", 16, 1 }, + { "runt", 0, 16 }, + { "MAC_PORT_EEE_STATUS", 0x38918, 0 }, + { "eee_tx_10g_state", 10, 2 }, + { "eee_rx_10g_state", 8, 2 }, + { "eee_tx_1g_state", 6, 2 }, + { "eee_rx_1g_state", 4, 2 }, + { "pma_rx_refresh", 3, 1 }, + { "pma_rx_quiet", 2, 1 }, + { "pma_tx_refresh", 1, 1 }, + { "pma_tx_quiet", 0, 1 }, + { "MAC_PORT_CGEN", 0x3891c, 0 }, + { "CGEN", 8, 1 }, + { "sd7_CGEN", 7, 1 }, + { "sd6_CGEN", 6, 1 }, + { "sd5_CGEN", 5, 1 }, + { "sd4_CGEN", 4, 1 }, + { "sd3_CGEN", 3, 1 }, + { "sd2_CGEN", 2, 1 }, + { "sd1_CGEN", 1, 1 }, + { "sd0_CGEN", 0, 1 }, + { "MAC_PORT_CGEN_MTIP", 0x38920, 0 }, + { "MACSEG5_CGEN", 11, 1 }, + { "PCSSEG5_CGEN", 10, 1 }, + { "MACSEG4_CGEN", 9, 1 }, + { "PCSSEG4_CGEN", 8, 1 }, + { "MACSEG3_CGEN", 7, 1 }, + { "PCSSEG3_CGEN", 6, 1 }, + { "MACSEG2_CGEN", 5, 1 }, + { "PCSSEG2_CGEN", 4, 1 }, + { "MACSEG1_CGEN", 3, 1 }, + { "PCSSEG1_CGEN", 2, 1 }, + { "MACSEG0_CGEN", 1, 1 }, + { "PCSSEG0_CGEN", 0, 1 }, + { "MAC_PORT_TX_TS_ID", 0x38924, 0 }, + { "MAC_PORT_TX_TS_VAL_LO", 0x38928, 0 }, + { "MAC_PORT_TX_TS_VAL_HI", 0x3892c, 0 }, + { "MAC_PORT_EEE_CTL", 0x38930, 0 }, + { "EEE_CTRL", 2, 30 }, + { "TICK_START", 1, 1 }, + { "En", 0, 1 }, + { "MAC_PORT_EEE_TX_CTL", 0x38934, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_ACTIVE", 3, 1 }, + { "LPI_TXHOLD", 2, 1 }, + { "LPI_REQ", 1, 1 }, + { "EEE_TX_RESET", 0, 1 }, + { "MAC_PORT_EEE_RX_CTL", 0x38938, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_IND", 1, 1 }, + { "EEE_RX_RESET", 0, 1 }, + { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3893c, 0 }, + { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x38940, 0 }, + { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x38944, 0 }, + { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x38948, 0 }, + { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3894c, 0 }, + { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x38950, 0 }, + { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x38954, 0 }, + { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x38958, 0 }, + { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3895c, 0 }, + { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x38960, 0 }, + { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x38964, 0 }, + { "MAC_PORT_EEE_WF_COUNT", 0x38968, 0 }, + { "wake_cnt_clr", 16, 1 }, + { "wake_cnt", 0, 16 }, + { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3896c, 0 }, + { "MAC_PORT_PTP_TIMER_RD0_HI", 0x38970, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_LO", 0x38974, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_HI", 0x38978, 0 }, + { "MAC_PORT_PTP_TIMER_WR_LO", 0x3897c, 0 }, + { "MAC_PORT_PTP_TIMER_WR_HI", 0x38980, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x38984, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x38988, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3898c, 0 }, + { "MAC_PORT_PTP_SUM_LO", 0x38990, 0 }, + { "MAC_PORT_PTP_SUM_HI", 0x38994, 0 }, + { "MAC_PORT_PTP_TIMER_INCR0", 0x38998, 0 }, + { "Y", 16, 16 }, + { "X", 0, 16 }, + { "MAC_PORT_PTP_TIMER_INCR1", 0x3899c, 0 }, + { "Y_TICK", 16, 16 }, + { "X_TICK", 0, 16 }, + { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x389a0, 0 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x389a4, 0 }, + { "B", 16, 16 }, + { "A", 0, 16 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x389a8, 0 }, + { "MAC_PORT_PTP_CFG", 0x389ac, 0 }, + { "FRZ", 18, 1 }, + { "OFFSER_ADJUST_SIGN", 17, 1 }, + { "ADD_OFFSET", 16, 1 }, + { "CYCLE1", 8, 8 }, + { "Q", 0, 8 }, + { "MAC_PORT_MTIP_REVISION", 0x38a00, 0 }, + { "CUSTREV", 16, 16 }, + { "VER", 8, 8 }, + { "REV", 0, 8 }, + { "MAC_PORT_MTIP_SCRATCH", 0x38a04, 0 }, + { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x38a08, 0 }, + { "TX_FLUSH", 22, 1 }, + { "RX_SFD_ANY", 21, 1 }, + { "PAUSE_PFC_COMP", 20, 1 }, + { "PFC_MODE", 19, 1 }, + { "RS_COL_CNT_EXT", 18, 1 }, + { "NO_LGTH_CHECK", 17, 1 }, + { "SEND_IDLE", 16, 1 }, + { "PHY_TXENA", 15, 1 }, + { "RX_ERR_DISC", 14, 1 }, + { "CMD_FRAME_ENA", 13, 1 }, + { "SW_RESET", 12, 1 }, + { "TX_PAD_EN", 11, 1 }, + { "LOOPBACK_EN", 10, 1 }, + { "TX_ADDR_INS", 9, 1 }, + { "PAUSE_IGNORE", 8, 1 }, + { "PAUSE_FWD", 7, 1 }, + { "CRC_FWD", 6, 1 }, + { "PAD_EN", 5, 1 }, + { "PROMIS_EN", 4, 1 }, + { "WAN_MODE", 3, 1 }, + { "RX_ENA", 1, 1 }, + { "TX_ENA", 0, 1 }, + { "MAC_PORT_MTIP_MAC_ADDR_0", 0x38a0c, 0 }, + { "MAC_PORT_MTIP_MAC_ADDR_1", 0x38a10, 0 }, + { "MAC_PORT_MTIP_FRM_LENGTH", 0x38a14, 0 }, + { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x38a1c, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x38a20, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x38a24, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x38a28, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x38a2c, 0 }, + { "ENABLE", 8, 1 }, + { "ADDR", 0, 6 }, + { "MAC_PORT_MTIP_MAC_STATUS", 0x38a40, 0 }, + { "TS_AVAIL", 3, 1 }, + { "PHY_LOS", 2, 1 }, + { "RX_REM_FAULT", 1, 1 }, + { "RX_LOC_FAULT", 0, 1 }, + { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x38a44, 0 }, + { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x38a48, 0 }, + { "MAC_PORT_MTIP_INIT_CREDIT", 0x38a4c, 0 }, + { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x38a50, 0 }, + { "MAC_PORT_RX_PAUSE_STATUS", 0x38a74, 0 }, + { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x38a7c, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x38a80, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x38a84, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOK", 0x38a88, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x38a8c, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x38a90, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x38a94, 0 }, + { "MAC_PORT_AALIGNMENTERRORS", 0x38a98, 0 }, + { "MAC_PORT_AALIGNMENTERRORSHI", 0x38a9c, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x38aa0, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x38aa4, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x38aa8, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x38aac, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORS", 0x38ab0, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x38ab4, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORS", 0x38ab8, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x38abc, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOK", 0x38ac0, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x38ac4, 0 }, + { "MAC_PORT_VLANRECEIVEDOK", 0x38ac8, 0 }, + { "MAC_PORT_VLANRECEIVEDOKHI", 0x38acc, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x38ad0, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x38ad4, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOK", 0x38ad8, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x38adc, 0 }, + { "MAC_PORT_IFINUCASTPKTS", 0x38ae0, 0 }, + { "MAC_PORT_IFINUCASTPKTSHI", 0x38ae4, 0 }, + { "MAC_PORT_IFINMULTICASTPKTS", 0x38ae8, 0 }, + { "MAC_PORT_IFINMULTICASTPKTSHI", 0x38aec, 0 }, + { "MAC_PORT_IFINBROADCASTPKTS", 0x38af0, 0 }, + { "MAC_PORT_IFINBROADCASTPKTSHI", 0x38af4, 0 }, + { "MAC_PORT_IFOUTERRORS", 0x38af8, 0 }, + { "MAC_PORT_IFOUTERRORSHI", 0x38afc, 0 }, + { "MAC_PORT_IFOUTUCASTPKTS", 0x38b08, 0 }, + { "MAC_PORT_IFOUTUCASTPKTSHI", 0x38b0c, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTS", 0x38b10, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x38b14, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTS", 0x38b18, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x38b1c, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x38b20, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x38b24, 0 }, + { "MAC_PORT_ETHERSTATSOCTETS", 0x38b28, 0 }, + { "MAC_PORT_ETHERSTATSOCTETSHI", 0x38b2c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS", 0x38b30, 0 }, + { "MAC_PORT_ETHERSTATSPKTSHI", 0x38b34, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x38b38, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x38b3c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x38b40, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x38b44, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x38b48, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x38b4c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x38b50, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x38b54, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x38b58, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x38b5c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x38b60, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x38b64, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x38b68, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x38b6c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x38b70, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x38b74, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x38b78, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x38b7c, 0 }, + { "MAC_PORT_ETHERSTATSJABBERS", 0x38b80, 0 }, + { "MAC_PORT_ETHERSTATSJABBERSHI", 0x38b84, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x38b88, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x38b8c, 0 }, + { "MAC_PORT_IFINERRORS", 0x38b90, 0 }, + { "MAC_PORT_IFINERRORSHI", 0x38b94, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x38b98, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x38b9c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x38ba0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x38ba4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x38ba8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x38bac, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x38bb0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x38bb4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x38bb8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x38bbc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x38bc0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x38bc4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x38bc8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x38bcc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x38bd0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x38bd4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x38bd8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x38bdc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x38be0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x38be4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x38be8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x38bec, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x38bf0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x38bf4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x38bf8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x38bfc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x38c00, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x38c04, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x38c08, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x38c0c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x38c10, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x38c14, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x38c18, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x38c1c, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x38c20, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x38c24, 0 }, + { "MAC_PORT_MTIP_SGMII_CONTROL", 0x38d00, 0 }, + { "Reset", 15, 1 }, + { "Loopback", 14, 1 }, + { "sppedsel1", 13, 1 }, + { "AN_EN", 12, 1 }, + { "PWRDWN", 11, 1 }, + { "Isolate", 10, 1 }, + { "AN_RESTART", 9, 1 }, + { "DPLX", 8, 1 }, + { "CollisionTest", 7, 1 }, + { "SpeedSel0", 6, 1 }, + { "MAC_PORT_MTIP_SGMII_STATUS", 0x38d04, 0 }, + { "100BaseT4", 15, 1 }, + { "100BaseXFullDplx", 14, 1 }, + { "100BaseXHalfDplx", 13, 1 }, + { "10MbpsFullDplx", 12, 1 }, + { "10MbpsHalfDplx", 11, 1 }, + { "100BaseT2FullDplx", 10, 1 }, + { "100BaseT2HalfDplx", 9, 1 }, + { "ExtdStatus", 8, 1 }, + { "AN_Complete", 5, 1 }, + { "SGMII_REM_FAULT", 4, 1 }, + { "AN_Ability", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "JabberDetect", 1, 1 }, + { "ExtdCapability", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x38d08, 0 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x38d0c, 0 }, + { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x38d10, 0 }, + { "NP", 15, 1 }, + { "ACK", 14, 1 }, + { "RF2", 13, 1 }, + { "RF1", 12, 1 }, + { "PS2", 8, 1 }, + { "PS1", 7, 1 }, + { "HD", 6, 1 }, + { "FD", 5, 1 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x38d14, 0 }, + { "CuLinkStatus", 15, 1 }, + { "ACK", 14, 1 }, + { "CuDplxStatus", 12, 1 }, + { "CuSpeed", 10, 2 }, + { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x38d18, 0 }, + { "PgRcvd", 1, 1 }, + { "RealTimePgRcvd", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x38d1c, 0 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x38d20, 0 }, + { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x38d3c, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x38d48, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x38d4c, 0 }, + { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x38d50, 0 }, + { "SGMII_PCS_ENABLE", 5, 1 }, + { "SGMII_HDUPLEX", 4, 1 }, + { "SGMII_SPEED", 2, 2 }, + { "USE_SGMII_AN", 1, 1 }, + { "SGMII_ENA", 0, 1 }, + { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x39200, 0 }, + { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x39204, 0 }, + { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x39208, 0 }, + { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3920c, 0 }, + { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x39220, 0 }, + { "MAC_PORT_MTIP_VL_INTVL", 0x39240, 0 }, + { "VL_INTVL", 1, 1 }, + { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x39600, 0 }, + { "CLK_DIV", 7, 9 }, + { "CL45_EN", 6, 1 }, + { "disable_preamble", 5, 1 }, + { "mdio_hold_time", 2, 3 }, + { "mdio_read_err", 1, 1 }, + { "mdio_busy", 0, 1 }, + { "MAC_PORT_MTIP_MDIO_COMMAND", 0x39604, 0 }, + { "read", 15, 1 }, + { "read_incr", 14, 1 }, + { "port_addr", 5, 5 }, + { "dev_addr", 0, 5 }, + { "MAC_PORT_MTIP_MDIO_DATA", 0x39608, 0 }, + { "readbusy", 31, 1 }, + { "data_word", 0, 16 }, + { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3960c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_0", 0x39a00, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_1", 0x39a04, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_2", 0x39a08, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_3", 0x39a0c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_4", 0x39a10, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_5", 0x39a14, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_6", 0x39a18, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_7", 0x39a1c, 0 }, + { "MAC_PORT_MTIP_PCS_CTL", 0x39e00, 0 }, + { "RESET", 15, 1 }, + { "LPBK", 14, 1 }, + { "SPEED_SEL1", 13, 1 }, + { "LP_MODE", 11, 1 }, + { "SPEED_SEL0", 6, 1 }, + { "SPEED", 2, 4 }, + { "MAC_PORT_MTIP_PCS_STATUS1", 0x39e04, 0 }, + { "FaultDet", 7, 1 }, + { "rx_link_status", 2, 1 }, + { "LoPwrAbl", 1, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x39e08, 0 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x39e0c, 0 }, + { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x39e10, 0 }, + { "100G", 8, 1 }, + { "40G", 7, 1 }, + { "10BASE_TL", 1, 1 }, + { "10G", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x39e14, 0 }, + { "TC", 6, 1 }, + { "DTEXS", 5, 1 }, + { "PHYXS", 4, 1 }, + { "PCS", 3, 1 }, + { "WIS", 2, 1 }, + { "PMD_PMA", 1, 1 }, + { "CL22", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x39e18, 0 }, + { "VendDev2", 15, 1 }, + { "VendDev1", 14, 1 }, + { "CL22EXT", 13, 1 }, + { "MAC_PORT_MTIP_PCS_CTL2", 0x39e1c, 0 }, + { "MAC_PORT_MTIP_PCS_STATUS2", 0x39e20, 0 }, + { "Device", 15, 1 }, + { "TxFault", 7, 1 }, + { "RxFault", 6, 1 }, + { "100BASE_R", 5, 1 }, + { "40GBASE_R", 4, 1 }, + { "10GBASE_T", 3, 1 }, + { "10GBASE_W", 2, 1 }, + { "10GBASE_X", 1, 1 }, + { "10GBASE_R", 0, 1 }, + { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x39e38, 0 }, + { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x39e3c, 0 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x39e80, 0 }, + { "RxLinkStatus", 12, 1 }, + { "RESEREVED", 4, 8 }, + { "10GPRBS9", 3, 1 }, + { "10GPRBS31", 2, 1 }, + { "HiBER", 1, 1 }, + { "blocklock", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x39e84, 0 }, + { "blocklockLL", 15, 1 }, + { "HiBERLH", 14, 1 }, + { "HiBERCount", 8, 6 }, + { "ErrBlkCnt", 0, 8 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x39e88, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x39e8c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x39e90, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x39e94, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x39e98, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x39e9c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x39ea0, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x39ea4, 0 }, + { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x39ea8, 0 }, + { "TXPRBS9", 6, 1 }, + { "RXPRBS31", 5, 1 }, + { "TXPRBS31", 4, 1 }, + { "TxTestPatEn", 3, 1 }, + { "RxTestPatEn", 2, 1 }, + { "TestPatSel", 1, 1 }, + { "DataPatSel", 0, 1 }, + { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x39eac, 0 }, + { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x39eb0, 0 }, + { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x39eb4, 0 }, + { "HiCountPrsnt", 15, 1 }, + { "BLOCK_CNT_HI", 0, 14 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x39ec8, 0 }, + { "alignstatus", 12, 1 }, + { "Lane7", 7, 1 }, + { "Lane6", 6, 1 }, + { "Lane5", 5, 1 }, + { "Lane4", 4, 1 }, + { "Lane3", 3, 1 }, + { "Lane2", 2, 1 }, + { "Lane1", 1, 1 }, + { "Lane0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x39ecc, 0 }, + { "Lane19", 11, 1 }, + { "Lane18", 10, 1 }, + { "Lane17", 9, 1 }, + { "Lane16", 8, 1 }, + { "Lane15", 7, 1 }, + { "Lane14", 6, 1 }, + { "Lane13", 5, 1 }, + { "Lane12", 4, 1 }, + { "Lane11", 3, 1 }, + { "Lane10", 2, 1 }, + { "Lane9", 1, 1 }, + { "Lane8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x39ed0, 0 }, + { "AMLOCK7", 7, 1 }, + { "AMLOCK6", 6, 1 }, + { "AMLOCK5", 5, 1 }, + { "AMLOCK4", 4, 1 }, + { "AMLOCK3", 3, 1 }, + { "AMLOCK2", 2, 1 }, + { "AMLOCK1", 1, 1 }, + { "AMLOCK0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x39ed4, 0 }, + { "AMLOCK19", 11, 1 }, + { "AMLOCK18", 10, 1 }, + { "AMLOCK17", 9, 1 }, + { "AMLOCK16", 8, 1 }, + { "AMLOCK15", 7, 1 }, + { "AMLOCK14", 6, 1 }, + { "AMLOCK13", 5, 1 }, + { "AMLOCK12", 4, 1 }, + { "AMLOCK11", 3, 1 }, + { "AMLOCK10", 2, 1 }, + { "AMLOCK9", 1, 1 }, + { "AMLOCK8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x39f68, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x39f6c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x39f70, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x39f74, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x39f78, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x39f7c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x39f80, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x39f84, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x39f88, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x39f8c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x39f90, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x39f94, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x39f98, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x39f9c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x39fa0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x39fa4, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x39fa8, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x39fac, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x39fb0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x39fb4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x39fb8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x39fbc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x39fc0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x39fc4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x39fc8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x39fcc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x39fd0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x39fd4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x39fd8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x39fdc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x39fe0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x39fe4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x39fe8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x39fec, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x39ff0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x39ff4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x39ff8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x39ffc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3a000, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3a004, 0 }, + { "MAC_PORT_BEAN_CTL", 0x3a200, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS", 0x3a204, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0", 0x3a208, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1", 0x3a20c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2", 0x3a210, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0", 0x3a214, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1", 0x3a218, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3a21c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT", 0x3a220, 0 }, + { "MAC_PORT_BEAN_XNP_0", 0x3a224, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1", 0x3a228, 0 }, + { "MAC_PORT_BEAN_XNP_2", 0x3a22c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0", 0x3a230, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1", 0x3a234, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2", 0x3a238, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS", 0x3a23c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE1", 0x3a240, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE1", 0x3a244, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3a248, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3a24c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3a250, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3a254, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3a258, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3a25c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3a260, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE1", 0x3a264, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE1", 0x3a268, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3a26c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3a270, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3a274, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3a278, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3a27c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE2", 0x3a280, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE2", 0x3a284, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3a288, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3a28c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3a290, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3a294, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3a298, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3a29c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3a2a0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE2", 0x3a2a4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE2", 0x3a2a8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE2", 0x3a2ac, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3a2b0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3a2b4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3a2b8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3a2bc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE3", 0x3a2c0, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE3", 0x3a2c4, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3a2c8, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3a2cc, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3a2d0, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3a2d4, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3a2d8, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3a2dc, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3a2e0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE3", 0x3a2e4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE3", 0x3a2e8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE3", 0x3a2ec, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3a2f0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3a2f4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3a2f8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3a2fc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_FEC_KR_CONTROL", 0x3a600, 0 }, + { "enable_tr", 1, 1 }, + { "restart_tr", 0, 1 }, + { "MAC_PORT_FEC_KR_STATUS", 0x3a604, 0 }, + { "fecKRsigdet", 15, 1 }, + { "train_fail", 3, 1 }, + { "startup_status", 2, 1 }, + { "frame_lock", 1, 1 }, + { "rx_status", 0, 1 }, + { "MAC_PORT_FEC_KR_LP_COEFF", 0x3a608, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LP_STAT", 0x3a60c, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_COEFF", 0x3a610, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_STAT", 0x3a614, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_ABILITY", 0x3a618, 0 }, + { "fec_ind_ability", 1, 1 }, + { "ability", 0, 1 }, + { "MAC_PORT_FEC_CONTROL", 0x3a61c, 0 }, + { "fec_en_err_ind", 1, 1 }, + { "fec_en", 0, 1 }, + { "MAC_PORT_FEC_STATUS", 0x3a620, 0 }, + { "FEC_LOCKED_100", 1, 1 }, + { "FEC_LOCKED", 0, 1 }, + { "MAC_PORT_FEC_CERR_CNT_0", 0x3a624, 0 }, + { "MAC_PORT_FEC_CERR_CNT_1", 0x3a628, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_0", 0x3a62c, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_1", 0x3a630, 0 }, + { "MAC_PORT_AE_RX_COEF_REQ", 0x3aa00, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT", 0x3aa04, 0 }, + { "T5_AE0_RXSTAT_RDY", 15, 1 }, + { "T5_AE0_RXSTAT_C2", 4, 2 }, + { "T5_AE0_RXSTAT_C1", 2, 2 }, + { "T5_AE0_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ", 0x3aa08, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT", 0x3aa0c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE", 0x3aa10, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL", 0x3aa14, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL", 0x3aa18, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE", 0x3aa1c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_1", 0x3aa20, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_1", 0x3aa24, 0 }, + { "T5_AE1_RXSTAT_RDY", 15, 1 }, + { "T5_AE1_RXSTAT_C2", 4, 2 }, + { "T5_AE1_RXSTAT_C1", 2, 2 }, + { "T5_AE1_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_1", 0x3aa28, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_1", 0x3aa2c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_1", 0x3aa30, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_1", 0x3aa34, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_1", 0x3aa38, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_1", 0x3aa3c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_2", 0x3aa40, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_2", 0x3aa44, 0 }, + { "T5_AE2_RXSTAT_RDY", 15, 1 }, + { "T5_AE2_RXSTAT_C2", 4, 2 }, + { "T5_AE2_RXSTAT_C1", 2, 2 }, + { "T5_AE2_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_2", 0x3aa48, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_2", 0x3aa4c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_2", 0x3aa50, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_2", 0x3aa54, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_2", 0x3aa58, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_2", 0x3aa5c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_3", 0x3aa60, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_3", 0x3aa64, 0 }, + { "T5_AE3_RXSTAT_RDY", 15, 1 }, + { "T5_AE3_RXSTAT_C2", 4, 2 }, + { "T5_AE3_RXSTAT_C1", 2, 2 }, + { "T5_AE3_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_3", 0x3aa68, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_3", 0x3aa6c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_3", 0x3aa70, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_3", 0x3aa74, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_3", 0x3aa78, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_3", 0x3aa7c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_TX_DIS", 0x3aa80, 0 }, + { "MAC_PORT_AE_KR_CTRL", 0x3aa84, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET", 0x3aa88, 0 }, + { "MAC_PORT_AE_KR_STATUS", 0x3aa8c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_1", 0x3aa90, 0 }, + { "MAC_PORT_AE_KR_CTRL_1", 0x3aa94, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_1", 0x3aa98, 0 }, + { "MAC_PORT_AE_KR_STATUS_1", 0x3aa9c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_2", 0x3aaa0, 0 }, + { "MAC_PORT_AE_KR_CTRL_2", 0x3aaa4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_2", 0x3aaa8, 0 }, + { "MAC_PORT_AE_KR_STATUS_2", 0x3aaac, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_3", 0x3aab0, 0 }, + { "MAC_PORT_AE_KR_CTRL_3", 0x3aab4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_3", 0x3aab8, 0 }, + { "MAC_PORT_AE_KR_STATUS_3", 0x3aabc, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3ab00, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3ab04, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_0", 0x3ab08, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3ab0c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_0", 0x3ab10, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3ab20, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3ab24, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_1", 0x3ab28, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3ab2c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_1", 0x3ab30, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3ab40, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3ab44, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_2", 0x3ab48, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3ab4c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_2", 0x3ab50, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3ab60, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3ab64, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_3", 0x3ab68, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3ab6c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_3", 0x3ab70, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_ANALOG_TEST_MUX", 0x3b814, 0 }, + { "MAC_PORT_BANDGAP_CONTROL", 0x3b82c, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3b880, 0 }, + { "RCCTL1", 5, 1 }, + { "RCCTL0", 4, 1 }, + { "RCAMP1", 3, 1 }, + { "RCAMP0", 2, 1 }, + { "RCAMPEN", 1, 1 }, + { "RCRST", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3b884, 0 }, + { "RCERR", 1, 1 }, + { "RCCOMP", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3b888, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3b88c, 0 }, + { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3b8e8, 0 }, + { "LBIST", 7, 1 }, + { "LOGICTEST", 6, 1 }, + { "MAVDHI", 5, 1 }, + { "AUXEN", 4, 1 }, + { "JTAGMD", 3, 1 }, + { "RXACMODE", 2, 1 }, + { "HSSACJPC", 1, 1 }, + { "HSSACJAC", 0, 1 }, + { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3b8ec, 0 }, + { "REFVALIDD", 6, 1 }, + { "REFVALIDC", 5, 1 }, + { "REFVALIDB", 4, 1 }, + { "REFVALIDA", 3, 1 }, + { "REFSELRESET", 2, 1 }, + { "SOFTRESET", 1, 1 }, + { "MACROTEST", 0, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3bb00, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3bb04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3bb08, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3bb0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3bb10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3bb28, 0 }, + { "MAC_PORT_PLLA_PCLK_CONTROL", 0x3bb3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3bb40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bb44, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bb48, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bb4c, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bb50, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3bbf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3bbf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3bbf8, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3bbfc, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3bc00, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3bc04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3bc08, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3bc0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3bc10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3bc28, 0 }, + { "MAC_PORT_PLLB_PCLK_CONTROL", 0x3bc3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3bc40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bc44, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bc48, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bc4c, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bc50, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3bcf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3bcf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3bcf8, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3bcfc, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3b000, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3b004, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3b008, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b00c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b010, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b014, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b018, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b01c, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3b020, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3b024, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3b028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3b030, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3b034, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b038, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b03c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b040, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b044, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b048, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b060, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b064, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b068, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b070, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b074, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b078, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b07c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b080, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b084, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b088, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3b08c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3b090, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3b094, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3b098, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3b09c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b0f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b0f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b0f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b0fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3b100, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3b104, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3b108, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b10c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b110, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b114, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b118, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b11c, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3b120, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3b124, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3b128, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3b130, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3b134, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b138, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b13c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b140, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b144, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b148, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b160, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b164, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b168, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b170, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b174, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b178, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b17c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b180, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b184, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b188, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3b18c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3b190, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3b194, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3b198, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3b19c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b1f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b1f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b1f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b1fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3b400, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3b404, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3b408, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b40c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b410, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b414, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b418, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b41c, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3b420, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3b424, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3b428, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3b430, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3b434, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b438, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b43c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b440, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b444, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b448, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b460, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b464, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b468, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b470, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b474, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b478, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b47c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b480, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b484, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b488, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3b48c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3b490, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3b494, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3b498, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3b49c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b4f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b4f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b4f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b4fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3b500, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3b504, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3b508, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b50c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b510, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b514, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b518, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b51c, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3b520, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3b524, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3b528, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3b530, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3b534, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b538, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b53c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b540, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b544, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b548, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b560, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b564, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b568, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b570, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b574, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b578, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b57c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b580, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b584, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b588, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3b58c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3b590, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3b594, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3b598, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3b59c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b5f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b5f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b5f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b5fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3b900, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3b904, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3b908, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b90c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b910, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b914, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b918, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b91c, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3b920, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3b924, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3b928, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3b930, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3b934, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b938, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b93c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b940, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b944, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b948, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b960, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b964, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b968, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b970, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b974, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b978, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b97c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b980, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b984, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b988, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3b98c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3b990, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3b994, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3b998, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3b99c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b9f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b9f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b9f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b9fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 }, + { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3b200, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3b204, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3b208, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b20c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3b210, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3b214, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b218, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b21c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3b220, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3b224, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3b228, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3b22c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3b230, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3b234, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3b238, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3b240, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3b248, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b24c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3b250, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b25c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b260, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b264, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b270, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3b274, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3b278, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3b27c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3b280, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3b284, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3b288, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3b28c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3b290, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3b294, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3b298, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3b29c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b2a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3b2a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3b2a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3b2ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b2b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b2b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b2b8, 0 }, + { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3b2c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKA_DFE_H1", 0x3b2c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H2", 0x3b2c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_H3", 0x3b2cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H4", 0x3b2d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H5", 0x3b2d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3b2d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3b2dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3b2e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H12", 0x3b2e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b2f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b2fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3b300, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3b304, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3b308, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b30c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3b310, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3b314, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b318, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b31c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3b320, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3b324, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3b328, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3b32c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3b330, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3b334, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3b338, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3b340, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3b348, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b34c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3b350, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b35c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b360, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b364, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b370, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3b374, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3b378, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3b37c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3b380, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3b384, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3b388, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3b38c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3b390, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3b394, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3b398, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3b39c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b3a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3b3a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3b3a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3b3ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b3b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b3b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b3b8, 0 }, + { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3b3c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKB_DFE_H1", 0x3b3c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H2", 0x3b3c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_H3", 0x3b3cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H4", 0x3b3d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H5", 0x3b3d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3b3d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3b3dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3b3e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H12", 0x3b3e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b3f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b3fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3b600, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3b604, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3b608, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b60c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3b610, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3b614, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b618, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b61c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3b620, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3b624, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3b628, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3b62c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3b630, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3b634, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3b638, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3b640, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3b648, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b64c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3b650, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b65c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b660, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b664, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b670, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3b674, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3b678, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3b67c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3b680, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3b684, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3b688, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3b68c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3b690, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3b694, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3b698, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3b69c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b6a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3b6a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3b6a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3b6ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b6b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b6b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b6b8, 0 }, + { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3b6c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKC_DFE_H1", 0x3b6c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H2", 0x3b6c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_H3", 0x3b6cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H4", 0x3b6d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H5", 0x3b6d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3b6d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3b6dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3b6e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H12", 0x3b6e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b6f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b6fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3b700, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3b704, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3b708, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b70c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3b710, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3b714, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b718, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b71c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3b720, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3b724, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3b728, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3b72c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3b730, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3b734, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3b738, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3b740, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3b748, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b74c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3b750, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b75c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b760, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b764, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b770, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3b774, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3b778, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3b77c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3b780, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3b784, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3b788, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3b78c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3b790, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3b794, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3b798, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3b79c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b7a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3b7a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3b7a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3b7ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b7b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b7b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b7b8, 0 }, + { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3b7c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKD_DFE_H1", 0x3b7c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H2", 0x3b7c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_H3", 0x3b7cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H4", 0x3b7d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H5", 0x3b7d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3b7d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3b7dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3b7e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H12", 0x3b7e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b7f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b7fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3ba00, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3ba04, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3ba08, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3ba0c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3ba10, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3ba14, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3ba18, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3ba1c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3ba20, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3ba24, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3ba28, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3ba2c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3ba30, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3ba34, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3ba38, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3ba40, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3ba48, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3ba4c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3ba50, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3ba5c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3ba60, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3ba64, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3ba70, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3ba74, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3ba78, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3ba7c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3ba80, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3ba84, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3ba88, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3ba8c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3ba90, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3ba94, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3ba98, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3ba9c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3baa0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3baa4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3baa8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3baac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3bab0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3bab4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3bab8, 0 }, + { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3bac0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3bac4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3bac8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3bacc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3bad0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3bad4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3bad8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3badc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3bae0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3bae4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3baf8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3bafc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_CFG", 0x3c800, 0 }, + { "MAC_Clk_Sel", 29, 3 }, + { "SinkTx", 27, 1 }, + { "SinkTxOnLinkDown", 26, 1 }, + { "LoopNoFwd", 24, 1 }, + { "Smux_Rx_Loop", 19, 1 }, + { "Rx_Lane_Swap", 18, 1 }, + { "Tx_Lane_Swap", 17, 1 }, + { "Signal_Det", 14, 1 }, + { "SmuxTxSel", 9, 1 }, + { "SmuxRxSel", 8, 1 }, + { "PortSpeed", 4, 2 }, + { "Rx_Byte_Swap", 3, 1 }, + { "Tx_Byte_Swap", 2, 1 }, + { "Port_Sel", 0, 1 }, + { "MAC_PORT_RESET_CTRL", 0x3c804, 0 }, + { "TWGDSK_HSSC16B", 31, 1 }, + { "EEE_RESET", 30, 1 }, + { "PTP_TIMER", 29, 1 }, + { "MtipRefReset", 28, 1 }, + { "MtipTxffReset", 27, 1 }, + { "MtipRxffReset", 26, 1 }, + { "MtipRegReset", 25, 1 }, + { "AEC3Reset", 23, 1 }, + { "AEC2Reset", 22, 1 }, + { "AEC1Reset", 21, 1 }, + { "AEC0Reset", 20, 1 }, + { "AET3Reset", 19, 1 }, + { "AET2Reset", 18, 1 }, + { "AET1Reset", 17, 1 }, + { "AET0Reset", 16, 1 }, + { "TXIF_Reset", 12, 1 }, + { "RXIF_Reset", 11, 1 }, + { "AuxExt_Reset", 10, 1 }, + { "MtipSd3TxRst", 9, 1 }, + { "MtipSd2TxRst", 8, 1 }, + { "MtipSd1TxRst", 7, 1 }, + { "MtipSd0TxRst", 6, 1 }, + { "MtipSd3RxRst", 5, 1 }, + { "MtipSd2RxRst", 4, 1 }, + { "MtipSd1RxRst", 3, 1 }, + { "WOL_Reset", 2, 1 }, + { "MtipSd0RxRst", 1, 1 }, + { "HSS_Reset", 0, 1 }, + { "MAC_PORT_LED_CFG", 0x3c808, 0 }, + { "Led1_Cfg", 5, 3 }, + { "Led1_Polarity_Inv", 4, 1 }, + { "Led0_Cfg", 1, 3 }, + { "Led0_Polarity_Inv", 0, 1 }, + { "MAC_PORT_LED_COUNTHI", 0x3c80c, 0 }, + { "MAC_PORT_LED_COUNTLO", 0x3c810, 0 }, + { "MAC_PORT_CFG3", 0x3c814, 0 }, + { "FPGA_PTP_PORT", 26, 2 }, + { "FCSDisCtrl", 25, 1 }, + { "SigDetCtrl", 24, 1 }, + { "tx_lane", 23, 1 }, + { "rx_lane", 22, 1 }, + { "se_clr", 21, 1 }, + { "an_ena", 17, 4 }, + { "sd_rx_clk_ena", 13, 4 }, + { "sd_tx_clk_ena", 9, 4 }, + { "SGMIISEL", 8, 1 }, + { "HSSPLLSEL", 4, 4 }, + { "HSSC16C20SEL", 0, 4 }, + { "MAC_PORT_CFG2", 0x3c818, 0 }, + { "Rx_Polarity_Inv", 28, 4 }, + { "Tx_Polarity_Inv", 24, 4 }, + { "InstanceNum", 22, 2 }, + { "StopOnPerr", 21, 1 }, + { "PatEn", 18, 1 }, + { "MagicEn", 17, 1 }, + { "T5_AEC_PMA_TX_READY", 4, 4 }, + { "T5_AEC_PMA_RX_READY", 0, 4 }, + { "MAC_PORT_PKT_COUNT", 0x3c81c, 0 }, + { "tx_sop_count", 24, 8 }, + { "tx_eop_count", 16, 8 }, + { "rx_sop_count", 8, 8 }, + { "rx_eop_count", 0, 8 }, + { "MAC_PORT_CFG4", 0x3c820, 0 }, + { "AEC3_RX_WIDTH", 14, 2 }, + { "AEC2_RX_WIDTH", 12, 2 }, + { "AEC1_RX_WIDTH", 10, 2 }, + { "AEC0_RX_WIDTH", 8, 2 }, + { "AEC3_TX_WIDTH", 6, 2 }, + { "AEC2_TX_WIDTH", 4, 2 }, + { "AEC1_TX_WIDTH", 2, 2 }, + { "AEC0_TX_WIDTH", 0, 2 }, + { "MAC_PORT_MAGIC_MACID_LO", 0x3c824, 0 }, + { "MAC_PORT_MAGIC_MACID_HI", 0x3c828, 0 }, + { "MAC_PORT_LINK_STATUS", 0x3c834, 0 }, + { "an_done", 6, 1 }, + { "align_done", 5, 1 }, + { "block_lock", 4, 1 }, + { "remflt", 3, 1 }, + { "locflt", 2, 1 }, + { "linkup", 1, 1 }, + { "linkdn", 0, 1 }, + { "MAC_PORT_EPIO_DATA0", 0x3c8c0, 0 }, + { "MAC_PORT_EPIO_DATA1", 0x3c8c4, 0 }, + { "MAC_PORT_EPIO_DATA2", 0x3c8c8, 0 }, + { "MAC_PORT_EPIO_DATA3", 0x3c8cc, 0 }, + { "MAC_PORT_EPIO_OP", 0x3c8d0, 0 }, + { "Busy", 31, 1 }, + { "Write", 8, 1 }, + { "Address", 0, 8 }, + { "MAC_PORT_WOL_STATUS", 0x3c8d4, 0 }, + { "MagicDetected", 31, 1 }, + { "PatDetected", 30, 1 }, + { "ClearMagic", 4, 1 }, + { "ClearMatch", 3, 1 }, + { "MatchedFilter", 0, 3 }, + { "MAC_PORT_INT_EN", 0x3c8d8, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_INT_CAUSE", 0x3c8dc, 0 }, + { "tx_ts_avail", 29, 1 }, + { "PatDetWake", 26, 1 }, + { "MagicWake", 25, 1 }, + { "SigDetChg", 24, 1 }, + { "AE_Train_Local", 22, 1 }, + { "HSSPLL_LOCK", 21, 1 }, + { "HSSPRT_READY", 20, 1 }, + { "AutoNeg_Done", 19, 1 }, + { "PCS_Link_Good", 12, 1 }, + { "PCS_Link_Fail", 11, 1 }, + { "RxFifoOverFlow", 10, 1 }, + { "HSSPRBSErr", 9, 1 }, + { "HSSEyeQual", 8, 1 }, + { "RemoteFault", 7, 1 }, + { "LocalFault", 6, 1 }, + { "MAC_Link_Down", 5, 1 }, + { "MAC_Link_Up", 4, 1 }, + { "an_page_rcvd", 2, 1 }, + { "TxFifo_prty_err", 1, 1 }, + { "RxFifo_prty_err", 0, 1 }, + { "MAC_PORT_PERR_INT_EN", 0x3c8e0, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INT_CAUSE", 0x3c8e4, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_ENABLE", 0x3c8e8, 0 }, + { "Perr_pkt_ram", 24, 1 }, + { "Perr_mask_ram", 23, 1 }, + { "Perr_crc_ram", 22, 1 }, + { "rx_dff_seg0", 21, 1 }, + { "rx_sff_seg0", 20, 1 }, + { "rx_dff_mac10", 19, 1 }, + { "rx_sff_mac10", 18, 1 }, + { "tx_dff_seg0", 17, 1 }, + { "tx_sff_seg0", 16, 1 }, + { "tx_dff_mac10", 15, 1 }, + { "tx_sff_mac10", 14, 1 }, + { "rx_stats", 13, 1 }, + { "tx_stats", 12, 1 }, + { "Perr3_rx_mix", 11, 1 }, + { "Perr3_rx_sd", 10, 1 }, + { "Perr3_tx", 9, 1 }, + { "Perr2_rx_mix", 8, 1 }, + { "Perr2_rx_sd", 7, 1 }, + { "Perr2_tx", 6, 1 }, + { "Perr1_rx_mix", 5, 1 }, + { "Perr1_rx_sd", 4, 1 }, + { "Perr1_tx", 3, 1 }, + { "Perr0_rx_mix", 2, 1 }, + { "Perr0_rx_sd", 1, 1 }, + { "Perr0_tx", 0, 1 }, + { "MAC_PORT_PERR_INJECT", 0x3c8ec, 0 }, + { "MemSel", 1, 5 }, + { "InjectDataErr", 0, 1 }, + { "MAC_PORT_HSS_CFG0", 0x3c8f0, 0 }, + { "TXDTS", 31, 1 }, + { "TXCTS", 30, 1 }, + { "TXBTS", 29, 1 }, + { "TXATS", 28, 1 }, + { "TXDOBS", 27, 1 }, + { "TXCOBS", 26, 1 }, + { "TXBOBS", 25, 1 }, + { "TXAOBS", 24, 1 }, + { "HSSREFCLKVALIDA", 20, 1 }, + { "HSSREFCLKVALIDB", 19, 1 }, + { "HSSRESYNCA", 18, 1 }, + { "HSSAVDHI", 17, 1 }, + { "HSSRESYNCB", 16, 1 }, + { "HSSRECCALA", 15, 1 }, + { "HSSRXACMODE", 14, 1 }, + { "HSSRECCALB", 13, 1 }, + { "HSSPLLBYPA", 12, 1 }, + { "HSSPLLBYPB", 11, 1 }, + { "HSSPDWNPLLA", 10, 1 }, + { "HSSPDWNPLLB", 9, 1 }, + { "HSSVCOSELA", 8, 1 }, + { "HSSVCOSELB", 7, 1 }, + { "HSSCALCOMP", 6, 1 }, + { "HSSCALENAB", 5, 1 }, + { "HSSEXTC16SEL", 4, 1 }, + { "MAC_PORT_HSS_CFG1", 0x3c8f4, 0 }, + { "RXACONFIGSEL", 30, 2 }, + { "RXAQUIET", 29, 1 }, + { "RXAREFRESH", 28, 1 }, + { "RXBCONFIGSEL", 26, 2 }, + { "RXBQUIET", 25, 1 }, + { "RXBREFRESH", 24, 1 }, + { "RXCCONFIGSEL", 22, 2 }, + { "RXCQUIET", 21, 1 }, + { "RXCREFRESH", 20, 1 }, + { "RXDCONFIGSEL", 18, 2 }, + { "RXDQUIET", 17, 1 }, + { "RXDREFRESH", 16, 1 }, + { "TXACONFIGSEL", 14, 2 }, + { "TXAQUIET", 13, 1 }, + { "TXAREFRESH", 12, 1 }, + { "TXBCONFIGSEL", 10, 2 }, + { "TXBQUIET", 9, 1 }, + { "TXBREFRESH", 8, 1 }, + { "TXCCONFIGSEL", 6, 2 }, + { "TXCQUIET", 5, 1 }, + { "TXCREFRESH", 4, 1 }, + { "TXDCONFIGSEL", 2, 2 }, + { "TXDQUIET", 1, 1 }, + { "TXDREFRESH", 0, 1 }, + { "MAC_PORT_HSS_CFG2", 0x3c8f8, 0 }, + { "RXAASSTCLK", 31, 1 }, + { "T5RXAPRBSRST", 30, 1 }, + { "RXBASSTCLK", 29, 1 }, + { "T5RXBPRBSRST", 28, 1 }, + { "RXCASSTCLK", 27, 1 }, + { "T5RXCPRBSRST", 26, 1 }, + { "RXDASSTCLK", 25, 1 }, + { "T5RXDPRBSRST", 24, 1 }, + { "RXDDATASYNC", 23, 1 }, + { "RXCDATASYNC", 22, 1 }, + { "RXBDATASYNC", 21, 1 }, + { "RXADATASYNC", 20, 1 }, + { "RXDEARLYIN", 19, 1 }, + { "RXDLATEIN", 18, 1 }, + { "RXDPHSLOCK", 17, 1 }, + { "RXDPHSDNIN", 16, 1 }, + { "RXDPHSUPIN", 15, 1 }, + { "RXCEARLYIN", 14, 1 }, + { "RXCLATEIN", 13, 1 }, + { "RXCPHSLOCK", 12, 1 }, + { "RXCPHSDNIN", 11, 1 }, + { "RXCPHSUPIN", 10, 1 }, + { "RXBEARLYIN", 9, 1 }, + { "RXBLATEIN", 8, 1 }, + { "RXBPHSLOCK", 7, 1 }, + { "RXBPHSDNIN", 6, 1 }, + { "RXBPHSUPIN", 5, 1 }, + { "RXAEARLYIN", 4, 1 }, + { "RXALATEIN", 3, 1 }, + { "RXAPHSLOCK", 2, 1 }, + { "RXAPHSDNIN", 1, 1 }, + { "RXAPHSUPIN", 0, 1 }, + { "MAC_PORT_HSS_CFG3", 0x3c8fc, 0 }, + { "HSSCALSSTN", 25, 3 }, + { "HSSCALSSTP", 22, 3 }, + { "HSSVBOOSTDIVB", 19, 3 }, + { "HSSVBOOSTDIVA", 16, 3 }, + { "HSSPLLCONFIGB", 8, 8 }, + { "HSSPLLCONFIGA", 0, 8 }, + { "MAC_PORT_HSS_CFG4", 0x3c900, 0 }, + { "HSSDIVSELA", 9, 9 }, + { "HSSDIVSELB", 0, 9 }, + { "MAC_PORT_HSS_STATUS", 0x3c904, 0 }, + { "RXDPRBSSYNC", 15, 1 }, + { "RXCPRBSSYNC", 14, 1 }, + { "RXBPRBSSYNC", 13, 1 }, + { "RXAPRBSSYNC", 12, 1 }, + { "RXDPRBSERR", 11, 1 }, + { "RXCPRBSERR", 10, 1 }, + { "RXBPRBSERR", 9, 1 }, + { "RXAPRBSERR", 8, 1 }, + { "RXDSIGDET", 7, 1 }, + { "RXCSIGDET", 6, 1 }, + { "RXBSIGDET", 5, 1 }, + { "RXASIGDET", 4, 1 }, + { "HSSPLLLOCKB", 3, 1 }, + { "HSSPLLLOCKA", 2, 1 }, + { "HSSPRTREADYB", 1, 1 }, + { "HSSPRTREADYA", 0, 1 }, + { "MAC_PORT_HSS_EEE_STATUS", 0x3c908, 0 }, + { "RXAQUIET_STATUS", 15, 1 }, + { "RXAREFRESH_STATUS", 14, 1 }, + { "RXBQUIET_STATUS", 13, 1 }, + { "RXBREFRESH_STATUS", 12, 1 }, + { "RXCQUIET_STATUS", 11, 1 }, + { "RXCREFRESH_STATUS", 10, 1 }, + { "RXDQUIET_STATUS", 9, 1 }, + { "RXDREFRESH_STATUS", 8, 1 }, + { "TXAQUIET_STATUS", 7, 1 }, + { "TXAREFRESH_STATUS", 6, 1 }, + { "TXBQUIET_STATUS", 5, 1 }, + { "TXBREFRESH_STATUS", 4, 1 }, + { "TXCQUIET_STATUS", 3, 1 }, + { "TXCREFRESH_STATUS", 2, 1 }, + { "TXDQUIET_STATUS", 1, 1 }, + { "TXDREFRESH_STATUS", 0, 1 }, + { "MAC_PORT_HSS_SIGDET_STATUS", 0x3c90c, 0 }, + { "MAC_PORT_HSS_PL_CTL", 0x3c910, 0 }, + { "TOV", 16, 8 }, + { "TSU", 8, 8 }, + { "IPW", 0, 8 }, + { "MAC_PORT_RUNT_FRAME", 0x3c914, 0 }, + { "runtclear", 16, 1 }, + { "runt", 0, 16 }, + { "MAC_PORT_EEE_STATUS", 0x3c918, 0 }, + { "eee_tx_10g_state", 10, 2 }, + { "eee_rx_10g_state", 8, 2 }, + { "eee_tx_1g_state", 6, 2 }, + { "eee_rx_1g_state", 4, 2 }, + { "pma_rx_refresh", 3, 1 }, + { "pma_rx_quiet", 2, 1 }, + { "pma_tx_refresh", 1, 1 }, + { "pma_tx_quiet", 0, 1 }, + { "MAC_PORT_CGEN", 0x3c91c, 0 }, + { "CGEN", 8, 1 }, + { "sd7_CGEN", 7, 1 }, + { "sd6_CGEN", 6, 1 }, + { "sd5_CGEN", 5, 1 }, + { "sd4_CGEN", 4, 1 }, + { "sd3_CGEN", 3, 1 }, + { "sd2_CGEN", 2, 1 }, + { "sd1_CGEN", 1, 1 }, + { "sd0_CGEN", 0, 1 }, + { "MAC_PORT_CGEN_MTIP", 0x3c920, 0 }, + { "MACSEG5_CGEN", 11, 1 }, + { "PCSSEG5_CGEN", 10, 1 }, + { "MACSEG4_CGEN", 9, 1 }, + { "PCSSEG4_CGEN", 8, 1 }, + { "MACSEG3_CGEN", 7, 1 }, + { "PCSSEG3_CGEN", 6, 1 }, + { "MACSEG2_CGEN", 5, 1 }, + { "PCSSEG2_CGEN", 4, 1 }, + { "MACSEG1_CGEN", 3, 1 }, + { "PCSSEG1_CGEN", 2, 1 }, + { "MACSEG0_CGEN", 1, 1 }, + { "PCSSEG0_CGEN", 0, 1 }, + { "MAC_PORT_TX_TS_ID", 0x3c924, 0 }, + { "MAC_PORT_TX_TS_VAL_LO", 0x3c928, 0 }, + { "MAC_PORT_TX_TS_VAL_HI", 0x3c92c, 0 }, + { "MAC_PORT_EEE_CTL", 0x3c930, 0 }, + { "EEE_CTRL", 2, 30 }, + { "TICK_START", 1, 1 }, + { "En", 0, 1 }, + { "MAC_PORT_EEE_TX_CTL", 0x3c934, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_ACTIVE", 3, 1 }, + { "LPI_TXHOLD", 2, 1 }, + { "LPI_REQ", 1, 1 }, + { "EEE_TX_RESET", 0, 1 }, + { "MAC_PORT_EEE_RX_CTL", 0x3c938, 0 }, + { "WAKE_TIMER", 16, 16 }, + { "HSS_TIMER", 5, 4 }, + { "HSS_CTL", 4, 1 }, + { "LPI_IND", 1, 1 }, + { "EEE_RX_RESET", 0, 1 }, + { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3c93c, 0 }, + { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x3c940, 0 }, + { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x3c944, 0 }, + { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x3c948, 0 }, + { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3c94c, 0 }, + { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x3c950, 0 }, + { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x3c954, 0 }, + { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x3c958, 0 }, + { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3c95c, 0 }, + { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x3c960, 0 }, + { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x3c964, 0 }, + { "MAC_PORT_EEE_WF_COUNT", 0x3c968, 0 }, + { "wake_cnt_clr", 16, 1 }, + { "wake_cnt", 0, 16 }, + { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3c96c, 0 }, + { "MAC_PORT_PTP_TIMER_RD0_HI", 0x3c970, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_LO", 0x3c974, 0 }, + { "MAC_PORT_PTP_TIMER_RD1_HI", 0x3c978, 0 }, + { "MAC_PORT_PTP_TIMER_WR_LO", 0x3c97c, 0 }, + { "MAC_PORT_PTP_TIMER_WR_HI", 0x3c980, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x3c984, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x3c988, 0 }, + { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3c98c, 0 }, + { "MAC_PORT_PTP_SUM_LO", 0x3c990, 0 }, + { "MAC_PORT_PTP_SUM_HI", 0x3c994, 0 }, + { "MAC_PORT_PTP_TIMER_INCR0", 0x3c998, 0 }, + { "Y", 16, 16 }, + { "X", 0, 16 }, + { "MAC_PORT_PTP_TIMER_INCR1", 0x3c99c, 0 }, + { "Y_TICK", 16, 16 }, + { "X_TICK", 0, 16 }, + { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x3c9a0, 0 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x3c9a4, 0 }, + { "B", 16, 16 }, + { "A", 0, 16 }, + { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x3c9a8, 0 }, + { "MAC_PORT_PTP_CFG", 0x3c9ac, 0 }, + { "FRZ", 18, 1 }, + { "OFFSER_ADJUST_SIGN", 17, 1 }, + { "ADD_OFFSET", 16, 1 }, + { "CYCLE1", 8, 8 }, + { "Q", 0, 8 }, + { "MAC_PORT_MTIP_REVISION", 0x3ca00, 0 }, + { "CUSTREV", 16, 16 }, + { "VER", 8, 8 }, + { "REV", 0, 8 }, + { "MAC_PORT_MTIP_SCRATCH", 0x3ca04, 0 }, + { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x3ca08, 0 }, + { "TX_FLUSH", 22, 1 }, + { "RX_SFD_ANY", 21, 1 }, + { "PAUSE_PFC_COMP", 20, 1 }, + { "PFC_MODE", 19, 1 }, + { "RS_COL_CNT_EXT", 18, 1 }, + { "NO_LGTH_CHECK", 17, 1 }, + { "SEND_IDLE", 16, 1 }, + { "PHY_TXENA", 15, 1 }, + { "RX_ERR_DISC", 14, 1 }, + { "CMD_FRAME_ENA", 13, 1 }, + { "SW_RESET", 12, 1 }, + { "TX_PAD_EN", 11, 1 }, + { "LOOPBACK_EN", 10, 1 }, + { "TX_ADDR_INS", 9, 1 }, + { "PAUSE_IGNORE", 8, 1 }, + { "PAUSE_FWD", 7, 1 }, + { "CRC_FWD", 6, 1 }, + { "PAD_EN", 5, 1 }, + { "PROMIS_EN", 4, 1 }, + { "WAN_MODE", 3, 1 }, + { "RX_ENA", 1, 1 }, + { "TX_ENA", 0, 1 }, + { "MAC_PORT_MTIP_MAC_ADDR_0", 0x3ca0c, 0 }, + { "MAC_PORT_MTIP_MAC_ADDR_1", 0x3ca10, 0 }, + { "MAC_PORT_MTIP_FRM_LENGTH", 0x3ca14, 0 }, + { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x3ca1c, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x3ca20, 0 }, + { "AVAIL", 16, 16 }, + { "EMPTY", 0, 16 }, + { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x3ca24, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x3ca28, 0 }, + { "AlmstFull", 16, 16 }, + { "AlmstEmpty", 0, 16 }, + { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x3ca2c, 0 }, + { "ENABLE", 8, 1 }, + { "ADDR", 0, 6 }, + { "MAC_PORT_MTIP_MAC_STATUS", 0x3ca40, 0 }, + { "TS_AVAIL", 3, 1 }, + { "PHY_LOS", 2, 1 }, + { "RX_REM_FAULT", 1, 1 }, + { "RX_LOC_FAULT", 0, 1 }, + { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x3ca44, 0 }, + { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x3ca48, 0 }, + { "MAC_PORT_MTIP_INIT_CREDIT", 0x3ca4c, 0 }, + { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x3ca50, 0 }, + { "MAC_PORT_RX_PAUSE_STATUS", 0x3ca74, 0 }, + { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x3ca7c, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x3ca80, 0 }, + { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x3ca84, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOK", 0x3ca88, 0 }, + { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x3ca8c, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x3ca90, 0 }, + { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x3ca94, 0 }, + { "MAC_PORT_AALIGNMENTERRORS", 0x3ca98, 0 }, + { "MAC_PORT_AALIGNMENTERRORSHI", 0x3ca9c, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x3caa0, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x3caa4, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x3caa8, 0 }, + { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x3caac, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORS", 0x3cab0, 0 }, + { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x3cab4, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORS", 0x3cab8, 0 }, + { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x3cabc, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOK", 0x3cac0, 0 }, + { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x3cac4, 0 }, + { "MAC_PORT_VLANRECEIVEDOK", 0x3cac8, 0 }, + { "MAC_PORT_VLANRECEIVEDOKHI", 0x3cacc, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x3cad0, 0 }, + { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x3cad4, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOK", 0x3cad8, 0 }, + { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x3cadc, 0 }, + { "MAC_PORT_IFINUCASTPKTS", 0x3cae0, 0 }, + { "MAC_PORT_IFINUCASTPKTSHI", 0x3cae4, 0 }, + { "MAC_PORT_IFINMULTICASTPKTS", 0x3cae8, 0 }, + { "MAC_PORT_IFINMULTICASTPKTSHI", 0x3caec, 0 }, + { "MAC_PORT_IFINBROADCASTPKTS", 0x3caf0, 0 }, + { "MAC_PORT_IFINBROADCASTPKTSHI", 0x3caf4, 0 }, + { "MAC_PORT_IFOUTERRORS", 0x3caf8, 0 }, + { "MAC_PORT_IFOUTERRORSHI", 0x3cafc, 0 }, + { "MAC_PORT_IFOUTUCASTPKTS", 0x3cb08, 0 }, + { "MAC_PORT_IFOUTUCASTPKTSHI", 0x3cb0c, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTS", 0x3cb10, 0 }, + { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x3cb14, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTS", 0x3cb18, 0 }, + { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x3cb1c, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x3cb20, 0 }, + { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x3cb24, 0 }, + { "MAC_PORT_ETHERSTATSOCTETS", 0x3cb28, 0 }, + { "MAC_PORT_ETHERSTATSOCTETSHI", 0x3cb2c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS", 0x3cb30, 0 }, + { "MAC_PORT_ETHERSTATSPKTSHI", 0x3cb34, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x3cb38, 0 }, + { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x3cb3c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x3cb40, 0 }, + { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x3cb44, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x3cb48, 0 }, + { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x3cb4c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x3cb50, 0 }, + { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x3cb54, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x3cb58, 0 }, + { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x3cb5c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x3cb60, 0 }, + { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x3cb64, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x3cb68, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x3cb6c, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x3cb70, 0 }, + { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x3cb74, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x3cb78, 0 }, + { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x3cb7c, 0 }, + { "MAC_PORT_ETHERSTATSJABBERS", 0x3cb80, 0 }, + { "MAC_PORT_ETHERSTATSJABBERSHI", 0x3cb84, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x3cb88, 0 }, + { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x3cb8c, 0 }, + { "MAC_PORT_IFINERRORS", 0x3cb90, 0 }, + { "MAC_PORT_IFINERRORSHI", 0x3cb94, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x3cb98, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x3cb9c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x3cba0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x3cba4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x3cba8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x3cbac, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x3cbb0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x3cbb4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x3cbb8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x3cbbc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x3cbc0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x3cbc4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x3cbc8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x3cbcc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x3cbd0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x3cbd4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x3cbd8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x3cbdc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x3cbe0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x3cbe4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x3cbe8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x3cbec, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x3cbf0, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x3cbf4, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x3cbf8, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x3cbfc, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x3cc00, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x3cc04, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x3cc08, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x3cc0c, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x3cc10, 0 }, + { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x3cc14, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x3cc18, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x3cc1c, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x3cc20, 0 }, + { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x3cc24, 0 }, + { "MAC_PORT_MTIP_SGMII_CONTROL", 0x3cd00, 0 }, + { "Reset", 15, 1 }, + { "Loopback", 14, 1 }, + { "sppedsel1", 13, 1 }, + { "AN_EN", 12, 1 }, + { "PWRDWN", 11, 1 }, + { "Isolate", 10, 1 }, + { "AN_RESTART", 9, 1 }, + { "DPLX", 8, 1 }, + { "CollisionTest", 7, 1 }, + { "SpeedSel0", 6, 1 }, + { "MAC_PORT_MTIP_SGMII_STATUS", 0x3cd04, 0 }, + { "100BaseT4", 15, 1 }, + { "100BaseXFullDplx", 14, 1 }, + { "100BaseXHalfDplx", 13, 1 }, + { "10MbpsFullDplx", 12, 1 }, + { "10MbpsHalfDplx", 11, 1 }, + { "100BaseT2FullDplx", 10, 1 }, + { "100BaseT2HalfDplx", 9, 1 }, + { "ExtdStatus", 8, 1 }, + { "AN_Complete", 5, 1 }, + { "SGMII_REM_FAULT", 4, 1 }, + { "AN_Ability", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "JabberDetect", 1, 1 }, + { "ExtdCapability", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x3cd08, 0 }, + { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3cd0c, 0 }, + { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x3cd10, 0 }, + { "NP", 15, 1 }, + { "ACK", 14, 1 }, + { "RF2", 13, 1 }, + { "RF1", 12, 1 }, + { "PS2", 8, 1 }, + { "PS1", 7, 1 }, + { "HD", 6, 1 }, + { "FD", 5, 1 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x3cd14, 0 }, + { "CuLinkStatus", 15, 1 }, + { "ACK", 14, 1 }, + { "CuDplxStatus", 12, 1 }, + { "CuSpeed", 10, 2 }, + { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x3cd18, 0 }, + { "PgRcvd", 1, 1 }, + { "RealTimePgRcvd", 0, 1 }, + { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x3cd1c, 0 }, + { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x3cd20, 0 }, + { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3cd3c, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x3cd48, 0 }, + { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3cd4c, 0 }, + { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x3cd50, 0 }, + { "SGMII_PCS_ENABLE", 5, 1 }, + { "SGMII_HDUPLEX", 4, 1 }, + { "SGMII_SPEED", 2, 2 }, + { "USE_SGMII_AN", 1, 1 }, + { "SGMII_ENA", 0, 1 }, + { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x3d200, 0 }, + { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x3d204, 0 }, + { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x3d208, 0 }, + { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3d20c, 0 }, + { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x3d220, 0 }, + { "MAC_PORT_MTIP_VL_INTVL", 0x3d240, 0 }, + { "VL_INTVL", 1, 1 }, + { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x3d600, 0 }, + { "CLK_DIV", 7, 9 }, + { "CL45_EN", 6, 1 }, + { "disable_preamble", 5, 1 }, + { "mdio_hold_time", 2, 3 }, + { "mdio_read_err", 1, 1 }, + { "mdio_busy", 0, 1 }, + { "MAC_PORT_MTIP_MDIO_COMMAND", 0x3d604, 0 }, + { "read", 15, 1 }, + { "read_incr", 14, 1 }, + { "port_addr", 5, 5 }, + { "dev_addr", 0, 5 }, + { "MAC_PORT_MTIP_MDIO_DATA", 0x3d608, 0 }, + { "readbusy", 31, 1 }, + { "data_word", 0, 16 }, + { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3d60c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_0", 0x3da00, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_1", 0x3da04, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_2", 0x3da08, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_3", 0x3da0c, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_4", 0x3da10, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_5", 0x3da14, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_6", 0x3da18, 0 }, + { "MAC_PORT_MTIP_VLAN_TPID_7", 0x3da1c, 0 }, + { "MAC_PORT_MTIP_PCS_CTL", 0x3de00, 0 }, + { "RESET", 15, 1 }, + { "LPBK", 14, 1 }, + { "SPEED_SEL1", 13, 1 }, + { "LP_MODE", 11, 1 }, + { "SPEED_SEL0", 6, 1 }, + { "SPEED", 2, 4 }, + { "MAC_PORT_MTIP_PCS_STATUS1", 0x3de04, 0 }, + { "FaultDet", 7, 1 }, + { "rx_link_status", 2, 1 }, + { "LoPwrAbl", 1, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x3de08, 0 }, + { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x3de0c, 0 }, + { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x3de10, 0 }, + { "100G", 8, 1 }, + { "40G", 7, 1 }, + { "10BASE_TL", 1, 1 }, + { "10G", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x3de14, 0 }, + { "TC", 6, 1 }, + { "DTEXS", 5, 1 }, + { "PHYXS", 4, 1 }, + { "PCS", 3, 1 }, + { "WIS", 2, 1 }, + { "PMD_PMA", 1, 1 }, + { "CL22", 0, 1 }, + { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x3de18, 0 }, + { "VendDev2", 15, 1 }, + { "VendDev1", 14, 1 }, + { "CL22EXT", 13, 1 }, + { "MAC_PORT_MTIP_PCS_CTL2", 0x3de1c, 0 }, + { "MAC_PORT_MTIP_PCS_STATUS2", 0x3de20, 0 }, + { "Device", 15, 1 }, + { "TxFault", 7, 1 }, + { "RxFault", 6, 1 }, + { "100BASE_R", 5, 1 }, + { "40GBASE_R", 4, 1 }, + { "10GBASE_T", 3, 1 }, + { "10GBASE_W", 2, 1 }, + { "10GBASE_X", 1, 1 }, + { "10GBASE_R", 0, 1 }, + { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x3de38, 0 }, + { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x3de3c, 0 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x3de80, 0 }, + { "RxLinkStatus", 12, 1 }, + { "RESEREVED", 4, 8 }, + { "10GPRBS9", 3, 1 }, + { "10GPRBS31", 2, 1 }, + { "HiBER", 1, 1 }, + { "blocklock", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x3de84, 0 }, + { "blocklockLL", 15, 1 }, + { "HiBERLH", 14, 1 }, + { "HiBERCount", 8, 6 }, + { "ErrBlkCnt", 0, 8 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x3de88, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x3de8c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x3de90, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x3de94, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x3de98, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x3de9c, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x3dea0, 0 }, + { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x3dea4, 0 }, + { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x3dea8, 0 }, + { "TXPRBS9", 6, 1 }, + { "RXPRBS31", 5, 1 }, + { "TXPRBS31", 4, 1 }, + { "TxTestPatEn", 3, 1 }, + { "RxTestPatEn", 2, 1 }, + { "TestPatSel", 1, 1 }, + { "DataPatSel", 0, 1 }, + { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x3deac, 0 }, + { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x3deb0, 0 }, + { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x3deb4, 0 }, + { "HiCountPrsnt", 15, 1 }, + { "BLOCK_CNT_HI", 0, 14 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x3dec8, 0 }, + { "alignstatus", 12, 1 }, + { "Lane7", 7, 1 }, + { "Lane6", 6, 1 }, + { "Lane5", 5, 1 }, + { "Lane4", 4, 1 }, + { "Lane3", 3, 1 }, + { "Lane2", 2, 1 }, + { "Lane1", 1, 1 }, + { "Lane0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x3decc, 0 }, + { "Lane19", 11, 1 }, + { "Lane18", 10, 1 }, + { "Lane17", 9, 1 }, + { "Lane16", 8, 1 }, + { "Lane15", 7, 1 }, + { "Lane14", 6, 1 }, + { "Lane13", 5, 1 }, + { "Lane12", 4, 1 }, + { "Lane11", 3, 1 }, + { "Lane10", 2, 1 }, + { "Lane9", 1, 1 }, + { "Lane8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x3ded0, 0 }, + { "AMLOCK7", 7, 1 }, + { "AMLOCK6", 6, 1 }, + { "AMLOCK5", 5, 1 }, + { "AMLOCK4", 4, 1 }, + { "AMLOCK3", 3, 1 }, + { "AMLOCK2", 2, 1 }, + { "AMLOCK1", 1, 1 }, + { "AMLOCK0", 0, 1 }, + { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x3ded4, 0 }, + { "AMLOCK19", 11, 1 }, + { "AMLOCK18", 10, 1 }, + { "AMLOCK17", 9, 1 }, + { "AMLOCK16", 8, 1 }, + { "AMLOCK15", 7, 1 }, + { "AMLOCK14", 6, 1 }, + { "AMLOCK13", 5, 1 }, + { "AMLOCK12", 4, 1 }, + { "AMLOCK11", 3, 1 }, + { "AMLOCK10", 2, 1 }, + { "AMLOCK9", 1, 1 }, + { "AMLOCK8", 0, 1 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x3df68, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x3df6c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x3df70, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x3df74, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x3df78, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x3df7c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x3df80, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x3df84, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x3df88, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x3df8c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x3df90, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x3df94, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x3df98, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x3df9c, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x3dfa0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x3dfa4, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x3dfa8, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x3dfac, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x3dfb0, 0 }, + { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x3dfb4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x3dfb8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x3dfbc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x3dfc0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x3dfc4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x3dfc8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x3dfcc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x3dfd0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x3dfd4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x3dfd8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x3dfdc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x3dfe0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x3dfe4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x3dfe8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x3dfec, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x3dff0, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x3dff4, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x3dff8, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x3dffc, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3e000, 0 }, + { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3e004, 0 }, + { "MAC_PORT_BEAN_CTL", 0x3e200, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS", 0x3e204, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0", 0x3e208, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1", 0x3e20c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2", 0x3e210, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0", 0x3e214, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1", 0x3e218, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3e21c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT", 0x3e220, 0 }, + { "MAC_PORT_BEAN_XNP_0", 0x3e224, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1", 0x3e228, 0 }, + { "MAC_PORT_BEAN_XNP_2", 0x3e22c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0", 0x3e230, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1", 0x3e234, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2", 0x3e238, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS", 0x3e23c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE1", 0x3e240, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE1", 0x3e244, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3e248, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3e24c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3e250, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3e254, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3e258, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3e25c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3e260, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE1", 0x3e264, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE1", 0x3e268, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3e26c, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3e270, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3e274, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3e278, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3e27c, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE2", 0x3e280, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE2", 0x3e284, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3e288, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3e28c, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3e290, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3e294, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3e298, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3e29c, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3e2a0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE2", 0x3e2a4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE2", 0x3e2a8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE2", 0x3e2ac, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3e2b0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3e2b4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3e2b8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3e2bc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_BEAN_CTL_LANE3", 0x3e2c0, 0 }, + { "AN_RESET", 15, 1 }, + { "EXT_NXP_CTRL", 13, 1 }, + { "BEAN_EN", 12, 1 }, + { "RESTART_BEAN", 9, 1 }, + { "MAC_PORT_BEAN_STATUS_LANE3", 0x3e2c4, 0 }, + { "PDF", 9, 1 }, + { "EXT_NXP_STATUS", 7, 1 }, + { "PAGE_RCVD", 6, 1 }, + { "BEAN_COMPLETE", 5, 1 }, + { "REM_FAULT_STATUS", 4, 1 }, + { "BEAN_ABILITY", 3, 1 }, + { "LINK_STATUS", 2, 1 }, + { "LP_BEAN_ABILITY", 0, 1 }, + { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3e2c8, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3e2cc, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3e2d0, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3e2d4, 0 }, + { "NXP", 15, 1 }, + { "ACK", 14, 1 }, + { "REM_FAULT", 13, 1 }, + { "PAUSE_ABILITY", 10, 3 }, + { "ECHO_NONCE", 5, 5 }, + { "SELECTOR", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3e2d8, 0 }, + { "TECH_ABILITY_1", 5, 11 }, + { "TX_NONCE", 0, 5 }, + { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3e2dc, 0 }, + { "T5_FEC_ABILITY", 14, 2 }, + { "TECH_ABILITY_2", 0, 14 }, + { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3e2e0, 0 }, + { "MAC_PORT_BEAN_XNP_0_LANE3", 0x3e2e4, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_BEAN_XNP_1_LANE3", 0x3e2e8, 0 }, + { "MAC_PORT_BEAN_XNP_2_LANE3", 0x3e2ec, 0 }, + { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3e2f0, 0 }, + { "XNP", 15, 1 }, + { "ACKNOWLEDGE", 14, 1 }, + { "MP", 13, 1 }, + { "ACK2", 12, 1 }, + { "TOGGLE", 11, 1 }, + { "MU", 0, 11 }, + { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3e2f4, 0 }, + { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3e2f8, 0 }, + { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3e2fc, 0 }, + { "100GCR10", 8, 1 }, + { "40GCR4", 6, 1 }, + { "40GKR4", 5, 1 }, + { "FEC", 4, 1 }, + { "10GKR", 3, 1 }, + { "10GKX4", 2, 1 }, + { "1GKX", 1, 1 }, + { "MAC_PORT_FEC_KR_CONTROL", 0x3e600, 0 }, + { "enable_tr", 1, 1 }, + { "restart_tr", 0, 1 }, + { "MAC_PORT_FEC_KR_STATUS", 0x3e604, 0 }, + { "fecKRsigdet", 15, 1 }, + { "train_fail", 3, 1 }, + { "startup_status", 2, 1 }, + { "frame_lock", 1, 1 }, + { "rx_status", 0, 1 }, + { "MAC_PORT_FEC_KR_LP_COEFF", 0x3e608, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LP_STAT", 0x3e60c, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_COEFF", 0x3e610, 0 }, + { "Preset", 13, 1 }, + { "Initialize", 12, 1 }, + { "CP1_UPD", 4, 2 }, + { "C0_UPD", 2, 2 }, + { "CN1_UPD", 0, 2 }, + { "MAC_PORT_FEC_KR_LD_STAT", 0x3e614, 0 }, + { "rx_ready", 15, 1 }, + { "CP1_STAT", 4, 2 }, + { "C0_STAT", 2, 2 }, + { "CN1_STAT", 0, 2 }, + { "MAC_PORT_FEC_ABILITY", 0x3e618, 0 }, + { "fec_ind_ability", 1, 1 }, + { "ability", 0, 1 }, + { "MAC_PORT_FEC_CONTROL", 0x3e61c, 0 }, + { "fec_en_err_ind", 1, 1 }, + { "fec_en", 0, 1 }, + { "MAC_PORT_FEC_STATUS", 0x3e620, 0 }, + { "FEC_LOCKED_100", 1, 1 }, + { "FEC_LOCKED", 0, 1 }, + { "MAC_PORT_FEC_CERR_CNT_0", 0x3e624, 0 }, + { "MAC_PORT_FEC_CERR_CNT_1", 0x3e628, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_0", 0x3e62c, 0 }, + { "MAC_PORT_FEC_NCERR_CNT_1", 0x3e630, 0 }, + { "MAC_PORT_AE_RX_COEF_REQ", 0x3ea00, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT", 0x3ea04, 0 }, + { "T5_AE0_RXSTAT_RDY", 15, 1 }, + { "T5_AE0_RXSTAT_C2", 4, 2 }, + { "T5_AE0_RXSTAT_C1", 2, 2 }, + { "T5_AE0_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ", 0x3ea08, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT", 0x3ea0c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE", 0x3ea10, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL", 0x3ea14, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL", 0x3ea18, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE", 0x3ea1c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_1", 0x3ea20, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_1", 0x3ea24, 0 }, + { "T5_AE1_RXSTAT_RDY", 15, 1 }, + { "T5_AE1_RXSTAT_C2", 4, 2 }, + { "T5_AE1_RXSTAT_C1", 2, 2 }, + { "T5_AE1_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_1", 0x3ea28, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_1", 0x3ea2c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_1", 0x3ea30, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_1", 0x3ea34, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_1", 0x3ea38, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_1", 0x3ea3c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_2", 0x3ea40, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_2", 0x3ea44, 0 }, + { "T5_AE2_RXSTAT_RDY", 15, 1 }, + { "T5_AE2_RXSTAT_C2", 4, 2 }, + { "T5_AE2_RXSTAT_C1", 2, 2 }, + { "T5_AE2_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_2", 0x3ea48, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_2", 0x3ea4c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_2", 0x3ea50, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_2", 0x3ea54, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_2", 0x3ea58, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_2", 0x3ea5c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_RX_COEF_REQ_3", 0x3ea60, 0 }, + { "RXREQ_CPRE", 13, 1 }, + { "RXREQ_CINIT", 12, 1 }, + { "T5_RXREQ_C2", 4, 2 }, + { "T5_RXREQ_C1", 2, 2 }, + { "T5_RXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_RX_COEF_STAT_3", 0x3ea64, 0 }, + { "T5_AE3_RXSTAT_RDY", 15, 1 }, + { "T5_AE3_RXSTAT_C2", 4, 2 }, + { "T5_AE3_RXSTAT_C1", 2, 2 }, + { "T5_AE3_RXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_REQ_3", 0x3ea68, 0 }, + { "TXREQ_CPRE", 13, 1 }, + { "TXREQ_CINIT", 12, 1 }, + { "T5_TXREQ_C2", 4, 2 }, + { "T5_TXREQ_C1", 2, 2 }, + { "T5_TXREQ_C0", 0, 2 }, + { "MAC_PORT_AE_TX_COEF_STAT_3", 0x3ea6c, 0 }, + { "TXSTAT_RDY", 15, 1 }, + { "T5_TXSTAT_C2", 4, 2 }, + { "T5_TXSTAT_C1", 2, 2 }, + { "T5_TXSTAT_C0", 0, 2 }, + { "MAC_PORT_AE_REG_MODE_3", 0x3ea70, 0 }, + { "AET_RSVD", 7, 1 }, + { "AET_ENABLE", 6, 1 }, + { "MAN_DEC", 4, 2 }, + { "MANUAL_RDY", 3, 1 }, + { "MWT_DISABLE", 2, 1 }, + { "MDIO_OVR", 1, 1 }, + { "STICKY_MODE", 0, 1 }, + { "MAC_PORT_AE_PRBS_CTL_3", 0x3ea74, 0 }, + { "PRBS_CHK_ERRCNT", 8, 8 }, + { "PRBS_SYNCCNT", 5, 3 }, + { "PRBS_CHK_SYNC", 4, 1 }, + { "PRBS_CHK_RST", 3, 1 }, + { "PRBS_CHK_OFF", 2, 1 }, + { "PRBS_GEN_FRCERR", 1, 1 }, + { "PRBS_GEN_OFF", 0, 1 }, + { "MAC_PORT_AE_FSM_CTL_3", 0x3ea78, 0 }, + { "CIN_ENABLE", 15, 1 }, + { "FSM_TR_LCL", 14, 1 }, + { "FSM_GDMRK", 11, 3 }, + { "FSM_BADMRK", 8, 3 }, + { "FSM_TR_FAIL", 7, 1 }, + { "FSM_TR_ACT", 6, 1 }, + { "FSM_FRM_LCK", 5, 1 }, + { "FSM_TR_COMP", 4, 1 }, + { "MC_RX_RDY", 3, 1 }, + { "FSM_CU_DIS", 2, 1 }, + { "FSM_TR_RST", 1, 1 }, + { "FSM_TR_EN", 0, 1 }, + { "MAC_PORT_AE_FSM_STATE_3", 0x3ea7c, 0 }, + { "CC2FSM_STATE", 13, 3 }, + { "CC1FSM_STATE", 10, 3 }, + { "CC0FSM_STATE", 7, 3 }, + { "FLFSM_STATE", 4, 3 }, + { "TFSM_STATE", 0, 3 }, + { "MAC_PORT_AE_TX_DIS", 0x3ea80, 0 }, + { "MAC_PORT_AE_KR_CTRL", 0x3ea84, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET", 0x3ea88, 0 }, + { "MAC_PORT_AE_KR_STATUS", 0x3ea8c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_1", 0x3ea90, 0 }, + { "MAC_PORT_AE_KR_CTRL_1", 0x3ea94, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_1", 0x3ea98, 0 }, + { "MAC_PORT_AE_KR_STATUS_1", 0x3ea9c, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_2", 0x3eaa0, 0 }, + { "MAC_PORT_AE_KR_CTRL_2", 0x3eaa4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_2", 0x3eaa8, 0 }, + { "MAC_PORT_AE_KR_STATUS_2", 0x3eaac, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AE_TX_DIS_3", 0x3eab0, 0 }, + { "MAC_PORT_AE_KR_CTRL_3", 0x3eab4, 0 }, + { "Training_Enable", 1, 1 }, + { "Restart_Training", 0, 1 }, + { "MAC_PORT_AE_RX_SIGDET_3", 0x3eab8, 0 }, + { "MAC_PORT_AE_KR_STATUS_3", 0x3eabc, 0 }, + { "Training_Failure", 3, 1 }, + { "Training", 2, 1 }, + { "Frame_Lock", 1, 1 }, + { "RX_Trained", 0, 1 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3eb00, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3eb04, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_0", 0x3eb08, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3eb0c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_0", 0x3eb10, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3eb20, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3eb24, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_1", 0x3eb28, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3eb2c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_1", 0x3eb30, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3eb40, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3eb44, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_2", 0x3eb48, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3eb4c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_2", 0x3eb50, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3eb60, 0 }, + { "EN_HOLD_FAIL", 14, 1 }, + { "INIT_METH", 12, 2 }, + { "CE_DECS", 8, 4 }, + { "EN_ZFE", 7, 1 }, + { "EN_GAIN_TOG", 6, 1 }, + { "EN_AI_C1", 5, 1 }, + { "EN_MAX_ST", 4, 1 }, + { "EN_H1T_EQ", 3, 1 }, + { "H1TEQ_GOAL", 0, 3 }, + { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3eb64, 0 }, + { "GAIN_TH", 6, 5 }, + { "EN_SD_TH", 5, 1 }, + { "EN_AMIN_TH", 4, 1 }, + { "AMIN_TH", 0, 4 }, + { "MAC_PORT_AET_ZFE_LIMITS_3", 0x3eb68, 0 }, + { "ACC_LIM", 8, 4 }, + { "CNV_LIM", 4, 4 }, + { "TOG_LIM", 0, 4 }, + { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3eb6c, 0 }, + { "BOOT_LUT7", 12, 4 }, + { "BOOT_LUT6", 8, 4 }, + { "BOOT_LUT45", 4, 4 }, + { "BOOT_LUT0123", 2, 2 }, + { "BOOT_DEC_C0", 1, 1 }, + { "MAC_PORT_AET_STATUS_3", 0x3eb70, 0 }, + { "AET_STAT", 9, 4 }, + { "NEU_STATE", 5, 4 }, + { "CTRL_STATE", 0, 5 }, + { "MAC_PORT_ANALOG_TEST_MUX", 0x3f814, 0 }, + { "MAC_PORT_BANDGAP_CONTROL", 0x3f82c, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3f880, 0 }, + { "RCCTL1", 5, 1 }, + { "RCCTL0", 4, 1 }, + { "RCAMP1", 3, 1 }, + { "RCAMP0", 2, 1 }, + { "RCAMPEN", 1, 1 }, + { "RCRST", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3f884, 0 }, + { "RCERR", 1, 1 }, + { "RCCOMP", 0, 1 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3f888, 0 }, + { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3f88c, 0 }, + { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3f8e8, 0 }, + { "LBIST", 7, 1 }, + { "LOGICTEST", 6, 1 }, + { "MAVDHI", 5, 1 }, + { "AUXEN", 4, 1 }, + { "JTAGMD", 3, 1 }, + { "RXACMODE", 2, 1 }, + { "HSSACJPC", 1, 1 }, + { "HSSACJAC", 0, 1 }, + { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3f8ec, 0 }, + { "REFVALIDD", 6, 1 }, + { "REFVALIDC", 5, 1 }, + { "REFVALIDB", 4, 1 }, + { "REFVALIDA", 3, 1 }, + { "REFSELRESET", 2, 1 }, + { "SOFTRESET", 1, 1 }, + { "MACROTEST", 0, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3fb00, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3fb04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3fb08, 0 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3fb0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3fb10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3fb28, 0 }, + { "MAC_PORT_PLLA_PCLK_CONTROL", 0x3fb3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3fb40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fb44, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fb48, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fb4c, 0 }, + { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fb50, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3fbf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3fbf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3fbf8, 0 }, + { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3fbfc, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3fc00, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3fc04, 0 }, + { "LDET", 4, 1 }, + { "CCERR", 3, 1 }, + { "CCCMP", 2, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3fc08, 0 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3fc0c, 0 }, + { "FMIN", 3, 1 }, + { "FMAX", 2, 1 }, + { "CVHOLD", 1, 1 }, + { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3fc10, 0 }, + { "CMETH", 2, 1 }, + { "RECAL", 1, 1 }, + { "CCLD", 0, 1 }, + { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3fc28, 0 }, + { "MAC_PORT_PLLB_PCLK_CONTROL", 0x3fc3c, 0 }, + { "SPEDIV", 3, 5 }, + { "PCKSEL", 0, 3 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3fc40, 0 }, + { "EMIL", 2, 1 }, + { "EMID", 1, 1 }, + { "EMIS", 0, 1 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fc44, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fc48, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fc4c, 0 }, + { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fc50, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3fcf0, 0 }, + { "VBST", 1, 3 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3fcf4, 0 }, + { "RESYNC", 6, 1 }, + { "RXCLKSEL", 5, 1 }, + { "FRCBAND", 4, 1 }, + { "PLLBYP", 3, 1 }, + { "PDWNP", 2, 1 }, + { "VCOSEL", 1, 1 }, + { "DIVSEL8", 0, 1 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3fcf8, 0 }, + { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3fcfc, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3f000, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3f004, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3f008, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f00c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f010, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f014, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f018, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f01c, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3f020, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3f024, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3f028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3f030, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3f034, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f038, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f03c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f040, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f044, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f048, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f060, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f064, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f068, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f070, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f074, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f078, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f07c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f080, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f084, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f088, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3f08c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3f090, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3f094, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3f098, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3f09c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f0f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f0f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f0f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f0fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 }, + { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3f100, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3f104, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3f108, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f10c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f110, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f114, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f118, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f11c, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3f120, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3f124, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3f128, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3f130, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3f134, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f138, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f13c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f140, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f144, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f148, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f160, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f164, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f168, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f170, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f174, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f178, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f17c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f180, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f184, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f188, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3f18c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3f190, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3f194, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3f198, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3f19c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f1f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f1f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f1f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f1fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 }, + { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3f400, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3f404, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3f408, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f40c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f410, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f414, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f418, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f41c, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3f420, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3f424, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3f428, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3f430, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3f434, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f438, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f43c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f440, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f444, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f448, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f460, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f464, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f468, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f470, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f474, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f478, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f47c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f480, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f484, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f488, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3f48c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3f490, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3f494, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3f498, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3f49c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f4f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f4f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f4f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f4fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 }, + { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3f500, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3f504, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3f508, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f50c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f510, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f514, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f518, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f51c, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3f520, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3f524, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3f528, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3f530, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3f534, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f538, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f53c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f540, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f544, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f548, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f560, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f564, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f568, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f570, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f574, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f578, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f57c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f580, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f584, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f588, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3f58c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3f590, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3f594, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3f598, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3f59c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f5f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f5f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f5f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f5fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 }, + { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3f900, 0 }, + { "T5_TX_LINKEN", 15, 1 }, + { "T5_TX_LINKRST", 14, 1 }, + { "T5_TX_CFGWRT", 13, 1 }, + { "T5_TX_CFGPTR", 11, 2 }, + { "T5_TX_CFGEXT", 10, 1 }, + { "T5_TX_CFGACT", 9, 1 }, + { "T5_TX_RSYNCC", 8, 1 }, + { "T5_TX_PLLSEL", 6, 2 }, + { "T5_TX_EXTC16", 5, 1 }, + { "T5_TX_DCKSEL", 4, 1 }, + { "T5_TX_RXLOOP", 3, 1 }, + { "T5_TX_BWSEL", 2, 1 }, + { "T5_TX_RTSEL", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3f904, 0 }, + { "SPSEL", 11, 3 }, + { "AFDWEN", 7, 1 }, + { "PRST", 4, 1 }, + { "TPGMD", 3, 1 }, + { "TPSEL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3f908, 0 }, + { "ZCALOVRD", 8, 1 }, + { "AMMODE", 7, 1 }, + { "AEPOL", 6, 1 }, + { "AESRC", 5, 1 }, + { "EQMODE", 4, 1 }, + { "OCOEF", 3, 1 }, + { "COEFRST", 2, 1 }, + { "ALOAD", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f90c, 0 }, + { "T5DRVHIZ", 5, 1 }, + { "T5SASIMP", 4, 1 }, + { "T5SLEW", 2, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f910, 0 }, + { "T5C2BUFDCEN", 5, 1 }, + { "T5DCCEN", 4, 1 }, + { "T5REGBYP", 3, 1 }, + { "T5REGAEN", 2, 1 }, + { "T5REGAMP", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f914, 0 }, + { "RSTEP", 15, 1 }, + { "RLOCK", 14, 1 }, + { "RPOS", 8, 6 }, + { "DCLKSAM", 7, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f918, 0 }, + { "CALSSTN", 3, 3 }, + { "CALSSTP", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f91c, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3f920, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3f924, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3f928, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3f930, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3f934, 0 }, + { "TXPOL", 4, 3 }, + { "NXTPOL", 0, 3 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f938, 0 }, + { "CPREST", 13, 1 }, + { "CINIT", 12, 1 }, + { "C2UPDT", 4, 2 }, + { "C1UPDT", 2, 2 }, + { "C0UPDT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f93c, 0 }, + { "C2STAT", 4, 2 }, + { "C1STAT", 2, 2 }, + { "C0STAT", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f940, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f944, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f948, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f960, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f964, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f968, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f970, 0 }, + { "MAINSC", 6, 6 }, + { "POSTSC", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f974, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f978, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f97c, 0 }, + { "T5XADDR", 1, 5 }, + { "T5XWR", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f980, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f984, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f988, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3f98c, 0 }, + { "DCCTIMEDOUT", 15, 1 }, + { "DCCTIMEEN", 14, 1 }, + { "DCCLOCK", 13, 1 }, + { "DCCOFFSET", 8, 5 }, + { "DCCSTEP", 6, 2 }, + { "DCCASTEP", 1, 5 }, + { "DCCAEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3f990, 0 }, + { "DCCOUT", 12, 1 }, + { "DCCCLK", 11, 1 }, + { "DCCHOLD", 10, 1 }, + { "DCCSIGN", 8, 2 }, + { "DCCAMP", 1, 7 }, + { "DCCOEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3f994, 0 }, + { "DCCASIGN", 7, 2 }, + { "DCCAAMP", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3f998, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3f99c, 0 }, + { "LPIDCLK", 4, 1 }, + { "LPITERM", 2, 2 }, + { "LPIPRCD", 0, 2 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f9f0, 0 }, + { "SDOVRDEN", 8, 1 }, + { "SDOVRD", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f9f4, 0 }, + { "SLEWCODE", 1, 2 }, + { "ASEGEN", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f9f8, 0 }, + { "AECMDVAL", 14, 1 }, + { "AECMD1312", 12, 2 }, + { "AECMD70", 0, 8 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f9fc, 0 }, + { "C48DIVCTL", 12, 3 }, + { "RATEDIVCTL", 9, 3 }, + { "ANLGFLSH", 8, 1 }, + { "DCCTSTOUT", 7, 1 }, + { "BSOUT", 6, 1 }, + { "BSIN", 5, 1 }, + { "JTAGAMPL", 3, 2 }, + { "JTAGTS", 2, 1 }, + { "TS", 1, 1 }, + { "OBS", 0, 1 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 }, + { "C0MAX", 8, 5 }, + { "C0MIN", 0, 5 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 }, + { "C1MAX", 8, 7 }, + { "C1MIN", 0, 7 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 }, + { "C2MAX", 8, 6 }, + { "C2MIN", 0, 6 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 }, + { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 }, + { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3f200, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3f204, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3f208, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f20c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3f210, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3f214, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f218, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f21c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3f220, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3f224, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3f228, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3f22c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3f230, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3f234, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3f238, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3f240, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3f248, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f24c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3f250, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f25c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f260, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f264, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f270, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3f274, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3f278, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3f27c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3f280, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3f284, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3f288, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3f28c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3f290, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3f294, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3f298, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3f29c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f2a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3f2a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3f2a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3f2ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f2b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f2b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f2b8, 0 }, + { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3f2c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKA_DFE_H1", 0x3f2c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKA_DFE_H2", 0x3f2c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKA_DFE_H3", 0x3f2cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H4", 0x3f2d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H5", 0x3f2d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3f2d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3f2dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3f2e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_DFE_H12", 0x3f2e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f2f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f2fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3f300, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3f304, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3f308, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f30c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3f310, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3f314, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f318, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f31c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3f320, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3f324, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3f328, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3f32c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3f330, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3f334, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3f338, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3f340, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3f348, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f34c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3f350, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f35c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f360, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f364, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f370, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3f374, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3f378, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3f37c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3f380, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3f384, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3f388, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3f38c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3f390, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3f394, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3f398, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3f39c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f3a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3f3a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3f3a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3f3ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f3b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f3b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f3b8, 0 }, + { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3f3c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKB_DFE_H1", 0x3f3c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKB_DFE_H2", 0x3f3c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKB_DFE_H3", 0x3f3cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H4", 0x3f3d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H5", 0x3f3d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3f3d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3f3dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3f3e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_DFE_H12", 0x3f3e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f3f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f3fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3f600, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3f604, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3f608, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f60c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3f610, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3f614, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f618, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f61c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3f620, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3f624, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3f628, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3f62c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3f630, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3f634, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3f638, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3f640, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3f648, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f64c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3f650, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f65c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f660, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f664, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f670, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3f674, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3f678, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3f67c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3f680, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3f684, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3f688, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3f68c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3f690, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3f694, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3f698, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3f69c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f6a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3f6a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3f6a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3f6ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f6b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f6b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f6b8, 0 }, + { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3f6c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKC_DFE_H1", 0x3f6c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKC_DFE_H2", 0x3f6c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKC_DFE_H3", 0x3f6cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H4", 0x3f6d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H5", 0x3f6d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3f6d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3f6dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3f6e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_DFE_H12", 0x3f6e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f6f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f6fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3f700, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3f704, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3f708, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f70c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3f710, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3f714, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f718, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f71c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3f720, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3f724, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3f728, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3f72c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3f730, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3f734, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3f738, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3f740, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3f748, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f74c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3f750, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f75c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f760, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f764, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f770, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3f774, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3f778, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3f77c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3f780, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3f784, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3f788, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3f78c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3f790, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3f794, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3f798, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3f79c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f7a0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3f7a4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3f7a8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3f7ac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f7b0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f7b4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f7b8, 0 }, + { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3f7c0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINKD_DFE_H1", 0x3f7c4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINKD_DFE_H2", 0x3f7c8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINKD_DFE_H3", 0x3f7cc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H4", 0x3f7d0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H5", 0x3f7d4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3f7d8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3f7dc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3f7e0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_DFE_H12", 0x3f7e4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f7f8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f7fc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3fa00, 0 }, + { "T5_RX_LINKEN", 15, 1 }, + { "T5_RX_LINKRST", 14, 1 }, + { "T5_RX_CFGWRT", 13, 1 }, + { "T5_RX_CFGPTR", 11, 2 }, + { "T5_RX_CFGEXT", 10, 1 }, + { "T5_RX_CFGACT", 9, 1 }, + { "T5_RX_AUXCLK", 8, 1 }, + { "T5_RX_PLLSEL", 6, 2 }, + { "T5_RX_DMSEL", 4, 2 }, + { "T5_RX_BWSEL", 2, 2 }, + { "T5_RX_RTSEL", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3fa04, 0 }, + { "RCLKEN", 15, 1 }, + { "RRATE", 13, 2 }, + { "FERRST", 10, 1 }, + { "ERRST", 9, 1 }, + { "SYNCST", 8, 1 }, + { "WRPSM", 7, 1 }, + { "WPLPEN", 6, 1 }, + { "WRPMD", 5, 1 }, + { "PRST", 4, 1 }, + { "PCHKEN", 3, 1 }, + { "PATSEL", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3fa08, 0 }, + { "FTHROT", 12, 4 }, + { "RTHROT", 11, 1 }, + { "FILTCTL", 7, 4 }, + { "RSRVO", 5, 2 }, + { "EXTEL", 4, 1 }, + { "RSTUCK", 3, 1 }, + { "FRZFW", 2, 1 }, + { "RSTFW", 1, 1 }, + { "SSCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3fa0c, 0 }, + { "RSNP", 11, 1 }, + { "TSOEN", 10, 1 }, + { "OFFEN", 9, 1 }, + { "TMSCAL", 7, 2 }, + { "APADJ", 6, 1 }, + { "RSEL", 5, 1 }, + { "PHOFFS", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3fa10, 0 }, + { "ROT0A", 8, 6 }, + { "ROT00", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3fa14, 0 }, + { "FREQFW", 8, 8 }, + { "FWSNAP", 7, 1 }, + { "ROT90", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3fa18, 0 }, + { "RCALER", 15, 1 }, + { "RAOOFF", 10, 5 }, + { "RAEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3fa1c, 0 }, + { "RCALER", 15, 1 }, + { "RBOOFF", 10, 5 }, + { "RBEOFF", 5, 5 }, + { "RDOFF", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3fa20, 0 }, + { "REQCMP", 15, 1 }, + { "DFEREQ", 14, 1 }, + { "SPCEN", 13, 1 }, + { "GATEEN", 12, 1 }, + { "SPIFMT", 9, 3 }, + { "DFEPWR", 6, 3 }, + { "STNDBY", 5, 1 }, + { "FRCH", 4, 1 }, + { "NONRND", 3, 1 }, + { "NONRNF", 2, 1 }, + { "FSTLCK", 1, 1 }, + { "DFERST", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3fa24, 0 }, + { "T5BYTE1", 8, 8 }, + { "T5BYTE0", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3fa28, 0 }, + { "T5_RX_SMODE", 8, 3 }, + { "T5_RX_ADCORR", 7, 1 }, + { "T5_RX_TRAINEN", 6, 1 }, + { "T5_RX_ASAMPQ", 3, 3 }, + { "T5_RX_ASAMP", 0, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3fa2c, 0 }, + { "POLE", 12, 2 }, + { "PEAK", 8, 3 }, + { "VOFFSN", 6, 2 }, + { "VOFFA", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3fa30, 0 }, + { "T5SHORTV", 10, 1 }, + { "T5VGAIN", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3fa34, 0 }, + { "HBND1", 10, 1 }, + { "HBND0", 9, 1 }, + { "VLCKD", 8, 1 }, + { "VLCKDF", 7, 1 }, + { "AMAXT", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3fa38, 0 }, + { "IQSEP", 10, 5 }, + { "DUTYQ", 5, 5 }, + { "DUTYI", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3fa40, 0 }, + { "DTHR", 8, 6 }, + { "SNUL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3fa48, 0 }, + { "DACAN", 8, 8 }, + { "DACAP", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3fa4c, 0 }, + { "DACAZ", 8, 8 }, + { "DACAM", 0, 8 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3fa50, 0 }, + { "ADSN_ReadWrite", 8, 1 }, + { "ADSN_ReadOnly", 7, 1 }, + { "ADMAG", 0, 7 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3fa5c, 0 }, + { "H1O2", 8, 6 }, + { "H1E2", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3fa60, 0 }, + { "H1O3", 8, 6 }, + { "H1E3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3fa64, 0 }, + { "H1O4", 8, 6 }, + { "H1E4", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3fa70, 0 }, + { "DPCMD", 14, 1 }, + { "DPCCVG", 13, 1 }, + { "DACCVG", 12, 1 }, + { "DPCTGT", 9, 3 }, + { "BLKH1T", 8, 1 }, + { "BLKOAE", 7, 1 }, + { "H1TGT", 4, 3 }, + { "OAE", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3fa74, 0 }, + { "OLS", 11, 5 }, + { "OES", 6, 5 }, + { "BLKODEC", 5, 1 }, + { "ODEC", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3fa78, 0 }, + { "T5BER6VAL", 15, 1 }, + { "T5BER6", 14, 1 }, + { "T5BER3VAL", 13, 1 }, + { "T5TOOFAST", 12, 1 }, + { "T5DPCCMP", 9, 1 }, + { "T5DACCMP", 8, 1 }, + { "T5DDCCMP", 7, 1 }, + { "T5AERRFLG", 6, 1 }, + { "T5WERRFLG", 5, 1 }, + { "T5TRCMP", 4, 1 }, + { "T5VLCKF", 3, 1 }, + { "T5ROCCMP", 2, 1 }, + { "T5DQCCCMP", 1, 1 }, + { "T5OCCMP", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3fa7c, 0 }, + { "FDPC", 15, 1 }, + { "FDAC", 14, 1 }, + { "FDDC", 13, 1 }, + { "FNRND", 12, 1 }, + { "FVGAIN", 11, 1 }, + { "FVOFF", 10, 1 }, + { "FSDET", 9, 1 }, + { "FBER6", 8, 1 }, + { "FROTO", 7, 1 }, + { "FH4H5", 6, 1 }, + { "FH2H3", 5, 1 }, + { "FH1", 4, 1 }, + { "FH1SN", 3, 1 }, + { "FNRDF", 2, 1 }, + { "FLOFF", 1, 1 }, + { "FADAC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3fa80, 0 }, + { "H25SPC", 15, 1 }, + { "FTOOFAST", 8, 1 }, + { "FINTTRIM", 7, 1 }, + { "FDINV", 6, 1 }, + { "FHGS", 5, 1 }, + { "FH6H12", 4, 1 }, + { "FH1CAL", 3, 1 }, + { "FINTCAL", 2, 1 }, + { "FDCA", 1, 1 }, + { "FDQCC", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3fa84, 0 }, + { "LOFE2S_ReadWrite", 16, 1 }, + { "LOFE2S_ReadOnly", 14, 2 }, + { "LOFE2", 8, 6 }, + { "LOFE1S_ReadWrite", 7, 1 }, + { "LOFE1S_ReadOnly", 6, 1 }, + { "LOFE1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3fa88, 0 }, + { "LOFO2S_ReadWrite", 15, 1 }, + { "LOFO2S_ReadOnly", 14, 1 }, + { "LOFO2", 8, 6 }, + { "LOFO1S_ReadWrite", 7, 1 }, + { "LOFO1S_ReadOnly", 6, 1 }, + { "LOFO1", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3fa8c, 0 }, + { "LOFE4S_ReadWrite", 15, 1 }, + { "LOFE4S_ReadOnly", 14, 1 }, + { "LOFE", 8, 6 }, + { "LOFE3S_ReadWrite", 7, 1 }, + { "LOFE3S_ReadOnly", 6, 1 }, + { "LOFE3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3fa90, 0 }, + { "LOFO4S_ReadWrite", 15, 1 }, + { "LOFO4S_ReadOnly", 14, 1 }, + { "LOFO4", 8, 6 }, + { "LOFO3S_ReadWrite", 7, 1 }, + { "LOFO3S_ReadOnly", 6, 1 }, + { "LOFO3", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3fa94, 0 }, + { "T5E1SN_ReadWrite", 15, 1 }, + { "T5E1SN_ReadOnly", 14, 1 }, + { "T5E1AMP", 8, 6 }, + { "T5E0SN_ReadWrite", 7, 1 }, + { "T5E0SN_ReadOnly", 6, 1 }, + { "T5E0AMP", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3fa98, 0 }, + { "T5LFREG", 12, 1 }, + { "T5LFRC", 11, 1 }, + { "T5LFSEL", 8, 3 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3fa9c, 0 }, + { "OFFSN_ReadWrite", 14, 1 }, + { "OFFSN_ReadOnly", 13, 1 }, + { "OFFAMP", 8, 5 }, + { "SDACDC", 7, 1 }, + { "SDPDN", 6, 1 }, + { "SIGDET", 5, 1 }, + { "SDLVL", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3faa0, 0 }, + { "T5_RX_SETHDIS", 7, 1 }, + { "T5_RX_PDTERM", 6, 1 }, + { "T5_RX_BYPASS", 5, 1 }, + { "T5_RX_LPFEN", 4, 1 }, + { "T5_RX_VGABOD", 3, 1 }, + { "T5_RX_VTBYP", 2, 1 }, + { "T5_RX_VTERM", 0, 2 }, + { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3faa4, 0 }, + { "ISTRIMS", 14, 2 }, + { "ISTRIM", 8, 6 }, + { "HALF1", 7, 1 }, + { "HALF2", 6, 1 }, + { "INTDAC", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3faa8, 0 }, + { "BLKAZ", 15, 1 }, + { "WIDTH", 10, 5 }, + { "MINWDTH", 5, 5 }, + { "MINAMP", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3faac, 0 }, + { "T5SMQM", 13, 3 }, + { "T5SMQ", 5, 8 }, + { "T5EMMD", 3, 2 }, + { "T5EMBRDY", 2, 1 }, + { "T5EMBUMP", 1, 1 }, + { "T5EMEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3fab0, 0 }, + { "EMF8", 15, 1 }, + { "EMCNT", 4, 8 }, + { "EMOFLO", 2, 1 }, + { "EMCRST", 1, 1 }, + { "EMCEN", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3fab4, 0 }, + { "SM2RDY", 15, 1 }, + { "SM2RST", 14, 1 }, + { "APDF", 0, 12 }, + { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3fab8, 0 }, + { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3fac0, 0 }, + { "H_EN", 1, 12 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3fac4, 0 }, + { "H1OSN", 14, 2 }, + { "H1OMAG", 8, 6 }, + { "H1ESN", 6, 2 }, + { "H1EMAG", 0, 6 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3fac8, 0 }, + { "H2OSN_ReadWrite", 14, 1 }, + { "H2OSN_ReadOnly", 13, 1 }, + { "H2OMAG", 8, 5 }, + { "H2ESN_ReadWrite", 6, 1 }, + { "H2ESN_ReadOnly", 5, 1 }, + { "H2EMAG", 0, 5 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3facc, 0 }, + { "H3OSN_ReadWrite", 13, 1 }, + { "H3OSN_ReadOnly", 12, 1 }, + { "H3OMAG", 8, 4 }, + { "H3ESN_ReadWrite", 5, 1 }, + { "H3ESN_ReadOnly", 4, 1 }, + { "H3EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3fad0, 0 }, + { "H4OGS", 14, 2 }, + { "H4OSN_ReadWrite", 13, 1 }, + { "H4OSN_ReadOnly", 12, 1 }, + { "H4OMAG", 8, 4 }, + { "H4EGS", 6, 2 }, + { "H4ESN_ReadWrite", 5, 1 }, + { "H4ESN_ReadOnly", 4, 1 }, + { "H4EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3fad4, 0 }, + { "H5OGS", 14, 2 }, + { "H5OSN_ReadWrite", 13, 1 }, + { "H5OSN_ReadOnly", 12, 1 }, + { "H5OMAG", 8, 4 }, + { "H5EGS", 6, 2 }, + { "H5ESN_ReadWrite", 5, 1 }, + { "H5ESN_ReadOnly", 4, 1 }, + { "H5EMAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3fad8, 0 }, + { "H7GS", 14, 2 }, + { "H7SN_ReadWrite", 13, 1 }, + { "H7SN_ReadOnly", 12, 1 }, + { "H7MAG", 8, 4 }, + { "H6GS", 6, 2 }, + { "H6SN_ReadWrite", 5, 1 }, + { "H6SN_ReadOnly", 4, 1 }, + { "H6MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3fadc, 0 }, + { "H9GS", 14, 2 }, + { "H9SN_ReadWrite", 13, 1 }, + { "H9SN_ReadOnly", 12, 1 }, + { "H9MAG", 8, 4 }, + { "H8GS", 6, 2 }, + { "H8SN_ReadWrite", 5, 1 }, + { "H8SN_ReadOnly", 4, 1 }, + { "H8MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3fae0, 0 }, + { "H11GS", 14, 2 }, + { "H11SN_ReadWrite", 13, 1 }, + { "H11SN_ReadOnly", 12, 1 }, + { "H11MAG", 8, 4 }, + { "H10GS", 6, 2 }, + { "H10SN_ReadWrite", 5, 1 }, + { "H10SN_ReadOnly", 4, 1 }, + { "H10MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3fae4, 0 }, + { "H12GS", 6, 2 }, + { "H12SN_ReadWrite", 5, 1 }, + { "H12SN_ReadOnly", 4, 1 }, + { "H12MAG", 0, 4 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3faf8, 0 }, + { "DFEDACLSSD", 6, 1 }, + { "SDLSSD", 5, 1 }, + { "DFEOBSBIAS", 4, 1 }, + { "GBOFSTLSSD", 3, 1 }, + { "RXDOBS", 2, 1 }, + { "ACJZPT", 1, 1 }, + { "ACJZNT", 0, 1 }, + { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3fafc, 0 }, + { "PHSLOCK", 10, 1 }, + { "TESTMODE", 9, 1 }, + { "CALMODE", 8, 1 }, + { "AMPSEL", 7, 1 }, + { "WHICHNRZ", 6, 1 }, + { "BANKA", 5, 1 }, + { "BANKB", 4, 1 }, + { "ACJPDP", 3, 1 }, + { "ACJPDN", 2, 1 }, + { "LSSDT", 1, 1 }, + { "MTHOLD", 0, 1 }, + { NULL } +}; + +struct reg_info t5_mc_0_regs[] = { + { "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 }, + { "DP18_PLL_LOCK", 1, 15 }, + { "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 }, + { "AD32S_PLL_LOCK", 14, 2 }, + { "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 }, + { "RANK_PAIR0_PRI", 13, 3 }, + { "RANK_PAIR0_PRI_V", 12, 1 }, + { "RANK_PAIR0_SEC", 9, 3 }, + { "RANK_PAIR0_SEC_V", 8, 1 }, + { "RANK_PAIR1_PRI", 5, 3 }, + { "RANK_PAIR1_PRI_V", 4, 1 }, + { "RANK_PAIR1_SEC", 1, 3 }, + { "RANK_PAIR1_SEC_V", 0, 1 }, + { "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 }, + { "RANK_PAIR2_PRI", 13, 3 }, + { "RANK_PAIR2_PRI_V", 12, 1 }, + { "RANK_PAIR2_SEC", 9, 3 }, + { "RANK_PAIR2_SEC_V", 8, 1 }, + { "RANK_PAIR3_PRI", 5, 3 }, + { "RANK_PAIR3_PRI_V", 4, 1 }, + { "RANK_PAIR3_SEC", 1, 3 }, + { "RANK_PAIR3_SEC_V", 0, 1 }, + { "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 }, + { "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 }, + { "PERIODIC_CAL_REQ_EN", 15, 1 }, + { "PERIODIC_RELOAD_VALUE0", 0, 15 }, + { "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 }, + { "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 }, + { "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 }, + { "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 }, + { "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 }, + { "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 }, + { "PER_ENA_RANK_PAIR", 12, 4 }, + { "PER_ENA_ZCAL", 11, 1 }, + { "PER_ENA_SYSCLK_ALIGN", 10, 1 }, + { "ENA_PER_RDCLK_ALIGN", 9, 1 }, + { "ENA_PER_DQS_ALIGN", 8, 1 }, + { "ENA_PER_READ_CTR", 7, 1 }, + { "PER_NEXT_RANK_PAIR", 5, 2 }, + { "FAST_SIM_PER_CNTR", 4, 1 }, + { "START_INIT_CAL", 3, 1 }, + { "START_PER_CAL", 2, 1 }, + { "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 }, + { "PER_ZCAL_ENA_RANK", 8, 8 }, + { "PER_ZCAL_NEXT_RANK", 5, 3 }, + { "START_PER_ZCAL", 4, 1 }, + { "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 }, + { "PROTOCOL_DDR", 12, 4 }, + { "DATA_MUX4_1MODE", 11, 1 }, + { "DDR4_CMD_SIG_REDUCTION", 9, 1 }, + { "SYSCLK_2X_MEMINTCLKO", 8, 1 }, + { "RANK_OVERRIDE", 7, 1 }, + { "RANK_OVERRIDE_VALUE", 4, 3 }, + { "LOW_LATENCY", 3, 1 }, + { "DDR4_BANK_REFRESH", 2, 1 }, + { "DDR4_VLEVEL_BANK_GROUP", 1, 1 }, + { "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 }, + { "WRITE_LATENCY_OFFSET", 12, 4 }, + { "READ_LATENCY_OFFSET", 8, 4 }, + { "MEMCTL_CIC_FAST", 7, 1 }, + { "MEMCTL_CTRN_IGNORE", 6, 1 }, + { "DISABLE_MEMCTL_CAL", 5, 1 }, + { "MC_DDRPHY_PC_RESETS", 0x47038, 0 }, + { "PLL_RESET", 15, 1 }, + { "SYSCLK_RESET", 14, 1 }, + { "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 }, + { "RC_ERROR", 15, 1 }, + { "WC_ERROR", 14, 1 }, + { "SEQ_ERROR", 13, 1 }, + { "CC_ERROR", 12, 1 }, + { "APB_ERROR", 11, 1 }, + { "PC_ERROR", 10, 1 }, + { "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 }, + { "RC_ERROR_MASK", 15, 1 }, + { "WC_ERROR_MASK", 14, 1 }, + { "SEQ_ERROR_MASK", 13, 1 }, + { "CC_ERROR_MASK", 12, 1 }, + { "APB_ERROR_MASK", 11, 1 }, + { "PC_ERROR_MASK", 10, 1 }, + { "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 }, + { "PVTP", 11, 5 }, + { "PVTN", 6, 5 }, + { "PVT_OVERRIDE", 5, 1 }, + { "ENABLE_ZCAL", 4, 1 }, + { "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 }, + { "VREFDQ0DSGN", 15, 1 }, + { "VREFDQ0D", 11, 4 }, + { "VREFDQ1DSGN", 10, 1 }, + { "VREFDQ1D", 6, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 }, + { "ENA_WR_LEVEL", 15, 1 }, + { "ENA_INITIAL_PAT_WR", 14, 1 }, + { "ENA_DQS_ALIGN", 13, 1 }, + { "ENA_RDCLK_ALIGN", 12, 1 }, + { "ENA_READ_CTR", 11, 1 }, + { "ENA_WRITE_CTR", 10, 1 }, + { "ENA_INITIAL_COARSE_WR", 9, 1 }, + { "ENA_COARSE_RD", 8, 1 }, + { "ENA_CUSTOM_RD", 7, 1 }, + { "ENA_CUSTOM_WR", 6, 1 }, + { "ABORT_ON_CAL_ERROR", 5, 1 }, + { "ENA_DIGITAL_EYE", 4, 1 }, + { "ENA_RANK_PAIR", 0, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 }, + { "REFRESH_COUNT", 12, 4 }, + { "REFRESH_CONTROL", 10, 2 }, + { "REFRESH_ALL_RANKS", 9, 1 }, + { "REFRESH_INTERVAL", 0, 7 }, + { "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 }, + { "ERROR_WR_LEVEL", 15, 1 }, + { "ERROR_INITIAL_PAT_WRITE", 14, 1 }, + { "ERROR_DQS_ALIGN", 13, 1 }, + { "ERROR_RDCLK_ALIGN", 12, 1 }, + { "ERROR_READ_CTR", 11, 1 }, + { "ERROR_WRITE_CTR", 10, 1 }, + { "ERROR_INITIAL_COARSE_WR", 9, 1 }, + { "ERROR_COARSE_RD", 8, 1 }, + { "ERROR_CUSTOM_RD", 7, 1 }, + { "ERROR_CUSTOM_WR", 6, 1 }, + { "ERROR_DIGITAL_EYE", 5, 1 }, + { "ERROR_RANK_PAIR", 0, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 }, + { "ERROR_WR_LEVEL_MASK", 15, 1 }, + { "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 }, + { "ERROR_DQS_ALIGN_MASK", 13, 1 }, + { "ERROR_RDCLK_ALIGN_MASK", 12, 1 }, + { "ERROR_READ_CTR_MASK", 11, 1 }, + { "ERROR_WRITE_CTR_MASK", 10, 1 }, + { "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 }, + { "ERROR_COARSE_RD_MASK", 8, 1 }, + { "ERROR_CUSTOM_RD_MASK", 7, 1 }, + { "ERROR_CUSTOM_WR_MASK", 6, 1 }, + { "ERROR_DIGITAL_EYE_MASK", 5, 1 }, + { "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 }, + { "INIT_CAL_COMPLETE", 12, 4 }, + { "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 }, + { "PVTP", 11, 5 }, + { "PVTN", 6, 5 }, + { "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 }, + { "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 }, + { "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 }, + { "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 }, + { "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 }, + { "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 }, + { "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 }, + { "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 }, + { "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 }, + { "ADDR_MIRROR_RP0_PRI", 15, 1 }, + { "ADDR_MIRROR_RP0_SEC", 14, 1 }, + { "ADDR_MIRROR_RP1_PRI", 13, 1 }, + { "ADDR_MIRROR_RP1_SEC", 12, 1 }, + { "ADDR_MIRROR_RP2_PRI", 11, 1 }, + { "ADDR_MIRROR_RP2_SEC", 10, 1 }, + { "ADDR_MIRROR_RP3_PRI", 9, 1 }, + { "ADDR_MIRROR_RP3_SEC", 8, 1 }, + { "RANK_GROUPING", 6, 2 }, + { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45000, 0 }, + { "BIT_ENABLE_0_11", 4, 12 }, + { "BIT_ENABLE_12_15", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45004, 0 }, + { "DI_ADR0_ADR1", 15, 1 }, + { "DI_ADR2_ADR3", 14, 1 }, + { "DI_ADR4_ADR5", 13, 1 }, + { "DI_ADR6_ADR7", 12, 1 }, + { "DI_ADR8_ADR9", 11, 1 }, + { "DI_ADR10_ADR11", 10, 1 }, + { "DI_ADR12_ADR13", 9, 1 }, + { "DI_ADR14_ADR15", 8, 1 }, + { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45010, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45014, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45018, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4501c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45020, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45024, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45028, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4502c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45030, 0 }, + { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 }, + { "ADR_TEST_DATA_EN", 7, 1 }, + { "DADR_TEST_MODE", 5, 2 }, + { "ADR_TEST_4TO1_MODE", 4, 1 }, + { "ADR_TEST_RESET", 3, 1 }, + { "ADR_TEST_GEN_EN", 2, 1 }, + { "ADR_TEST_CLEAR_ERROR", 1, 1 }, + { "ADR_TEST_CHECK_EN", 0, 1 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45040, 0 }, + { "EN_SLICE_N_WR_0", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45044, 0 }, + { "EN_SLICE_N_WR_1", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45048, 0 }, + { "EN_SLICE_N_WR_2", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4504c, 0 }, + { "EN_SLICE_N_WR_3", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45050, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45054, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45058, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4505c, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45080, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45084, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45060, 0 }, + { "POST_CURSOR0", 12, 4 }, + { "POST_CURSOR1", 8, 4 }, + { "POST_CURSOR2", 4, 4 }, + { "POST_CURSOR3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x450a0, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x450a4, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45068, 0 }, + { "SLEW_CTL0", 12, 4 }, + { "SLEW_CTL1", 8, 4 }, + { "SLEW_CTL2", 4, 4 }, + { "SLEW_CTL3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x450a8, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x450ac, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x450b0, 0 }, + { "ADR_LANE_0_11_PD", 4, 12 }, + { "ADR_LANE_12_15_PD", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45200, 0 }, + { "BIT_ENABLE_0_11", 4, 12 }, + { "BIT_ENABLE_12_15", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45204, 0 }, + { "DI_ADR0_ADR1", 15, 1 }, + { "DI_ADR2_ADR3", 14, 1 }, + { "DI_ADR4_ADR5", 13, 1 }, + { "DI_ADR6_ADR7", 12, 1 }, + { "DI_ADR8_ADR9", 11, 1 }, + { "DI_ADR10_ADR11", 10, 1 }, + { "DI_ADR12_ADR13", 9, 1 }, + { "DI_ADR14_ADR15", 8, 1 }, + { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45210, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45214, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45218, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4521c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45220, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45224, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45228, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4522c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45230, 0 }, + { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 }, + { "ADR_TEST_DATA_EN", 7, 1 }, + { "DADR_TEST_MODE", 5, 2 }, + { "ADR_TEST_4TO1_MODE", 4, 1 }, + { "ADR_TEST_RESET", 3, 1 }, + { "ADR_TEST_GEN_EN", 2, 1 }, + { "ADR_TEST_CLEAR_ERROR", 1, 1 }, + { "ADR_TEST_CHECK_EN", 0, 1 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45240, 0 }, + { "EN_SLICE_N_WR_0", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45244, 0 }, + { "EN_SLICE_N_WR_1", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45248, 0 }, + { "EN_SLICE_N_WR_2", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4524c, 0 }, + { "EN_SLICE_N_WR_3", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45250, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45254, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45258, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4525c, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45280, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45284, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45260, 0 }, + { "POST_CURSOR0", 12, 4 }, + { "POST_CURSOR1", 8, 4 }, + { "POST_CURSOR2", 4, 4 }, + { "POST_CURSOR3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x452a0, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x452a4, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45268, 0 }, + { "SLEW_CTL0", 12, 4 }, + { "SLEW_CTL1", 8, 4 }, + { "SLEW_CTL2", 4, 4 }, + { "SLEW_CTL3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x452a8, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x452ac, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x452b0, 0 }, + { "ADR_LANE_0_11_PD", 4, 12 }, + { "ADR_LANE_12_15_PD", 0, 4 }, + { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x460c0, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x460c4, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "VREG_VREGSPARE", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "INTERP_SIG_SLEW_0_3", 1, 4 }, + { "ANALOG_WRAPON", 0, 1 }, + { "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x460c8, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESE", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "CE0DLTVCC", 0, 2 }, + { "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x460d0, 0 }, + { "SLEW_LATE_SAMPLE", 15, 1 }, + { "SYSCLK_ROT", 8, 7 }, + { "BB_LOCK", 7, 1 }, + { "SLEW_EARLY_SAMPLE", 6, 1 }, + { "SLEW_DONE_STATUS", 4, 2 }, + { "SLEW_CNTL", 0, 4 }, + { "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x460d4, 0 }, + { "FLUSH", 15, 1 }, + { "GIANT_MUX_TEST_EN", 14, 1 }, + { "GIANT_MUX_TEST_VAL", 13, 1 }, + { "HS_PROBE_A_SEL_", 8, 4 }, + { "HS_PROBE_B_SEL_", 4, 4 }, + { "ATEST1CTL0", 3, 1 }, + { "ATEST1CTL1", 2, 1 }, + { "ATEST1CTL2", 1, 1 }, + { "ATEST1CTL3", 0, 1 }, + { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x460d8, 0 }, + { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x460dc, 0 }, + { "MC_DDRPHY_ADR_POWERDOWN_1", 0x460e0, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x460e4, 0 }, + { "SLEW_CAL_ENABLE", 15, 1 }, + { "SLEW_CAL_START", 14, 1 }, + { "SLEW_CAL_OVERRIDE_EN", 12, 1 }, + { "SLEW_CAL_OVERRIDE", 8, 4 }, + { "SLEW_TARGET_PR_OFFSET", 0, 5 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 }, + { "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 }, + { "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 }, + { "MPR_PATTERN_BIT", 15, 1 }, + { "TWO_CYCLE_ADDR_EN", 14, 1 }, + { "MR_MASK_EN", 10, 4 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 }, + { "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 }, + { "MULTIPLE_REQ_ERROR", 15, 1 }, + { "INVALID_REQTYPE_ERRO", 14, 1 }, + { "EARLY_REQ_ERROR", 13, 1 }, + { "MULTIPLE_REQ_SOURCE", 10, 3 }, + { "INVALID_REQTYPE", 6, 4 }, + { "INVALID_REQ_SOURCE", 3, 3 }, + { "EARLY_REQ_SOURCE", 0, 3 }, + { "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 }, + { "MULT_REQ_ERR_MASK", 15, 1 }, + { "INVALID_REQTYPE_ERR_MASK", 14, 1 }, + { "EARLY_REQ_ERR_MASK", 13, 1 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 }, + { "TMOD_CYCLES", 12, 4 }, + { "TRCD_CYCLES", 8, 4 }, + { "TRP_CYCLES", 4, 4 }, + { "TRFC_CYCLES", 0, 4 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 }, + { "TZQINIT_CYCLES", 12, 4 }, + { "TZQCS_CYCLES", 8, 4 }, + { "TWLDQSEN_CYCLES", 4, 4 }, + { "TWRMRD_CYCLES", 0, 4 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 }, + { "TODTLON_OFF_CYCLES", 12, 4 }, + { "TRC_CYCLES", 8, 4 }, + { "TMRSC_CYCLES", 4, 4 }, + { "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 }, + { "TWLO_TWLOE", 8, 8 }, + { "WL_ONE_DQS_PULSE", 7, 1 }, + { "FW_WR_RD", 1, 6 }, + { "CUSTOM_INIT_WRITE", 0, 1 }, + { "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 }, + { "BIG_STEP", 12, 4 }, + { "SMALL_STEP", 9, 3 }, + { "WR_PRE_DLY", 3, 6 }, + { "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 }, + { "NUM_VALID_SAMPLES", 12, 4 }, + { "FW_RD_WR", 6, 6 }, + { "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 }, + { "DDR4_MRS_CMD_DQ_EN", 15, 1 }, + { "MRS_CMD_DQ_ON", 9, 6 }, + { "MRS_CMD_DQ_OFF", 3, 6 }, + { "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 }, + { "WRCLK_CAL_START", 15, 1 }, + { "WRCLK_CAL_DONE", 14, 1 }, + { "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 }, + { "WR_CNTL_ERROR", 15, 1 }, + { "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 }, + { "WR_CNTL_ERROR_MASK", 15, 1 }, + { "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 }, + { "GLOBAL_PHY_OFFSET", 12, 4 }, + { "ADVANCE_RD_VALID", 11, 1 }, + { "SINGLE_BIT_MPR_RP0", 6, 1 }, + { "SINGLE_BIT_MPR_RP1", 5, 1 }, + { "SINGLE_BIT_MPR_RP2", 4, 1 }, + { "SINGLE_BIT_MPR_RP3", 3, 1 }, + { "ALIGN_ON_EVEN_CYCLES", 2, 1 }, + { "PERFORM_RDCLK_ALIGN", 1, 1 }, + { "STAGGERED_PATTERN", 0, 1 }, + { "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 }, + { "OUTER_LOOP_CNT", 2, 14 }, + { "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 }, + { "CONSEQ_PASS", 11, 5 }, + { "BURST_WINDOW", 5, 2 }, + { "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 }, + { "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 }, + { "FINE_CAL_STEP_SIZE", 13, 3 }, + { "COARSE_CAL_STEP_SIZE", 9, 4 }, + { "DQ_SEL_QUAD", 7, 2 }, + { "DQ_SEL_LANE", 4, 3 }, + { "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 }, + { "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 }, + { "RD_CNTL_ERROR", 15, 1 }, + { "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 }, + { "RD_CNTL_ERROR_MASK", 15, 1 }, + { "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 }, + { "DISABLE_PARITY_CHECKER", 15, 1 }, + { "GENERATE_EVEN_PARITY", 14, 1 }, + { "FORCE_ON_CLK_GATE", 13, 1 }, + { "DEBUG_BUS_SEL_LO", 12, 1 }, + { "DEBUG_BUS_SEL_HI", 8, 4 }, + { "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 }, + { "INVALID_ADDRESS", 15, 1 }, + { "WR_PAR_ERR", 14, 1 }, + { "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 }, + { "INVALID_ADDRESS_MASK", 15, 1 }, + { "WR_PAR_ERR_MASK", 14, 1 }, + { "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 }, + { "DP18_0_Populated", 15, 1 }, + { "DP18_1_Populated", 14, 1 }, + { "DP18_2_Populated", 13, 1 }, + { "DP18_3_Populated", 12, 1 }, + { "DP18_4_Populated", 11, 1 }, + { "DP18_5_Populated", 10, 1 }, + { "DP18_6_Populated", 9, 1 }, + { "DP18_7_Populated", 8, 1 }, + { "DP18_8_Populated", 7, 1 }, + { "DP18_9_Populated", 6, 1 }, + { "DP18_10_Populated", 5, 1 }, + { "DP18_11_Populated", 4, 1 }, + { "DP18_12_Populated", 3, 1 }, + { "DP18_13_Populated", 2, 1 }, + { "DP18_14_Populated", 1, 1 }, + { "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 }, + { "ADR16_0_Populated", 15, 1 }, + { "ADR16_1_Populated", 14, 1 }, + { "ADR16_2_Populated", 13, 1 }, + { "ADR16_3_Populated", 12, 1 }, + { "ADR12_0_Populated", 7, 1 }, + { "ADR12_1_Populated", 6, 1 }, + { "ADR12_2_Populated", 5, 1 }, + { "ADR12_3_Populated", 4, 1 }, + { "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 }, + { "ATEST_CNTL", 10, 6 }, + { "MC_UPCTL_SCFG", 0x40000, 0 }, + { "bbflags_timing", 8, 4 }, + { "nfifo_nif1_dis", 6, 1 }, + { "hw_low_power_en", 0, 1 }, + { "MC_UPCTL_SCTL", 0x40004, 0 }, + { "MC_UPCTL_STAT", 0x40008, 0 }, + { "lp_trig", 4, 3 }, + { "ctl_stat", 0, 3 }, + { "MC_UPCTL_INTRSTAT", 0x4000c, 0 }, + { "parity_intr", 1, 1 }, + { "ecc_intr", 0, 1 }, + { "MC_UPCTL_MCMD", 0x40040, 0 }, + { "start_cmd", 31, 1 }, + { "cmd_add_del", 24, 4 }, + { "rank_sel", 20, 4 }, + { "bank_addr", 17, 3 }, + { "cmd_addr", 4, 13 }, + { "cmd_opcode0", 0, 4 }, + { "MC_UPCTL_POWCTL", 0x40044, 0 }, + { "MC_UPCTL_POWSTAT", 0x40048, 0 }, + { "MC_UPCTL_CMDTSTAT", 0x4004c, 0 }, + { "MC_UPCTL_CMDTSTATEN", 0x40050, 0 }, + { "MC_UPCTL_MRRCFG0", 0x40060, 0 }, + { "MC_UPCTL_MRRSTAT0", 0x40064, 0 }, + { "mrrstat_beat3", 24, 8 }, + { "mrrstat_beat2", 16, 8 }, + { "mrrstat_beat1", 8, 8 }, + { "mrrstat_beat0", 0, 8 }, + { "MC_UPCTL_MRRSTAT1", 0x40068, 0 }, + { "mrrstat_beat7", 24, 8 }, + { "mrrstat_beat6", 16, 8 }, + { "mrrstat_beat5", 8, 8 }, + { "mrrstat_beat4", 0, 8 }, + { "MC_UPCTL_MCFG1", 0x4007c, 0 }, + { "hw_exit_idle_en", 31, 1 }, + { "hw_idle", 16, 8 }, + { "sr_idle", 0, 8 }, + { "MC_UPCTL_MCFG", 0x40080, 0 }, + { "mddr_lpddr2_clk_stop_idle", 24, 8 }, + { "mddr_lpddr2_en", 22, 2 }, + { "mddr_lpddr2_bl", 20, 2 }, + { "tfaw_cfg", 18, 2 }, + { "pd_exit_mode", 17, 1 }, + { "pd_type", 16, 1 }, + { "pd_idle", 8, 8 }, + { "lpddr2_s4", 6, 1 }, + { "ddr3_en", 5, 1 }, + { "stagger_cs", 4, 1 }, + { "two_t_en", 3, 1 }, + { "bl8int_en", 2, 1 }, + { "cke_or_en", 1, 1 }, + { "mem_bl", 0, 1 }, + { "MC_UPCTL_PPCFG", 0x40084, 0 }, + { "rpmem_dis", 1, 8 }, + { "ppmem_en", 0, 1 }, + { "MC_UPCTL_MSTAT", 0x40088, 0 }, + { "self_refresh", 2, 1 }, + { "clock_stop", 1, 1 }, + { "power_down", 0, 1 }, + { "MC_UPCTL_LPDDR2ZQCFG", 0x4008c, 0 }, + { "zqcl_op", 24, 8 }, + { "zqcl_ma", 16, 8 }, + { "zqcs_op", 8, 8 }, + { "zqcs_ma", 0, 8 }, + { "MC_UPCTL_DTUPDES", 0x40094, 0 }, + { "dtu_rd_missing", 13, 1 }, + { "dtu_eaffl", 9, 4 }, + { "dtu_random_error", 8, 1 }, + { "dtu_err_b7", 7, 1 }, + { "dtu_err_b6", 6, 1 }, + { "dtu_err_b5", 5, 1 }, + { "dtu_err_b4", 4, 1 }, + { "dtu_err_b3", 3, 1 }, + { "dtu_err_b2", 2, 1 }, + { "dtu_err_b1", 1, 1 }, + { "dtu_err_b0", 0, 1 }, + { "MC_UPCTL_DTUNA", 0x40098, 0 }, + { "MC_UPCTL_DTUNE", 0x4009c, 0 }, + { "MC_UPCTL_DTUPRD0", 0x400a0, 0 }, + { "dtu_allbits_1", 16, 16 }, + { "dtu_allbits_0", 0, 16 }, + { "MC_UPCTL_DTUPRD1", 0x400a4, 0 }, + { "dtu_allbits_3", 16, 16 }, + { "dtu_allbits_2", 0, 16 }, + { "MC_UPCTL_DTUPRD2", 0x400a8, 0 }, + { "dtu_allbits_5", 16, 16 }, + { "dtu_allbits_4", 0, 16 }, + { "MC_UPCTL_DTUPRD3", 0x400ac, 0 }, + { "dtu_allbits_7", 16, 16 }, + { "dtu_allbits_6", 0, 16 }, + { "MC_UPCTL_DTUAWDT", 0x400b0, 0 }, + { "number_ranks", 9, 2 }, + { "row_addr_width", 6, 2 }, + { "bank_addr_width", 3, 2 }, + { "column_addr_width", 0, 2 }, + { "MC_UPCTL_TOGCNT1U", 0x400c0, 0 }, + { "MC_UPCTL_TINIT", 0x400c4, 0 }, + { "MC_UPCTL_TRSTH", 0x400c8, 0 }, + { "MC_UPCTL_TOGCNT100N", 0x400cc, 0 }, + { "MC_UPCTL_TREFI", 0x400d0, 0 }, + { "MC_UPCTL_TMRD", 0x400d4, 0 }, + { "MC_UPCTL_TRFC", 0x400d8, 0 }, + { "MC_UPCTL_TRP", 0x400dc, 0 }, + { "prea_extra", 16, 2 }, + { "t_rp", 0, 4 }, + { "MC_UPCTL_TRTW", 0x400e0, 0 }, + { "MC_UPCTL_TAL", 0x400e4, 0 }, + { "MC_UPCTL_TCL", 0x400e8, 0 }, + { "MC_UPCTL_TCWL", 0x400ec, 0 }, + { "MC_UPCTL_TRAS", 0x400f0, 0 }, + { "MC_UPCTL_TRC", 0x400f4, 0 }, + { "MC_UPCTL_TRCD", 0x400f8, 0 }, + { "MC_UPCTL_TRRD", 0x400fc, 0 }, + { "MC_UPCTL_TRTP", 0x40100, 0 }, + { "MC_UPCTL_TWR", 0x40104, 0 }, + { "MC_UPCTL_TWTR", 0x40108, 0 }, + { "MC_UPCTL_TEXSR", 0x4010c, 0 }, + { "MC_UPCTL_TXP", 0x40110, 0 }, + { "MC_UPCTL_TXPDLL", 0x40114, 0 }, + { "MC_UPCTL_TZQCS", 0x40118, 0 }, + { "MC_UPCTL_TZQCSI", 0x4011c, 0 }, + { "MC_UPCTL_TDQS", 0x40120, 0 }, + { "MC_UPCTL_TCKSRE", 0x40124, 0 }, + { "MC_UPCTL_TCKSRX", 0x40128, 0 }, + { "MC_UPCTL_TCKE", 0x4012c, 0 }, + { "MC_UPCTL_TMOD", 0x40130, 0 }, + { "MC_UPCTL_TRSTL", 0x40134, 0 }, + { "MC_UPCTL_TZQCL", 0x40138, 0 }, + { "MC_UPCTL_TMRR", 0x4013c, 0 }, + { "MC_UPCTL_TCKESR", 0x40140, 0 }, + { "MC_UPCTL_TDPD", 0x40144, 0 }, + { "MC_UPCTL_ECCCFG", 0x40180, 0 }, + { "inline_syn_en", 4, 1 }, + { "ecc_en", 3, 1 }, + { "ecc_intr_en", 2, 1 }, + { "MC_UPCTL_ECCTST", 0x40184, 0 }, + { "MC_UPCTL_ECCCLR", 0x40188, 0 }, + { "clr_ecc_log", 1, 1 }, + { "clr_ecc_intr", 0, 1 }, + { "MC_UPCTL_ECCLOG", 0x4018c, 0 }, + { "MC_UPCTL_DTUWACTL", 0x40200, 0 }, + { "dtu_wr_rank", 30, 2 }, + { "dtu_wr_row0", 13, 16 }, + { "dtu_wr_bank", 10, 3 }, + { "dtu_wr_col", 0, 10 }, + { "MC_UPCTL_DTURACTL", 0x40204, 0 }, + { "dtu_rd_rank", 30, 2 }, + { "dtu_rd_row0", 13, 16 }, + { "dtu_rd_bank", 10, 3 }, + { "dtu_rd_col", 0, 10 }, + { "MC_UPCTL_DTUCFG", 0x40208, 0 }, + { "dtu_row_increments", 16, 7 }, + { "dtu_wr_multi_rd", 15, 1 }, + { "dtu_data_mask_en", 14, 1 }, + { "dtu_target_lane", 10, 4 }, + { "dtu_generate_random", 9, 1 }, + { "dtu_incr_banks", 8, 1 }, + { "dtu_incr_cols", 7, 1 }, + { "dtu_nalen", 1, 6 }, + { "dtu_enable", 0, 1 }, + { "MC_UPCTL_DTUECTL", 0x4020c, 0 }, + { "wr_multi_rd_rst", 2, 1 }, + { "run_error_reports", 1, 1 }, + { "run_dtu", 0, 1 }, + { "MC_UPCTL_DTUWD0", 0x40210, 0 }, + { "dtu_wr_byte3", 24, 8 }, + { "dtu_wr_byte2", 16, 8 }, + { "dtu_wr_byte1", 8, 8 }, + { "dtu_wr_byte0", 0, 8 }, + { "MC_UPCTL_DTUWD1", 0x40214, 0 }, + { "dtu_wr_byte7", 24, 8 }, + { "dtu_wr_byte6", 16, 8 }, + { "dtu_wr_byte5", 8, 8 }, + { "dtu_wr_byte4", 0, 8 }, + { "MC_UPCTL_DTUWD2", 0x40218, 0 }, + { "dtu_wr_byte11", 24, 8 }, + { "dtu_wr_byte10", 16, 8 }, + { "dtu_wr_byte9", 8, 8 }, + { "dtu_wr_byte8", 0, 8 }, + { "MC_UPCTL_DTUWD3", 0x4021c, 0 }, + { "dtu_wr_byte15", 24, 8 }, + { "dtu_wr_byte14", 16, 8 }, + { "dtu_wr_byte13", 8, 8 }, + { "dtu_wr_byte12", 0, 8 }, + { "MC_UPCTL_DTUWDM", 0x40220, 0 }, + { "MC_UPCTL_DTURD0", 0x40224, 0 }, + { "dtu_rd_byte3", 24, 8 }, + { "dtu_rd_byte2", 16, 8 }, + { "dtu_rd_byte1", 8, 8 }, + { "dtu_rd_byte0", 0, 8 }, + { "MC_UPCTL_DTURD1", 0x40228, 0 }, + { "dtu_rd_byte7", 24, 8 }, + { "dtu_rd_byte6", 16, 8 }, + { "dtu_rd_byte5", 8, 8 }, + { "dtu_rd_byte4", 0, 8 }, + { "MC_UPCTL_DTURD2", 0x4022c, 0 }, + { "dtu_rd_byte11", 24, 8 }, + { "dtu_rd_byte10", 16, 8 }, + { "dtu_rd_byte9", 8, 8 }, + { "dtu_rd_byte8", 0, 8 }, + { "MC_UPCTL_DTURD3", 0x40230, 0 }, + { "dtu_rd_byte15", 24, 8 }, + { "dtu_rd_byte14", 16, 8 }, + { "dtu_rd_byte13", 8, 8 }, + { "dtu_rd_byte12", 0, 8 }, + { "MC_UPCTL_DTULFSRWD", 0x40234, 0 }, + { "MC_UPCTL_DTULFSRRD", 0x40238, 0 }, + { "MC_UPCTL_DTUEAF", 0x4023c, 0 }, + { "ea_rank", 30, 2 }, + { "ea_row0", 13, 16 }, + { "ea_bank", 10, 3 }, + { "ea_column", 0, 10 }, + { "MC_UPCTL_DFITCTRLDELAY", 0x40240, 0 }, + { "MC_UPCTL_DFIODTCFG", 0x40244, 0 }, + { "rank3_odt_default", 28, 1 }, + { "rank3_odt_write_sel", 27, 1 }, + { "rank3_odt_write_nsel", 26, 1 }, + { "rank3_odt_read_sel", 25, 1 }, + { "rank3_odt_read_nsel", 24, 1 }, + { "rank2_odt_default", 20, 1 }, + { "rank2_odt_write_sel", 19, 1 }, + { "rank2_odt_write_nsel", 18, 1 }, + { "rank2_odt_read_sel", 17, 1 }, + { "rank2_odt_read_nsel", 16, 1 }, + { "rank1_odt_default", 12, 1 }, + { "rank1_odt_write_sel", 11, 1 }, + { "rank1_odt_write_nsel", 10, 1 }, + { "rank1_odt_read_sel", 9, 1 }, + { "rank1_odt_read_nsel", 8, 1 }, + { "rank0_odt_default", 4, 1 }, + { "rank0_odt_write_sel", 3, 1 }, + { "rank0_odt_write_nsel", 2, 1 }, + { "rank0_odt_read_sel", 1, 1 }, + { "rank0_odt_read_nsel", 0, 1 }, + { "MC_UPCTL_DFIODTCFG1", 0x40248, 0 }, + { "odt_len_b8_r", 24, 3 }, + { "odt_len_bl8_w", 16, 3 }, + { "odt_lat_r", 8, 5 }, + { "odt_lat_w", 0, 5 }, + { "MC_UPCTL_DFIODTRANKMAP", 0x4024c, 0 }, + { "odt_rank_map3", 12, 4 }, + { "odt_rank_map2", 8, 4 }, + { "odt_rank_map1", 4, 4 }, + { "odt_rank_map0", 0, 4 }, + { "MC_UPCTL_DFITPHYWRDATA", 0x40250, 0 }, + { "MC_UPCTL_DFITPHYWRLAT", 0x40254, 0 }, + { "MC_UPCTL_DFITRDDATAEN", 0x40260, 0 }, + { "MC_UPCTL_DFITPHYRDLAT", 0x40264, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE0", 0x40270, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE1", 0x40274, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE2", 0x40278, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE3", 0x4027c, 0 }, + { "MC_UPCTL_DFITCTRLUPDMIN", 0x40280, 0 }, + { "MC_UPCTL_DFITCTRLUPDMAX", 0x40284, 0 }, + { "MC_UPCTL_DFITCTRLUPDDLY", 0x40288, 0 }, + { "MC_UPCTL_DFIUPDCFG", 0x40290, 0 }, + { "dfi_phyupd_en", 1, 1 }, + { "dfi_ctrlupd_en", 0, 1 }, + { "MC_UPCTL_DFITREFMSKI", 0x40294, 0 }, + { "MC_UPCTL_DFITCTRLUPDI", 0x40298, 0 }, + { "MC_UPCTL_DFITRCFG0", 0x402ac, 0 }, + { "dfi_wrlvl_rank_sel", 16, 4 }, + { "dfi_rdlvl_edge", 4, 9 }, + { "dfi_rdlvl_rank_sel", 0, 4 }, + { "MC_UPCTL_DFITRSTAT0", 0x402b0, 0 }, + { "dfi_wrlvl_mode", 16, 2 }, + { "dfi_rdlvl_gate_mode", 8, 2 }, + { "dfi_rdlvl_mode", 0, 2 }, + { "MC_UPCTL_DFITRWRLVLEN", 0x402b4, 0 }, + { "MC_UPCTL_DFITRRDLVLEN", 0x402b8, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEEN", 0x402bc, 0 }, + { "MC_UPCTL_DFISTSTAT0", 0x402c0, 0 }, + { "dfi_data_byte_disable", 16, 9 }, + { "dfi_freq_ratio", 4, 2 }, + { "dfi_init_start0", 1, 1 }, + { "dfi_init_complete", 0, 1 }, + { "MC_UPCTL_DFISTCFG0", 0x402c4, 0 }, + { "dfi_data_byte_disable_en", 2, 1 }, + { "dfi_freq_ratio_en", 1, 1 }, + { "dfi_init_start", 0, 1 }, + { "MC_UPCTL_DFISTCFG1", 0x402c8, 0 }, + { "dfi_dram_clk_disable_en_dpd", 1, 1 }, + { "dfi_dram_clk_disable_en", 0, 1 }, + { "MC_UPCTL_DFITDRAMCLKEN", 0x402d0, 0 }, + { "MC_UPCTL_DFITDRAMCLKDIS", 0x402d4, 0 }, + { "MC_UPCTL_DFISTCFG2", 0x402d8, 0 }, + { "parity_en", 1, 1 }, + { "parity_intr_en", 0, 1 }, + { "MC_UPCTL_DFISTPARCLR", 0x402dc, 0 }, + { "parity_log_clr", 1, 1 }, + { "parity_intr_clr", 0, 1 }, + { "MC_UPCTL_DFISTPARLOG", 0x402e0, 0 }, + { "MC_UPCTL_DFILPCFG0", 0x402f0, 0 }, + { "dfi_lp_wakeup_dpd", 28, 4 }, + { "dfi_lp_en_dpd", 24, 1 }, + { "dfi_tlp_resp", 16, 4 }, + { "dfi_lp_en_sr", 8, 1 }, + { "dfi_lp_wakeup_pd", 4, 4 }, + { "dfi_lp_en_pd", 0, 1 }, + { "MC_UPCTL_DFITRWRLVLRESP0", 0x40300, 0 }, + { "MC_UPCTL_DFITRWRLVLRESP1", 0x40304, 0 }, + { "MC_UPCTL_DFITRWRLVLRESP2", 0x40308, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP0", 0x4030c, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP1", 0x40310, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP2", 0x40314, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY0", 0x40318, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY1", 0x4031c, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY2", 0x40320, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY0", 0x40324, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY1", 0x40328, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY2", 0x4032c, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x40330, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x40334, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x40338, 0 }, + { "MC_UPCTL_DFITRCMD", 0x4033c, 0 }, + { "dfitrcmd_start", 31, 1 }, + { "dfitrcmd_en", 4, 9 }, + { "dfitrcmd_opcode", 0, 2 }, + { "MC_UPCTL_IPVR", 0x403f8, 0 }, + { "MC_UPCTL_IPTR", 0x403fc, 0 }, + { "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 }, + { "PHY_DRAM_WL", 17, 5 }, + { "PHY_CALIB_DONE", 5, 1 }, + { "CTL_CAL_REQ", 4, 1 }, + { "CTL_CKE", 3, 1 }, + { "CTL_RST_N", 2, 1 }, + { "DDRIO_ENABLE", 1, 1 }, + { "PHY_RST_N", 0, 1 }, + { "MC_P_PERFORMANCE_CTRL", 0x41304, 0 }, + { "STALL_CHK_BIT", 2, 1 }, + { "DDR3_BRC_MODE", 1, 1 }, + { "RMW_PERF_CTRL", 0, 1 }, + { "MC_P_ECC_CTRL", 0x41308, 0 }, + { "ECC_BYPASS_BIST", 1, 1 }, + { "ECC_DISABLE", 0, 1 }, + { "MC_P_PAR_ENABLE", 0x4130c, 0 }, + { "ECC_UE_PAR_ENABLE", 3, 1 }, + { "ECC_CE_PAR_ENABLE", 2, 1 }, + { "PERR_REG_INT_ENABLE", 1, 1 }, + { "PERR_BLK_INT_ENABLE", 0, 1 }, + { "MC_P_PAR_CAUSE", 0x41310, 0 }, + { "ECC_UE_PAR_CAUSE", 3, 1 }, + { "ECC_CE_PAR_CAUSE", 2, 1 }, + { "FIFOR_PAR_CAUSE", 1, 1 }, + { "RDATA_FIFOR_PAR_CAUSE", 0, 1 }, + { "MC_P_INT_ENABLE", 0x41314, 0 }, + { "ECC_UE_INT_ENABLE", 2, 1 }, + { "ECC_CE_INT_ENABLE", 1, 1 }, + { "PERR_INT_ENABLE", 0, 1 }, + { "MC_P_INT_CAUSE", 0x41318, 0 }, + { "ECC_UE_INT_CAUSE", 2, 1 }, + { "ECC_CE_INT_CAUSE", 1, 1 }, + { "PERR_INT_CAUSE", 0, 1 }, + { "MC_P_ECC_STATUS", 0x4131c, 0 }, + { "ECC_CECNT", 16, 16 }, + { "ECC_UECNT", 0, 16 }, + { "MC_P_PHY_CTRL", 0x41320, 0 }, + { "MC_P_STATIC_CFG_STATUS", 0x41324, 0 }, + { "STATIC_AWEN", 23, 1 }, + { "STATIC_SWLAT", 18, 5 }, + { "STATIC_WLAT", 17, 1 }, + { "STATIC_ALIGN", 16, 1 }, + { "STATIC_SLAT", 11, 5 }, + { "STATIC_LAT", 10, 1 }, + { "STATIC_MODE", 9, 1 }, + { "STATIC_DEN", 6, 3 }, + { "STATIC_ORG", 5, 1 }, + { "STATIC_RKS", 4, 1 }, + { "STATIC_WIDTH", 1, 3 }, + { "STATIC_SLOW", 0, 1 }, + { "MC_P_CORE_PCTL_STAT", 0x41328, 0 }, + { "MC_P_DEBUG_CNT", 0x4132c, 0 }, + { "WDATA_OCNT", 8, 5 }, + { "RDATA_OCNT", 0, 5 }, + { "MC_CE_ERR_DATA_RDATA", 0x41330, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x41334, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x41338, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x41340, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x41344, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x41348, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41350, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41354, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41358, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x4135c, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41360, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41364, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x41368, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x4136c, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41370, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41374, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41378, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41380, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41384, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x41388, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x41390, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x41394, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x41398, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x4139c, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x413a0, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x413a4, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x413a8, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x413ac, 0 }, + { "MC_CE_ADDR", 0x413b0, 0 }, + { "MC_UE_ADDR", 0x413b4, 0 }, + { "MC_P_DEEP_SLEEP", 0x413b8, 0 }, + { "SleepStatus", 1, 1 }, + { "SleepReq", 0, 1 }, + { "MC_P_FPGA_BONUS", 0x413bc, 0 }, + { "MC_P_DEBUG_CFG", 0x413c0, 0 }, + { "DEBUG_OR", 15, 1 }, + { "DEBUG_HI", 14, 1 }, + { "DEBUG_RPT", 13, 1 }, + { "DEBUGPAGE", 10, 3 }, + { "DEBUGSELH", 5, 5 }, + { "DEBUGSELL", 0, 5 }, + { "MC_P_DEBUG_RPT", 0x413c4, 0 }, + { "MC_P_BIST_CMD", 0x41400, 0 }, + { "START_BIST", 31, 1 }, + { "BURST_LEN", 16, 2 }, + { "BIST_CMD_GAP", 8, 8 }, + { "BIST_OPCODE", 0, 2 }, + { "MC_P_BIST_CMD_ADDR", 0x41404, 0 }, + { "MC_P_BIST_CMD_LEN", 0x41408, 0 }, + { "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 }, + { "MC_P_BIST_USER_WDATA0", 0x41414, 0 }, + { "MC_P_BIST_USER_WDATA1", 0x41418, 0 }, + { "MC_P_BIST_USER_WDATA2", 0x4141c, 0 }, + { "USER_DATA_MASK", 8, 9 }, + { "USER_DATA2", 0, 8 }, + { "MC_P_BIST_NUM_ERR", 0x41480, 0 }, + { "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x41488, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x41490, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x41494, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x41498, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 }, + { "MC_P_BIST_CRC_SEED", 0x414d0, 0 }, + { NULL } +}; + +struct reg_info t5_mc_1_regs[] = { + { "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x4f000, 0 }, + { "DP18_PLL_LOCK", 1, 15 }, + { "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x4f004, 0 }, + { "AD32S_PLL_LOCK", 14, 2 }, + { "MC_DDRPHY_PC_RANK_PAIR0", 0x4f008, 0 }, + { "RANK_PAIR0_PRI", 13, 3 }, + { "RANK_PAIR0_PRI_V", 12, 1 }, + { "RANK_PAIR0_SEC", 9, 3 }, + { "RANK_PAIR0_SEC_V", 8, 1 }, + { "RANK_PAIR1_PRI", 5, 3 }, + { "RANK_PAIR1_PRI_V", 4, 1 }, + { "RANK_PAIR1_SEC", 1, 3 }, + { "RANK_PAIR1_SEC_V", 0, 1 }, + { "MC_DDRPHY_PC_RANK_PAIR1", 0x4f00c, 0 }, + { "RANK_PAIR2_PRI", 13, 3 }, + { "RANK_PAIR2_PRI_V", 12, 1 }, + { "RANK_PAIR2_SEC", 9, 3 }, + { "RANK_PAIR2_SEC_V", 8, 1 }, + { "RANK_PAIR3_PRI", 5, 3 }, + { "RANK_PAIR3_PRI_V", 4, 1 }, + { "RANK_PAIR3_SEC", 1, 3 }, + { "RANK_PAIR3_SEC_V", 0, 1 }, + { "MC_DDRPHY_PC_BASE_CNTR0", 0x4f010, 0 }, + { "MC_DDRPHY_PC_RELOAD_VALUE0", 0x4f014, 0 }, + { "PERIODIC_CAL_REQ_EN", 15, 1 }, + { "PERIODIC_RELOAD_VALUE0", 0, 15 }, + { "MC_DDRPHY_PC_BASE_CNTR1", 0x4f018, 0 }, + { "MC_DDRPHY_PC_CAL_TIMER", 0x4f01c, 0 }, + { "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x4f020, 0 }, + { "MC_DDRPHY_PC_ZCAL_TIMER", 0x4f024, 0 }, + { "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x4f028, 0 }, + { "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4f02c, 0 }, + { "PER_ENA_RANK_PAIR", 12, 4 }, + { "PER_ENA_ZCAL", 11, 1 }, + { "PER_ENA_SYSCLK_ALIGN", 10, 1 }, + { "ENA_PER_RDCLK_ALIGN", 9, 1 }, + { "ENA_PER_DQS_ALIGN", 8, 1 }, + { "ENA_PER_READ_CTR", 7, 1 }, + { "PER_NEXT_RANK_PAIR", 5, 2 }, + { "FAST_SIM_PER_CNTR", 4, 1 }, + { "START_INIT_CAL", 3, 1 }, + { "START_PER_CAL", 2, 1 }, + { "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4f03c, 0 }, + { "PER_ZCAL_ENA_RANK", 8, 8 }, + { "PER_ZCAL_NEXT_RANK", 5, 3 }, + { "START_PER_ZCAL", 4, 1 }, + { "MC_DDRPHY_PC_CONFIG0", 0x4f030, 0 }, + { "PROTOCOL_DDR", 12, 4 }, + { "DATA_MUX4_1MODE", 11, 1 }, + { "DDR4_CMD_SIG_REDUCTION", 9, 1 }, + { "SYSCLK_2X_MEMINTCLKO", 8, 1 }, + { "RANK_OVERRIDE", 7, 1 }, + { "RANK_OVERRIDE_VALUE", 4, 3 }, + { "LOW_LATENCY", 3, 1 }, + { "DDR4_BANK_REFRESH", 2, 1 }, + { "DDR4_VLEVEL_BANK_GROUP", 1, 1 }, + { "MC_DDRPHY_PC_CONFIG1", 0x4f034, 0 }, + { "WRITE_LATENCY_OFFSET", 12, 4 }, + { "READ_LATENCY_OFFSET", 8, 4 }, + { "MEMCTL_CIC_FAST", 7, 1 }, + { "MEMCTL_CTRN_IGNORE", 6, 1 }, + { "DISABLE_MEMCTL_CAL", 5, 1 }, + { "MC_DDRPHY_PC_RESETS", 0x4f038, 0 }, + { "PLL_RESET", 15, 1 }, + { "SYSCLK_RESET", 14, 1 }, + { "MC_DDRPHY_PC_ERROR_STATUS0", 0x4f048, 0 }, + { "RC_ERROR", 15, 1 }, + { "WC_ERROR", 14, 1 }, + { "SEQ_ERROR", 13, 1 }, + { "CC_ERROR", 12, 1 }, + { "APB_ERROR", 11, 1 }, + { "PC_ERROR", 10, 1 }, + { "MC_DDRPHY_PC_ERROR_MASK0", 0x4f04c, 0 }, + { "RC_ERROR_MASK", 15, 1 }, + { "WC_ERROR_MASK", 14, 1 }, + { "SEQ_ERROR_MASK", 13, 1 }, + { "CC_ERROR_MASK", 12, 1 }, + { "APB_ERROR_MASK", 11, 1 }, + { "PC_ERROR_MASK", 10, 1 }, + { "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x4f050, 0 }, + { "PVTP", 11, 5 }, + { "PVTN", 6, 5 }, + { "PVT_OVERRIDE", 5, 1 }, + { "ENABLE_ZCAL", 4, 1 }, + { "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x4f054, 0 }, + { "VREFDQ0DSGN", 15, 1 }, + { "VREFDQ0D", 11, 4 }, + { "VREFDQ1DSGN", 10, 1 }, + { "VREFDQ1D", 6, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x4f058, 0 }, + { "ENA_WR_LEVEL", 15, 1 }, + { "ENA_INITIAL_PAT_WR", 14, 1 }, + { "ENA_DQS_ALIGN", 13, 1 }, + { "ENA_RDCLK_ALIGN", 12, 1 }, + { "ENA_READ_CTR", 11, 1 }, + { "ENA_WRITE_CTR", 10, 1 }, + { "ENA_INITIAL_COARSE_WR", 9, 1 }, + { "ENA_COARSE_RD", 8, 1 }, + { "ENA_CUSTOM_RD", 7, 1 }, + { "ENA_CUSTOM_WR", 6, 1 }, + { "ABORT_ON_CAL_ERROR", 5, 1 }, + { "ENA_DIGITAL_EYE", 4, 1 }, + { "ENA_RANK_PAIR", 0, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4f05c, 0 }, + { "REFRESH_COUNT", 12, 4 }, + { "REFRESH_CONTROL", 10, 2 }, + { "REFRESH_ALL_RANKS", 9, 1 }, + { "REFRESH_INTERVAL", 0, 7 }, + { "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x4f060, 0 }, + { "ERROR_WR_LEVEL", 15, 1 }, + { "ERROR_INITIAL_PAT_WRITE", 14, 1 }, + { "ERROR_DQS_ALIGN", 13, 1 }, + { "ERROR_RDCLK_ALIGN", 12, 1 }, + { "ERROR_READ_CTR", 11, 1 }, + { "ERROR_WRITE_CTR", 10, 1 }, + { "ERROR_INITIAL_COARSE_WR", 9, 1 }, + { "ERROR_COARSE_RD", 8, 1 }, + { "ERROR_CUSTOM_RD", 7, 1 }, + { "ERROR_CUSTOM_WR", 6, 1 }, + { "ERROR_DIGITAL_EYE", 5, 1 }, + { "ERROR_RANK_PAIR", 0, 4 }, + { "MC_DDRPHY_PC_INIT_CAL_MASK", 0x4f068, 0 }, + { "ERROR_WR_LEVEL_MASK", 15, 1 }, + { "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 }, + { "ERROR_DQS_ALIGN_MASK", 13, 1 }, + { "ERROR_RDCLK_ALIGN_MASK", 12, 1 }, + { "ERROR_READ_CTR_MASK", 11, 1 }, + { "ERROR_WRITE_CTR_MASK", 10, 1 }, + { "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 }, + { "ERROR_COARSE_RD_MASK", 8, 1 }, + { "ERROR_CUSTOM_RD_MASK", 7, 1 }, + { "ERROR_CUSTOM_WR_MASK", 6, 1 }, + { "ERROR_DIGITAL_EYE_MASK", 5, 1 }, + { "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x4f064, 0 }, + { "INIT_CAL_COMPLETE", 12, 4 }, + { "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4f06c, 0 }, + { "PVTP", 11, 5 }, + { "PVTN", 6, 5 }, + { "MC_DDRPHY_PC_MR0_PRI_RP", 0x4f070, 0 }, + { "MC_DDRPHY_PC_MR1_PRI_RP", 0x4f074, 0 }, + { "MC_DDRPHY_PC_MR2_PRI_RP", 0x4f078, 0 }, + { "MC_DDRPHY_PC_MR3_PRI_RP", 0x4f07c, 0 }, + { "MC_DDRPHY_PC_MR0_SEC_RP", 0x4f080, 0 }, + { "MC_DDRPHY_PC_MR1_SEC_RP", 0x4f084, 0 }, + { "MC_DDRPHY_PC_MR2_SEC_RP", 0x4f088, 0 }, + { "MC_DDRPHY_PC_MR3_SEC_RP", 0x4f08c, 0 }, + { "MC_DDRPHY_PC_RANK_GROUP", 0x4f044, 0 }, + { "ADDR_MIRROR_RP0_PRI", 15, 1 }, + { "ADDR_MIRROR_RP0_SEC", 14, 1 }, + { "ADDR_MIRROR_RP1_PRI", 13, 1 }, + { "ADDR_MIRROR_RP1_SEC", 12, 1 }, + { "ADDR_MIRROR_RP2_PRI", 11, 1 }, + { "ADDR_MIRROR_RP2_SEC", 10, 1 }, + { "ADDR_MIRROR_RP3_PRI", 9, 1 }, + { "ADDR_MIRROR_RP3_SEC", 8, 1 }, + { "RANK_GROUPING", 6, 2 }, + { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d000, 0 }, + { "BIT_ENABLE_0_11", 4, 12 }, + { "BIT_ENABLE_12_15", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d004, 0 }, + { "DI_ADR0_ADR1", 15, 1 }, + { "DI_ADR2_ADR3", 14, 1 }, + { "DI_ADR4_ADR5", 13, 1 }, + { "DI_ADR6_ADR7", 12, 1 }, + { "DI_ADR8_ADR9", 11, 1 }, + { "DI_ADR10_ADR11", 10, 1 }, + { "DI_ADR12_ADR13", 9, 1 }, + { "DI_ADR14_ADR15", 8, 1 }, + { "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d010, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d014, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d018, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d01c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d020, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d024, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d028, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d02c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d030, 0 }, + { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 }, + { "ADR_TEST_DATA_EN", 7, 1 }, + { "DADR_TEST_MODE", 5, 2 }, + { "ADR_TEST_4TO1_MODE", 4, 1 }, + { "ADR_TEST_RESET", 3, 1 }, + { "ADR_TEST_GEN_EN", 2, 1 }, + { "ADR_TEST_CLEAR_ERROR", 1, 1 }, + { "ADR_TEST_CHECK_EN", 0, 1 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d040, 0 }, + { "EN_SLICE_N_WR_0", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d044, 0 }, + { "EN_SLICE_N_WR_1", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d048, 0 }, + { "EN_SLICE_N_WR_2", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d04c, 0 }, + { "EN_SLICE_N_WR_3", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d050, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d054, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d058, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d05c, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d080, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d084, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d060, 0 }, + { "POST_CURSOR0", 12, 4 }, + { "POST_CURSOR1", 8, 4 }, + { "POST_CURSOR2", 4, 4 }, + { "POST_CURSOR3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d0a0, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d0a4, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d068, 0 }, + { "SLEW_CTL0", 12, 4 }, + { "SLEW_CTL1", 8, 4 }, + { "SLEW_CTL2", 4, 4 }, + { "SLEW_CTL3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d0a8, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d0ac, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d0b0, 0 }, + { "ADR_LANE_0_11_PD", 4, 12 }, + { "ADR_LANE_12_15_PD", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d200, 0 }, + { "BIT_ENABLE_0_11", 4, 12 }, + { "BIT_ENABLE_12_15", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d204, 0 }, + { "DI_ADR0_ADR1", 15, 1 }, + { "DI_ADR2_ADR3", 14, 1 }, + { "DI_ADR4_ADR5", 13, 1 }, + { "DI_ADR6_ADR7", 12, 1 }, + { "DI_ADR8_ADR9", 11, 1 }, + { "DI_ADR10_ADR11", 10, 1 }, + { "DI_ADR12_ADR13", 9, 1 }, + { "DI_ADR14_ADR15", 8, 1 }, + { "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d210, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d214, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d218, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d21c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d220, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d224, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d228, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d22c, 0 }, + { "ADR_DELAY_BITS1_7", 8, 7 }, + { "ADR_DELAY_BITS9_15", 0, 7 }, + { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d230, 0 }, + { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 }, + { "ADR_TEST_DATA_EN", 7, 1 }, + { "DADR_TEST_MODE", 5, 2 }, + { "ADR_TEST_4TO1_MODE", 4, 1 }, + { "ADR_TEST_RESET", 3, 1 }, + { "ADR_TEST_GEN_EN", 2, 1 }, + { "ADR_TEST_CLEAR_ERROR", 1, 1 }, + { "ADR_TEST_CHECK_EN", 0, 1 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d240, 0 }, + { "EN_SLICE_N_WR_0", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d244, 0 }, + { "EN_SLICE_N_WR_1", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d248, 0 }, + { "EN_SLICE_N_WR_2", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d24c, 0 }, + { "EN_SLICE_N_WR_3", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d250, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d254, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d258, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d25c, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d280, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d284, 0 }, + { "SLICE_SEL_REG_BITS0_1", 14, 2 }, + { "SLICE_SEL_REG_BITS2_3", 12, 2 }, + { "SLICE_SEL_REG_BITS4_5", 10, 2 }, + { "SLICE_SEL_REG_BITS6_7", 8, 2 }, + { "SLICE_SEL_REG_BITS8_9", 6, 2 }, + { "SLICE_SEL_REG_BITS10_11", 4, 2 }, + { "SLICE_SEL_REG_BITS12_13", 2, 2 }, + { "SLICE_SEL_REG_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d260, 0 }, + { "POST_CURSOR0", 12, 4 }, + { "POST_CURSOR1", 8, 4 }, + { "POST_CURSOR2", 4, 4 }, + { "POST_CURSOR3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d2a0, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d2a4, 0 }, + { "POST_CUR_SEL_BITS0_1", 14, 2 }, + { "POST_CUR_SEL_BITS2_3", 12, 2 }, + { "POST_CUR_SEL_BITS4_5", 10, 2 }, + { "POST_CUR_SEL_BITS6_7", 8, 2 }, + { "POST_CUR_SEL_BITS8_9", 6, 2 }, + { "POST_CUR_SEL_BITS10_11", 4, 2 }, + { "POST_CUR_SEL_BITS12_13", 2, 2 }, + { "POST_CUR_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d268, 0 }, + { "SLEW_CTL0", 12, 4 }, + { "SLEW_CTL1", 8, 4 }, + { "SLEW_CTL2", 4, 4 }, + { "SLEW_CTL3", 0, 4 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d2a8, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d2ac, 0 }, + { "SLEW_CTL_SEL_BITS0_1", 14, 2 }, + { "SLEW_CTL_SEL_BITS2_3", 12, 2 }, + { "SLEW_CTL_SEL_BITS4_5", 10, 2 }, + { "SLEW_CTL_SEL_BITS6_7", 8, 2 }, + { "SLEW_CTL_SEL_BITS8_9", 6, 2 }, + { "SLEW_CTL_SEL_BITS10_11", 4, 2 }, + { "SLEW_CTL_SEL_BITS12_13", 2, 2 }, + { "SLEW_CTL_SEL_BITS14_15", 0, 2 }, + { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d2b0, 0 }, + { "ADR_LANE_0_11_PD", 4, 12 }, + { "ADR_LANE_12_15_PD", 0, 4 }, + { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x4e0c0, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x4e0c4, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "VREG_VREGSPARE", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "INTERP_SIG_SLEW_0_3", 1, 4 }, + { "ANALOG_WRAPON", 0, 1 }, + { "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x4e0c8, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESE", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "CE0DLTVCC", 0, 2 }, + { "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x4e0cc, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x4e0d0, 0 }, + { "SLEW_LATE_SAMPLE", 15, 1 }, + { "SYSCLK_ROT", 8, 7 }, + { "BB_LOCK", 7, 1 }, + { "SLEW_EARLY_SAMPLE", 6, 1 }, + { "SLEW_DONE_STATUS", 4, 2 }, + { "SLEW_CNTL", 0, 4 }, + { "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x4e0d4, 0 }, + { "FLUSH", 15, 1 }, + { "GIANT_MUX_TEST_EN", 14, 1 }, + { "GIANT_MUX_TEST_VAL", 13, 1 }, + { "HS_PROBE_A_SEL_", 8, 4 }, + { "HS_PROBE_B_SEL_", 4, 4 }, + { "ATEST1CTL0", 3, 1 }, + { "ATEST1CTL1", 2, 1 }, + { "ATEST1CTL2", 1, 1 }, + { "ATEST1CTL3", 0, 1 }, + { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x4e0d8, 0 }, + { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x4e0dc, 0 }, + { "MC_DDRPHY_ADR_POWERDOWN_1", 0x4e0e0, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x4e0e4, 0 }, + { "SLEW_CAL_ENABLE", 15, 1 }, + { "SLEW_CAL_START", 14, 1 }, + { "SLEW_CAL_OVERRIDE_EN", 12, 1 }, + { "SLEW_CAL_OVERRIDE", 8, 4 }, + { "SLEW_TARGET_PR_OFFSET", 0, 5 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c000, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c004, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c1f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c1f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c008, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c00c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c010, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c014, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c1f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c018, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c01c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c1cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c1d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c0c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c0c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c024, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c170, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c174, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c0e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c0e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c0e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c0ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c0f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c0f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c0f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c0fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c100, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c104, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c108, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c10c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c110, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c114, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c118, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c11c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c120, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c124, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c128, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c12c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c130, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c134, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c138, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c13c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c140, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c144, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c148, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c14c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c150, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c154, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c158, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c15c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c160, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c164, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c168, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c16c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c030, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c034, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c1c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c1c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c1c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c180, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c184, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c188, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c18c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c190, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c194, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c198, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c19c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c1a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c1a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c1a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c1ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c028, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c038, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c03c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c040, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c044, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c04c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c050, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c054, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c05c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c060, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c064, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c068, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c06c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c070, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c1d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c1dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c1e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c1e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c1e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c1ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c1d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c074, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c020, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c0c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c0cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c0d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c078, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c0d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c0d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c1b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c1b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c0dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c02c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c1fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c048, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c200, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c204, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c3f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c3f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c208, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c20c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c210, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c214, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c3f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c218, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c21c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c3cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c3d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c2c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c2c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c224, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c370, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c374, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c2e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c2e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c2e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c2ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c2f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c2f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c2f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c2fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c300, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c304, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c308, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c30c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c310, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c314, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c318, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c31c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c320, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c324, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c328, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c32c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c330, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c334, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c338, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c33c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c340, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c344, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c348, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c34c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c350, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c354, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c358, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c35c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c360, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c364, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c368, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c36c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c230, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c234, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c3c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c3c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c3c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c380, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c384, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c388, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c38c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c390, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c394, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c398, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c39c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c3a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c3a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c3a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c3ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c228, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c238, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c23c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c240, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c244, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c24c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c250, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c254, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c25c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c260, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c264, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c268, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c26c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c270, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c3d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c3dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c3e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c3e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c3e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c3ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c3d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c274, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c220, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c2c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c2cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c2d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c278, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c2d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c2d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c3b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c3b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c2dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c22c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c3fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c248, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c400, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c404, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c5f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c5f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c408, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c40c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c410, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c414, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c5f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c418, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c41c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c5cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c5d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c4c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c4c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c424, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c570, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c574, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c4e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c4e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c4e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c4ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c4f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c4f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c4f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c4fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c500, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c504, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c508, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c50c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c510, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c514, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c518, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c51c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c520, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c524, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c528, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c52c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c530, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c534, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c538, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c53c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c540, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c544, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c548, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c54c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c550, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c554, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c558, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c55c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c560, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c564, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c568, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c56c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c430, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c434, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c5c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c5c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c5c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c580, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c584, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c588, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c58c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c590, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c594, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c598, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c59c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c5a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c5a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c5a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c5ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c428, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c438, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c43c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c440, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c444, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c44c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c450, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c454, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c45c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c460, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c464, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c468, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c46c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c470, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c5d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c5dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c5e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c5e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c5e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c5ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c5d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c474, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c420, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c4c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c4cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c4d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c478, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c4d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c4d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c5b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c5b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c4dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c42c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c5fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c448, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c600, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c604, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c7f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c7f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c608, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c60c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c610, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c614, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c7f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c618, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c61c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c7cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c7d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c6c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c6c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c624, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c770, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c774, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c6e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c6e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c6e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c6ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c6f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c6f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c6f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c6fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c700, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c704, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c708, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c70c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c710, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c714, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c718, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c71c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c720, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c724, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c728, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c72c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c730, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c734, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c738, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c73c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c740, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c744, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c748, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c74c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c750, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c754, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c758, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c75c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c760, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c764, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c768, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c76c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c630, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c634, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c7c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c7c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c7c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c780, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c784, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c788, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c78c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c790, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c794, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c798, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c79c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c7a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c7a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c7a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c7ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c628, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c638, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c63c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c640, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c644, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c64c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c650, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c654, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c65c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c660, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c664, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c668, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c66c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c670, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c7d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c7dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c7e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c7e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c7e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c7ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c7d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c674, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c620, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c6c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c6cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c6d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c678, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c6d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c6d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c7b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c7b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c6dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c62c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c7fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c648, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c800, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c804, 0 }, + { "DATA_BIT_ENABLE_16_23", 8, 8 }, + { "DFT_FORCE_OUTPUTS", 7, 1 }, + { "DFT_PRBS7_GEN_EN", 6, 1 }, + { "WRAPSEL", 5, 1 }, + { "MRS_CMD_DATA_N0", 3, 1 }, + { "MRS_CMD_DATA_N1", 2, 1 }, + { "MRS_CMD_DATA_N2", 1, 1 }, + { "MRS_CMD_DATA_N3", 0, 1 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c9f0, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c9f4, 0 }, + { "DATA_BIT_DISABLE_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c808, 0 }, + { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c80c, 0 }, + { "DATA_BIT_DIR_16_23", 8, 8 }, + { "WL_ADVANCE_DISABLE", 7, 1 }, + { "DISABLE_PING_PONG", 6, 1 }, + { "DELAY_PING_PONG_HALF", 5, 1 }, + { "ADVANCE_PING_PONG", 4, 1 }, + { "ATEST_MUX_CTL0", 3, 1 }, + { "ATEST_MUX_CTL1", 2, 1 }, + { "ATEST_MUX_CTL2", 1, 1 }, + { "ATEST_MUX_CTL3", 0, 1 }, + { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c810, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c814, 0 }, + { "QUAD0_CLK16_BIT0", 15, 1 }, + { "QUAD1_CLK16_BIT1", 14, 1 }, + { "QUAD2_CLK16_BIT2", 13, 1 }, + { "QUAD3_CLK16_BIT3", 12, 1 }, + { "QUAD0_CLK18_BIT4", 11, 1 }, + { "QUAD1_CLK18_BIT5", 10, 1 }, + { "QUAD2_CLK20_BIT6", 9, 1 }, + { "QUAD3_CLK20_BIT7", 8, 1 }, + { "QUAD2_CLK22_BIT8", 7, 1 }, + { "QUAD3_CLK22_BIT9", 6, 1 }, + { "CLK16_SINGLE_ENDED_BIT10", 5, 1 }, + { "CLK18_SINGLE_ENDED_BIT11", 4, 1 }, + { "CLK20_SINGLE_ENDED_BIT12", 3, 1 }, + { "CLK22_SINGLE_ENDED_BIT13", 2, 1 }, + { "QUAD2_CLK18_BIT14", 1, 1 }, + { "QUAD3_CLK18_BIT15", 0, 1 }, + { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c9f8, 0 }, + { "DQ_WR_OFFSET_N0", 12, 4 }, + { "DQ_WR_OFFSET_N1", 8, 4 }, + { "DQ_WR_OFFSET_N2", 4, 4 }, + { "DQ_WR_OFFSET_N3", 0, 4 }, + { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c818, 0 }, + { "PEAK_AMP_CTL_SIDE0", 13, 3 }, + { "PEAK_AMP_CTL_SIDE1", 9, 3 }, + { "SxMCVREF_0_3", 4, 4 }, + { "SxPODVREF", 3, 1 }, + { "DISABLE_TERMINATION", 2, 1 }, + { "READ_CENTERING_MODE", 0, 2 }, + { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c81c, 0 }, + { "SYSCLK_ENABLE", 15, 1 }, + { "SYSCLK_ROT_OVERRIDE", 8, 7 }, + { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 }, + { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 }, + { "SYSCLK_PHASE_CNTL_EN", 5, 1 }, + { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 }, + { "SYSCLK_POS_EDGE_ALIGN", 3, 1 }, + { "CONTINUOUS_UPDATE", 2, 1 }, + { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c9cc, 0 }, + { "SYSCLK_ROT", 8, 7 }, + { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c9d0, 0 }, + { "TSYS_WRCLK", 8, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c8c0, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c8c4, 0 }, + { "DQSCLK_ROT_CLK_N0_N2", 8, 7 }, + { "DQSCLK_ROT_CLK_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c824, 0 }, + { "DQSCLK_SELECT0", 14, 2 }, + { "RDCLK_SELECT0", 12, 2 }, + { "DQSCLK_SELECT1", 10, 2 }, + { "RDCLK_SELECT1", 8, 2 }, + { "DQSCLK_SELECT2", 6, 2 }, + { "RDCLK_SELECT2", 4, 2 }, + { "DQSCLK_SELECT3", 2, 2 }, + { "RDCLK_SELECT3", 0, 2 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c970, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c974, 0 }, + { "INITIAL_DQS_ROT_N0_N2", 8, 7 }, + { "INITIAL_DQS_ROT_N1_N3", 0, 7 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c8e0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c8e4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c8e8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c8ec, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c8f0, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c8f4, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c8f8, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c8fc, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c900, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c904, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c908, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c90c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c910, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c914, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c918, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c91c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c920, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c924, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c928, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c92c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c930, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c934, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c938, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c93c, 0 }, + { "WR_DELAY", 6, 10 }, + { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c940, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c944, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c948, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c94c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c950, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c954, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c958, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c95c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c960, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c964, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c968, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c96c, 0 }, + { "RD_DELAY_BITS0_6", 9, 7 }, + { "RD_DELAY_BITS8_14", 1, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c830, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c834, 0 }, + { "OFFSET_BITS1_7", 8, 7 }, + { "OFFSET_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c9c0, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c9c4, 0 }, + { "REFERENCE_BITS1_7", 8, 7 }, + { "REFERENCE_BITS9_15", 0, 7 }, + { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c9c8, 0 }, + { "REFERENCE", 8, 7 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c980, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c984, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c988, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c98c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c990, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c994, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c998, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c99c, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c9a0, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c9a4, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c9a8, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c9ac, 0 }, + { "RD_EYE_SIZE_BITS2_7", 8, 6 }, + { "RD_EYE_SIZE_BITS10_15", 0, 6 }, + { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c828, 0 }, + { "MIN_RD_EYE_SIZE", 8, 6 }, + { "MAX_DQS_DRIFT", 0, 6 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c838, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c83c, 0 }, + { "LEADING_EDGE_NOT_FOUND_1", 8, 8 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c840, 0 }, + { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c844, 0 }, + { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 }, + { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c84c, 0 }, + { "DQS_GATE_DELAY_N0", 12, 3 }, + { "DQS_GATE_DELAY_N1", 8, 3 }, + { "DQS_GATE_DELAY_N2", 4, 3 }, + { "DQS_GATE_DELAY_N3", 0, 3 }, + { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c850, 0 }, + { "NO_EYE_DETECTED", 15, 1 }, + { "LEADING_EDGE_FOUND", 14, 1 }, + { "TRAILING_EDGE_FOUND", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3", 9, 1 }, + { "COARSE_PATTERN_ERR_N0", 8, 1 }, + { "COARSE_PATTERN_ERR_N1", 7, 1 }, + { "COARSE_PATTERN_ERR_N2", 6, 1 }, + { "COARSE_PATTERN_ERR_N3", 5, 1 }, + { "EYE_CLIPPING", 4, 1 }, + { "NO_DQS", 3, 1 }, + { "NO_LOCK", 2, 1 }, + { "DRIFT_ERROR", 1, 1 }, + { "MIN_EYE", 0, 1 }, + { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c854, 0 }, + { "NO_EYE_DETECTED_MASK", 15, 1 }, + { "LEADING_EDGE_FOUND_MASK", 14, 1 }, + { "TRAILING_EDGE_FOUND_MASK", 13, 1 }, + { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 }, + { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 }, + { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 }, + { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 }, + { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 }, + { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 }, + { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 }, + { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 }, + { "EYE_CLIPPING_MASK", 4, 1 }, + { "NO_DQS_MASK", 3, 1 }, + { "NO_LOCK_MASK", 2, 1 }, + { "DRIFT_ERROR_MASK", 1, 1 }, + { "MIN_EYE_MASK", 0, 1 }, + { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c85c, 0 }, + { "CLK_LEVEL", 14, 2 }, + { "FINE_STEPPING", 13, 1 }, + { "DONE", 12, 1 }, + { "WL_ERR_CLK16_ST", 11, 1 }, + { "WL_ERR_CLK18_ST", 10, 1 }, + { "WL_ERR_CLK20_ST", 9, 1 }, + { "WL_ERR_CLK22_ST", 8, 1 }, + { "ZERO_DETECTED", 7, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c860, 0 }, + { "BIT_CENTERED", 11, 5 }, + { "SMALL_STEP_LEFT", 10, 1 }, + { "BIG_STEP_RIGHT", 9, 1 }, + { "MATCH_STEP_RIGHT", 8, 1 }, + { "JUMP_BACK_RIGHT", 7, 1 }, + { "SMALL_STEP_RIGHT", 6, 1 }, + { "DDONE", 5, 1 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c864, 0 }, + { "FW_LEFT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c868, 0 }, + { "FW_RIGHT_SIDE", 5, 11 }, + { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c86c, 0 }, + { "WL_ERR_CLK16", 15, 1 }, + { "WL_ERR_CLK18", 14, 1 }, + { "WL_ERR_CLK20", 13, 1 }, + { "WL_ERR_CLK22", 12, 1 }, + { "VALID_NS_BIG_L", 7, 1 }, + { "INVALID_NS_SMALL_L", 6, 1 }, + { "VALID_NS_BIG_R", 5, 1 }, + { "INVALID_NS_BIG_R", 4, 1 }, + { "VALID_NS_JUMP_BACK", 3, 1 }, + { "INVALID_NS_SMALL_R", 2, 1 }, + { "OFFSET_ERR", 1, 1 }, + { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c870, 0 }, + { "WL_ERR_CLK16_MASK", 15, 1 }, + { "WL_ERR_CLK18_MASK", 14, 1 }, + { "WL_ERR_CLK20_MASK", 13, 1 }, + { "WR_ERR_CLK22_MASK", 12, 1 }, + { "VALID_NS_BIG_L_MASK", 7, 1 }, + { "INVALID_NS_SMALL_L_MASK", 6, 1 }, + { "VALID_NS_BIG_R_MASK", 5, 1 }, + { "INVALID_NS_BIG_R_MASK", 4, 1 }, + { "VALID_NS_JUMP_BACK_MASK", 3, 1 }, + { "INVALID_NS_SMALL_R_MASK", 2, 1 }, + { "OFFSET_ERR_MASK", 1, 1 }, + { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c9d8, 0 }, + { "PLL_TUNE_0_2", 13, 3 }, + { "PLL_TUNECP_0_2", 10, 3 }, + { "PLL_TUNEF_0_5", 4, 6 }, + { "PLL_TUNEVCO_0_1", 2, 2 }, + { "PLL_PLLXTR_0_1", 0, 2 }, + { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c9dc, 0 }, + { "PLL_TUNETDIV_0_2", 13, 3 }, + { "PLL_TUNEMDIV_0_1", 11, 2 }, + { "PLL_TUNEATST", 10, 1 }, + { "VREG_RANGE_0_1", 8, 2 }, + { "CE0DLTVCCA", 7, 1 }, + { "VREG_VCCTUNE_0_1", 5, 2 }, + { "CE0DLTVCCD1", 4, 1 }, + { "CE0DLTVCCD2", 3, 1 }, + { "S0INSDLYTAP", 2, 1 }, + { "S1INSDLYTAP", 1, 1 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c9e0, 0 }, + { "EN_SLICE_N_WR", 8, 8 }, + { "EN_SLICE_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c9e8, 0 }, + { "EN_TERM_N_WR", 8, 8 }, + { "EN_TERM_N_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c9e4, 0 }, + { "EN_SLICE_P_WR", 8, 8 }, + { "EN_SLICE_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c9ec, 0 }, + { "EN_TERM_P_WR", 8, 8 }, + { "EN_TERM_P_WR_FFE", 4, 4 }, + { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c9d4, 0 }, + { "INTERP_SIG_SLEW", 12, 4 }, + { "POST_CURSOR", 8, 4 }, + { "SLEW_CTL", 4, 4 }, + { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c874, 0 }, + { "CHECKER_RESET", 14, 1 }, + { "SYNC", 6, 6 }, + { "ERROR", 0, 6 }, + { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c820, 0 }, + { "DIGITAL_EYE_EN", 15, 1 }, + { "BUMP", 14, 1 }, + { "TRIG_PERIOD", 13, 1 }, + { "CNTL_POL", 12, 1 }, + { "CNTL_SRC", 8, 1 }, + { "DIGITAL_EYE_VALUE", 0, 8 }, + { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c8c8, 0 }, + { "MEMINTD00_POS", 14, 2 }, + { "MEMINTD01_PO", 12, 2 }, + { "MEMINTD02_POS", 10, 2 }, + { "MEMINTD03_POS", 8, 2 }, + { "MEMINTD04_POS", 6, 2 }, + { "MEMINTD05_POS", 4, 2 }, + { "MEMINTD06_POS", 2, 2 }, + { "MEMINTD07_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c8cc, 0 }, + { "MEMINTD08_POS", 14, 2 }, + { "MEMINTD09_POS", 12, 2 }, + { "MEMINTD10_POS", 10, 2 }, + { "MEMINTD11_POS", 8, 2 }, + { "MEMINTD12_POS", 6, 2 }, + { "MEMINTD13_POS", 4, 2 }, + { "MEMINTD14_POS", 2, 2 }, + { "MEMINTD15_POS", 0, 2 }, + { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c8d0, 0 }, + { "MEMINTD16_POS", 14, 2 }, + { "MEMINTD17_POS", 12, 2 }, + { "MEMINTD18_POS", 10, 2 }, + { "MEMINTD19_POS", 8, 2 }, + { "MEMINTD20_POS", 6, 2 }, + { "MEMINTD21_POS", 4, 2 }, + { "MEMINTD22_POS", 2, 2 }, + { "MEMINTD23_POS", 0, 2 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c878, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c8d4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c8d8, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c9b4, 0 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c9b8, 0 }, + { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c8dc, 0 }, + { "DQS_OFFSET", 8, 7 }, + { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c82c, 0 }, + { "HS_PROBE_A_SEL", 11, 5 }, + { "HS_PROBE_B_SEL", 6, 5 }, + { "RD_DEBUG_SEL", 3, 3 }, + { "WR_DEBUG_SEL", 0, 3 }, + { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c9fc, 0 }, + { "MASTER_PD_CNTL", 15, 1 }, + { "ANALOG_INPUT_STAB2", 14, 1 }, + { "ANALOG_INPUT_STAB1", 8, 1 }, + { "SYSCLK_CLK_GATE", 6, 2 }, + { "WR_FIFO_STAB", 5, 1 }, + { "ADR_RX_PD", 4, 1 }, + { "TX_TRISTATE_CNTL", 1, 1 }, + { "DVCC_REG_PD", 0, 1 }, + { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c848, 0 }, + { "DYN_POWER_CNTL_EN", 15, 1 }, + { "DYN_MCTERM_CNTL_EN", 14, 1 }, + { "DYN_RX_GATE_CNTL_EN", 13, 1 }, + { "CALGATE_ON", 12, 1 }, + { "PER_RDCLK_UPDATE_DIS", 11, 1 }, + { "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x4f200, 0 }, + { "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x4f204, 0 }, + { "MC_DDRPHY_SEQ_CONFIG0", 0x4f208, 0 }, + { "MPR_PATTERN_BIT", 15, 1 }, + { "TWO_CYCLE_ADDR_EN", 14, 1 }, + { "MR_MASK_EN", 10, 4 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4f20c, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x4f210, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x4f214, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x4f218, 0 }, + { "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4f21c, 0 }, + { "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x4f220, 0 }, + { "MULTIPLE_REQ_ERROR", 15, 1 }, + { "INVALID_REQTYPE_ERRO", 14, 1 }, + { "EARLY_REQ_ERROR", 13, 1 }, + { "MULTIPLE_REQ_SOURCE", 10, 3 }, + { "INVALID_REQTYPE", 6, 4 }, + { "INVALID_REQ_SOURCE", 3, 3 }, + { "EARLY_REQ_SOURCE", 0, 3 }, + { "MC_DDRPHY_SEQ_ERROR_MASK0", 0x4f224, 0 }, + { "MULT_REQ_ERR_MASK", 15, 1 }, + { "INVALID_REQTYPE_ERR_MASK", 14, 1 }, + { "EARLY_REQ_ERR_MASK", 13, 1 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x4f228, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4f22c, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x4f230, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x4f234, 0 }, + { "ODT_WR_VALUES_BITS0_7", 8, 8 }, + { "ODT_WR_VALUES_BITS8_15", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x4f238, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4f23c, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x4f240, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x4f244, 0 }, + { "ODT_RD_VALUES_x2", 8, 8 }, + { "ODT_RD_VALUES_x2plus1", 0, 8 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x4f248, 0 }, + { "TMOD_CYCLES", 12, 4 }, + { "TRCD_CYCLES", 8, 4 }, + { "TRP_CYCLES", 4, 4 }, + { "TRFC_CYCLES", 0, 4 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4f24c, 0 }, + { "TZQINIT_CYCLES", 12, 4 }, + { "TZQCS_CYCLES", 8, 4 }, + { "TWLDQSEN_CYCLES", 4, 4 }, + { "TWRMRD_CYCLES", 0, 4 }, + { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x4f250, 0 }, + { "TODTLON_OFF_CYCLES", 12, 4 }, + { "TRC_CYCLES", 8, 4 }, + { "TMRSC_CYCLES", 4, 4 }, + { "MC_DDRPHY_WC_CONFIG0", 0x4f600, 0 }, + { "TWLO_TWLOE", 8, 8 }, + { "WL_ONE_DQS_PULSE", 7, 1 }, + { "FW_WR_RD", 1, 6 }, + { "CUSTOM_INIT_WRITE", 0, 1 }, + { "MC_DDRPHY_WC_CONFIG1", 0x4f604, 0 }, + { "BIG_STEP", 12, 4 }, + { "SMALL_STEP", 9, 3 }, + { "WR_PRE_DLY", 3, 6 }, + { "MC_DDRPHY_WC_CONFIG2", 0x4f608, 0 }, + { "NUM_VALID_SAMPLES", 12, 4 }, + { "FW_RD_WR", 6, 6 }, + { "MC_DDRPHY_WC_CONFIG3", 0x4f614, 0 }, + { "DDR4_MRS_CMD_DQ_EN", 15, 1 }, + { "MRS_CMD_DQ_ON", 9, 6 }, + { "MRS_CMD_DQ_OFF", 3, 6 }, + { "MC_DDRPHY_WC_WRCLK_CNTL", 0x4f618, 0 }, + { "WRCLK_CAL_START", 15, 1 }, + { "WRCLK_CAL_DONE", 14, 1 }, + { "MC_DDRPHY_WC_ERROR_STATUS0", 0x4f60c, 0 }, + { "WR_CNTL_ERROR", 15, 1 }, + { "MC_DDRPHY_WC_ERROR_MASK0", 0x4f610, 0 }, + { "WR_CNTL_ERROR_MASK", 15, 1 }, + { "MC_DDRPHY_RC_CONFIG0", 0x4f400, 0 }, + { "GLOBAL_PHY_OFFSET", 12, 4 }, + { "ADVANCE_RD_VALID", 11, 1 }, + { "SINGLE_BIT_MPR_RP0", 6, 1 }, + { "SINGLE_BIT_MPR_RP1", 5, 1 }, + { "SINGLE_BIT_MPR_RP2", 4, 1 }, + { "SINGLE_BIT_MPR_RP3", 3, 1 }, + { "ALIGN_ON_EVEN_CYCLES", 2, 1 }, + { "PERFORM_RDCLK_ALIGN", 1, 1 }, + { "STAGGERED_PATTERN", 0, 1 }, + { "MC_DDRPHY_RC_CONFIG1", 0x4f404, 0 }, + { "OUTER_LOOP_CNT", 2, 14 }, + { "MC_DDRPHY_RC_CONFIG2", 0x4f408, 0 }, + { "CONSEQ_PASS", 11, 5 }, + { "BURST_WINDOW", 5, 2 }, + { "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 }, + { "MC_DDRPHY_RC_CONFIG3", 0x4f41c, 0 }, + { "FINE_CAL_STEP_SIZE", 13, 3 }, + { "COARSE_CAL_STEP_SIZE", 9, 4 }, + { "DQ_SEL_QUAD", 7, 2 }, + { "DQ_SEL_LANE", 4, 3 }, + { "MC_DDRPHY_RC_PERIODIC", 0x4f420, 0 }, + { "MC_DDRPHY_RC_ERROR_STATUS0", 0x4f414, 0 }, + { "RD_CNTL_ERROR", 15, 1 }, + { "MC_DDRPHY_RC_ERROR_MASK0", 0x4f418, 0 }, + { "RD_CNTL_ERROR_MASK", 15, 1 }, + { "MC_DDRPHY_APB_CONFIG0", 0x4f800, 0 }, + { "DISABLE_PARITY_CHECKER", 15, 1 }, + { "GENERATE_EVEN_PARITY", 14, 1 }, + { "FORCE_ON_CLK_GATE", 13, 1 }, + { "DEBUG_BUS_SEL_LO", 12, 1 }, + { "DEBUG_BUS_SEL_HI", 8, 4 }, + { "MC_DDRPHY_APB_ERROR_STATUS0", 0x4f804, 0 }, + { "INVALID_ADDRESS", 15, 1 }, + { "WR_PAR_ERR", 14, 1 }, + { "MC_DDRPHY_APB_ERROR_MASK0", 0x4f808, 0 }, + { "INVALID_ADDRESS_MASK", 15, 1 }, + { "WR_PAR_ERR_MASK", 14, 1 }, + { "MC_DDRPHY_APB_DP18_POPULATION", 0x4f80c, 0 }, + { "DP18_0_Populated", 15, 1 }, + { "DP18_1_Populated", 14, 1 }, + { "DP18_2_Populated", 13, 1 }, + { "DP18_3_Populated", 12, 1 }, + { "DP18_4_Populated", 11, 1 }, + { "DP18_5_Populated", 10, 1 }, + { "DP18_6_Populated", 9, 1 }, + { "DP18_7_Populated", 8, 1 }, + { "DP18_8_Populated", 7, 1 }, + { "DP18_9_Populated", 6, 1 }, + { "DP18_10_Populated", 5, 1 }, + { "DP18_11_Populated", 4, 1 }, + { "DP18_12_Populated", 3, 1 }, + { "DP18_13_Populated", 2, 1 }, + { "DP18_14_Populated", 1, 1 }, + { "MC_DDRPHY_APB_ADR_POPULATION", 0x4f810, 0 }, + { "ADR16_0_Populated", 15, 1 }, + { "ADR16_1_Populated", 14, 1 }, + { "ADR16_2_Populated", 13, 1 }, + { "ADR16_3_Populated", 12, 1 }, + { "ADR12_0_Populated", 7, 1 }, + { "ADR12_1_Populated", 6, 1 }, + { "ADR12_2_Populated", 5, 1 }, + { "ADR12_3_Populated", 4, 1 }, + { "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x4f814, 0 }, + { "ATEST_CNTL", 10, 6 }, + { "MC_UPCTL_SCFG", 0x48000, 0 }, + { "bbflags_timing", 8, 4 }, + { "nfifo_nif1_dis", 6, 1 }, + { "hw_low_power_en", 0, 1 }, + { "MC_UPCTL_SCTL", 0x48004, 0 }, + { "MC_UPCTL_STAT", 0x48008, 0 }, + { "lp_trig", 4, 3 }, + { "ctl_stat", 0, 3 }, + { "MC_UPCTL_INTRSTAT", 0x4800c, 0 }, + { "parity_intr", 1, 1 }, + { "ecc_intr", 0, 1 }, + { "MC_UPCTL_MCMD", 0x48040, 0 }, + { "start_cmd", 31, 1 }, + { "cmd_add_del", 24, 4 }, + { "rank_sel", 20, 4 }, + { "bank_addr", 17, 3 }, + { "cmd_addr", 4, 13 }, + { "cmd_opcode0", 0, 4 }, + { "MC_UPCTL_POWCTL", 0x48044, 0 }, + { "MC_UPCTL_POWSTAT", 0x48048, 0 }, + { "MC_UPCTL_CMDTSTAT", 0x4804c, 0 }, + { "MC_UPCTL_CMDTSTATEN", 0x48050, 0 }, + { "MC_UPCTL_MRRCFG0", 0x48060, 0 }, + { "MC_UPCTL_MRRSTAT0", 0x48064, 0 }, + { "mrrstat_beat3", 24, 8 }, + { "mrrstat_beat2", 16, 8 }, + { "mrrstat_beat1", 8, 8 }, + { "mrrstat_beat0", 0, 8 }, + { "MC_UPCTL_MRRSTAT1", 0x48068, 0 }, + { "mrrstat_beat7", 24, 8 }, + { "mrrstat_beat6", 16, 8 }, + { "mrrstat_beat5", 8, 8 }, + { "mrrstat_beat4", 0, 8 }, + { "MC_UPCTL_MCFG1", 0x4807c, 0 }, + { "hw_exit_idle_en", 31, 1 }, + { "hw_idle", 16, 8 }, + { "sr_idle", 0, 8 }, + { "MC_UPCTL_MCFG", 0x48080, 0 }, + { "mddr_lpddr2_clk_stop_idle", 24, 8 }, + { "mddr_lpddr2_en", 22, 2 }, + { "mddr_lpddr2_bl", 20, 2 }, + { "tfaw_cfg", 18, 2 }, + { "pd_exit_mode", 17, 1 }, + { "pd_type", 16, 1 }, + { "pd_idle", 8, 8 }, + { "lpddr2_s4", 6, 1 }, + { "ddr3_en", 5, 1 }, + { "stagger_cs", 4, 1 }, + { "two_t_en", 3, 1 }, + { "bl8int_en", 2, 1 }, + { "cke_or_en", 1, 1 }, + { "mem_bl", 0, 1 }, + { "MC_UPCTL_PPCFG", 0x48084, 0 }, + { "rpmem_dis", 1, 8 }, + { "ppmem_en", 0, 1 }, + { "MC_UPCTL_MSTAT", 0x48088, 0 }, + { "self_refresh", 2, 1 }, + { "clock_stop", 1, 1 }, + { "power_down", 0, 1 }, + { "MC_UPCTL_LPDDR2ZQCFG", 0x4808c, 0 }, + { "zqcl_op", 24, 8 }, + { "zqcl_ma", 16, 8 }, + { "zqcs_op", 8, 8 }, + { "zqcs_ma", 0, 8 }, + { "MC_UPCTL_DTUPDES", 0x48094, 0 }, + { "dtu_rd_missing", 13, 1 }, + { "dtu_eaffl", 9, 4 }, + { "dtu_random_error", 8, 1 }, + { "dtu_err_b7", 7, 1 }, + { "dtu_err_b6", 6, 1 }, + { "dtu_err_b5", 5, 1 }, + { "dtu_err_b4", 4, 1 }, + { "dtu_err_b3", 3, 1 }, + { "dtu_err_b2", 2, 1 }, + { "dtu_err_b1", 1, 1 }, + { "dtu_err_b0", 0, 1 }, + { "MC_UPCTL_DTUNA", 0x48098, 0 }, + { "MC_UPCTL_DTUNE", 0x4809c, 0 }, + { "MC_UPCTL_DTUPRD0", 0x480a0, 0 }, + { "dtu_allbits_1", 16, 16 }, + { "dtu_allbits_0", 0, 16 }, + { "MC_UPCTL_DTUPRD1", 0x480a4, 0 }, + { "dtu_allbits_3", 16, 16 }, + { "dtu_allbits_2", 0, 16 }, + { "MC_UPCTL_DTUPRD2", 0x480a8, 0 }, + { "dtu_allbits_5", 16, 16 }, + { "dtu_allbits_4", 0, 16 }, + { "MC_UPCTL_DTUPRD3", 0x480ac, 0 }, + { "dtu_allbits_7", 16, 16 }, + { "dtu_allbits_6", 0, 16 }, + { "MC_UPCTL_DTUAWDT", 0x480b0, 0 }, + { "number_ranks", 9, 2 }, + { "row_addr_width", 6, 2 }, + { "bank_addr_width", 3, 2 }, + { "column_addr_width", 0, 2 }, + { "MC_UPCTL_TOGCNT1U", 0x480c0, 0 }, + { "MC_UPCTL_TINIT", 0x480c4, 0 }, + { "MC_UPCTL_TRSTH", 0x480c8, 0 }, + { "MC_UPCTL_TOGCNT100N", 0x480cc, 0 }, + { "MC_UPCTL_TREFI", 0x480d0, 0 }, + { "MC_UPCTL_TMRD", 0x480d4, 0 }, + { "MC_UPCTL_TRFC", 0x480d8, 0 }, + { "MC_UPCTL_TRP", 0x480dc, 0 }, + { "prea_extra", 16, 2 }, + { "t_rp", 0, 4 }, + { "MC_UPCTL_TRTW", 0x480e0, 0 }, + { "MC_UPCTL_TAL", 0x480e4, 0 }, + { "MC_UPCTL_TCL", 0x480e8, 0 }, + { "MC_UPCTL_TCWL", 0x480ec, 0 }, + { "MC_UPCTL_TRAS", 0x480f0, 0 }, + { "MC_UPCTL_TRC", 0x480f4, 0 }, + { "MC_UPCTL_TRCD", 0x480f8, 0 }, + { "MC_UPCTL_TRRD", 0x480fc, 0 }, + { "MC_UPCTL_TRTP", 0x48100, 0 }, + { "MC_UPCTL_TWR", 0x48104, 0 }, + { "MC_UPCTL_TWTR", 0x48108, 0 }, + { "MC_UPCTL_TEXSR", 0x4810c, 0 }, + { "MC_UPCTL_TXP", 0x48110, 0 }, + { "MC_UPCTL_TXPDLL", 0x48114, 0 }, + { "MC_UPCTL_TZQCS", 0x48118, 0 }, + { "MC_UPCTL_TZQCSI", 0x4811c, 0 }, + { "MC_UPCTL_TDQS", 0x48120, 0 }, + { "MC_UPCTL_TCKSRE", 0x48124, 0 }, + { "MC_UPCTL_TCKSRX", 0x48128, 0 }, + { "MC_UPCTL_TCKE", 0x4812c, 0 }, + { "MC_UPCTL_TMOD", 0x48130, 0 }, + { "MC_UPCTL_TRSTL", 0x48134, 0 }, + { "MC_UPCTL_TZQCL", 0x48138, 0 }, + { "MC_UPCTL_TMRR", 0x4813c, 0 }, + { "MC_UPCTL_TCKESR", 0x48140, 0 }, + { "MC_UPCTL_TDPD", 0x48144, 0 }, + { "MC_UPCTL_ECCCFG", 0x48180, 0 }, + { "inline_syn_en", 4, 1 }, + { "ecc_en", 3, 1 }, + { "ecc_intr_en", 2, 1 }, + { "MC_UPCTL_ECCTST", 0x48184, 0 }, + { "MC_UPCTL_ECCCLR", 0x48188, 0 }, + { "clr_ecc_log", 1, 1 }, + { "clr_ecc_intr", 0, 1 }, + { "MC_UPCTL_ECCLOG", 0x4818c, 0 }, + { "MC_UPCTL_DTUWACTL", 0x48200, 0 }, + { "dtu_wr_rank", 30, 2 }, + { "dtu_wr_row0", 13, 16 }, + { "dtu_wr_bank", 10, 3 }, + { "dtu_wr_col", 0, 10 }, + { "MC_UPCTL_DTURACTL", 0x48204, 0 }, + { "dtu_rd_rank", 30, 2 }, + { "dtu_rd_row0", 13, 16 }, + { "dtu_rd_bank", 10, 3 }, + { "dtu_rd_col", 0, 10 }, + { "MC_UPCTL_DTUCFG", 0x48208, 0 }, + { "dtu_row_increments", 16, 7 }, + { "dtu_wr_multi_rd", 15, 1 }, + { "dtu_data_mask_en", 14, 1 }, + { "dtu_target_lane", 10, 4 }, + { "dtu_generate_random", 9, 1 }, + { "dtu_incr_banks", 8, 1 }, + { "dtu_incr_cols", 7, 1 }, + { "dtu_nalen", 1, 6 }, + { "dtu_enable", 0, 1 }, + { "MC_UPCTL_DTUECTL", 0x4820c, 0 }, + { "wr_multi_rd_rst", 2, 1 }, + { "run_error_reports", 1, 1 }, + { "run_dtu", 0, 1 }, + { "MC_UPCTL_DTUWD0", 0x48210, 0 }, + { "dtu_wr_byte3", 24, 8 }, + { "dtu_wr_byte2", 16, 8 }, + { "dtu_wr_byte1", 8, 8 }, + { "dtu_wr_byte0", 0, 8 }, + { "MC_UPCTL_DTUWD1", 0x48214, 0 }, + { "dtu_wr_byte7", 24, 8 }, + { "dtu_wr_byte6", 16, 8 }, + { "dtu_wr_byte5", 8, 8 }, + { "dtu_wr_byte4", 0, 8 }, + { "MC_UPCTL_DTUWD2", 0x48218, 0 }, + { "dtu_wr_byte11", 24, 8 }, + { "dtu_wr_byte10", 16, 8 }, + { "dtu_wr_byte9", 8, 8 }, + { "dtu_wr_byte8", 0, 8 }, + { "MC_UPCTL_DTUWD3", 0x4821c, 0 }, + { "dtu_wr_byte15", 24, 8 }, + { "dtu_wr_byte14", 16, 8 }, + { "dtu_wr_byte13", 8, 8 }, + { "dtu_wr_byte12", 0, 8 }, + { "MC_UPCTL_DTUWDM", 0x48220, 0 }, + { "MC_UPCTL_DTURD0", 0x48224, 0 }, + { "dtu_rd_byte3", 24, 8 }, + { "dtu_rd_byte2", 16, 8 }, + { "dtu_rd_byte1", 8, 8 }, + { "dtu_rd_byte0", 0, 8 }, + { "MC_UPCTL_DTURD1", 0x48228, 0 }, + { "dtu_rd_byte7", 24, 8 }, + { "dtu_rd_byte6", 16, 8 }, + { "dtu_rd_byte5", 8, 8 }, + { "dtu_rd_byte4", 0, 8 }, + { "MC_UPCTL_DTURD2", 0x4822c, 0 }, + { "dtu_rd_byte11", 24, 8 }, + { "dtu_rd_byte10", 16, 8 }, + { "dtu_rd_byte9", 8, 8 }, + { "dtu_rd_byte8", 0, 8 }, + { "MC_UPCTL_DTURD3", 0x48230, 0 }, + { "dtu_rd_byte15", 24, 8 }, + { "dtu_rd_byte14", 16, 8 }, + { "dtu_rd_byte13", 8, 8 }, + { "dtu_rd_byte12", 0, 8 }, + { "MC_UPCTL_DTULFSRWD", 0x48234, 0 }, + { "MC_UPCTL_DTULFSRRD", 0x48238, 0 }, + { "MC_UPCTL_DTUEAF", 0x4823c, 0 }, + { "ea_rank", 30, 2 }, + { "ea_row0", 13, 16 }, + { "ea_bank", 10, 3 }, + { "ea_column", 0, 10 }, + { "MC_UPCTL_DFITCTRLDELAY", 0x48240, 0 }, + { "MC_UPCTL_DFIODTCFG", 0x48244, 0 }, + { "rank3_odt_default", 28, 1 }, + { "rank3_odt_write_sel", 27, 1 }, + { "rank3_odt_write_nsel", 26, 1 }, + { "rank3_odt_read_sel", 25, 1 }, + { "rank3_odt_read_nsel", 24, 1 }, + { "rank2_odt_default", 20, 1 }, + { "rank2_odt_write_sel", 19, 1 }, + { "rank2_odt_write_nsel", 18, 1 }, + { "rank2_odt_read_sel", 17, 1 }, + { "rank2_odt_read_nsel", 16, 1 }, + { "rank1_odt_default", 12, 1 }, + { "rank1_odt_write_sel", 11, 1 }, + { "rank1_odt_write_nsel", 10, 1 }, + { "rank1_odt_read_sel", 9, 1 }, + { "rank1_odt_read_nsel", 8, 1 }, + { "rank0_odt_default", 4, 1 }, + { "rank0_odt_write_sel", 3, 1 }, + { "rank0_odt_write_nsel", 2, 1 }, + { "rank0_odt_read_sel", 1, 1 }, + { "rank0_odt_read_nsel", 0, 1 }, + { "MC_UPCTL_DFIODTCFG1", 0x48248, 0 }, + { "odt_len_b8_r", 24, 3 }, + { "odt_len_bl8_w", 16, 3 }, + { "odt_lat_r", 8, 5 }, + { "odt_lat_w", 0, 5 }, + { "MC_UPCTL_DFIODTRANKMAP", 0x4824c, 0 }, + { "odt_rank_map3", 12, 4 }, + { "odt_rank_map2", 8, 4 }, + { "odt_rank_map1", 4, 4 }, + { "odt_rank_map0", 0, 4 }, + { "MC_UPCTL_DFITPHYWRDATA", 0x48250, 0 }, + { "MC_UPCTL_DFITPHYWRLAT", 0x48254, 0 }, + { "MC_UPCTL_DFITRDDATAEN", 0x48260, 0 }, + { "MC_UPCTL_DFITPHYRDLAT", 0x48264, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE0", 0x48270, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE1", 0x48274, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE2", 0x48278, 0 }, + { "MC_UPCTL_DFITPHYUPDTYPE3", 0x4827c, 0 }, + { "MC_UPCTL_DFITCTRLUPDMIN", 0x48280, 0 }, + { "MC_UPCTL_DFITCTRLUPDMAX", 0x48284, 0 }, + { "MC_UPCTL_DFITCTRLUPDDLY", 0x48288, 0 }, + { "MC_UPCTL_DFIUPDCFG", 0x48290, 0 }, + { "dfi_phyupd_en", 1, 1 }, + { "dfi_ctrlupd_en", 0, 1 }, + { "MC_UPCTL_DFITREFMSKI", 0x48294, 0 }, + { "MC_UPCTL_DFITCTRLUPDI", 0x48298, 0 }, + { "MC_UPCTL_DFITRCFG0", 0x482ac, 0 }, + { "dfi_wrlvl_rank_sel", 16, 4 }, + { "dfi_rdlvl_edge", 4, 9 }, + { "dfi_rdlvl_rank_sel", 0, 4 }, + { "MC_UPCTL_DFITRSTAT0", 0x482b0, 0 }, + { "dfi_wrlvl_mode", 16, 2 }, + { "dfi_rdlvl_gate_mode", 8, 2 }, + { "dfi_rdlvl_mode", 0, 2 }, + { "MC_UPCTL_DFITRWRLVLEN", 0x482b4, 0 }, + { "MC_UPCTL_DFITRRDLVLEN", 0x482b8, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEEN", 0x482bc, 0 }, + { "MC_UPCTL_DFISTSTAT0", 0x482c0, 0 }, + { "dfi_data_byte_disable", 16, 9 }, + { "dfi_freq_ratio", 4, 2 }, + { "dfi_init_start0", 1, 1 }, + { "dfi_init_complete", 0, 1 }, + { "MC_UPCTL_DFISTCFG0", 0x482c4, 0 }, + { "dfi_data_byte_disable_en", 2, 1 }, + { "dfi_freq_ratio_en", 1, 1 }, + { "dfi_init_start", 0, 1 }, + { "MC_UPCTL_DFISTCFG1", 0x482c8, 0 }, + { "dfi_dram_clk_disable_en_dpd", 1, 1 }, + { "dfi_dram_clk_disable_en", 0, 1 }, + { "MC_UPCTL_DFITDRAMCLKEN", 0x482d0, 0 }, + { "MC_UPCTL_DFITDRAMCLKDIS", 0x482d4, 0 }, + { "MC_UPCTL_DFISTCFG2", 0x482d8, 0 }, + { "parity_en", 1, 1 }, + { "parity_intr_en", 0, 1 }, + { "MC_UPCTL_DFISTPARCLR", 0x482dc, 0 }, + { "parity_log_clr", 1, 1 }, + { "parity_intr_clr", 0, 1 }, + { "MC_UPCTL_DFISTPARLOG", 0x482e0, 0 }, + { "MC_UPCTL_DFILPCFG0", 0x482f0, 0 }, + { "dfi_lp_wakeup_dpd", 28, 4 }, + { "dfi_lp_en_dpd", 24, 1 }, + { "dfi_tlp_resp", 16, 4 }, + { "dfi_lp_en_sr", 8, 1 }, + { "dfi_lp_wakeup_pd", 4, 4 }, + { "dfi_lp_en_pd", 0, 1 }, + { "MC_UPCTL_DFITRWRLVLRESP0", 0x48300, 0 }, + { "MC_UPCTL_DFITRWRLVLRESP1", 0x48304, 0 }, + { "MC_UPCTL_DFITRWRLVLRESP2", 0x48308, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP0", 0x4830c, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP1", 0x48310, 0 }, + { "MC_UPCTL_DFITRRDLVLRESP2", 0x48314, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY0", 0x48318, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY1", 0x4831c, 0 }, + { "MC_UPCTL_DFITRWRLVLDELAY2", 0x48320, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY0", 0x48324, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY1", 0x48328, 0 }, + { "MC_UPCTL_DFITRRDLVLDELAY2", 0x4832c, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x48330, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x48334, 0 }, + { "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x48338, 0 }, + { "MC_UPCTL_DFITRCMD", 0x4833c, 0 }, + { "dfitrcmd_start", 31, 1 }, + { "dfitrcmd_en", 4, 9 }, + { "dfitrcmd_opcode", 0, 2 }, + { "MC_UPCTL_IPVR", 0x483f8, 0 }, + { "MC_UPCTL_IPTR", 0x483fc, 0 }, + { "MC_P_DDRPHY_RST_CTRL", 0x49300, 0 }, + { "PHY_DRAM_WL", 17, 5 }, + { "PHY_CALIB_DONE", 5, 1 }, + { "CTL_CAL_REQ", 4, 1 }, + { "CTL_CKE", 3, 1 }, + { "CTL_RST_N", 2, 1 }, + { "DDRIO_ENABLE", 1, 1 }, + { "PHY_RST_N", 0, 1 }, + { "MC_P_PERFORMANCE_CTRL", 0x49304, 0 }, + { "STALL_CHK_BIT", 2, 1 }, + { "DDR3_BRC_MODE", 1, 1 }, + { "RMW_PERF_CTRL", 0, 1 }, + { "MC_P_ECC_CTRL", 0x49308, 0 }, + { "ECC_BYPASS_BIST", 1, 1 }, + { "ECC_DISABLE", 0, 1 }, + { "MC_P_PAR_ENABLE", 0x4930c, 0 }, + { "ECC_UE_PAR_ENABLE", 3, 1 }, + { "ECC_CE_PAR_ENABLE", 2, 1 }, + { "PERR_REG_INT_ENABLE", 1, 1 }, + { "PERR_BLK_INT_ENABLE", 0, 1 }, + { "MC_P_PAR_CAUSE", 0x49310, 0 }, + { "ECC_UE_PAR_CAUSE", 3, 1 }, + { "ECC_CE_PAR_CAUSE", 2, 1 }, + { "FIFOR_PAR_CAUSE", 1, 1 }, + { "RDATA_FIFOR_PAR_CAUSE", 0, 1 }, + { "MC_P_INT_ENABLE", 0x49314, 0 }, + { "ECC_UE_INT_ENABLE", 2, 1 }, + { "ECC_CE_INT_ENABLE", 1, 1 }, + { "PERR_INT_ENABLE", 0, 1 }, + { "MC_P_INT_CAUSE", 0x49318, 0 }, + { "ECC_UE_INT_CAUSE", 2, 1 }, + { "ECC_CE_INT_CAUSE", 1, 1 }, + { "PERR_INT_CAUSE", 0, 1 }, + { "MC_P_ECC_STATUS", 0x4931c, 0 }, + { "ECC_CECNT", 16, 16 }, + { "ECC_UECNT", 0, 16 }, + { "MC_P_PHY_CTRL", 0x49320, 0 }, + { "MC_P_STATIC_CFG_STATUS", 0x49324, 0 }, + { "STATIC_AWEN", 23, 1 }, + { "STATIC_SWLAT", 18, 5 }, + { "STATIC_WLAT", 17, 1 }, + { "STATIC_ALIGN", 16, 1 }, + { "STATIC_SLAT", 11, 5 }, + { "STATIC_LAT", 10, 1 }, + { "STATIC_MODE", 9, 1 }, + { "STATIC_DEN", 6, 3 }, + { "STATIC_ORG", 5, 1 }, + { "STATIC_RKS", 4, 1 }, + { "STATIC_WIDTH", 1, 3 }, + { "STATIC_SLOW", 0, 1 }, + { "MC_P_CORE_PCTL_STAT", 0x49328, 0 }, + { "MC_P_DEBUG_CNT", 0x4932c, 0 }, + { "WDATA_OCNT", 8, 5 }, + { "RDATA_OCNT", 0, 5 }, + { "MC_CE_ERR_DATA_RDATA", 0x49330, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x49334, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x49338, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x4933c, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x49340, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x49344, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x49348, 0 }, + { "MC_CE_ERR_DATA_RDATA", 0x4934c, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49350, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49354, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49358, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x4935c, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49360, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49364, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x49368, 0 }, + { "MC_CE_COR_DATA_RDATA", 0x4936c, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49370, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49374, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49378, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x4937c, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49380, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49384, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x49388, 0 }, + { "MC_UE_ERR_DATA_RDATA", 0x4938c, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x49390, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x49394, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x49398, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x4939c, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x493a0, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x493a4, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x493a8, 0 }, + { "MC_UE_COR_DATA_RDATA", 0x493ac, 0 }, + { "MC_CE_ADDR", 0x493b0, 0 }, + { "MC_UE_ADDR", 0x493b4, 0 }, + { "MC_P_DEEP_SLEEP", 0x493b8, 0 }, + { "SleepStatus", 1, 1 }, + { "SleepReq", 0, 1 }, + { "MC_P_FPGA_BONUS", 0x493bc, 0 }, + { "MC_P_DEBUG_CFG", 0x493c0, 0 }, + { "DEBUG_OR", 15, 1 }, + { "DEBUG_HI", 14, 1 }, + { "DEBUG_RPT", 13, 1 }, + { "DEBUGPAGE", 10, 3 }, + { "DEBUGSELH", 5, 5 }, + { "DEBUGSELL", 0, 5 }, + { "MC_P_DEBUG_RPT", 0x493c4, 0 }, + { "MC_P_BIST_CMD", 0x49400, 0 }, + { "START_BIST", 31, 1 }, + { "BURST_LEN", 16, 2 }, + { "BIST_CMD_GAP", 8, 8 }, + { "BIST_OPCODE", 0, 2 }, + { "MC_P_BIST_CMD_ADDR", 0x49404, 0 }, + { "MC_P_BIST_CMD_LEN", 0x49408, 0 }, + { "MC_P_BIST_DATA_PATTERN", 0x4940c, 0 }, + { "MC_P_BIST_USER_WDATA0", 0x49414, 0 }, + { "MC_P_BIST_USER_WDATA1", 0x49418, 0 }, + { "MC_P_BIST_USER_WDATA2", 0x4941c, 0 }, + { "USER_DATA_MASK", 8, 9 }, + { "USER_DATA2", 0, 8 }, + { "MC_P_BIST_NUM_ERR", 0x49480, 0 }, + { "MC_P_BIST_ERR_FIRST_ADDR", 0x49484, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x49488, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x4948c, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x49490, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x49494, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x49498, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x4949c, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494a0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494a4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494a8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494ac, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494b0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494b4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494b8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494bc, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494c0, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494c4, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494c8, 0 }, + { "MC_P_BIST_STATUS_RDATA", 0x494cc, 0 }, + { "MC_P_BIST_CRC_SEED", 0x494d0, 0 }, + { NULL } +}; + +struct reg_info t5_edc_t50_regs[] = { + { "EDC_H_REF", 0x50000, 0 }, + { "SleepStatus", 31, 1 }, + { "SleepReq", 30, 1 }, + { "PING_PONG", 29, 1 }, + { "EDC_INST_NUM", 18, 1 }, + { "ENABLE_PERF", 17, 1 }, + { "ECC_BYPASS", 16, 1 }, + { "RefFreq", 0, 16 }, + { "EDC_H_BIST_CMD", 0x50004, 0 }, + { "START_BIST", 31, 1 }, + { "BURST_LEN", 16, 2 }, + { "BIST_CMD_GAP", 8, 8 }, + { "BIST_OPCODE", 0, 2 }, + { "EDC_H_BIST_CMD_ADDR", 0x50008, 0 }, + { "EDC_H_BIST_CMD_LEN", 0x5000c, 0 }, + { "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 }, + { "EDC_H_BIST_USER_WDATA0", 0x50014, 0 }, + { "EDC_H_BIST_USER_WDATA1", 0x50018, 0 }, + { "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 }, + { "USER_DATA_MASK", 8, 9 }, + { "USER_DATA2", 0, 8 }, + { "EDC_H_BIST_NUM_ERR", 0x50020, 0 }, + { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 }, + { "EDC_H_PAR_ENABLE", 0x50070, 0 }, + { "ECC_UE_PAR_ENABLE", 2, 1 }, + { "ECC_CE_PAR_ENABLE", 1, 1 }, + { "PERR_PAR_ENABLE", 0, 1 }, + { "EDC_H_INT_ENABLE", 0x50074, 0 }, + { "ECC_UE_INT_ENABLE", 2, 1 }, + { "ECC_CE_INT_ENABLE", 1, 1 }, + { "PERR_INT_ENABLE", 0, 1 }, + { "EDC_H_INT_CAUSE", 0x50078, 0 }, + { "ECC_UE_INT_CAUSE", 2, 1 }, + { "ECC_CE_INT_CAUSE", 1, 1 }, + { "PERR_INT_CAUSE", 0, 1 }, + { "EDC_H_ECC_STATUS", 0x5007c, 0 }, + { "ECC_CECNT", 16, 16 }, + { "ECC_UECNT", 0, 16 }, + { "EDC_H_ECC_ERR_SEL", 0x50080, 0 }, + { "EDC_H_ECC_ERR_ADDR", 0x50084, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 }, + { "EDC_H_BIST_CRC_SEED", 0x50400, 0 }, + { NULL } +}; + +struct reg_info t5_edc_t51_regs[] = { + { "EDC_H_REF", 0x50800, 0 }, + { "SleepStatus", 31, 1 }, + { "SleepReq", 30, 1 }, + { "PING_PONG", 29, 1 }, + { "EDC_INST_NUM", 18, 1 }, + { "ENABLE_PERF", 17, 1 }, + { "ECC_BYPASS", 16, 1 }, + { "RefFreq", 0, 16 }, + { "EDC_H_BIST_CMD", 0x50804, 0 }, + { "START_BIST", 31, 1 }, + { "BURST_LEN", 16, 2 }, + { "BIST_CMD_GAP", 8, 8 }, + { "BIST_OPCODE", 0, 2 }, + { "EDC_H_BIST_CMD_ADDR", 0x50808, 0 }, + { "EDC_H_BIST_CMD_LEN", 0x5080c, 0 }, + { "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 }, + { "EDC_H_BIST_USER_WDATA0", 0x50814, 0 }, + { "EDC_H_BIST_USER_WDATA1", 0x50818, 0 }, + { "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 }, + { "USER_DATA_MASK", 8, 9 }, + { "USER_DATA2", 0, 8 }, + { "EDC_H_BIST_NUM_ERR", 0x50820, 0 }, + { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 }, + { "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 }, + { "EDC_H_PAR_ENABLE", 0x50870, 0 }, + { "ECC_UE_PAR_ENABLE", 2, 1 }, + { "ECC_CE_PAR_ENABLE", 1, 1 }, + { "PERR_PAR_ENABLE", 0, 1 }, + { "EDC_H_INT_ENABLE", 0x50874, 0 }, + { "ECC_UE_INT_ENABLE", 2, 1 }, + { "ECC_CE_INT_ENABLE", 1, 1 }, + { "PERR_INT_ENABLE", 0, 1 }, + { "EDC_H_INT_CAUSE", 0x50878, 0 }, + { "ECC_UE_INT_CAUSE", 2, 1 }, + { "ECC_CE_INT_CAUSE", 1, 1 }, + { "PERR_INT_CAUSE", 0, 1 }, + { "EDC_H_ECC_STATUS", 0x5087c, 0 }, + { "ECC_CECNT", 16, 16 }, + { "ECC_UECNT", 0, 16 }, + { "EDC_H_ECC_ERR_SEL", 0x50880, 0 }, + { "EDC_H_ECC_ERR_ADDR", 0x50884, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 }, + { "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 }, + { "EDC_H_BIST_CRC_SEED", 0x50c00, 0 }, + { NULL } +}; + +struct reg_info t5_hma_t5_regs[] = { + { "HMA_TABLE_ACCESS", 0x51000, 0 }, + { "TRIG", 31, 1 }, + { "RW", 30, 1 }, + { "L_SEL", 0, 4 }, + { "HMA_TABLE_LINE0", 0x51004, 0 }, + { "HMA_TABLE_LINE1", 0x51008, 0 }, + { "HMA_TABLE_LINE2", 0x5100c, 0 }, + { "HMA_TABLE_LINE3", 0x51010, 0 }, + { "HMA_TABLE_LINE4", 0x51014, 0 }, + { "HMA_TABLE_LINE5", 0x51018, 0 }, + { "FID", 16, 11 }, + { "NOS", 15, 1 }, + { "RO", 14, 1 }, + { "HMA_COOKIE", 0x5101c, 0 }, + { "C_REQ", 31, 1 }, + { "C_FID", 18, 11 }, + { "C_VAL", 8, 10 }, + { "C_SEL", 0, 4 }, + { "HMA_PAR_ENABLE", 0x51300, 0 }, + { "HMA_INT_ENABLE", 0x51304, 0 }, + { "HMA_INT_CAUSE", 0x51308, 0 }, + { NULL } +};