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Import device-tree files from Linux 6.12

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This commit is contained in:
Emmanuel Vadot 2025-01-02 10:11:32 +01:00
parent beb6e748a9
commit cd989bfc73
1144 changed files with 61595 additions and 8939 deletions
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33
Bindings/arc/snps,archs-pct.yaml Normal file
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@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARC HS Performance Counters
maintainers:
- Aryabhatta Dey <aryabhattadey35@gmail.com>
description:
The ARC HS can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters.
It also supports overflow interrupts.
properties:
compatible:
const: snps,archs-pct
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
additionalProperties: false

16
Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
View file

@ -25,10 +25,18 @@ select:
properties:
compatible:
items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
oneOf:
- items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
- items:
- enum:
- amlogic,a4-ao-secure
- amlogic,c3-ao-secure
- amlogic,s4-ao-secure
- amlogic,t7-ao-secure
- const: amlogic,meson-gx-ao-secure
- const: syscon
reg:
maxItems: 1

2
Bindings/arm/arm,coresight-dummy-source.yaml
View file

@ -17,7 +17,7 @@ description: |
The Coresight dummy source component is for the specific coresight source
devices kernel don't have permission to access or configure. For some SOCs,
there would be Coresight source trace components on sub-processor which
are conneted to AP processor via debug bus. For these devices, a dummy driver
are connected to AP processor via debug bus. For these devices, a dummy driver
is needed to register them as Coresight source devices, so that paths can be
created in the driver. It provides Coresight API for operations on dummy
source devices, such as enabling and disabling them. It also provides the

4
Bindings/arm/arm,corstone1000.yaml
View file

@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Corstone1000
maintainers:
- Vishnu Banavath <vishnu.banavath@arm.com>
- Rui Miguel Silva <rui.silva@linaro.org>
- Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
- Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
description: |+
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that

3
Bindings/arm/aspeed/aspeed.yaml
View file

@ -79,6 +79,7 @@ properties:
- aspeed,ast2600-evb-a1
- asus,x4tf-bmc
- facebook,bletchley-bmc
- facebook,catalina-bmc
- facebook,cloudripper-bmc
- facebook,elbert-bmc
- facebook,fuji-bmc
@ -86,7 +87,9 @@ properties:
- facebook,harma-bmc
- facebook,minerva-cmc
- facebook,yosemite4-bmc
- ibm,blueridge-bmc
- ibm,everest-bmc
- ibm,fuji-bmc
- ibm,rainier-bmc
- ibm,system1-bmc
- ibm,tacoma-bmc

6
Bindings/arm/atmel-sysregs.txt
View file

@ -11,7 +11,8 @@ PIT Timer required properties:
shared across all System Controller members.
PIT64B Timer required properties:
- compatible: Should be "microchip,sam9x60-pit64b"
- compatible: Should be "microchip,sam9x60-pit64b" or
"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for PIT64B timer
- clocks: Should contain the available clock sources for PIT64B timer.
@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc",
"microchip,sama7g5-uddrc"
"microchip,sama7g5-uddrc",
"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
- reg: Should contain registers location and length
Examples:

38
Bindings/arm/cirrus/cirrus,ep9301.yaml Normal file
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@ -0,0 +1,38 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic EP93xx platforms
description:
The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU.
maintainers:
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
- Nikita Shubin <nikita.shubin@maquefel.me>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: The TS-7250 is a compact, full-featured Single Board
Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU
items:
- const: technologic,ts7250
- const: cirrus,ep9301
- description: The Liebherr BK3 is a derivate from ts7250 board
items:
- const: liebherr,bk3
- const: cirrus,ep9301
- description: EDB302 is an evaluation board by Cirrus Logic,
based on a Cirrus Logic EP9302 CPU
items:
- const: cirrus,edb9302
- const: cirrus,ep9301
additionalProperties: true

38
Bindings/arm/fsl.yaml
View file

@ -809,19 +809,19 @@ properties:
- const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLx SoM on MBa6ULx board
- description: TQ-Systems TQMa6ULLx SoM on MBa6ULx board
items:
- enum:
- tq,imx6ull-tqma6ull2-mba6ulx
- const: tq,imx6ull-tqma6ull2 # MCIMX6Y2
- tq,imx6ull-tqma6ull2-mba6ulx # TQMa6ULL socketable SoM with MCIMX6Y2 on MBa6ULx EVK
- const: tq,imx6ull-tqma6ull2 # TQMa6ULL socketable SoM with MCIMX6Y2
- const: fsl,imx6ull
- description: TQ Systems TQMa6ULLxL SoM on MBa6ULx[L] board
- description: TQ-Systems TQMa6ULLxL SoM on MBa6ULx[L] board
items:
- enum:
- tq,imx6ull-tqma6ull2l-mba6ulx # using LGA adapter
- tq,imx6ull-tqma6ull2l-mba6ulxl
- const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant
- tq,imx6ull-tqma6ull2l-mba6ulx # TQMa6ULLxL LGA SoM with socketable Adapter on MBa6ULx EVK
- tq,imx6ull-tqma6ull2l-mba6ulxl # TQMa6ULLxL LGA SoM on MBa6ULxL gateway board
- const: tq,imx6ull-tqma6ull2l # TQMa6ULLxL LGA SoM with MCIMX6Y2
- const: fsl,imx6ull
- description: Seeed Stuido i.MX6ULL SoM on dev boards
@ -939,8 +939,8 @@ properties:
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
- gateworks,imx8mm-gw7904
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
@ -953,7 +953,6 @@ properties:
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
@ -1082,7 +1081,7 @@ properties:
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
@ -1168,6 +1167,12 @@ properties:
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
- const: fsl,imx8mp
- description: Variscite VAR-SOM-MX8M Plus based boards
items:
- const: variscite,var-som-mx8mp-symphony
- const: variscite,var-som-mx8mp
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
items:
- enum:
@ -1293,6 +1298,7 @@ properties:
- enum:
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
- const: fsl,imx93
- description: i.MX95 based Boards
@ -1344,6 +1350,12 @@ properties:
- const: variscite,var-som-mx93
- const: fsl,imx93
- description: Kontron OSM-S i.MX93 SoM based boards
items:
- const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings
@ -1523,6 +1535,12 @@ properties:
- fsl,ls2080a-rdb
- const: fsl,ls2080a
- description: LS2081A based Boards
items:
- enum:
- fsl,ls2081a-rdb
- const: fsl,ls2081a
- description: LS2088A based Boards
items:
- enum:

19
Bindings/arm/qcom.yaml
View file

@ -155,6 +155,11 @@ properties:
- const: qcom,msm8926
- const: qcom,msm8226
- items:
- enum:
- wingtech,wt82918hd
- const: qcom,msm8929
- items:
- enum:
- huawei,kiwi
@ -162,6 +167,8 @@ properties:
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
- wingtech,wt82918
- wingtech,wt82918hdhw39
- const: qcom,msm8939
- items:
@ -228,12 +235,15 @@ properties:
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j3ltetw
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
- yiming,uz801-v3
- const: qcom,msm8916
@ -250,6 +260,7 @@ properties:
- items:
- enum:
- lg,bullhead
- lg,h815
- microsoft,talkman
- xiaomi,libra
- const: qcom,msm8992
@ -1038,10 +1049,18 @@ properties:
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- lenovo,thinkpad-t14s
- const: qcom,x1e78100
- const: qcom,x1e80100
- items:
- enum:
- asus,vivobook-s15
- lenovo,yoga-slim7x
- microsoft,romulus13
- microsoft,romulus15
- qcom,x1e80100-crd
- qcom,x1e80100-qcp
- const: qcom,x1e80100

42
Bindings/arm/rockchip.yaml
View file

@ -96,6 +96,13 @@ properties:
- const: coolpi,pi-cm5
- const: rockchip,rk3588
- description: Cool Pi CM5 GenBook
items:
- enum:
- coolpi,pi-cm5-genbook
- const: coolpi,pi-cm5
- const: rockchip,rk3588
- description: Cool Pi 4 Model B
items:
- const: coolpi,pi-4b
@ -148,6 +155,12 @@ properties:
- const: engicam,px30-core
- const: rockchip,px30
- description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
items:
- const: firefly,px30-jd4-core-mb
- const: firefly,px30-jd4-core
- const: rockchip,px30
- description: Firefly Firefly-RK3288
items:
- enum:
@ -216,6 +229,7 @@ properties:
- friendlyarm,nanopi-r2c
- friendlyarm,nanopi-r2c-plus
- friendlyarm,nanopi-r2s
- friendlyarm,nanopi-r2s-plus
- const: rockchip,rk3328
- description: FriendlyElec NanoPi4 series boards
@ -243,9 +257,11 @@ properties:
- friendlyarm,nanopi-r6s
- const: rockchip,rk3588s
- description: FriendlyElec NanoPC T6
- description: FriendlyElec NanoPC T6 series boards
items:
- const: friendlyarm,nanopc-t6
- enum:
- friendlyarm,nanopc-t6
- friendlyarm,nanopc-t6-lts
- const: rockchip,rk3588
- description: FriendlyElec CM3588-based boards
@ -255,6 +271,11 @@ properties:
- const: friendlyarm,cm3588
- const: rockchip,rk3588
- description: GameForce Ace
items:
- const: gameforce,ace
- const: rockchip,rk3588s
- description: GameForce Chi
items:
- const: gameforce,chi
@ -581,9 +602,19 @@ properties:
- description: Hardkernel Odroid M1
items:
- const: rockchip,rk3568-odroid-m1
- const: hardkernel,odroid-m1
- const: rockchip,rk3568
- description: Hardkernel Odroid M1S
items:
- const: hardkernel,odroid-m1s
- const: rockchip,rk3566
- description: Hardkernel Odroid M2
items:
- const: hardkernel,odroid-m2
- const: rockchip,rk3588s
- description: Hugsun X99 TV Box
items:
- const: hugsun,x99
@ -622,6 +653,11 @@ properties:
- const: leez,p710
- const: rockchip,rk3399
- description: LCKFB Taishan Pi RK3566
items:
- const: lckfb,tspi-rk3566
- const: rockchip,rk3566
- description: Lunzn FastRhino R66S / R68S
items:
- enum:

2
Bindings/arm/rockchip/pmu.yaml
View file

@ -26,6 +26,7 @@ select:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
@ -43,6 +44,7 @@ properties:
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
- const: syscon

8
Bindings/arm/stm32/stm32.yaml
View file

@ -54,6 +54,8 @@ properties:
- description: ST STM32MP151 based Boards
items:
- enum:
- prt,mecio1r0 # Protonic MECIO1r0
- prt,mect1s # Protonic MECT1S
- prt,prtt1a # Protonic PRTT1A
- prt,prtt1c # Protonic PRTT1C
- prt,prtt1s # Protonic PRTT1S
@ -71,6 +73,12 @@ properties:
- const: dh,stm32mp151a-dhcor-som
- const: st,stm32mp151
- description: ST STM32MP153 based Boards
items:
- enum:
- prt,mecio1r1 # Protonic MECIO1r1
- const: st,stm32mp153
- description: DH STM32MP153 DHCOM SoM based Boards
items:
- const: dh,stm32mp153c-dhcom-drc02

9
Bindings/arm/sunxi.yaml
View file

@ -61,14 +61,19 @@ properties:
- const: anbernic,rg35xx-2024
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX H
items:
- const: anbernic,rg35xx-h
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX Plus
items:
- const: anbernic,rg35xx-plus
- const: allwinner,sun50i-h700
- description: Anbernic RG35XX H
- description: Anbernic RG35XX SP
items:
- const: anbernic,rg35xx-h
- const: anbernic,rg35xx-sp
- const: allwinner,sun50i-h700
- description: Amarula A64 Relic

42
Bindings/arm/tegra.yaml
View file

@ -127,6 +127,48 @@ properties:
- nvidia,norrin
- const: nvidia,tegra132
- const: nvidia,tegra124
- items:
- const: google,nyan-blaze-rev10
- const: google,nyan-blaze-rev9
- const: google,nyan-blaze-rev8
- const: google,nyan-blaze-rev7
- const: google,nyan-blaze-rev6
- const: google,nyan-blaze-rev5
- const: google,nyan-blaze-rev4
- const: google,nyan-blaze-rev3
- const: google,nyan-blaze-rev2
- const: google,nyan-blaze-rev1
- const: google,nyan-blaze-rev0
- const: google,nyan-blaze
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev10
- const: google,nyan-big-rev9
- const: google,nyan-big-rev8
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- enum:
- nvidia,darcy

1
Bindings/arm/ti/k3.yaml
View file

@ -140,6 +140,7 @@ properties:
- description: K3 J722S SoC and Boards
items:
- enum:
- beagle,am67a-beagley-ai
- ti,j722s-evm
- const: ti,j722s

33
Bindings/ata/ahci-platform.yaml
View file

@ -30,6 +30,8 @@ select:
- marvell,armada-3700-ahci
- marvell,armada-8k-ahci
- marvell,berlin2q-ahci
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
- socionext,uniphier-pro4-ahci
- socionext,uniphier-pxs2-ahci
- socionext,uniphier-pxs3-ahci
@ -45,6 +47,8 @@ properties:
- marvell,armada-8k-ahci
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
- socionext,uniphier-pro4-ahci
- socionext,uniphier-pxs2-ahci
- socionext,uniphier-pxs3-ahci
@ -64,11 +68,11 @@ properties:
clocks:
minItems: 1
maxItems: 3
maxItems: 5
clock-names:
minItems: 1
maxItems: 3
maxItems: 5
interrupts:
maxItems: 1
@ -97,6 +101,31 @@ required:
allOf:
- $ref: ahci-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,apq8064-ahci
- qcom,ipq806x-ahci
then:
properties:
clocks:
minItems: 5
clock-names:
items:
- const: slave_iface
- const: iface
- const: core
- const: rxoob
- const: pmalive
required:
- phys
- phy-names
- clocks
- clock-names
- if:
properties:
compatible:

42
Bindings/ata/cirrus,ep9312-pata.yaml Normal file
View file

@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic EP9312 PATA controller
maintainers:
- Damien Le Moal <dlemoal@kernel.org>
properties:
compatible:
oneOf:
- const: cirrus,ep9312-pata
- items:
- const: cirrus,ep9315-pata
- const: cirrus,ep9312-pata
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
ide@800a0000 {
compatible = "cirrus,ep9312-pata";
reg = <0x800a0000 0x38>;
interrupt-parent = <&vic1>;
interrupts = <8>;
pinctrl-names = "default";
pinctrl-0 = <&ide_default_pins>;
};

47
Bindings/ata/imx-sata.yaml
View file

@ -19,6 +19,7 @@ properties:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
- fsl,imx8qm-ahci
reg:
maxItems: 1
@ -27,12 +28,14 @@ properties:
maxItems: 1
clocks:
minItems: 2
items:
- description: sata clock
- description: sata reference clock
- description: ahb clock
clock-names:
minItems: 2
items:
- const: sata
- const: sata_ref
@ -58,6 +61,25 @@ properties:
$ref: /schemas/types.yaml#/definitions/flag
description: if present, disable spread-spectrum clocking on the SATA link.
phys:
items:
- description: phandle to SATA PHY.
Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
calibration result will be stored, passed through second lane, and
shared with all three lanes PHY. The first two lanes PHY are used as
calibration PHYs, although only the third lane PHY is used by SATA.
- description: phandle to the first lane PHY of i.MX8QM.
- description: phandle to the second lane PHY of i.MX8QM.
phy-names:
items:
- const: sata-phy
- const: cali-phy0
- const: cali-phy1
power-domains:
maxItems: 1
required:
- compatible
- reg
@ -65,6 +87,31 @@ required:
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
then:
properties:
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-ahci
then:
properties:
clock-names:
minItems: 2
additionalProperties: false
examples:

32
Bindings/board/fsl,bcsr.yaml Normal file
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@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/board/fsl,bcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Board Control and Status
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
enum:
- fsl,mpc8360mds-bcsr
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
board@f8000000 {
compatible = "fsl,mpc8360mds-bcsr";
reg = <0xf8000000 0x8000>;
};

70
Bindings/board/fsl,fpga-qixis-i2c.yaml Normal file
View file

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale on-board FPGA connected on I2C bus
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,bsc9132qds-fpga
- const: fsl,fpga-qixis-i2c
- items:
- enum:
- fsl,ls1028aqds-fpga
- fsl,lx2160aqds-fpga
- const: fsl,fpga-qixis-i2c
- const: simple-mfd
interrupts:
maxItems: 1
reg:
maxItems: 1
mux-controller:
$ref: /schemas/mux/reg-mux.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
board-control@66 {
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
reg = <0x66>;
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
board-control@66 {
compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
"simple-mfd";
reg = <0x66>;
mux-controller {
compatible = "reg-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
};
};
};

81
Bindings/board/fsl,fpga-qixis.yaml Normal file
View file

@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale on-board FPGA/CPLD
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- const: fsl,p1022ds-fpga
- const: fsl,fpga-ngpixis
- items:
- enum:
- fsl,ls1088aqds-fpga
- fsl,ls1088ardb-fpga
- fsl,ls2080aqds-fpga
- fsl,ls2080ardb-fpga
- const: fsl,fpga-qixis
- items:
- enum:
- fsl,ls1043aqds-fpga
- fsl,ls1043ardb-fpga
- fsl,ls1046aqds-fpga
- fsl,ls1046ardb-fpga
- fsl,ls208xaqds-fpga
- const: fsl,fpga-qixis
- const: simple-mfd
- enum:
- fsl,ls1043ardb-cpld
- fsl,ls1046ardb-cpld
- fsl,t1040rdb-cpld
- fsl,t1042rdb-cpld
- fsl,t1042rdb_pi-cpld
interrupts:
maxItems: 1
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
patternProperties:
'^mdio-mux@[a-f0-9,]+$':
$ref: /schemas/net/mdio-mux-mmioreg.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
board-control@3 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0x30>;
interrupt-parent = <&mpic>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW 0 0>;
};
- |
board-control@3 {
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
reg = <0x3 0x10000>;
};

239
Bindings/bus/qcom,ebi2.yaml Normal file
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@ -0,0 +1,239 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm External Bus Interface 2 (EBI2)
description: |
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
external memory (such as NAND or other memory-mapped peripherals) whereas
LCDC handles LCD displays.
As it says it connects devices to an external bus interface, meaning address
lines (up to 9 address lines so can only address 1KiB external memory space),
data lines (16 bits), OE (output enable), ADV (address valid, used on some
NOR flash memories), WE (write enable). This on top of 6 different chip selects
(CS0 thru CS5) so that in theory 6 different devices can be connected.
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
and the bus can only come out on these pins, however if some of the pins are
unused they can be left unconnected or remuxed to be used as GPIO or in some
cases other orthogonal functions as well.
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
The chip selects have the following memory range assignments. This region of
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
Chip Select Physical address base
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
August 6, 2012 contains some incomplete documentation of the EBI2.
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
We have not been able to figure out which bit fields these correspond to
in the hardware, or what valid values exist. The current hypothesis is that
this is something just used on the FAST chip selects and that the SLOW
chip selects are understood fully. There is also a "byte device enable"
flag somewhere for 8bit memories.
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
unclear what this means, if they are mutually exclusive or can be used
together, or if some chip selects are hardwired to be FAST and others are SLOW
by design.
The XMEM registers are totally undocumented but could be partially decoded
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
similar register layout, see: http://www.cypress.com/file/105771/download
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
- qcom,apq8060-ebi2
- qcom,msm8660-ebi2
reg:
items:
- description: EBI2 config region
- description: XMEM config region
reg-names:
items:
- const: ebi2
- const: xmem
ranges: true
clocks:
items:
- description: EBI_2X clock
- description: EBI clock
clock-names:
items:
- const: ebi2x
- const: ebi2
'#address-cells':
const: 2
'#size-cells':
const: 1
required:
- compatible
- reg
- reg-names
- ranges
- clocks
- clock-names
- '#address-cells'
- '#size-cells'
patternProperties:
"^.*@[0-5],[0-9a-f]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
required:
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
external-bus@1a100000 {
compatible = "qcom,msm8660-ebi2";
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
#address-cells = <2>;
#size-cells = <1>;
ethernet@2,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <2 0x0 0x100>;
interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
phy-mode = "mii";
reg-io-width = <2>;
smsc,force-external-phy;
smsc,irq-push-pull;
/* SLOW chipselect config */
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};

7
Bindings/clock/amlogic,c3-pll-clkc.yaml
View file

@ -24,11 +24,13 @@ properties:
items:
- description: input top pll
- description: input mclk pll
- description: input fix pll
clock-names:
items:
- const: top
- const: mclk
- const: fix
"#clock-cells":
const: 1
@ -52,8 +54,9 @@ examples:
compatible = "amlogic,c3-pll-clkc";
reg = <0x0 0x8000 0x0 0x1a4>;
clocks = <&scmi_clk 2>,
<&scmi_clk 5>;
clock-names = "top", "mclk";
<&scmi_clk 5>,
<&scmi_clk 12>;
clock-names = "top", "mclk", "fix";
#clock-cells = <1>;
};
};

2
Bindings/clock/atmel,at91rm9200-pmc.yaml
View file

@ -42,6 +42,7 @@ properties:
- atmel,sama5d3-pmc
- atmel,sama5d4-pmc
- microchip,sam9x60-pmc
- microchip,sam9x7-pmc
- microchip,sama7g5-pmc
- const: syscon
@ -88,6 +89,7 @@ allOf:
contains:
enum:
- microchip,sam9x60-pmc
- microchip,sam9x7-pmc
- microchip,sama7g5-pmc
then:
properties:

4
Bindings/clock/atmel,at91sam9x5-sckc.yaml
View file

@ -18,7 +18,9 @@ properties:
- atmel,sama5d4-sckc
- microchip,sam9x60-sckc
- items:
- const: microchip,sama7g5-sckc
- enum:
- microchip,sam9x7-sckc
- microchip,sama7g5-sckc
- const: microchip,sam9x60-sckc
reg:

8
Bindings/clock/baikal,bt1-ccu-div.yaml
View file

@ -134,9 +134,13 @@ properties:
"#reset-cells":
const: 1
clocks: true
clocks:
minItems: 3
maxItems: 4
clock-names: true
clock-names:
minItems: 3
maxItems: 4
additionalProperties: false

6
Bindings/clock/cirrus,lochnagar.yaml
View file

@ -67,9 +67,9 @@ properties:
minItems: 1
maxItems: 19
clocks: true
assigned-clocks: true
assigned-clock-parents: true
clocks:
minItems: 1
maxItems: 19
additionalProperties: false

2
Bindings/clock/idt,versaclock5.yaml
View file

@ -126,8 +126,6 @@ required:
- compatible
- reg
- '#clock-cells'
- idt,shutdown
- idt,output-enable-active
allOf:
- if:

3
Bindings/clock/imx8mp-audiomix.yaml
View file

@ -44,6 +44,9 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
'#reset-cells':
const: 1
required:
- compatible
- reg

2
Bindings/clock/mediatek,apmixedsys.yaml
View file

@ -35,7 +35,7 @@ properties:
- mediatek,mt2701-apmixedsys
- mediatek,mt2712-apmixedsys
- mediatek,mt6765-apmixedsys
- mediatek,mt6779-apmixedsys
- mediatek,mt6779-apmixed
- mediatek,mt6795-apmixedsys
- mediatek,mt7629-apmixedsys
- mediatek,mt8167-apmixedsys

85
Bindings/clock/mediatek,infracfg.yaml Normal file
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@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Infrastructure System Configuration Controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The Mediatek infracfg controller provides various clocks and reset outputs
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
and reset values in <dt-bindings/reset/mt*-reset.h> and
<dt-bindings/reset/mt*-resets.h>.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt6765-infracfg
- mediatek,mt6795-infracfg
- mediatek,mt6779-infracfg_ao
- mediatek,mt6797-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7629-infracfg
- mediatek,mt7981-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt7988-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
- mediatek,mt8516-infracfg
- const: syscon
- items:
- const: mediatek,mt7623-infracfg
- const: mediatek,mt2701-infracfg
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt6795-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
then:
required:
- '#reset-cells'
additionalProperties: false
examples:
- |
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

56
Bindings/clock/mediatek,mt8186-clock.yaml Normal file
View file

@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8186
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description: |
The clock architecture in MediaTek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices provide clock gate control in different IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8186-imp_iic_wrap
- mediatek,mt8186-mfgsys
- mediatek,mt8186-wpesys
- mediatek,mt8186-imgsys1
- mediatek,mt8186-imgsys2
- mediatek,mt8186-vdecsys
- mediatek,mt8186-vencsys
- mediatek,mt8186-camsys
- mediatek,mt8186-camsys_rawa
- mediatek,mt8186-camsys_rawb
- mediatek,mt8186-mdpsys
- mediatek,mt8186-ipesys
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
imp_iic_wrap: clock-controller@11017000 {
compatible = "mediatek,mt8186-imp_iic_wrap";
reg = <0x11017000 0x1000>;
#clock-cells = <1>;
};

57
Bindings/clock/mediatek,mt8186-sys-clock.yaml Normal file
View file

@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8186
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description: |
The clock architecture in MediaTek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys provides most of PLLs which generated from SoC 26m.
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
The mcusys provides mux control to select the clock source in AP MCU.
The device nodes also provide the system control capacity for configuration.
properties:
compatible:
items:
- enum:
- mediatek,mt8186-mcusys
- mediatek,mt8186-topckgen
- mediatek,mt8186-infracfg_ao
- mediatek,mt8186-apmixedsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8186-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};

191
Bindings/clock/mediatek,mt8192-clock.yaml Normal file
View file

@ -0,0 +1,191 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8192
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The Mediatek functional clock controller provides various clocks on MT8192.
properties:
compatible:
items:
- enum:
- mediatek,mt8192-scp_adsp
- mediatek,mt8192-imp_iic_wrap_c
- mediatek,mt8192-imp_iic_wrap_e
- mediatek,mt8192-imp_iic_wrap_s
- mediatek,mt8192-imp_iic_wrap_ws
- mediatek,mt8192-imp_iic_wrap_w
- mediatek,mt8192-imp_iic_wrap_n
- mediatek,mt8192-msdc_top
- mediatek,mt8192-mfgcfg
- mediatek,mt8192-imgsys
- mediatek,mt8192-imgsys2
- mediatek,mt8192-vdecsys_soc
- mediatek,mt8192-vdecsys
- mediatek,mt8192-vencsys
- mediatek,mt8192-camsys
- mediatek,mt8192-camsys_rawa
- mediatek,mt8192-camsys_rawb
- mediatek,mt8192-camsys_rawc
- mediatek,mt8192-ipesys
- mediatek,mt8192-mdpsys
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0x10720000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_c: clock-controller@11007000 {
compatible = "mediatek,mt8192-imp_iic_wrap_c";
reg = <0x11007000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_e: clock-controller@11cb1000 {
compatible = "mediatek,mt8192-imp_iic_wrap_e";
reg = <0x11cb1000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8192-imp_iic_wrap_s";
reg = <0x11d03000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_ws: clock-controller@11d23000 {
compatible = "mediatek,mt8192-imp_iic_wrap_ws";
reg = <0x11d23000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_w: clock-controller@11e01000 {
compatible = "mediatek,mt8192-imp_iic_wrap_w";
reg = <0x11e01000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_n: clock-controller@11f02000 {
compatible = "mediatek,mt8192-imp_iic_wrap_n";
reg = <0x11f02000 0x1000>;
#clock-cells = <1>;
};
- |
msdc_top: clock-controller@11f10000 {
compatible = "mediatek,mt8192-msdc_top";
reg = <0x11f10000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg";
reg = <0x13fbf000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0x15020000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0x15820000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0x1600f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0x1602f000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys: clock-controller@17000000 {
compatible = "mediatek,mt8192-vencsys";
reg = <0x17000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0x1a04f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawb: clock-controller@1a06f000 {
compatible = "mediatek,mt8192-camsys_rawb";
reg = <0x1a06f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawc: clock-controller@1a08f000 {
compatible = "mediatek,mt8192-camsys_rawc";
reg = <0x1a08f000 0x1000>;
#clock-cells = <1>;
};
- |
ipesys: clock-controller@1b000000 {
compatible = "mediatek,mt8192-ipesys";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
};
- |
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0x1f000000 0x1000>;
#clock-cells = <1>;
};

68
Bindings/clock/mediatek,mt8192-sys-clock.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8192
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The Mediatek system clock controller provides various clocks and system configuration
like reset and bus protection on MT8192.
properties:
compatible:
items:
- enum:
- mediatek,mt8192-topckgen
- mediatek,mt8192-infracfg
- mediatek,mt8192-pericfg
- mediatek,mt8192-apmixedsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8192-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
- |
infracfg: syscon@10001000 {
compatible = "mediatek,mt8192-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
};
- |
pericfg: syscon@10003000 {
compatible = "mediatek,mt8192-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
};
- |
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8192-apmixedsys", "syscon";
reg = <0x1000c000 0x1000>;
#clock-cells = <1>;
};

238
Bindings/clock/mediatek,mt8195-clock.yaml Normal file
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@ -0,0 +1,238 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices except apusys_pll provide clock gate control in different IP blocks.
The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-scp_adsp
- mediatek,mt8195-imp_iic_wrap_s
- mediatek,mt8195-imp_iic_wrap_w
- mediatek,mt8195-mfgcfg
- mediatek,mt8195-wpesys
- mediatek,mt8195-wpesys_vpp0
- mediatek,mt8195-wpesys_vpp1
- mediatek,mt8195-imgsys
- mediatek,mt8195-imgsys1_dip_top
- mediatek,mt8195-imgsys1_dip_nr
- mediatek,mt8195-imgsys1_wpe
- mediatek,mt8195-ipesys
- mediatek,mt8195-camsys
- mediatek,mt8195-camsys_rawa
- mediatek,mt8195-camsys_yuva
- mediatek,mt8195-camsys_rawb
- mediatek,mt8195-camsys_yuvb
- mediatek,mt8195-camsys_mraw
- mediatek,mt8195-ccusys
- mediatek,mt8195-vdecsys_soc
- mediatek,mt8195-vdecsys
- mediatek,mt8195-vdecsys_core1
- mediatek,mt8195-vencsys
- mediatek,mt8195-vencsys_core1
- mediatek,mt8195-apusys_pll
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0x10720000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s";
reg = <0x11d03000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_w: clock-controller@11e05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w";
reg = <0x11e05000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg";
reg = <0x13fbf000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0x14e00000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp0: clock-controller@14e02000 {
compatible = "mediatek,mt8195-wpesys_vpp0";
reg = <0x14e02000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp1: clock-controller@14e03000 {
compatible = "mediatek,mt8195-wpesys_vpp1";
reg = <0x14e03000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0x15000000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0x15110000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0x15130000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_wpe: clock-controller@15220000 {
compatible = "mediatek,mt8195-imgsys1_wpe";
reg = <0x15220000 0x1000>;
#clock-cells = <1>;
};
- |
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0x15330000 0x1000>;
#clock-cells = <1>;
};
- |
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0x16000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0x1604f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8195-camsys_yuva";
reg = <0x1606f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8195-camsys_rawb";
reg = <0x1608f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8195-camsys_yuvb";
reg = <0x160af000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_mraw: clock-controller@16140000 {
compatible = "mediatek,mt8195-camsys_mraw";
reg = <0x16140000 0x1000>;
#clock-cells = <1>;
};
- |
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0x17200000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0x1800f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0x1802f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0x1803f000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys: clock-controller@1a000000 {
compatible = "mediatek,mt8195-vencsys";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
};
- |
apusys_pll: clock-controller@190f3000 {
compatible = "mediatek,mt8195-apusys_pll";
reg = <0x190f3000 0x1000>;
#clock-cells = <1>;
};

76
Bindings/clock/mediatek,mt8195-sys-clock.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys provides most of PLLs which generated from SoC 26m.
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-topckgen
- mediatek,mt8195-infracfg_ao
- mediatek,mt8195-apmixedsys
- mediatek,mt8195-pericfg_ao
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8195-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
- |
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
};
- |
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8195-apmixedsys", "syscon";
reg = <0x1000c000 0x1000>;
#clock-cells = <1>;
};
- |
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8195-pericfg_ao", "syscon";
reg = <0x11003000 0x1000>;
#clock-cells = <1>;
};

71
Bindings/clock/mediatek,pericfg.yaml Normal file
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@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,pericfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Peripheral Configuration Controller
maintainers:
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
description:
The Mediatek pericfg controller provides various clocks and reset outputs
to the system.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-pericfg
- mediatek,mt2712-pericfg
- mediatek,mt6765-pericfg
- mediatek,mt6795-pericfg
- mediatek,mt7622-pericfg
- mediatek,mt7629-pericfg
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
- mediatek,mt8188-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
- items:
# Special case for mt7623 for backward compatibility
- const: mediatek,mt7623-pericfg
- const: mediatek,mt2701-pericfg
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pericfg@10003000 {
compatible = "mediatek,mt8173-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
pericfg@10003000 {
compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

93
Bindings/clock/mediatek,syscon.yaml Normal file
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@ -0,0 +1,93 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Clock controller syscon's
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description:
The MediaTek clock controller syscon's provide various clocks to the system.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-bdpsys
- mediatek,mt2701-imgsys
- mediatek,mt2701-vdecsys
- mediatek,mt2712-bdpsys
- mediatek,mt2712-imgsys
- mediatek,mt2712-jpgdecsys
- mediatek,mt2712-mcucfg
- mediatek,mt2712-mfgcfg
- mediatek,mt2712-vdecsys
- mediatek,mt2712-vencsys
- mediatek,mt6765-camsys
- mediatek,mt6765-imgsys
- mediatek,mt6765-mipi0a
- mediatek,mt6765-vcodecsys
- mediatek,mt6779-camsys
- mediatek,mt6779-imgsys
- mediatek,mt6779-ipesys
- mediatek,mt6779-mfgcfg
- mediatek,mt6779-vdecsys
- mediatek,mt6779-vencsys
- mediatek,mt6797-imgsys
- mediatek,mt6797-vdecsys
- mediatek,mt6797-vencsys
- mediatek,mt8167-imgsys
- mediatek,mt8167-mfgcfg
- mediatek,mt8167-vdecsys
- mediatek,mt8173-imgsys
- mediatek,mt8173-vdecsys
- mediatek,mt8173-vencltsys
- mediatek,mt8173-vencsys
- mediatek,mt8183-camsys
- mediatek,mt8183-imgsys
- mediatek,mt8183-ipu_conn
- mediatek,mt8183-ipu_adl
- mediatek,mt8183-ipu_core0
- mediatek,mt8183-ipu_core1
- mediatek,mt8183-mcucfg
- mediatek,mt8183-mfgcfg
- mediatek,mt8183-vdecsys
- mediatek,mt8183-vencsys
- const: syscon
- items:
- const: mediatek,mt7623-bdpsys
- const: mediatek,mt2701-bdpsys
- const: syscon
- items:
- const: mediatek,mt7623-imgsys
- const: mediatek,mt2701-imgsys
- const: syscon
- items:
- const: mediatek,mt7623-vdecsys
- const: mediatek,mt2701-vdecsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@11220000 {
compatible = "mediatek,mt2701-bdpsys", "syscon";
reg = <0x11220000 0x2000>;
#clock-cells = <1>;
};

1
Bindings/clock/nxp,imx95-blk-ctl.yaml
View file

@ -16,6 +16,7 @@ properties:
- nxp,imx95-lvds-csr
- nxp,imx95-display-csr
- nxp,imx95-camera-csr
- nxp,imx95-netcmix-blk-ctrl
- nxp,imx95-vpu-csr
- const: syscon

51
Bindings/clock/nxp,lpc3220-clk.yaml Normal file
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx Clock Controller
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
const: nxp,lpc3220-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
items:
- description: External 32768 Hz oscillator.
- description: Optional high frequency oscillator.
clock-names:
minItems: 1
items:
- const: xtal_32k
- const: xtal
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller@0 {
compatible = "nxp,lpc3220-clk";
reg = <0x00 0x114>;
#clock-cells = <1>;
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
};

35
Bindings/clock/nxp,lpc3220-usb-clk.yaml Normal file
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@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-usb-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx USB Clock Controller
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
const: nxp,lpc3220-usb-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@f00 {
compatible = "nxp,lpc3220-usb-clk";
reg = <0xf00 0x100>;
#clock-cells = <1>;
};

4
Bindings/clock/qcom,a53pll.yaml
View file

@ -21,6 +21,7 @@ properties:
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,ipq9574-a73pll
- qcom,msm8226-a7pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll
@ -40,6 +41,9 @@ properties:
operating-points-v2: true
opp-table:
type: object
required:
- compatible
- reg

2
Bindings/clock/qcom,ipq5332-gcc.yaml
View file

@ -31,6 +31,8 @@ properties:
- description: USB PCIE wrapper pipe clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible

47
Bindings/clock/qcom,qcs404-turingcc.yaml Normal file
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@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Turing Clock & Reset Controller on QCS404
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
const: qcom,qcs404-turingcc
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
clock-controller@800000 {
compatible = "qcom,qcs404-turingcc";
reg = <0x00800000 0x30000>;
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Bindings/clock/qcom,rpmcc.yaml
View file

@ -139,7 +139,7 @@ examples:
- |
rpm {
rpm-requests {
compatible = "qcom,rpm-msm8916";
compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
clock-controller {

13
Bindings/clock/qcom,sc8280xp-lpasscc.yaml
View file

@ -18,9 +18,16 @@ description: |
properties:
compatible:
enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
oneOf:
- enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
- items:
- const: qcom,x1e80100-lpassaudiocc
- const: qcom,sc8280xp-lpassaudiocc
- items:
- const: qcom,x1e80100-lpasscc
- const: qcom,sc8280xp-lpasscc
reg:
maxItems: 1

63
Bindings/clock/qcom,sm4450-camcc.yaml Normal file
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

71
Bindings/clock/qcom,sm4450-dispcc.yaml Normal file
View file

@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

77
Bindings/clock/qcom,sm8150-camcc.yaml Normal file
View file

@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM8150
maintainers:
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8150.
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
properties:
compatible:
const: qcom,sm8150-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock from GCC
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ad00000 {
compatible = "qcom,sm8150-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

19
Bindings/clock/qcom,sm8450-camcc.yaml
View file

@ -21,9 +21,6 @@ description: |
include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
@ -57,7 +54,21 @@ required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
then:
required:
- required-opps
unevaluatedProperties: false

2
Bindings/clock/qcom,sm8450-gpucc.yaml
View file

@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc

11
Bindings/clock/qcom,sm8450-videocc.yaml
View file

@ -44,11 +44,20 @@ required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
then:
required:
- required-opps
unevaluatedProperties: false

8
Bindings/clock/renesas,cpg-clocks.yaml
View file

@ -32,12 +32,16 @@ properties:
reg:
maxItems: 1
clocks: true
clocks:
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
clock-output-names: true
clock-output-names:
minItems: 3
maxItems: 17
renesas,mode:
description: Board-specific settings of the MD_CK* bits on R-Mobile A1

1
Bindings/clock/renesas,cpg-mssr.yaml
View file

@ -31,6 +31,7 @@ properties:
- renesas,r8a7745-cpg-mssr # RZ/G1E
- renesas,r8a77470-cpg-mssr # RZ/G1C
- renesas,r8a774a1-cpg-mssr # RZ/G2M
- renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0
- renesas,r8a774b1-cpg-mssr # RZ/G2N
- renesas,r8a774c0-cpg-mssr # RZ/G2E
- renesas,r8a774e1-cpg-mssr # RZ/G2H

80
Bindings/clock/renesas,rzv2h-cpg.yaml Normal file
View file

@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
and control of clock signals for the IP modules, generation and control of resets,
and control over booting, low power consumption and power supply domains.
properties:
compatible:
const: renesas,r9a09g057-cpg
reg:
maxItems: 1
clocks:
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
clock-names:
items:
- const: audio_extal
- const: rtxin
- const: qextal
'#clock-cells':
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register
used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
calculation is (1 * 16 + 3) = 0x13.
const: 2
'#power-domain-cells':
const: 0
'#reset-cells':
description:
The single reset specifier cell must be the reset number. The reset number
is calculated as the reset register offset index multiplied by 16, plus the
actual bit in the register used to reset the specific IP block. For example,
for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@10420000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0x10420000 0x10000>;
clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
clock-names = "audio_extal", "rtxin", "qextal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

56
Bindings/clock/rockchip,rk3576-cru.yaml Normal file
View file

@ -0,0 +1,56 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip rk3576 Family Clock and Reset Control Module
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
- Detlev Casanova <detlev.casanova@collabora.com>
description:
The RK3576 clock controller generates the clock and also implements a reset
controller for SoC peripherals. For example it provides SCLK_UART2 and
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
module.
properties:
compatible:
const: rockchip,rk3576-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
maxItems: 2
clock-names:
items:
- const: xin24m
- const: xin32k
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0xfd7c0000 0x5c000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

4
Bindings/clock/rockchip,rk3588-cru.yaml
View file

@ -42,10 +42,6 @@ properties:
- const: xin24m
- const: xin32k
assigned-clocks: true
assigned-clock-rates: true
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: >

19
Bindings/clock/samsung,exynosautov9-clock.yaml
View file

@ -35,6 +35,7 @@ properties:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
- samsung,exynosautov9-cmu-dpum
- samsung,exynosautov9-cmu-fsys0
- samsung,exynosautov9-cmu-fsys1
- samsung,exynosautov9-cmu-fsys2
@ -109,6 +110,24 @@ allOf:
- const: oscclk
- const: dout_clkcmu_core_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-dpum
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: DPU Main bus clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- if:
properties:
compatible:

162
Bindings/clock/samsung,exynosautov920-clock.yaml Normal file
View file

@ -0,0 +1,162 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung ExynosAuto v920 SoC clock controller
maintainers:
- Sunyeal Hong <sunyeal.hong@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
ExynosAuto v920 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
properties:
compatible:
enum:
- samsung,exynosautov920-cmu-top
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_PERICn NOC clock (from CMU_TOP)
- description: CMU_PERICn IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: ip
- if:
properties:
compatible:
enum:
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-hsi0
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-hsi1
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_HSI1 NOC clock (from CMU_TOP)
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: usbdrd
- const: mmc_card
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_PERIC0
- |
#include <dt-bindings/clock/samsung,exynosautov920.h>
cmu_peric0: clock-controller@10800000 {
compatible = "samsung,exynosautov920-cmu-peric0";
reg = <0x10800000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
clock-names = "oscclk",
"noc",
"ip";
};
...

10
Bindings/clock/st,stm32mp1-rcc.yaml
View file

@ -60,8 +60,14 @@ properties:
- st,stm32mp1-rcc
- st,stm32mp13-rcc
- const: syscon
clocks: true
clock-names: true
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
reg:
maxItems: 1

2
Bindings/cpu/idle-states.yaml
View file

@ -385,7 +385,7 @@ patternProperties:
This property is required in idle state nodes of device tree meant
for RISC-V systems. For more details on the suspend_type parameter
refer the SBI specifiation v0.3 (or higher) [7].
refer the SBI specification v0.3 (or higher) [7].
local-timer-stop:
description:

5
Bindings/crypto/fsl,sec-v4.0.yaml
View file

@ -137,7 +137,10 @@ patternProperties:
- const: fsl,sec-v4.0-rtic
reg:
maxItems: 1
items:
- description: RTIC control and status register space.
- description: RTIC recoverable error indication register space.
minItems: 1
ranges:
maxItems: 1

1
Bindings/crypto/qcom,prng.yaml
View file

@ -17,6 +17,7 @@ properties:
- qcom,prng-ee # 8996 and later using EE
- items:
- enum:
- qcom,sa8255p-trng
- qcom,sa8775p-trng
- qcom,sc7280-trng
- qcom,sm8450-trng

21
Bindings/display/bridge/toshiba,tc358767.yaml
View file

@ -92,12 +92,31 @@ properties:
reference to a valid DPI output or input endpoint node.
port@2:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
eDP/DP output port. The remote endpoint phandle should be a
reference to a valid eDP panel input endpoint node. This port is
optional, treated as DP panel if not defined
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
toshiba,pre-emphasis:
description:
Display port output Pre-Emphasis settings for both DP lanes.
$ref: /schemas/types.yaml#/definitions/uint8-array
minItems: 2
maxItems: 2
items:
enum:
- 0 # No pre-emphasis
- 1 # 3.5dB pre-emphasis
- 2 # 6dB pre-emphasis
oneOf:
- required:
- port@0

54
Bindings/display/elgin,jg10309-01.yaml Normal file
View file

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/elgin,jg10309-01.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Elgin JG10309-01 SPI-controlled display
maintainers:
- Fabio Estevam <festevam@gmail.com>
description: |
The Elgin JG10309-01 SPI-controlled display is used on the RV1108-Elgin-r1
board and is a custom display.
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
const: elgin,jg10309-01
reg:
maxItems: 1
spi-max-frequency:
maximum: 24000000
spi-cpha: true
spi-cpol: true
required:
- compatible
- reg
- spi-cpha
- spi-cpol
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
display@0 {
compatible = "elgin,jg10309-01";
reg = <0>;
spi-max-frequency = <24000000>;
spi-cpha;
spi-cpol;
};
};

20
Bindings/display/fsl,lcdif.yaml
View file

@ -50,6 +50,14 @@ properties:
- const: disp_axi
minItems: 1
dmas:
items:
- description: DMA specifier for the RX DMA channel.
dma-names:
items:
- const: rx
interrupts:
items:
- description: LCDIF DMA interrupt
@ -156,6 +164,18 @@ allOf:
interrupts:
maxItems: 1
- if:
not:
properties:
compatible:
contains:
enum:
- fsl,imx28-lcdif
then:
properties:
dmas: false
dma-names: false
examples:
- |
#include <dt-bindings/clock/imx6sx-clock.h>

2
Bindings/display/lvds.yaml
View file

@ -16,7 +16,7 @@ maintainers:
description:
This binding extends the data mapping defined in lvds-data-mapping.yaml.
It supports reversing the bit order on the formats defined there in order
to accomodate for even more specialized data formats, since a variety of
to accommodate for even more specialized data formats, since a variety of
data formats and layouts is used to drive LVDS displays.
properties:

13
Bindings/display/mediatek/mediatek,dpi.yaml
View file

@ -62,6 +62,19 @@ properties:
- const: default
- const: sleep
power-domains:
description: |
The MediaTek DPI module is typically associated with one of the
following multimedia power domains:
POWER_DOMAIN_DISPLAY
POWER_DOMAIN_VDOSYS
POWER_DOMAIN_MM
The specific power domain used varies depending on the SoC design.
It is recommended to explicitly add the appropriate power domain
property to the DPI node in the device tree.
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description:

19
Bindings/display/mediatek/mediatek,split.yaml
View file

@ -38,6 +38,7 @@ properties:
description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
maxItems: 1
mediatek,gce-client-reg:
description:
@ -57,6 +58,9 @@ properties:
clocks:
items:
- description: SPLIT Clock
- description: Used for interfacing with the HDMI RX signal source.
- description: Paired with receiving HDMI RX metadata.
minItems: 1
required:
- compatible
@ -72,9 +76,24 @@ allOf:
const: mediatek,mt8195-mdp3-split
then:
properties:
clocks:
minItems: 3
required:
- mediatek,gce-client-reg
- if:
properties:
compatible:
contains:
const: mediatek,mt8173-disp-split
then:
properties:
clocks:
maxItems: 1
additionalProperties: false
examples:

28
Bindings/display/msm/hdmi.yaml
View file

@ -19,14 +19,15 @@ properties:
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
- qcom,hdmi-tx-8998
clocks:
minItems: 1
maxItems: 5
maxItems: 8
clock-names:
minItems: 1
maxItems: 5
maxItems: 8
reg:
minItems: 1
@ -142,6 +143,7 @@ allOf:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: mdp_core
@ -151,6 +153,28 @@ allOf:
- const: extp
hdmi-mux-supplies: false
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-tx-8998
then:
properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: mdp_core
- const: iface
- const: core
- const: alt_iface
- const: extp
- const: bus
- const: mnoc
- const: iface_mmss
additionalProperties: false
examples:

21
Bindings/display/panel/boe,th101mb31ig002-28a.yaml
View file

@ -9,20 +9,20 @@ title: BOE TH101MB31IG002-28A WXGA DSI Display Panel
maintainers:
- Manuel Traut <manut@mecka.net>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
enum:
# BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel
- boe,th101mb31ig002-28a
# The Starry-er88577 is a 10.1" WXGA TFT-LCD panel
- starry,er88577
reg:
maxItems: 1
backlight: true
enable-gpios: true
reset-gpios: true
power-supply: true
port: true
rotation: true
@ -33,6 +33,20 @@ required:
- enable-gpios
- power-supply
allOf:
- $ref: panel-common.yaml#
- if:
properties:
compatible:
# The Starry-er88577 is a 10.1" WXGA TFT-LCD panel
const: starry,er88577
then:
properties:
reset-gpios: false
else:
required:
- reset-gpios
additionalProperties: false
examples:
@ -47,6 +61,7 @@ examples:
reg = <0>;
backlight = <&backlight_lcd0>;
enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio 55 GPIO_ACTIVE_LOW>;
rotation = <90>;
power-supply = <&vcc_3v3>;
port {

63
Bindings/display/panel/boe,tv101wum-ll2.yaml Normal file
View file

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-ll2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BOE TV101WUM-LL2 DSI Display Panel
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: boe,tv101wum-ll2
reg:
maxItems: 1
description: DSI virtual channel
backlight: true
reset-gpios: true
vsp-supply: true
vsn-supply: true
port: true
rotation: true
required:
- compatible
- reg
- reset-gpios
- vsp-supply
- vsn-supply
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "boe,tv101wum-ll2";
reg = <0>;
vsn-supply = <&vsn_lcd>;
vsp-supply = <&vsp_lcd>;
reset-gpios = <&pio 45 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
...

17
Bindings/display/panel/himax,hx8394.yaml
View file

@ -15,14 +15,12 @@ description:
such as the HannStar HSD060BHW4 720x1440 TFT LCD panel connected with
a MIPI-DSI video interface.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- hannstar,hsd060bhw4
- microchip,ac40t08a-mipi-panel
- powkiddy,x55-panel
- const: himax,hx8394
@ -46,7 +44,6 @@ properties:
required:
- compatible
- reg
- reset-gpios
- backlight
- port
- vcc-supply
@ -54,6 +51,18 @@ required:
additionalProperties: false
allOf:
- $ref: panel-common.yaml#
- if:
not:
properties:
compatible:
enum:
- microchip,ac40t08a-mipi-panel
then:
required:
- reset-gpios
examples:
- |
#include <dt-bindings/gpio/gpio.h>

1
Bindings/display/panel/ilitek,ili9806e.yaml
View file

@ -16,6 +16,7 @@ properties:
compatible:
items:
- enum:
- densitron,dmt028vghmcmi-1d
- ortustech,com35h3p70ulc
- const: ilitek,ili9806e

1
Bindings/display/panel/jadard,jd9365da-h3.yaml
View file

@ -18,6 +18,7 @@ properties:
- enum:
- chongzhou,cz101b4001
- kingdisplay,kd101ne3-40ti
- melfas,lmfbx101117480
- radxa,display-10hd-ad001
- radxa,display-8hd-ad002
- const: jadard,jd9365da-h3

6
Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
View file

@ -84,11 +84,7 @@ properties:
- port@0
- port@1
backlight: true
enable-gpios: true
power-supply: true
additionalProperties: false
unevaluatedProperties: false
required:
- compatible

4
Bindings/display/panel/panel-simple.yaml
View file

@ -158,6 +158,8 @@ properties:
- innolux,at070tn92
# Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel
- innolux,g070ace-l01
# Innolux G070ACE-LH3 7" WVGA (800x480) TFT LCD panel with WLED backlight
- innolux,g070ace-lh3
# Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel
- innolux,g070y2-l01
# Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel
@ -222,6 +224,8 @@ properties:
- okaya,rs800480t-7x0gp
# Olimex 4.3" TFT LCD panel
- olimex,lcd-olinuxino-43-ts
# On Tat Industrial Company 5" DPI TFT panel.
- ontat,kd50g21-40nt-a1
# On Tat Industrial Company 7" DPI TFT panel.
- ontat,yx700wv03
# OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel

69
Bindings/display/panel/sitronix,st7701.yaml
View file

@ -20,21 +20,19 @@ description: |
Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel
which has built-in ST7701 chip.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- anbernic,rg-arc-panel
- anbernic,rg28xx-panel
- densitron,dmt028vghmcmi-1a
- elida,kd50t048a
- techstar,ts8550b
- const: sitronix,st7701
reg:
description: DSI virtual channel used by that screen
description: DSI / SPI channel used by that screen
maxItems: 1
VCC-supply:
@ -43,6 +41,13 @@ properties:
IOVCC-supply:
description: I/O system regulator
dc-gpios:
maxItems: 1
description:
Controller data/command selection (D/CX) in 4-line SPI mode.
If not set, the controller is in 3-line SPI mode.
Disallowed for DSI.
port: true
reset-gpios: true
rotation: true
@ -57,7 +62,38 @@ required:
- port
- reset-gpios
additionalProperties: false
allOf:
- $ref: panel-common.yaml#
- if:
properties:
compatible:
contains:
# SPI connected panels
enum:
- anbernic,rg28xx-panel
then:
$ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
properties:
compatible:
not:
contains:
# DSI or SPI without D/CX pin
enum:
- anbernic,rg-arc-panel
- anbernic,rg28xx-panel
- densitron,dmt028vghmcmi-1a
- elida,kd50t048a
- techstar,ts8550b
then:
required:
- dc-gpios
else:
properties:
dc-gpios: false
unevaluatedProperties: false
examples:
- |
@ -82,3 +118,26 @@ examples:
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "anbernic,rg28xx-panel", "sitronix,st7701";
reg = <0>;
spi-max-frequency = <3125000>;
VCC-supply = <&reg_lcd>;
IOVCC-supply = <&reg_lcd>;
reset-gpios = <&pio 8 14 GPIO_ACTIVE_HIGH>; /* LCD-RST: PI14 */
backlight = <&backlight>;
port {
panel_in_rgb: endpoint {
remote-endpoint = <&tcon_lcd0_out_lcd>;
};
};
};
};

32
Bindings/display/renesas,rzg2l-du.yaml
View file

@ -18,6 +18,7 @@ properties:
compatible:
oneOf:
- enum:
- renesas,r9a07g043u-du # RZ/G2UL
- renesas,r9a07g044-du # RZ/G2{L,LC}
- items:
- enum:
@ -60,9 +61,6 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
required:
- port@0
unevaluatedProperties: false
renesas,vsps:
@ -88,6 +86,34 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a07g043u-du
then:
properties:
ports:
properties:
port@0:
description: DPI
required:
- port@0
else:
properties:
ports:
properties:
port@0:
description: DSI
port@1:
description: DPI
required:
- port@0
- port@1
examples:
# RZ/G2L DU
- |

84
Bindings/dma/cirrus,ep9301-dma-m2m.yaml Normal file
View file

@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic ep93xx SoC DMA controller
maintainers:
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
- Nikita Shubin <nikita.shubin@maquefel.me>
allOf:
- $ref: dma-controller.yaml#
properties:
compatible:
oneOf:
- const: cirrus,ep9301-dma-m2m
- items:
- enum:
- cirrus,ep9302-dma-m2m
- cirrus,ep9307-dma-m2m
- cirrus,ep9312-dma-m2m
- cirrus,ep9315-dma-m2m
- const: cirrus,ep9301-dma-m2m
reg:
items:
- description: m2m0 channel registers
- description: m2m1 channel registers
clocks:
items:
- description: m2m0 channel gate clock
- description: m2m1 channel gate clock
clock-names:
items:
- const: m2m0
- const: m2m1
interrupts:
items:
- description: m2m0 channel interrupt
- description: m2m1 channel interrupt
'#dma-cells':
const: 2
description: |
The first cell is the unique device channel number as indicated by this
table for ep93xx:
10: SPI controller
11: IDE controller
The second cell is the DMA direction line number:
1: Memory to device
2: Device to memory
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
dma-controller@80000100 {
compatible = "cirrus,ep9301-dma-m2m";
reg = <0x80000100 0x0040>,
<0x80000140 0x0040>;
clocks = <&syscon EP93XX_CLK_M2M0>,
<&syscon EP93XX_CLK_M2M1>;
clock-names = "m2m0", "m2m1";
interrupt-parent = <&vic0>;
interrupts = <17>, <18>;
#dma-cells = <2>;
};

144
Bindings/dma/cirrus,ep9301-dma-m2p.yaml Normal file
View file

@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic ep93xx SoC M2P DMA controller
maintainers:
- Alexander Sverdlin <alexander.sverdlin@gmail.com>
- Nikita Shubin <nikita.shubin@maquefel.me>
allOf:
- $ref: dma-controller.yaml#
properties:
compatible:
oneOf:
- const: cirrus,ep9301-dma-m2p
- items:
- enum:
- cirrus,ep9302-dma-m2p
- cirrus,ep9307-dma-m2p
- cirrus,ep9312-dma-m2p
- cirrus,ep9315-dma-m2p
- const: cirrus,ep9301-dma-m2p
reg:
items:
- description: m2p0 channel registers
- description: m2p1 channel registers
- description: m2p2 channel registers
- description: m2p3 channel registers
- description: m2p4 channel registers
- description: m2p5 channel registers
- description: m2p6 channel registers
- description: m2p7 channel registers
- description: m2p8 channel registers
- description: m2p9 channel registers
clocks:
items:
- description: m2p0 channel gate clock
- description: m2p1 channel gate clock
- description: m2p2 channel gate clock
- description: m2p3 channel gate clock
- description: m2p4 channel gate clock
- description: m2p5 channel gate clock
- description: m2p6 channel gate clock
- description: m2p7 channel gate clock
- description: m2p8 channel gate clock
- description: m2p9 channel gate clock
clock-names:
items:
- const: m2p0
- const: m2p1
- const: m2p2
- const: m2p3
- const: m2p4
- const: m2p5
- const: m2p6
- const: m2p7
- const: m2p8
- const: m2p9
interrupts:
items:
- description: m2p0 channel interrupt
- description: m2p1 channel interrupt
- description: m2p2 channel interrupt
- description: m2p3 channel interrupt
- description: m2p4 channel interrupt
- description: m2p5 channel interrupt
- description: m2p6 channel interrupt
- description: m2p7 channel interrupt
- description: m2p8 channel interrupt
- description: m2p9 channel interrupt
'#dma-cells':
const: 2
description: |
The first cell is the unique device channel number as indicated by this
table for ep93xx:
0: I2S channel 1
1: I2S channel 2 (unused)
2: AC97 channel 1 (unused)
3: AC97 channel 2 (unused)
4: AC97 channel 3 (unused)
5: I2S channel 3 (unused)
6: UART1 (unused)
7: UART2 (unused)
8: UART3 (unused)
9: IRDA (unused)
The second cell is the DMA direction line number:
1: Memory to device
2: Device to memory
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cirrus,ep9301-syscon.h>
dma-controller@80000000 {
compatible = "cirrus,ep9301-dma-m2p";
reg = <0x80000000 0x0040>,
<0x80000040 0x0040>,
<0x80000080 0x0040>,
<0x800000c0 0x0040>,
<0x80000240 0x0040>,
<0x80000200 0x0040>,
<0x800002c0 0x0040>,
<0x80000280 0x0040>,
<0x80000340 0x0040>,
<0x80000300 0x0040>;
clocks = <&syscon EP93XX_CLK_M2P0>,
<&syscon EP93XX_CLK_M2P1>,
<&syscon EP93XX_CLK_M2P2>,
<&syscon EP93XX_CLK_M2P3>,
<&syscon EP93XX_CLK_M2P4>,
<&syscon EP93XX_CLK_M2P5>,
<&syscon EP93XX_CLK_M2P6>,
<&syscon EP93XX_CLK_M2P7>,
<&syscon EP93XX_CLK_M2P8>,
<&syscon EP93XX_CLK_M2P9>;
clock-names = "m2p0", "m2p1",
"m2p2", "m2p3",
"m2p4", "m2p5",
"m2p6", "m2p7",
"m2p8", "m2p9";
interrupt-parent = <&vic0>;
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
#dma-cells = <2>;
};

14
Bindings/dma/fsl,imx-dma.yaml
View file

@ -28,6 +28,14 @@ properties:
- description: DMA Error interrupt
minItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: ipg
- const: ahb
"#dma-cells":
const: 1
@ -42,15 +50,21 @@ required:
- reg
- interrupts
- "#dma-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx27-clock.h>
dma-controller@10001000 {
compatible = "fsl,imx27-dma";
reg = <0x10001000 0x1000>;
interrupts = <32 33>;
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, <&clks IMX27_CLK_DMA_AHB_GATE>;
clock-names = "ipg", "ahb";
};

15
Bindings/dma/fsl,mxs-dma.yaml
View file

@ -11,6 +11,17 @@ maintainers:
allOf:
- $ref: dma-controller.yaml#
- if:
properties:
compatible:
contains:
const: fsl,imx8qxp-dma-apbh
then:
required:
- power-domains
else:
properties:
power-domains: false
properties:
compatible:
@ -20,6 +31,7 @@ properties:
- fsl,imx6q-dma-apbh
- fsl,imx6sx-dma-apbh
- fsl,imx7d-dma-apbh
- fsl,imx8qxp-dma-apbh
- const: fsl,imx28-dma-apbh
- enum:
- fsl,imx23-dma-apbh
@ -42,6 +54,9 @@ properties:
dma-channels:
enum: [4, 8, 16]
power-domains:
maxItems: 1
required:
- compatible
- reg

13
Bindings/dma/fsl-qdma.yaml
View file

@ -11,11 +11,14 @@ maintainers:
properties:
compatible:
enum:
- fsl,ls1021a-qdma
- fsl,ls1028a-qdma
- fsl,ls1043a-qdma
- fsl,ls1046a-qdma
oneOf:
- const: fsl,ls1021a-qdma
- items:
- enum:
- fsl,ls1028a-qdma
- fsl,ls1043a-qdma
- fsl,ls1046a-qdma
- const: fsl,ls1021a-qdma
reg:
items:

65
Bindings/dma/loongson,ls1b-apbdma.yaml Normal file
View file

@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-1 APB DMA Controller
maintainers:
- Keguang Zhang <keguang.zhang@gmail.com>
description:
Loongson-1 APB DMA controller provides 3 independent channels for
peripherals such as NAND, audio playback and capture.
properties:
compatible:
oneOf:
- const: loongson,ls1b-apbdma
- items:
- enum:
- loongson,ls1a-apbdma
- loongson,ls1c-apbdma
- const: loongson,ls1b-apbdma
reg:
maxItems: 1
interrupts:
items:
- description: NAND interrupt
- description: Audio playback interrupt
- description: Audio capture interrupt
interrupt-names:
items:
- const: ch0
- const: ch1
- const: ch2
'#dma-cells':
const: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- '#dma-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma-controller@1fd01160 {
compatible = "loongson,ls1b-apbdma";
reg = <0x1fd01160 0x4>;
interrupt-parent = <&intc0>;
interrupts = <13 IRQ_TYPE_EDGE_RISING>,
<14 IRQ_TYPE_EDGE_RISING>,
<15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ch0", "ch1", "ch2";
#dma-cells = <1>;
};

61
Bindings/dma/marvell,xor-v2.yaml Normal file
View file

@ -0,0 +1,61 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell XOR v2 engines
maintainers:
- Andrew Lunn <andrew@lunn.ch>
properties:
compatible:
oneOf:
- const: marvell,xor-v2
- items:
- enum:
- marvell,armada-7k-xor
- const: marvell,xor-v2
reg:
items:
- description: DMA registers
- description: global registers
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: reg
msi-parent:
description:
Phandle to the MSI-capable interrupt controller used for
interrupts.
maxItems: 1
dma-coherent: true
required:
- compatible
- reg
- msi-parent
- dma-coherent
additionalProperties: false
examples:
- |
xor0@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
clocks = <&ap_clk 0>, <&ap_clk 1>;
clock-names = "core", "reg";
msi-parent = <&gic_v2m0>;
dma-coherent;
};

49
Bindings/dma/nxp,lpc3220-dmamux.yaml Normal file
View file

@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nxp,lpc3220-dmamux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DMA multiplexer for LPC32XX SoC (DMA request router)
maintainers:
- J.M.B. Downing <jonathan.downing@nautel.com>
- Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
allOf:
- $ref: dma-router.yaml#
properties:
compatible:
const: nxp,lpc3220-dmamux
reg:
maxItems: 1
dma-masters:
description: phandle to a dma node compatible with arm,pl080
maxItems: 1
"#dma-cells":
const: 3
description: |
First two cells same as for device pointed in dma-masters.
Third cell represents mux value for the request.
required:
- compatible
- reg
- dma-masters
additionalProperties: false
examples:
- |
dma-router@7c {
compatible = "nxp,lpc3220-dmamux";
reg = <0x7c 0x8>;
dma-masters = <&dma>;
#dma-cells = <3>;
};
...

1
Bindings/dma/renesas,rz-dmac.yaml
View file

@ -19,6 +19,7 @@ properties:
- renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
- renesas,r9a07g054-dmac # RZ/V2L
- renesas,r9a08g045-dmac # RZ/G3S
- const: renesas,rz-dmac
reg:

2
Bindings/dma/ti-dma-crossbar.txt
View file

@ -20,7 +20,7 @@ Optional properties:
memcpy channels in eDMA.
Notes:
When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
When requesting channel via ti,dra7-dma-crossbar, the DMA client must request
the DMA event number as crossbar ID (input to the DMA crossbar).
For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:

4
Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
View file

@ -24,7 +24,9 @@ properties:
const: 1
compatible:
const: xlnx,zynqmp-dma-1.0
enum:
- amd,versal2-dma-1.0
- xlnx,zynqmp-dma-1.0
reg:
description: memory map for gdma/adma module access

1
Bindings/eeprom/at24.yaml
View file

@ -116,6 +116,7 @@ properties:
- const: atmel,24c02
- items:
- enum:
- giantec,gt24c04a
- onnn,cat24c04
- onnn,cat24c05
- rohm,br24g04

11
Bindings/extcon/extcon-ptn5150.yaml
View file

@ -37,6 +37,11 @@ properties:
GPIO pin (output) used to control VBUS. If skipped, no such control
takes place.
port:
$ref: /schemas/graph.yaml#/properties/port
description:
A port node to link the usb controller for the dual role switch.
required:
- compatible
- interrupts
@ -58,5 +63,11 @@ examples:
interrupt-parent = <&msmgpio>;
interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
vbus-gpios = <&msmgpio 148 GPIO_ACTIVE_HIGH>;
port {
endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};

37
Bindings/extcon/linux,extcon-usb-gpio.yaml Normal file
View file

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/linux,extcon-usb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: USB GPIO Extcon device
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
This is a virtual device used to generate USB cable states from the USB ID pin
connected to a GPIO pin.
properties:
compatible:
const: linux,extcon-usb-gpio
id-gpios:
description: gpio for USB ID pin. See gpio binding.
vbus-gpios:
description: gpio for USB VBUS pin.
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
};

20
Bindings/firmware/arm,scmi.yaml
View file

@ -22,6 +22,9 @@ description: |
[0] https://developer.arm.com/documentation/den0056/latest
anyOf:
- $ref: /schemas/firmware/nxp,imx95-scmi.yaml
properties:
$nodename:
const: scmi
@ -121,6 +124,13 @@ properties:
atomic mode of operation, even if requested.
default: 0
arm,max-rx-timeout-ms:
description:
An optional time value, expressed in milliseconds, representing the
transport maximum timeout value for the receive channel. The value should
be a non-zero value if set.
minimum: 1
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@ -145,6 +155,14 @@ properties:
required:
- '#power-domain-cells'
protocol@12:
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x12
protocol@13:
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
@ -284,7 +302,7 @@ properties:
required:
- reg
additionalProperties: false
unevaluatedProperties: false
$defs:
protocol-node:

43
Bindings/firmware/nxp,imx95-scmi.yaml Normal file
View file

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2024 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX95 System Control and Management Interface(SCMI) Vendor Protocols Extension
maintainers:
- Peng Fan <peng.fan@nxp.com>
properties:
protocol@81:
$ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x81
protocol@84:
$ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x84
nxp,ctrl-ids:
description:
Each entry consists of 2 integers, represents the ctrl id and the value
items:
items:
- description: the ctrl id index
enum: [0, 1, 2, 3, 4, 5, 6, 7, 0x8000, 0x8001, 0x8002, 0x8003,
0x8004, 0x8005, 0x8006, 0x8007]
- description: the value assigned to the ctrl id
minItems: 1
maxItems: 16
$ref: /schemas/types.yaml#/definitions/uint32-matrix
additionalProperties: true

1
Bindings/gnss/brcm,bcm4751.yaml
View file

@ -18,6 +18,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:

5
Bindings/gnss/gnss-common.yaml
View file

@ -35,11 +35,6 @@ properties:
GPIO line, this is used.
maxItems: 1
current-speed:
description: The baudrate in bits per second of the device as it comes
online, current active speed.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
examples:

1
Bindings/gnss/mediatek.yaml
View file

@ -15,6 +15,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:

1
Bindings/gnss/sirfstar.yaml
View file

@ -21,6 +21,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:

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