From b61ab53cb789e568acbb2952fbead20ab853a696 Mon Sep 17 00:00:00 2001
From: Dimitry Andric
Date: Thu, 3 May 2012 16:50:55 +0000
Subject: [PATCH 1/2] Vendor import of llvm release_31 branch r155985:
http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985
---
CMakeLists.txt | 10 -
CREDITS.TXT | 20 +-
autoconf/configure.ac | 7 +
cmake/modules/HandleLLVMOptions.cmake | 6 +-
configure | 19 +-
docs/CodeGenerator.html | 10 +-
docs/CommandGuide/FileCheck.pod | 58 +-
docs/DebuggingJITedCode.html | 249 +-
docs/LLVMBuild.html | 8 +-
docs/LangRef.html | 23 +-
docs/ProgrammersManual.html | 5 +-
docs/ReleaseNotes.html | 63 +-
docs/TestingGuide.html | 20 +-
include/llvm-c/lto.h | 6 -
include/llvm/ADT/SmallPtrSet.h | 3 -
include/llvm/ADT/StringMap.h | 2 +-
include/llvm/CodeGen/DFAPacketizer.h | 44 +-
include/llvm/CodeGen/Passes.h | 2 +-
include/llvm/CodeGen/ScheduleDAGInstrs.h | 7 +
include/llvm/CodeGen/SlotIndexes.h | 211 +-
include/llvm/Config/config.h.cmake | 3 -
include/llvm/Config/config.h.in | 3 +
include/llvm/IntrinsicsX86.td | 20 -
include/llvm/LLVMContext.h | 2 +-
include/llvm/MC/MCParser/AsmLexer.h | 3 -
include/llvm/MC/MCParser/MCAsmLexer.h | 3 +-
include/llvm/Object/ELF.h | 9 +
include/llvm/Operator.h | 31 +-
include/llvm/Support/IRBuilder.h | 87 +-
include/llvm/Support/JSONParser.h | 448 --
include/llvm/Support/Locale.h | 17 +
include/llvm/Support/MDBuilder.h | 118 +
include/llvm/Support/Process.h | 4 +
include/llvm/Support/SourceMgr.h | 7 +-
include/llvm/Support/YAMLParser.h | 5 +-
include/llvm/Support/raw_ostream.h | 5 +
include/llvm/TableGen/Error.h | 5 +
include/llvm/TableGen/Record.h | 4 +-
include/llvm/Target/TargetLibraryInfo.h | 10 +-
include/llvm/Target/TargetRegisterInfo.h | 2 +-
.../llvm/Transforms/Utils/BasicBlockUtils.h | 3 +-
include/llvm/Transforms/Vectorize.h | 9 +
lib/Analysis/ConstantFolding.cpp | 14 +-
lib/Analysis/ScalarEvolution.cpp | 2 +-
lib/Analysis/ValueTracking.cpp | 2 +-
lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp | 49 +-
lib/CodeGen/AsmPrinter/DwarfAccelTable.h | 37 +-
lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 7 +-
lib/CodeGen/DFAPacketizer.cpp | 87 +-
lib/CodeGen/LiveIntervalAnalysis.cpp | 12 +-
lib/CodeGen/MachineBasicBlock.cpp | 36 +-
lib/CodeGen/MachineBlockPlacement.cpp | 249 +-
lib/CodeGen/Passes.cpp | 55 +-
lib/CodeGen/ScheduleDAGInstrs.cpp | 6 +-
lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 1 +
.../SelectionDAG/LegalizeVectorOps.cpp | 3 +-
.../SelectionDAG/ScheduleDAGSDNodes.cpp | 8 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 2 +-
lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +-
lib/CodeGen/SlotIndexes.cpp | 52 +-
.../RuntimeDyld/CMakeLists.txt | 3 +-
.../RuntimeDyld/GDBRegistrar.cpp | 214 +
.../RuntimeDyld/JITRegistrar.h | 43 +
lib/ExecutionEngine/RuntimeDyld/ObjectImage.h | 59 +
.../RuntimeDyld/RuntimeDyld.cpp | 37 +-
.../RuntimeDyld/RuntimeDyldELF.cpp | 173 +-
.../RuntimeDyld/RuntimeDyldELF.h | 12 +-
.../RuntimeDyld/RuntimeDyldImpl.h | 21 +-
.../RuntimeDyld/RuntimeDyldMachO.cpp | 4 +-
.../RuntimeDyld/RuntimeDyldMachO.h | 4 +-
lib/MC/MCParser/AsmParser.cpp | 10 +-
lib/Object/ELFObjectFile.cpp | 10 -
lib/Support/CMakeLists.txt | 2 +-
lib/Support/JSONParser.cpp | 302 --
lib/Support/Locale.cpp | 10 +
lib/Support/LocaleGeneric.inc | 17 +
lib/Support/LocaleWindows.inc | 15 +
lib/Support/LocaleXlocale.inc | 61 +
lib/Support/SmallPtrSet.cpp | 3 +-
lib/Support/SourceMgr.cpp | 48 +-
lib/Support/Unix/Process.inc | 4 +
lib/Support/Windows/Process.inc | 32 +
lib/Support/YAMLParser.cpp | 6 +-
lib/Support/raw_ostream.cpp | 13 +
lib/TableGen/Error.cpp | 16 +
lib/Target/ARM/ARMCallingConv.td | 4 -
lib/Target/ARM/ARMInstrFormats.td | 1 +
lib/Target/ARM/ARMInstrInfo.td | 62 +-
lib/Target/ARM/ARMInstrNEON.td | 183 +-
lib/Target/ARM/ARMTargetMachine.cpp | 20 +-
lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 45 +-
.../ARM/Disassembler/ARMDisassembler.cpp | 42 +-
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 4 +-
lib/Target/CellSPU/SPUCallingConv.td | 4 -
lib/Target/CellSPU/SPUTargetMachine.cpp | 6 +-
lib/Target/Hexagon/CMakeLists.txt | 7 +-
lib/Target/Hexagon/Hexagon.h | 1 -
lib/Target/Hexagon/HexagonAsmPrinter.cpp | 53 +-
lib/Target/Hexagon/HexagonISelLowering.cpp | 4 +-
lib/Target/Hexagon/HexagonInstrFormats.td | 96 +-
lib/Target/Hexagon/HexagonInstrFormatsV4.td | 27 +-
lib/Target/Hexagon/HexagonInstrInfo.cpp | 1009 +----
lib/Target/Hexagon/HexagonInstrInfo.h | 10 -
lib/Target/Hexagon/HexagonInstrInfo.td | 4 -
lib/Target/Hexagon/HexagonInstrInfoV3.td | 51 +-
lib/Target/Hexagon/HexagonInstrInfoV4.td | 2913 ++-----------
lib/Target/Hexagon/HexagonMCInst.h | 41 -
lib/Target/Hexagon/HexagonMCInstLower.cpp | 2 +-
lib/Target/Hexagon/HexagonSchedule.td | 31 +-
lib/Target/Hexagon/HexagonScheduleV4.td | 35 +-
lib/Target/Hexagon/HexagonTargetMachine.cpp | 19 +-
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 3642 -----------------
.../InstPrinter/HexagonInstPrinter.cpp | 65 +-
.../Hexagon/InstPrinter/HexagonInstPrinter.h | 2 -
.../Hexagon/MCTargetDesc/CMakeLists.txt | 2 +-
.../Hexagon/MCTargetDesc/HexagonBaseInfo.h | 31 +-
lib/Target/MBlaze/MBlazeCallingConv.td | 4 -
lib/Target/MBlaze/MBlazeTargetMachine.cpp | 4 +-
lib/Target/MSP430/MSP430TargetMachine.cpp | 4 +-
lib/Target/Mips/CMakeLists.txt | 3 +
lib/Target/Mips/Disassembler/CMakeLists.txt | 15 +
lib/Target/Mips/Disassembler/LLVMBuild.txt | 23 +
.../Target/Mips/Disassembler}/Makefile | 15 +-
.../Mips/Disassembler/MipsDisassembler.cpp | 552 +++
lib/Target/Mips/LLVMBuild.txt | 3 +-
.../Mips/MCTargetDesc/MipsAsmBackend.cpp | 6 +-
.../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 2 +-
.../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 41 +-
lib/Target/Mips/Makefile | 6 +-
lib/Target/Mips/Mips64InstrInfo.td | 55 +-
lib/Target/Mips/MipsCondMov.td | 48 +-
lib/Target/Mips/MipsISelLowering.cpp | 2 +
lib/Target/Mips/MipsInstrFPU.td | 68 +-
lib/Target/Mips/MipsInstrFormats.td | 6 +
lib/Target/Mips/MipsInstrInfo.td | 121 +-
lib/Target/Mips/MipsTargetMachine.cpp | 14 +-
lib/Target/PTX/PTXTargetMachine.cpp | 8 +-
lib/Target/PowerPC/PPCCallingConv.td | 4 -
lib/Target/PowerPC/PPCTargetMachine.cpp | 4 +-
lib/Target/Sparc/SparcTargetMachine.cpp | 6 +-
lib/Target/TargetLibraryInfo.cpp | 80 +-
lib/Target/X86/Utils/X86ShuffleDecode.cpp | 3 +
lib/Target/X86/X86ISelLowering.cpp | 108 +-
lib/Target/X86/X86ISelLowering.h | 6 +-
lib/Target/X86/X86InstrFragmentsSIMD.td | 2 +
lib/Target/X86/X86InstrInfo.cpp | 4 +-
lib/Target/X86/X86InstrSSE.td | 50 +-
lib/Target/X86/X86Subtarget.cpp | 4 +-
lib/Target/X86/X86TargetMachine.cpp | 12 +-
lib/Target/XCore/XCoreTargetMachine.cpp | 2 +-
lib/Transforms/IPO/Internalize.cpp | 2 +
lib/Transforms/IPO/PassManagerBuilder.cpp | 11 +-
lib/Transforms/Scalar/LoopStrengthReduce.cpp | 19 +-
lib/Transforms/Scalar/LoopUnswitch.cpp | 7 +-
lib/Transforms/Scalar/ObjCARC.cpp | 69 +-
lib/Transforms/Scalar/Reassociate.cpp | 5 +-
lib/Transforms/Scalar/SimplifyLibCalls.cpp | 25 +-
lib/Transforms/Utils/BreakCriticalEdges.cpp | 43 +-
lib/Transforms/Vectorize/BBVectorize.cpp | 65 +-
lib/VMCore/AutoUpgrade.cpp | 43 +-
lib/VMCore/Instructions.cpp | 17 +
lib/VMCore/LLVMContext.cpp | 6 +-
lib/VMCore/Module.cpp | 2 +-
lib/VMCore/Verifier.cpp | 20 +-
test/Analysis/ScalarEvolution/nsw-offset.ll | 6 +-
test/Analysis/ScalarEvolution/nsw.ll | 4 +-
test/CodeGen/ARM/2011-03-23-PeepholeBug.ll | 2 +-
test/CodeGen/ARM/fusedMAC.ll | 2 +-
test/CodeGen/ARM/ldr_post.ll | 19 +-
test/CodeGen/ARM/ldr_pre.ll | 10 +-
test/CodeGen/ARM/tail-opts.ll | 2 +-
test/CodeGen/ARM/vector-extend-narrow.ll | 14 +
test/CodeGen/ARM/widen-vmovs.ll | 3 +-
test/CodeGen/CellSPU/2009-01-01-BrCond.ll | 2 +-
test/CodeGen/Mips/analyzebranch.ll | 4 +-
test/CodeGen/Mips/eh.ll | 2 +-
test/CodeGen/Mips/fpbr.ll | 4 +-
test/CodeGen/PowerPC/ppc-vaarg-agg.ll | 46 +
test/CodeGen/Thumb2/thumb2-branch.ll | 4 +-
test/CodeGen/Thumb2/thumb2-ifcvt2.ll | 10 +-
test/CodeGen/Thumb2/thumb2-jtb.ll | 10 +-
.../2006-10-19-SwitchUnnecessaryBranching.ll | 4 +-
.../X86/2008-05-01-InvalidOrdCompare.ll | 2 +-
.../X86/2010-08-04-MaskedSignedCompare.ll | 2 +-
.../CodeGen/X86/2010-11-18-SelectOfExtload.ll | 2 +-
test/CodeGen/X86/2011-09-14-valcoalesce.ll | 2 +-
test/CodeGen/X86/2012-04-26-sdglue.ll | 46 +
test/CodeGen/X86/GC/cg-O0.ll | 17 +
test/CodeGen/X86/atom-sched.ll | 4 +
test/CodeGen/X86/atomic_op.ll | 20 +
test/CodeGen/X86/avx2-intrinsics-x86.ll | 16 -
test/CodeGen/X86/avx2-vperm.ll | 34 +
test/CodeGen/X86/block-placement.ll | 165 +-
test/CodeGen/X86/br-fold.ll | 2 +-
test/CodeGen/X86/call-push.ll | 2 +-
test/CodeGen/{Generic => X86}/dbg-declare.ll | 4 +-
test/CodeGen/X86/licm-dominance.ll | 4 +-
test/CodeGen/X86/loop-blocks.ll | 40 +-
test/CodeGen/X86/machine-cp.ll | 4 +-
test/CodeGen/X86/postra-licm.ll | 2 +-
test/CodeGen/X86/pr2659.ll | 3 +-
test/CodeGen/X86/select.ll | 4 +-
test/CodeGen/X86/sibcall.ll | 2 +-
test/CodeGen/X86/sink-hoist.ll | 9 +-
test/CodeGen/X86/smul-with-overflow.ll | 2 +-
test/CodeGen/X86/sse41-blend.ll | 8 +
test/CodeGen/X86/sub-with-overflow.ll | 4 +-
test/CodeGen/X86/switch-bt.ll | 12 +-
test/CodeGen/X86/tail-opts.ll | 9 +-
test/CodeGen/X86/uint64-to-float.ll | 7 +-
test/CodeGen/X86/vec_shuffle-20.ll | 2 +-
test/CodeGen/X86/xor-icmp.ll | 8 +-
test/CodeGen/XCore/ashr.ll | 14 +-
test/MC/ARM/neon-add-encoding.s | 81 +-
test/MC/ARM/neon-shift-encoding.s | 152 +-
test/MC/ARM/neon-sub-encoding.s | 26 +
test/MC/AsmParser/macro-args.s | 24 +
test/MC/Disassembler/ARM/arm-tests.txt | 3 +
.../MC/Disassembler/ARM/invalid-MRRC2-arm.txt | 4 +
test/MC/Disassembler/ARM/neon.txt | 37 +
test/MC/Disassembler/ARM/neont2.txt | 38 +
.../ARM/unpredictable-AI1cmp-arm.txt | 30 +
.../ARM/unpredictable-MRRC2-arm.txt | 13 +
.../ARM/unpredictable-MRS-arm.txt | 18 +
.../ARM/unpredictable-swp-arm.txt | 26 +
test/MC/Disassembler/Mips/mips32.txt | 421 ++
test/MC/Disassembler/Mips/mips32_le.txt | 424 ++
test/MC/Disassembler/Mips/mips32r2.txt | 439 ++
test/MC/Disassembler/Mips/mips32r2_le.txt | 442 ++
test/MC/Disassembler/Mips/mips64.txt | 67 +
test/MC/Disassembler/Mips/mips64_le.txt | 67 +
test/MC/Disassembler/Mips/mips64r2.txt | 91 +
test/MC/Disassembler/Mips/mips64r2_le.txt | 91 +
test/MC/Disassembler/X86/intel-syntax.txt | 2 +-
test/MC/Mips/elf-bigendian.ll | 20 +-
test/MC/Mips/sym-offset.ll | 22 +
test/Transforms/BBVectorize/no-ldstr-conn.ll | 23 +
.../BBVectorize/simple-ldstr-ptrs.ll | 81 +
test/Transforms/BBVectorize/simple-sel.ll | 30 +
.../GlobalOpt/constantfold-initializers.ll | 5 +
.../Transforms/InstCombine/2012-04-30-SRem.ll | 12 +
test/Transforms/InstCombine/apint-shift.ll | 63 +-
.../X86/2012-01-13-phielim.ll | 2 +-
test/Transforms/LoopStrengthReduce/pr12691.ll | 34 +
.../2012-04-30-LoopUnswitch-LPad-Crash.ll | 101 +
test/Transforms/ObjCARC/escape.ll | 131 +
test/Transforms/Reassociate/pr12245.ll | 50 +
test/Transforms/SimplifyLibCalls/floor.ll | 41 +-
test/Transforms/SimplifyLibCalls/win-math.ll | 275 ++
test/Verifier/fpaccuracy.ll | 31 -
test/Verifier/fpmath.ll | 31 +
test/lit.cfg | 7 +-
tools/llc/llc.cpp | 26 -
tools/lli/lli.cpp | 28 +
tools/llvm-mc/Disassembler.cpp | 67 +-
tools/llvm-mc/Disassembler.h | 15 +-
tools/llvm-mc/llvm-mc.cpp | 173 +-
tools/llvm-shlib/Makefile | 3 +
tools/llvm-stress/llvm-stress.cpp | 21 +-
tools/lto/LTOCodeGenerator.cpp | 8 +-
tools/lto/LTOCodeGenerator.h | 2 -
tools/lto/lto.cpp | 6 -
tools/lto/lto.exports | 1 -
tools/opt/opt.cpp | 7 +
unittests/CMakeLists.txt | 1 -
unittests/Support/JSONParserTest.cpp | 191 -
unittests/Support/MDBuilderTest.cpp | 105 +
unittests/VMCore/InstructionsTest.cpp | 17 +
utils/Makefile | 2 +-
utils/TableGen/AsmMatcherEmitter.cpp | 19 +-
utils/TableGen/AsmWriterEmitter.cpp | 7 +-
utils/TableGen/CodeGenDAGPatterns.cpp | 25 +-
utils/TableGen/CodeGenRegisters.cpp | 10 +-
utils/TableGen/EDEmitter.cpp | 1 +
utils/TableGen/RegisterInfoEmitter.cpp | 13 +-
utils/buildit/build_llvm | 13 -
utils/json-bench/CMakeLists.txt | 5 -
utils/json-bench/JSONBench.cpp | 85 -
utils/release/findRegressions-nightly.py | 2 +-
utils/release/findRegressions-simple.py | 2 +-
utils/release/tag.sh | 22 +-
utils/release/test-release.sh | 5 +-
282 files changed, 8111 insertions(+), 10178 deletions(-)
delete mode 100644 include/llvm/Support/JSONParser.h
create mode 100644 include/llvm/Support/Locale.h
create mode 100644 include/llvm/Support/MDBuilder.h
create mode 100644 lib/ExecutionEngine/RuntimeDyld/GDBRegistrar.cpp
create mode 100644 lib/ExecutionEngine/RuntimeDyld/JITRegistrar.h
create mode 100644 lib/ExecutionEngine/RuntimeDyld/ObjectImage.h
delete mode 100644 lib/Support/JSONParser.cpp
create mode 100644 lib/Support/Locale.cpp
create mode 100644 lib/Support/LocaleGeneric.inc
create mode 100644 lib/Support/LocaleWindows.inc
create mode 100644 lib/Support/LocaleXlocale.inc
delete mode 100644 lib/Target/Hexagon/HexagonMCInst.h
delete mode 100644 lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
create mode 100644 lib/Target/Mips/Disassembler/CMakeLists.txt
create mode 100644 lib/Target/Mips/Disassembler/LLVMBuild.txt
rename {utils/json-bench => lib/Target/Mips/Disassembler}/Makefile (51%)
create mode 100644 lib/Target/Mips/Disassembler/MipsDisassembler.cpp
create mode 100644 test/CodeGen/PowerPC/ppc-vaarg-agg.ll
create mode 100644 test/CodeGen/X86/2012-04-26-sdglue.ll
create mode 100644 test/CodeGen/X86/GC/cg-O0.ll
create mode 100755 test/CodeGen/X86/avx2-vperm.ll
rename test/CodeGen/{Generic => X86}/dbg-declare.ll (93%)
create mode 100644 test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
create mode 100644 test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
create mode 100644 test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt
create mode 100644 test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
create mode 100644 test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
create mode 100644 test/MC/Disassembler/Mips/mips32.txt
create mode 100644 test/MC/Disassembler/Mips/mips32_le.txt
create mode 100644 test/MC/Disassembler/Mips/mips32r2.txt
create mode 100644 test/MC/Disassembler/Mips/mips32r2_le.txt
create mode 100644 test/MC/Disassembler/Mips/mips64.txt
create mode 100644 test/MC/Disassembler/Mips/mips64_le.txt
create mode 100644 test/MC/Disassembler/Mips/mips64r2.txt
create mode 100644 test/MC/Disassembler/Mips/mips64r2_le.txt
create mode 100644 test/MC/Mips/sym-offset.ll
create mode 100644 test/Transforms/BBVectorize/no-ldstr-conn.ll
create mode 100644 test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
create mode 100644 test/Transforms/BBVectorize/simple-sel.ll
create mode 100644 test/Transforms/InstCombine/2012-04-30-SRem.ll
create mode 100644 test/Transforms/LoopStrengthReduce/pr12691.ll
create mode 100644 test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
create mode 100644 test/Transforms/ObjCARC/escape.ll
create mode 100644 test/Transforms/Reassociate/pr12245.ll
create mode 100644 test/Transforms/SimplifyLibCalls/win-math.ll
delete mode 100644 test/Verifier/fpaccuracy.ll
create mode 100644 test/Verifier/fpmath.ll
delete mode 100644 unittests/Support/JSONParserTest.cpp
create mode 100644 unittests/Support/MDBuilderTest.cpp
delete mode 100644 utils/json-bench/CMakeLists.txt
delete mode 100644 utils/json-bench/JSONBench.cpp
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 8336bc975e3..329dd30bb57 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -213,15 +213,6 @@ if( WIN32 AND NOT CYGWIN )
set(LLVM_LIT_TOOLS_DIR "" CACHE PATH "Path to GnuWin32 tools")
endif()
-# On Win32 using MS tools, provide an option to set the number of parallel jobs
-# to use.
-if( MSVC_IDE AND ( MSVC90 OR MSVC10 ) )
- # Only Visual Studio 2008 and 2010 officially supports /MP. Visual Studio
- # 2005 supports it but it is experimental.
- set(LLVM_COMPILER_JOBS "0" CACHE STRING
- "Number of parallel compiler jobs. 0 means use all processors. Default is 0.")
-endif()
-
# Define options to control the inclusion and default build behavior for
# components which may not strictly be necessary (tools, runtime, examples, and
# tests).
@@ -396,7 +387,6 @@ add_subdirectory(utils/FileUpdate)
add_subdirectory(utils/count)
add_subdirectory(utils/not)
add_subdirectory(utils/llvm-lit)
-add_subdirectory(utils/json-bench)
add_subdirectory(utils/yaml-bench)
add_subdirectory(projects)
diff --git a/CREDITS.TXT b/CREDITS.TXT
index ef471b0887e..bf32a4c565b 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -50,9 +50,15 @@ N: Cameron Buschardt
E: buschard@uiuc.edu
D: The `mem2reg' pass - promotes values stored in memory to registers
+N: Brendon Cahoon
+E: bcahoon@codeaurora.org
+D: Loop unrolling with run-time trip counts.
+
N: Chandler Carruth
E: chandlerc@gmail.com
-D: LinkTimeOptimizer for Linux, via binutils integration, and C API
+D: Hashing algorithms and interfaces
+D: Inline cost analysis
+D: Machine block placement pass
N: Casey Carter
E: ccarter@uiuc.edu
@@ -210,6 +216,10 @@ N: Benjamin Kramer
E: benny.kra@gmail.com
D: Miscellaneous bug fixes
+N: Sundeep Kushwaha
+E: sundeepk@codeaurora.org
+D: Implemented DFA-based target independent VLIW packetizer
+
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support, parts of noalias and restrict support
@@ -245,6 +255,10 @@ N: Nick Lewycky
E: nicholas@mxc.ca
D: PredicateSimplifier pass
+N: Tony Linthicum, et. al.
+E: tlinth@codeaurora.org
+D: Backend for Qualcomm's Hexagon VLIW processor.
+
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
W: http://www.brunocardoso.org
@@ -271,6 +285,10 @@ N: Scott Michel
E: scottm@aero.org
D: Added STI Cell SPU backend.
+N: Kai Nacke
+E: kai@redstar.de
+D: Support for implicit TLS model used with MS VC runtime
+
N: Takumi Nakamura
E: geek4civic@gmail.com
E: chapuni@hf.rim.or.jp
diff --git a/autoconf/configure.ac b/autoconf/configure.ac
index 0a2c8b69ddd..51f89217a9f 100644
--- a/autoconf/configure.ac
+++ b/autoconf/configure.ac
@@ -838,6 +838,13 @@ AC_ARG_WITH(gcc-toolchain,
AC_DEFINE_UNQUOTED(GCC_INSTALL_PREFIX,"$withval",
[Directory where gcc is installed.])
+AC_ARG_WITH(default-sysroot,
+ AS_HELP_STRING([--with-default-sysroot],
+ [Add --sysroot= to all compiler invocations.]),,
+ withval="")
+AC_DEFINE_UNQUOTED(DEFAULT_SYSROOT,"$withval",
+ [Default to all compiler invocations for --sysroot=.])
+
dnl Allow linking of LLVM with GPLv3 binutils code.
AC_ARG_WITH(binutils-include,
AS_HELP_STRING([--with-binutils-include],
diff --git a/cmake/modules/HandleLLVMOptions.cmake b/cmake/modules/HandleLLVMOptions.cmake
index 3a10a861d67..d10e59a0972 100644
--- a/cmake/modules/HandleLLVMOptions.cmake
+++ b/cmake/modules/HandleLLVMOptions.cmake
@@ -110,9 +110,9 @@ if( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT WIN32 )
endif( LLVM_BUILD_32_BITS )
endif( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT WIN32 )
-if( MSVC_IDE AND ( MSVC90 OR MSVC10 ) )
- # Only Visual Studio 2008 and 2010 officially supports /MP.
- # Visual Studio 2005 do support it but it's experimental there.
+# On Win32 using MS tools, provide an option to set the number of parallel jobs
+# to use.
+if( MSVC_IDE )
set(LLVM_COMPILER_JOBS "0" CACHE STRING
"Number of parallel compiler jobs. 0 means use all processors. Default is 0.")
if( NOT LLVM_COMPILER_JOBS STREQUAL "1" )
diff --git a/configure b/configure
index e87160d75c4..efa80dbeb95 100755
--- a/configure
+++ b/configure
@@ -1442,6 +1442,7 @@ Optional Packages:
--with-c-include-dirs Colon separated list of directories clang will
search for headers
--with-gcc-toolchain Directory where gcc is installed.
+ --with-default-sysroot Add --sysroot= to all compiler invocations.
--with-binutils-include Specify path to binutils/include/ containing
plugin-api.h file for gold plugin.
--with-bug-report-url Specify the URL where bug reports should be
@@ -3802,7 +3803,7 @@ else
llvm_cv_target_os_type="Darwin" ;;
*-*-minix*)
llvm_cv_target_os_type="Minix" ;;
- *-*-freebsd*| *-*-kfreebsd-gnu)
+ *-*-freebsd* | *-*-kfreebsd-gnu)
llvm_cv_target_os_type="FreeBSD" ;;
*-*-openbsd*)
llvm_cv_target_os_type="OpenBSD" ;;
@@ -5583,6 +5584,20 @@ _ACEOF
+# Check whether --with-default-sysroot was given.
+if test "${with_default_sysroot+set}" = set; then
+ withval=$with_default_sysroot;
+else
+ withval=""
+fi
+
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_SYSROOT "$withval"
+_ACEOF
+
+
+
# Check whether --with-binutils-include was given.
if test "${with_binutils_include+set}" = set; then
withval=$with_binutils_include;
@@ -10386,7 +10401,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <GenRegisterNames.inc file for that
architecture. For instance, by
- inspecting lib/Target/X86/X86GenRegisterNames.inc we see that the
- 32-bit register EAX is denoted by 15, and the MMX register
- MM0 is mapped to 48.
+ inspecting lib/Target/X86/X86GenRegisterInfo.inc we see that the
+ 32-bit register EAX is denoted by 43, and the MMX register
+ MM0 is mapped to 65.
Some architectures contain registers that share the same physical location. A
notable example is the X86 platform. For instance, in the X86 architecture,
@@ -1627,7 +1627,7 @@ def : Pat<(i32 imm:$imm),
bits. These physical registers are marked as aliased in LLVM. Given a
particular architecture, you can check which registers are aliased by
inspecting its RegisterInfo.td file. Moreover, the method
- TargetRegisterInfo::getAliasSet(p_reg) returns an array containing
+ MCRegisterInfo::getAliasSet(p_reg) returns an array containing
all the physical registers aliased to the register p_reg.
Physical registers, in LLVM, are grouped in Register Classes.
@@ -3182,7 +3182,7 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2012-03-27 13:25:16 +0200 (Tue, 27 Mar 2012) $
+ Last modified: $Date: 2012-04-15 22:22:36 +0200 (Sun, 15 Apr 2012) $