From cafceaebea0108edd3ff12c25c9cda85b807342a Mon Sep 17 00:00:00 2001
From: Justin Hibbits <jhibbits@FreeBSD.org>
Date: Sat, 20 Jul 2019 18:22:01 +0000
Subject: [PATCH] powerpc/SPE: Enable SPV bit for EFSCFD instruction emulation

EFSCFD (floating point single convert from double) emulation requires saving
the high word of the register, which uses SPE instructions.  Enable the SPE
to avoid an SPV Unavailable exception.

MFC after:	1 week
---
 sys/powerpc/booke/spe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/powerpc/booke/spe.c b/sys/powerpc/booke/spe.c
index 7b24f3b7a75..846d11aaccf 100644
--- a/sys/powerpc/booke/spe.c
+++ b/sys/powerpc/booke/spe.c
@@ -572,6 +572,7 @@ spe_handle_fpdata(struct trapframe *frame)
 			frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
 			break;
 		case EFSCFD:
+			mtmsr(msr | PSL_VEC);
 			spe_explode(&fpemu, &fpemu.fe_f3, DOUBLE,
 			    spe_save_reg_high(rb), frame->fixreg[rb]);
 			result = &fpemu.fe_f3;