mirror of
https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
Add support for the U4 PCI-Express bridge chipset used in late-generation
Powermac G5 systems. MSI and several other things are not presently supported. The U3/U4 internal device support portions of this change were contributed by Andreas Tobler. MFC after: 1 week
This commit is contained in:
Nathan Whitehorn
parent
ed3c664257
commit
ca2c19312e
9 changed files with 1620 additions and 993 deletions
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@ -139,7 +139,8 @@ powerpc/powermac/openpic_macio.c optional powermac pci
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powerpc/powermac/pswitch.c optional powermac pswitch
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powerpc/powermac/pmu.c optional powermac pmu
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powerpc/powermac/smu.c optional powermac smu
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powerpc/powermac/uninorth.c optional powermac pci
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powerpc/powermac/uninorth.c optional powermac
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powerpc/powermac/uninorthpci.c optional powermac pci
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powerpc/powermac/vcoregpio.c optional powermac
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powerpc/powerpc/altivec.c optional aim
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powerpc/powerpc/atomic.S standard
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@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#if defined(__i386__) || defined(__amd64__)
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#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
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#include <machine/intr_machdep.h>
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#endif
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@ -559,7 +559,7 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
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{
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#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
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#if defined(__i386__) || defined(__amd64__)
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#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
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uint64_t addr;
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#endif
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uint32_t val;
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@ -603,7 +603,7 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
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cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
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}
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break;
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#if defined(__i386__) || defined(__amd64__)
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#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
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case PCIY_HT: /* HyperTransport */
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/* Determine HT-specific capability type. */
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val = REG(ptr + PCIR_HT_COMMAND, 2);
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@ -30,6 +30,11 @@
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#define INTR_VECTORS 256
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/*
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* Default base address for MSI messages on PowerPC
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*/
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#define MSI_INTEL_ADDR_BASE 0xfee00000
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extern device_t pic;
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extern device_t pic8259;
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File diff suppressed because it is too large
Load diff
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@ -1,58 +0,0 @@
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/*-
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* Copyright (C) 2008 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_POWERMAC_CPCHTVAR_H_
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#define _POWERPC_POWERMAC_CPCHTVAR_H_
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struct cpcpci_range {
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u_int32_t pci_hi;
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u_int32_t pci_mid;
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u_int32_t pci_lo;
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u_int32_t junk;
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u_int32_t host_hi;
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u_int32_t host_lo;
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u_int32_t size_hi;
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u_int32_t size_lo;
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};
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struct cpcpci_softc {
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device_t sc_dev;
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phandle_t sc_node;
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vm_offset_t sc_data;
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int sc_bus;
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struct cpcpci_range sc_range[6];
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int sc_nrange;
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int sc_iostart;
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struct rman sc_io_rman;
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struct rman sc_mem_rman;
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bus_space_tag_t sc_iot;
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bus_space_tag_t sc_memt;
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bus_dma_tag_t sc_dmat;
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struct ofw_bus_iinfo sc_pci_iinfo;
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};
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#endif /* _POWERPC_POWERMAC_CPCHTVAR_H_ */
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File diff suppressed because it is too large
Load diff
543
sys/powerpc/powermac/uninorthpci.c
Normal file
543
sys/powerpc/powermac/uninorthpci.c
Normal file
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@ -0,0 +1,543 @@
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/*-
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <powerpc/powermac/uninorthvar.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include "pcib_if.h"
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#define UNINORTH_DEBUG 0
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/*
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* Device interface.
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*/
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static int uninorth_probe(device_t);
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static int uninorth_attach(device_t);
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/*
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* Bus interface.
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*/
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static int uninorth_read_ivar(device_t, device_t, int,
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uintptr_t *);
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static struct resource * uninorth_alloc_resource(device_t bus,
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device_t child, int type, int *rid, u_long start,
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u_long end, u_long count, u_int flags);
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static int uninorth_activate_resource(device_t bus, device_t child,
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int type, int rid, struct resource *res);
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/*
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* pcib interface.
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*/
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static int uninorth_maxslots(device_t);
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static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
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u_int, int);
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static void uninorth_write_config(device_t, u_int, u_int, u_int,
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u_int, u_int32_t, int);
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static int uninorth_route_interrupt(device_t, device_t, int);
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/*
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* OFW Bus interface
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*/
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static phandle_t uninorth_get_node(device_t bus, device_t dev);
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/*
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* Local routines.
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*/
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static int uninorth_enable_config(struct uninorth_softc *, u_int,
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u_int, u_int, u_int);
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/*
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* Driver methods.
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*/
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static device_method_t uninorth_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, uninorth_probe),
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DEVMETHOD(device_attach, uninorth_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, uninorth_read_ivar),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_alloc_resource, uninorth_alloc_resource),
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DEVMETHOD(bus_activate_resource, uninorth_activate_resource),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, uninorth_maxslots),
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DEVMETHOD(pcib_read_config, uninorth_read_config),
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DEVMETHOD(pcib_write_config, uninorth_write_config),
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DEVMETHOD(pcib_route_interrupt, uninorth_route_interrupt),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, uninorth_get_node),
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{ 0, 0 }
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};
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static driver_t uninorth_driver = {
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"pcib",
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uninorth_methods,
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sizeof(struct uninorth_softc)
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};
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static devclass_t uninorth_devclass;
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DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
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static int
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uninorth_probe(device_t dev)
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{
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const char *type, *compatible;
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type = ofw_bus_get_type(dev);
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compatible = ofw_bus_get_compat(dev);
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if (type == NULL || compatible == NULL)
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return (ENXIO);
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if (strcmp(type, "pci") != 0)
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return (ENXIO);
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if (strcmp(compatible, "uni-north") == 0) {
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device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
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return (0);
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} else if (strcmp(compatible, "u3-agp") == 0) {
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device_set_desc(dev, "Apple U3 Host-AGP bridge");
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return (0);
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} else if (strcmp(compatible, "u4-pcie") == 0) {
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device_set_desc(dev, "IBM CPC945 PCI Express Root");
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return (0);
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}
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return (ENXIO);
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}
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static int
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uninorth_attach(device_t dev)
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{
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struct uninorth_softc *sc;
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const char *compatible;
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phandle_t node;
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u_int32_t reg[3], busrange[2];
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struct uninorth_range *rp, *io, *mem[2];
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int nmem, i, error;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
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return (ENXIO);
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if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
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return (ENXIO);
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sc->sc_ver = 0;
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compatible = ofw_bus_get_compat(dev);
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if (strcmp(compatible, "u3-agp") == 0)
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sc->sc_ver = 3;
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if (strcmp(compatible, "u4-pcie") == 0)
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sc->sc_ver = 4;
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sc->sc_dev = dev;
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sc->sc_node = node;
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if (sc->sc_ver >= 3) {
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sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
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} else {
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sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
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}
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sc->sc_bus = busrange[0];
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bzero(sc->sc_range, sizeof(sc->sc_range));
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if (sc->sc_ver >= 3) {
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/*
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* On Apple U3 systems, we have an otherwise standard
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* Uninorth controller driving AGP. The one difference
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* is that it uses a new PCI ranges format, so do the
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* translation.
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*/
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struct uninorth_range64 range64[6];
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bzero(range64, sizeof(range64));
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sc->sc_nrange = OF_getprop(node, "ranges", range64,
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sizeof(range64));
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for (i = 0; range64[i].pci_hi != 0; i++) {
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sc->sc_range[i].pci_hi = range64[i].pci_hi;
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sc->sc_range[i].pci_mid = range64[i].pci_mid;
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sc->sc_range[i].pci_lo = range64[i].pci_lo;
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sc->sc_range[i].host = range64[i].host_lo;
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sc->sc_range[i].size_hi = range64[i].size_hi;
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sc->sc_range[i].size_lo = range64[i].size_lo;
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}
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} else {
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sc->sc_nrange = OF_getprop(node, "ranges", sc->sc_range,
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sizeof(sc->sc_range));
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}
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if (sc->sc_nrange == -1) {
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device_printf(dev, "could not get ranges\n");
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return (ENXIO);
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}
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sc->sc_range[6].pci_hi = 0;
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io = NULL;
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nmem = 0;
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for (rp = sc->sc_range; rp->pci_hi != 0; rp++) {
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switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
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case OFW_PCI_PHYS_HI_SPACE_CONFIG:
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break;
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case OFW_PCI_PHYS_HI_SPACE_IO:
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io = rp;
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break;
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case OFW_PCI_PHYS_HI_SPACE_MEM32:
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mem[nmem] = rp;
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nmem++;
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break;
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case OFW_PCI_PHYS_HI_SPACE_MEM64:
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break;
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}
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}
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if (io == NULL) {
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device_printf(dev, "can't find io range\n");
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return (ENXIO);
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}
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sc->sc_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_io_rman.rm_descr = "UniNorth PCI I/O Ports";
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sc->sc_iostart = io->host;
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if (rman_init(&sc->sc_io_rman) != 0 ||
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rman_manage_region(&sc->sc_io_rman, io->pci_lo,
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io->pci_lo + io->size_lo - 1) != 0) {
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panic("uninorth_attach: failed to set up I/O rman");
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}
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if (nmem == 0) {
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device_printf(dev, "can't find mem ranges\n");
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return (ENXIO);
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}
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "UniNorth PCI Memory";
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error = rman_init(&sc->sc_mem_rman);
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if (error) {
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device_printf(dev, "rman_init() failed. error = %d\n", error);
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return (error);
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}
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for (i = 0; i < nmem; i++) {
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error = rman_manage_region(&sc->sc_mem_rman, mem[i]->pci_lo,
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mem[i]->pci_lo + mem[i]->size_lo - 1);
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if (error) {
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device_printf(dev,
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"rman_manage_region() failed. error = %d\n", error);
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return (error);
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}
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}
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ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(cell_t));
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device_add_child(dev, "pci", device_get_unit(dev));
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return (bus_generic_attach(dev));
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}
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static int
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uninorth_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static u_int32_t
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uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int width)
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{
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struct uninorth_softc *sc;
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vm_offset_t caoff;
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sc = device_get_softc(dev);
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caoff = sc->sc_data + (reg & 0x07);
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if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
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switch (width) {
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case 1:
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return (in8rb(caoff));
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break;
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case 2:
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return (in16rb(caoff));
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break;
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case 4:
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return (in32rb(caoff));
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break;
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}
|
||||
}
|
||||
|
||||
return (0xffffffff);
|
||||
}
|
||||
|
||||
static void
|
||||
uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
u_int reg, u_int32_t val, int width)
|
||||
{
|
||||
struct uninorth_softc *sc;
|
||||
vm_offset_t caoff;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
caoff = sc->sc_data + (reg & 0x07);
|
||||
|
||||
if (uninorth_enable_config(sc, bus, slot, func, reg)) {
|
||||
switch (width) {
|
||||
case 1:
|
||||
out8rb(caoff, val);
|
||||
break;
|
||||
case 2:
|
||||
out16rb(caoff, val);
|
||||
break;
|
||||
case 4:
|
||||
out32rb(caoff, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
uninorth_route_interrupt(device_t bus, device_t dev, int pin)
|
||||
{
|
||||
struct uninorth_softc *sc;
|
||||
struct ofw_pci_register reg;
|
||||
uint32_t pintr, mintr;
|
||||
uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
pintr = pin;
|
||||
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
|
||||
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
|
||||
maskbuf))
|
||||
return (mintr);
|
||||
|
||||
/* Maybe it's a real interrupt, not an intpin */
|
||||
if (pin > 4)
|
||||
return (pin);
|
||||
|
||||
device_printf(bus, "could not route pin %d for device %d.%d\n",
|
||||
pin, pci_get_slot(dev), pci_get_function(dev));
|
||||
return (PCI_INVALID_IRQ);
|
||||
}
|
||||
|
||||
static int
|
||||
uninorth_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
||||
{
|
||||
struct uninorth_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = device_get_unit(dev);
|
||||
return (0);
|
||||
case PCIB_IVAR_BUS:
|
||||
*result = sc->sc_bus;
|
||||
return (0);
|
||||
}
|
||||
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static struct resource *
|
||||
uninorth_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct uninorth_softc *sc;
|
||||
struct resource *rv;
|
||||
struct rman *rm;
|
||||
int needactivate;
|
||||
|
||||
needactivate = flags & RF_ACTIVE;
|
||||
flags &= ~RF_ACTIVE;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
|
||||
switch (type) {
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_mem_rman;
|
||||
break;
|
||||
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_io_rman;
|
||||
break;
|
||||
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_alloc_resource(bus, type, rid, start, end, count,
|
||||
flags));
|
||||
|
||||
default:
|
||||
device_printf(bus, "unknown resource request from %s\n",
|
||||
device_get_nameunit(child));
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags, child);
|
||||
if (rv == NULL) {
|
||||
device_printf(bus, "failed to reserve resource for %s\n",
|
||||
device_get_nameunit(child));
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rman_set_rid(rv, *rid);
|
||||
|
||||
if (needactivate) {
|
||||
if (bus_activate_resource(child, type, *rid, rv) != 0) {
|
||||
device_printf(bus,
|
||||
"failed to activate resource for %s\n",
|
||||
device_get_nameunit(child));
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
}
|
||||
|
||||
return (rv);
|
||||
}
|
||||
|
||||
static int
|
||||
uninorth_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *res)
|
||||
{
|
||||
void *p;
|
||||
struct uninorth_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
|
||||
if (type == SYS_RES_IRQ)
|
||||
return (bus_activate_resource(bus, type, rid, res));
|
||||
|
||||
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
|
||||
vm_offset_t start;
|
||||
|
||||
start = (vm_offset_t)rman_get_start(res);
|
||||
/*
|
||||
* For i/o-ports, convert the start address to the
|
||||
* uninorth PCI i/o window
|
||||
*/
|
||||
if (type == SYS_RES_IOPORT)
|
||||
start += sc->sc_iostart;
|
||||
|
||||
if (bootverbose)
|
||||
printf("uninorth mapdev: start %zx, len %ld\n", start,
|
||||
rman_get_size(res));
|
||||
|
||||
p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
|
||||
if (p == NULL)
|
||||
return (ENOMEM);
|
||||
rman_set_virtual(res, p);
|
||||
rman_set_bustag(res, &bs_le_tag);
|
||||
rman_set_bushandle(res, (u_long)p);
|
||||
}
|
||||
|
||||
return (rman_activate_resource(res));
|
||||
}
|
||||
|
||||
static int
|
||||
uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
|
||||
u_int func, u_int reg)
|
||||
{
|
||||
uint32_t cfgval;
|
||||
uint32_t pass;
|
||||
|
||||
if (resource_int_value(device_get_name(sc->sc_dev),
|
||||
device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
|
||||
if (pass == slot)
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Issue type 0 configuration space accesses for the root bus.
|
||||
*
|
||||
* NOTE: On U4, issue only type 1 accesses. There is a secret
|
||||
* PCI Express <-> PCI Express bridge not present in the device tree,
|
||||
* and we need to route all of our configuration space through it.
|
||||
*/
|
||||
if (sc->sc_bus == bus && sc->sc_ver < 4) {
|
||||
/*
|
||||
* No slots less than 11 on the primary bus on U3 and lower
|
||||
*/
|
||||
if (slot < 11)
|
||||
return (0);
|
||||
|
||||
cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
|
||||
} else {
|
||||
cfgval = (bus << 16) | (slot << 11) | (func << 8) |
|
||||
(reg & 0xfc) | 1;
|
||||
}
|
||||
|
||||
/* Set extended register bits on U4 */
|
||||
if (sc->sc_ver == 4)
|
||||
cfgval |= (reg >> 8) << 28;
|
||||
|
||||
do {
|
||||
out32rb(sc->sc_addr, cfgval);
|
||||
} while (in32rb(sc->sc_addr) != cfgval);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
uninorth_get_node(device_t bus, device_t dev)
|
||||
{
|
||||
struct uninorth_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
/* We only have one child, the PCI bus, which needs our own node. */
|
||||
|
||||
return sc->sc_node;
|
||||
}
|
||||
|
||||
|
|
@ -63,16 +63,36 @@ struct uninorth_softc {
|
|||
bus_dma_tag_t sc_dmat;
|
||||
struct ofw_bus_iinfo sc_pci_iinfo;
|
||||
|
||||
int sc_u3;
|
||||
int sc_ver;
|
||||
};
|
||||
|
||||
struct unin_chip_softc {
|
||||
vm_offset_t sc_physaddr;
|
||||
u_int32_t sc_physaddr;
|
||||
vm_offset_t sc_addr;
|
||||
u_int sc_size;
|
||||
u_int32_t sc_size;
|
||||
struct rman sc_mem_rman;
|
||||
int sc_version;
|
||||
};
|
||||
|
||||
/*
|
||||
* Format of a unin reg property entry.
|
||||
*/
|
||||
struct unin_chip_reg {
|
||||
u_int32_t mr_base;
|
||||
u_int32_t mr_size;
|
||||
};
|
||||
|
||||
/*
|
||||
* Per unin device structure.
|
||||
*/
|
||||
struct unin_chip_devinfo {
|
||||
int udi_interrupts[6];
|
||||
int udi_ninterrupts;
|
||||
int udi_base;
|
||||
struct ofw_bus_devinfo udi_obdinfo;
|
||||
struct resource_list udi_resources;
|
||||
};
|
||||
|
||||
/*
|
||||
* Version register
|
||||
*/
|
||||
|
|
@ -81,7 +101,14 @@ struct unin_chip_softc {
|
|||
/*
|
||||
* Clock-control register
|
||||
*/
|
||||
#define UNIN_CLOCKCNTL 0x20
|
||||
#define UNIN_CLOCKCNTL_GMAC 0x2
|
||||
#define UNIN_CLOCKCNTL 0x20
|
||||
#define UNIN_CLOCKCNTL_GMAC 0x2
|
||||
|
||||
/*
|
||||
* Toggle registers
|
||||
*/
|
||||
#define UNIN_TOGGLE_REG 0xe0
|
||||
#define UNIN_MPIC_RESET 0x2
|
||||
#define UNIN_MPIC_OUTPUT_ENABLE 0x4
|
||||
|
||||
#endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */
|
||||
|
|
|
|||
|
|
@ -100,6 +100,16 @@ openpic_attach(device_t dev)
|
|||
sc->sc_bt = rman_get_bustag(sc->sc_memr);
|
||||
sc->sc_bh = rman_get_bushandle(sc->sc_memr);
|
||||
|
||||
/* Reset the PIC */
|
||||
x = openpic_read(sc, OPENPIC_CONFIG);
|
||||
x |= OPENPIC_CONFIG_RESET;
|
||||
openpic_write(sc, OPENPIC_CONFIG, x);
|
||||
|
||||
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
|
||||
powerpc_sync();
|
||||
DELAY(100);
|
||||
}
|
||||
|
||||
x = openpic_read(sc, OPENPIC_FEATURE);
|
||||
switch (x & OPENPIC_FEATURE_VERSION_MASK) {
|
||||
case 1:
|
||||
|
|
|
|||
Loading…
Reference in a new issue