From c82bcdb25e09ab7cc58c399d3bfa9b774797038e Mon Sep 17 00:00:00 2001
From: Ian Lepore <ian@FreeBSD.org>
Date: Mon, 23 Feb 2015 20:09:05 +0000
Subject: [PATCH] There is no reason to do i+dcache writeback and invalidate
 when changing the translation table (this may be left over from armv5 days). 
 It's especially bad to do so using a cache operation that isn't coherent on
 SMP systems.

Submitted by:	Michal Meloun
---
 sys/arm/arm/cpufunc_asm_armv7.S | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index 5dcc1714706..dee9a9a87a7 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -72,11 +72,7 @@ __FBSDID("$FreeBSD$");
 #endif
 
 ENTRY(armv7_setttb)
-	stmdb   sp!, {r0, lr}
- 	bl      _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
- 	ldmia   sp!, {r0, lr}
  	dsb
-				
 	orr 	r0, r0, #PT_ATTR
  	mcr	CP15_TTBR0(r0)
 	isb