Use intr_disable() and intr_restore() instead of frobbing the flags register

directly to disable interrupts.

Reviewed by:	bde (earlier version)
MFC after:	2 weeks

sys/amd64/include/profile.h

@@ -77,17 +77,17 @@
 #error this file needs to be ported to your compiler
 #endif /* !__GNUCLIKE_ASM */
 #else /* !GUPROF */
-#define	MCOUNT_DECL(s)	u_long s;
+#define	MCOUNT_DECL(s)	register_t s;
 #ifdef SMP
 extern int	mcount_lock;
-#define	MCOUNT_ENTER(s)	{ s = read_rflags(); disable_intr(); \
+#define	MCOUNT_ENTER(s)	{ s = intr_disable(); \
  			  while (!atomic_cmpset_acq_int(&mcount_lock, 0, 1)) \
 			  	/* nothing */ ; }
 #define	MCOUNT_EXIT(s)	{ atomic_store_rel_int(&mcount_lock, 0); \
-			  write_rflags(s); }
+			  intr_restore(s); }
 #else
-#define	MCOUNT_ENTER(s)	{ s = read_rflags(); disable_intr(); }
-#define	MCOUNT_EXIT(s)	(write_rflags(s))
+#define	MCOUNT_ENTER(s)	{ s = intr_disable(); }
+#define	MCOUNT_EXIT(s)	(intr_restore(s))
 #endif
 #endif /* GUPROF */
 

sys/i386/i386/elan-mmcr.c

@@ -228,19 +228,18 @@ elan_poll_pps(struct timecounter *tc)
 	static int state;
 	int i;
 	uint16_t u, x, y, z;
-	u_long eflags;
+	register_t saveintr;
 
 	/*
 	 * Grab the HW state as quickly and compactly as we can.  Disable
 	 * interrupts to avoid measuring our interrupt service time on
 	 * hw with quality clock sources.
 	 */
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 	x = *pps_ap[0];	/* state, must be first, see below */
 	y = *pps_ap[1]; /* timer2 */
 	z = *pps_ap[2]; /* timer1 */
-	write_eflags(eflags);
+	intr_restore(saveintr);
 
 	/*
 	 * Order is important here.  We need to check the state of the GPIO

sys/i386/i386/identcpu.c

@@ -1037,12 +1037,11 @@ identblue(void)
 static void
 identifycyrix(void)
 {
-	u_int	eflags;
+	register_t saveintr;
 	int	ccr2_test = 0, dir_test = 0;
 	u_char	ccr2, ccr3;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	ccr2 = read_cyrix_reg(CCR2);
 	write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
@@ -1067,7 +1066,7 @@ identifycyrix(void)
 	else
 		cyrix_did = 0x00ff;		/* Old 486SLC/DLC and TI486SXLC/SXL */
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 /* Update TSC freq with the value indicated by the caller. */

sys/i386/i386/initcpu.c

@@ -116,14 +116,13 @@ u_int	cpu_mxcsr_mask;		/* valid bits in mxcsr */
 static void
 init_bluelightning(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 
 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 	need_post_dma_flush = 1;
 #endif
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() | CR0_CD | CR0_NW);
 	invd();
@@ -144,7 +143,7 @@ init_bluelightning(void)
 	/* Enable caching in CR0. */
 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
 	invd();
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 /*
@@ -153,11 +152,10 @@ init_bluelightning(void)
 static void
 init_486dlc(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_char	ccr0;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 	invd();
 
 	ccr0 = read_cyrix_reg(CCR0);
@@ -189,7 +187,7 @@ init_486dlc(void)
 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
 	invd();
 #endif /* !CYRIX_CACHE_WORKS */
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 
@@ -199,11 +197,10 @@ init_486dlc(void)
 static void
 init_cy486dx(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_char	ccr2;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 	invd();
 
 	ccr2 = read_cyrix_reg(CCR2);
@@ -220,7 +217,7 @@ init_cy486dx(void)
 #endif
 
 	write_cyrix_reg(CCR2, ccr2);
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 
@@ -230,11 +227,10 @@ init_cy486dx(void)
 static void
 init_5x86(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_char	ccr2, ccr3, ccr4, pcr0;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() | CR0_CD | CR0_NW);
 	wbinvd();
@@ -320,29 +316,28 @@ init_5x86(void)
 	/* Lock NW bit in CR0. */
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 #ifdef CPU_I486_ON_386
 /*
  * There are i486 based upgrade products for i386 machines.
- * In this case, BIOS doesn't enables CPU cache.
+ * In this case, BIOS doesn't enable CPU cache.
  */
 static void
 init_i486_on_386(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 
 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 	need_post_dma_flush = 1;
 #endif
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0, NW = 0 */
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 #endif
 
@@ -354,11 +349,10 @@ init_i486_on_386(void)
 static void
 init_6x86(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_char	ccr3, ccr4;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() | CR0_CD | CR0_NW);
 	wbinvd();
@@ -422,7 +416,7 @@ init_6x86(void)
 	/* Lock NW bit in CR0. */
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 #endif /* I486_CPU */
 
@@ -435,11 +429,10 @@ init_6x86(void)
 static void
 init_6x86MX(void)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_char	ccr3, ccr4;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() | CR0_CD | CR0_NW);
 	wbinvd();
@@ -489,7 +482,7 @@ init_6x86MX(void)
 	/* Lock NW bit in CR0. */
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 static void
@@ -513,11 +506,10 @@ static void
 init_mendocino(void)
 {
 #ifdef CPU_PPRO2CELERON
-	u_long	eflags;
+	register_t	saveintr;
 	u_int64_t	bbl_cr_ctl3;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	load_cr0(rcr0() | CR0_CD | CR0_NW);
 	wbinvd();
@@ -541,7 +533,7 @@ init_mendocino(void)
 	}
 
 	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
-	write_eflags(eflags);
+	intr_restore(saveintr);
 #endif /* CPU_PPRO2CELERON */
 }
 
@@ -842,10 +834,9 @@ enable_K6_wt_alloc(void)
 {
 	quad_t	size;
 	u_int64_t	whcr;
-	u_long	eflags;
+	register_t	saveintr;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 	wbinvd();
 
 #ifdef CPU_DISABLE_CACHE
@@ -895,7 +886,7 @@ enable_K6_wt_alloc(void)
 #endif
 	wrmsr(0x0c0000082, whcr);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 
 void
@@ -903,10 +894,9 @@ enable_K6_2_wt_alloc(void)
 {
 	quad_t	size;
 	u_int64_t	whcr;
-	u_long	eflags;
+	register_t	saveintr;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 	wbinvd();
 
 #ifdef CPU_DISABLE_CACHE
@@ -956,7 +946,7 @@ enable_K6_2_wt_alloc(void)
 #endif
 	wrmsr(0x0c0000082, whcr);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 }
 #endif /* I585_CPU && CPU_WT_ALLOC */
 
@@ -966,15 +956,14 @@ enable_K6_2_wt_alloc(void)
 
 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 {
-	u_long	eflags;
+	register_t saveintr;
 	u_int	cr0;
 	u_char	ccr1, ccr2, ccr3;
 	u_char	ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
 
 	cr0 = rcr0();
 	if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-		eflags = read_eflags();
-		disable_intr();
+		saveintr = intr_disable();
 
 
 		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
@@ -992,7 +981,7 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 				pcr0 = read_cyrix_reg(PCR0);
 			write_cyrix_reg(CCR3, ccr3);		/* Restore CCR3. */
 		}
-		write_eflags(eflags);
+		intr_restore(saveintr);
 
 		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
 			printf("CCR0=%x, ", (u_int)ccr0);

sys/i386/i386/longrun.c

@@ -84,12 +84,11 @@ static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
 static u_int
 tmx86_get_longrun_mode(void)
 {
-	u_long		eflags;
+	register_t	saveintr;
 	union msrinfo	msrinfo;
 	u_int		low, high, flags, mode;
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
 	low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
@@ -105,40 +104,38 @@ tmx86_get_longrun_mode(void)
 	}
 	mode = LONGRUN_MODE_UNKNOWN;
 out:
-	write_eflags(eflags);
+	intr_restore(saveintr);
 	return (mode);
 }
 
 static u_int
 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
 {
-	u_long		eflags;
+	register_t	saveintr;
 	u_int		regs[4];
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	do_cpuid(0x80860007, regs);
 	*frequency = regs[0];
 	*voltage = regs[1];
 	*percentage = regs[2];
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 	return (1);
 }
 
 static u_int
 tmx86_set_longrun_mode(u_int mode)
 {
-	u_long		eflags;
+	register_t	saveintr;
 	union msrinfo	msrinfo;
 
 	if (mode >= LONGRUN_MODE_UNKNOWN) {
 		return (0);
 	}
 
-	eflags = read_eflags();
-	disable_intr();
+	saveintr = intr_disable();
 
 	/* Write LongRun mode values to Model Specific Register. */
 	msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
@@ -153,7 +150,7 @@ tmx86_set_longrun_mode(u_int mode)
 	msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
 	wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
 
-	write_eflags(eflags);
+	intr_restore(saveintr);
 	return (1);
 }
 

sys/i386/include/profile.h

@@ -77,17 +77,17 @@
 #error
 #endif /* !__GNUCLIKE_ASM */
 #else /* !GUPROF */
-#define	MCOUNT_DECL(s)	u_long s;
+#define	MCOUNT_DECL(s)	register_t s;
 #ifdef SMP
 extern int	mcount_lock;
-#define	MCOUNT_ENTER(s)	{ s = read_eflags(); disable_intr(); \
+#define	MCOUNT_ENTER(s)	{ s = intr_disable(); \
  			  while (!atomic_cmpset_acq_int(&mcount_lock, 0, 1)) \
 			  	/* nothing */ ; }
 #define	MCOUNT_EXIT(s)	{ atomic_store_rel_int(&mcount_lock, 0); \
-			  write_eflags(s); }
+			  intr_restore(s); }
 #else
-#define	MCOUNT_ENTER(s)	{ s = read_eflags(); disable_intr(); }
-#define	MCOUNT_EXIT(s)	(write_eflags(s))
+#define	MCOUNT_ENTER(s)	{ s = intr_disable(); }
+#define	MCOUNT_EXIT(s)	(intr_restore(s))
 #endif
 #endif /* GUPROF */