diff --git a/sys/mips/atheros/ar71xx_setup.c b/sys/mips/atheros/ar71xx_setup.c index 000a426abd4..9a405fe6642 100644 --- a/sys/mips/atheros/ar71xx_setup.c +++ b/sys/mips/atheros/ar71xx_setup.c @@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #define AR71XX_SYS_TYPE_LEN 128 @@ -105,6 +106,27 @@ ar71xx_detect_sys_type(void) } break; + case REV_ID_MAJOR_AR7240: + ar71xx_soc = AR71XX_SOC_AR7240; + chip = "7240"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7241: + ar71xx_soc = AR71XX_SOC_AR7241; + chip = "7241"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + + case REV_ID_MAJOR_AR7242: + ar71xx_soc = AR71XX_SOC_AR7242; + chip = "7242"; + ar71xx_cpu_ops = &ar724x_chip_def; + rev = (id & AR724X_REV_ID_REVISION_MASK); + break; + case REV_ID_MAJOR_AR913X: minor = id & AR91XX_REV_ID_MINOR_MASK; rev = id >> AR91XX_REV_ID_REVISION_SHIFT; diff --git a/sys/mips/atheros/ar71xxreg.h b/sys/mips/atheros/ar71xxreg.h index f4772a8d20c..62a3737c920 100644 --- a/sys/mips/atheros/ar71xxreg.h +++ b/sys/mips/atheros/ar71xxreg.h @@ -256,6 +256,9 @@ #define AR71XX_REV_ID_REVISION_MASK 0x3 #define AR71XX_REV_ID_REVISION_SHIFT 2 +/* AR724X chipset revision details */ +#define AR724X_REV_ID_REVISION_MASK 0x3 + /* AR91XX chipset revision details */ #define AR91XX_REV_ID_MINOR_MASK 0x3 #define AR91XX_REV_ID_MINOR_AR9130 0x0 diff --git a/sys/mips/atheros/ar724x_chip.c b/sys/mips/atheros/ar724x_chip.c new file mode 100644 index 00000000000..450dd19e942 --- /dev/null +++ b/sys/mips/atheros/ar724x_chip.c @@ -0,0 +1,165 @@ +/*- + * Copyright (c) 2010 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +static void +ar724x_chip_detect_mem_size(void) +{ +} + +static void +ar724x_chip_detect_sys_frequency(void) +{ + uint32_t pll; + uint32_t freq; + uint32_t div; + + pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); + + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * AR724X_BASE_FREQ; + + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); + freq *= div; + + u_ar71xx_cpu_freq = freq; + + div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + u_ar71xx_ddr_freq = freq / div; + + div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; + u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; +} + +static void +ar724x_chip_device_stop(uint32_t mask) +{ + uint32_t mask_inv, reg; + + mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; + reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); + reg |= mask; + reg &= ~mask_inv; + ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); +} + +static void +ar724x_chip_device_start(uint32_t mask) +{ + uint32_t mask_inv, reg; + + mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; + reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); + reg &= ~mask; + reg |= mask_inv; + ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); +} + +static int +ar724x_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); + return ((reg & mask) == mask); +} + +static void +ar724x_chip_set_pll_ge0(int speed) +{ +} + +static void +ar724x_chip_set_pll_ge1(int speed) +{ +} + +static void +ar724x_chip_ddr_flush_ge0(void) +{ +} + +static void +ar724x_chip_ddr_flush_ge1(void) +{ +} + +static uint32_t +ar724x_chip_get_eth_pll(unsigned int mac, int speed) +{ + return 0; +} + +struct ar71xx_cpu_def ar724x_chip_def = { + &ar724x_chip_detect_mem_size, + &ar724x_chip_detect_sys_frequency, + &ar724x_chip_device_stop, + &ar724x_chip_device_start, + &ar724x_chip_device_stopped, + &ar724x_chip_set_pll_ge0, + &ar724x_chip_set_pll_ge1, + &ar724x_chip_ddr_flush_ge0, + &ar724x_chip_ddr_flush_ge1, + &ar724x_chip_get_eth_pll, + NULL, /* ar71xx_chip_irq_flush_ip2 */ + NULL /* ar71xx_chip_init_usb_peripheral */ +}; diff --git a/sys/mips/atheros/ar724x_chip.h b/sys/mips/atheros/ar724x_chip.h new file mode 100644 index 00000000000..11b30b7a217 --- /dev/null +++ b/sys/mips/atheros/ar724x_chip.h @@ -0,0 +1,34 @@ +/*- + * Copyright (c) 2010 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef __AR724X_CHIP_H__ +#define __AR724X_CHIP_H__ + +extern struct ar71xx_cpu_def ar724x_chip_def; + +#endif diff --git a/sys/mips/atheros/ar724xreg.h b/sys/mips/atheros/ar724xreg.h index 53faa78294b..ec7ef1552c0 100644 --- a/sys/mips/atheros/ar724xreg.h +++ b/sys/mips/atheros/ar724xreg.h @@ -47,6 +47,9 @@ #define AR724X_BASE_FREQ 5000000 +#define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c +#define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3) + /* XXX so USB requires different init code? -adrian */ #define AR7240_OHCI_BASE 0x1b000000 #define AR7240_OHCI_SIZE 0x01000000 diff --git a/sys/mips/atheros/files.ar71xx b/sys/mips/atheros/files.ar71xx index c8d00e55bd8..6b0051574a4 100644 --- a/sys/mips/atheros/files.ar71xx +++ b/sys/mips/atheros/files.ar71xx @@ -17,4 +17,5 @@ mips/mips/intr_machdep.c standard mips/mips/tick.c standard mips/atheros/ar71xx_setup.c standard mips/atheros/ar71xx_chip.c standard +mips/atheros/ar724x_chip.c standard mips/atheros/ar91xx_chip.c standard