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https://github.com/opnsense/src.git
synced 2026-06-08 16:22:46 -04:00
- Consolidate duplicated code for reading and sizing BARs and writing base
addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
This commit is contained in:
John Baldwin
parent
b3096a0430
commit
bfee0576cb
1 changed files with 98 additions and 121 deletions
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@ -77,12 +77,11 @@ static int pci_mapsize(uint64_t testval);
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static int pci_maprange(uint64_t mapreg);
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static void pci_fixancient(pcicfgregs *cfg);
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static int pci_porten(device_t pcib, int b, int s, int f);
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static int pci_memen(device_t pcib, int b, int s, int f);
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static int pci_porten(device_t dev);
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static int pci_memen(device_t dev);
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static void pci_assign_interrupt(device_t bus, device_t dev,
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int force_route);
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static int pci_add_map(device_t pcib, device_t bus, device_t dev,
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int b, int s, int f, int reg,
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static int pci_add_map(device_t bus, device_t dev, int reg,
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struct resource_list *rl, int force, int prefetch);
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static int pci_probe(device_t dev);
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static int pci_attach(device_t dev);
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@ -2258,51 +2257,36 @@ pci_print_verbose(struct pci_devinfo *dinfo)
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}
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static int
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pci_porten(device_t pcib, int b, int s, int f)
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pci_porten(device_t dev)
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{
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return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
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& PCIM_CMD_PORTEN) != 0;
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return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
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}
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static int
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pci_memen(device_t pcib, int b, int s, int f)
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pci_memen(device_t dev)
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{
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return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
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& PCIM_CMD_MEMEN) != 0;
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return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
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}
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/*
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* Add a resource based on a pci map register. Return 1 if the map
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* register is a 32bit map register or 2 if it is a 64bit register.
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*/
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static int
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pci_add_map(device_t pcib, device_t bus, device_t dev,
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int b, int s, int f, int reg, struct resource_list *rl, int force,
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int prefetch)
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static void
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pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
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{
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pci_addr_t base, map;
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pci_addr_t start, end, count;
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uint8_t ln2size;
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uint8_t ln2range;
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uint32_t testval;
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pci_addr_t map, testval;
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int ln2range;
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uint16_t cmd;
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int type;
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int barlen;
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struct resource *res;
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map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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map = pci_read_config(dev, reg, 4);
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ln2range = pci_maprange(map);
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if (ln2range == 64)
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map |= (uint64_t)PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) <<
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32;
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map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
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/*
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* Disable decoding via the command register before
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* determining the BAR's length since we will be placing it in
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* a weird state.
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*/
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND,
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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pci_write_config(dev, PCIR_COMMAND,
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cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
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/*
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@ -2310,29 +2294,65 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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* log_2(size) bits of the BAR will stick as 0 when we read
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* the value back.
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*/
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
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testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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pci_write_config(dev, reg, 0xffffffff, 4);
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testval = pci_read_config(dev, reg, 4);
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if (ln2range == 64) {
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg + 4, 0xffffffff, 4);
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testval |= (uint64_t)PCIB_READ_CONFIG(pcib, b, s, f, reg + 4,
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4) << 32;
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pci_write_config(dev, reg + 4, 0xffffffff, 4);
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testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
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}
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/* Restore the BAR and command register. */
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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/*
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* Restore the original value of the BAR. We may have reprogrammed
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* the BAR of the low-level console device and when booting verbose,
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* we need the console device addressable.
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*/
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pci_write_config(dev, reg, map, 4);
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if (ln2range == 64)
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PCIB_WRITE_CONFIG(pcib, b, s, f, reg + 4, map >> 32, 4);
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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pci_write_config(dev, reg + 4, map >> 32, 4);
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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*mapp = map;
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*testvalp = testval;
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}
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static void
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pci_write_bar(device_t dev, int reg, pci_addr_t base)
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{
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pci_addr_t map;
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int ln2range;
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map = pci_read_config(dev, reg, 4);
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ln2range = pci_maprange(map);
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pci_write_config(dev, reg, base, 4);
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if (ln2range == 64)
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pci_write_config(dev, reg + 4, base >> 32, 4);
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}
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/*
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* Add a resource based on a pci map register. Return 1 if the map
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* register is a 32bit map register or 2 if it is a 64bit register.
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*/
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static int
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pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
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int force, int prefetch)
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{
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pci_addr_t base, map, testval;
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pci_addr_t start, end, count;
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int barlen, maprange, mapsize, type;
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uint16_t cmd;
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struct resource *res;
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pci_read_bar(dev, reg, &map, &testval);
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if (PCI_BAR_MEM(map)) {
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type = SYS_RES_MEMORY;
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if (map & PCIM_BAR_MEM_PREFETCH)
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prefetch = 1;
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} else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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mapsize = pci_mapsize(testval);
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base = pci_mapbase(map);
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barlen = ln2range == 64 ? 2 : 1;
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maprange = pci_maprange(map);
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barlen = maprange == 64 ? 2 : 1;
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/*
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* For I/O registers, if bottom bit is set, and the next bit up
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@ -2343,16 +2363,16 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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*/
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if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
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return (barlen);
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if ((type == SYS_RES_MEMORY && ln2size < 4) ||
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(type == SYS_RES_IOPORT && ln2size < 2))
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if ((type == SYS_RES_MEMORY && mapsize < 4) ||
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(type == SYS_RES_IOPORT && mapsize < 2))
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return (barlen);
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if (bootverbose) {
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printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
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reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
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if (type == SYS_RES_IOPORT && !pci_porten(dev))
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printf(", port disabled\n");
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else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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else if (type == SYS_RES_MEMORY && !pci_memen(dev))
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printf(", memory disabled\n");
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else
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printf(", enabled\n");
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@ -2374,7 +2394,8 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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if ((u_long)base != base) {
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device_printf(bus,
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"pci%d:%d:%d:%d bar %#x too many address bits",
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pci_get_domain(dev), b, s, f, reg);
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pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
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pci_get_function(dev), reg);
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return (barlen);
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}
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@ -2387,30 +2408,30 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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*/
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if (pci_enable_io_modes) {
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/* Turn on resources that have been left off by a lazy BIOS */
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_PORTEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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}
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
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cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
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if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_MEMEN;
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PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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}
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} else {
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if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
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if (type == SYS_RES_IOPORT && !pci_porten(dev))
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return (barlen);
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if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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if (type == SYS_RES_MEMORY && !pci_memen(dev))
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return (barlen);
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}
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count = 1 << ln2size;
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count = 1 << mapsize;
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if (base == 0 || base == pci_mapbase(testval)) {
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start = 0; /* Let the parent decide. */
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end = ~0ULL;
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} else {
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start = base;
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end = base + (1 << ln2size) - 1;
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end = base + (1 << mapsize) - 1;
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}
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resource_list_add(rl, type, reg, start, end, count);
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@ -2435,9 +2456,7 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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start = rman_get_start(res);
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rman_set_device(res, bus);
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}
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pci_write_config(dev, reg, start, 4);
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if (ln2range == 64)
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pci_write_config(dev, reg + 4, start >> 32, 4);
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pci_write_bar(dev, reg, start);
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return (barlen);
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}
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@ -2449,8 +2468,8 @@ pci_add_map(device_t pcib, device_t bus, device_t dev,
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* addressing mode.
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*/
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static void
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pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
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int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
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pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
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uint32_t prefetchmask)
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{
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struct resource *r;
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int rid, type, progif;
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@ -2468,9 +2487,9 @@ pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
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progif = pci_read_config(dev, PCIR_PROGIF, 1);
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type = SYS_RES_IOPORT;
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if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
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prefetchmask & (1 << 0));
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
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prefetchmask & (1 << 1));
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} else {
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rid = PCIR_BAR(0);
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@ -2485,9 +2504,9 @@ pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
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rman_set_device(r, bus);
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}
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if (progif & PCIP_STORAGE_IDE_MODESEC) {
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
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prefetchmask & (1 << 2));
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
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prefetchmask & (1 << 3));
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} else {
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rid = PCIR_BAR(2);
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@ -2501,9 +2520,9 @@ pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
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1, 0);
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rman_set_device(r, bus);
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}
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
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prefetchmask & (1 << 4));
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pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
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pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
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prefetchmask & (1 << 5));
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}
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@ -2558,18 +2577,11 @@ pci_assign_interrupt(device_t bus, device_t dev, int force_route)
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void
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pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
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{
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device_t pcib;
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct resource_list *rl = &dinfo->resources;
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struct pci_quirk *q;
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int b, i, f, s;
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pcib = device_get_parent(bus);
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b = cfg->bus;
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s = cfg->slot;
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f = cfg->func;
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int i;
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/* ATA devices needs special map treatment */
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if ((pci_get_class(dev) == PCIC_STORAGE) &&
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@ -2577,11 +2589,11 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
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((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
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(!pci_read_config(dev, PCIR_BAR(0), 4) &&
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!pci_read_config(dev, PCIR_BAR(2), 4))) )
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pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
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pci_ata_maps(bus, dev, rl, force, prefetchmask);
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else
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for (i = 0; i < cfg->nummaps;)
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i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
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rl, force, prefetchmask & (1 << i));
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i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
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prefetchmask & (1 << i));
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/*
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* Add additional, quirked resources.
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@ -2589,8 +2601,7 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
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for (q = &pci_quirks[0]; q->devid; q++) {
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if (q->devid == ((cfg->device << 16) | cfg->vendor)
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&& q->type == PCI_QUIRK_MAP_REG)
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pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
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force, 0);
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pci_add_map(bus, dev, q->arg1, rl, force, 0);
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}
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if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
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@ -3424,8 +3435,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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struct resource_list_entry *rle;
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struct resource *res;
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pci_addr_t map, testval;
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uint16_t cmd;
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int maprange, mapsize;
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int mapsize;
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/*
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* Weed out the bogons, and figure out how large the BAR/map
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@ -3435,38 +3445,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
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* it fails here, that other code is broken.
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*/
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res = NULL;
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map = pci_read_config(child, *rid, 4);
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maprange = pci_maprange(map);
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if (maprange == 64)
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map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
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/*
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* Disable decoding via the command register before
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* determining the BAR's length since we will be placing it in
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* a weird state.
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*/
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cmd = pci_read_config(child, PCIR_COMMAND, 2);
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pci_write_config(child, PCIR_COMMAND,
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cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
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/* Determine the BAR's length. */
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pci_write_config(child, *rid, 0xffffffff, 4);
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testval = pci_read_config(child, *rid, 4);
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if (maprange == 64) {
|
||||
pci_write_config(child, *rid + 4, 0xffffffff, 4);
|
||||
testval |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) <<
|
||||
32;
|
||||
}
|
||||
|
||||
/*
|
||||
* Restore the original value of the BAR. We may have reprogrammed
|
||||
* the BAR of the low-level console device and when booting verbose,
|
||||
* we need the console device addressable.
|
||||
*/
|
||||
pci_write_config(child, *rid, map, 4);
|
||||
if (maprange == 64)
|
||||
pci_write_config(child, *rid + 4, map >> 32, 4);
|
||||
pci_write_config(child, PCIR_COMMAND, cmd, 2);
|
||||
pci_read_bar(child, *rid, &map, &testval);
|
||||
|
||||
/* Ignore a BAR with a base of 0. */
|
||||
if (pci_mapbase(testval) == 0)
|
||||
|
|
@ -3491,6 +3470,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
|
|||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* For real BARs, we need to override the size that
|
||||
* the driver requests, because that's what the BAR
|
||||
|
|
@ -3531,9 +3511,7 @@ pci_alloc_map(device_t dev, device_t child, int type, int *rid,
|
|||
"Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
|
||||
count, *rid, type, rman_get_start(res));
|
||||
map = rman_get_start(res);
|
||||
pci_write_config(child, *rid, map, 4);
|
||||
if (maprange == 64)
|
||||
pci_write_config(child, *rid + 4, map >> 32, 4);
|
||||
pci_write_bar(child, *rid, map);
|
||||
out:;
|
||||
return (res);
|
||||
}
|
||||
|
|
@ -3698,8 +3676,7 @@ pci_delete_resource(device_t dev, device_t child, int type, int rid)
|
|||
switch (type) {
|
||||
case SYS_RES_IOPORT:
|
||||
case SYS_RES_MEMORY:
|
||||
/* XXX: 64-bit BARs? */
|
||||
pci_write_config(child, rid, 0, 4);
|
||||
pci_write_bar(child, rid, 0);
|
||||
break;
|
||||
}
|
||||
bus_release_resource(dev, type, rid, rle->res);
|
||||
|
|
|
|||
Loading…
Reference in a new issue