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Partial revert r185756.

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It seems that RTL8168D and RTL8102EL requires additional settle
time to complete RL_PHYAR register write. Accessing RL_PHYAR
register right after the write causes errors for subsequent PHY
register accesses.

Tested by:	george at luckytele dot com,
		Steve Wills < STEVE at stevenwills dot com >
This commit is contained in:
Pyun YongHyeon 2009-03-31 03:29:05 +00:00
parent 2b5b95c278
commit bd9bede57a
1 changed files with 2 additions and 0 deletions
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2
sys/dev/re/if_re.c
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@ -419,6 +419,7 @@ re_gmii_readreg(device_t dev, int phy, int reg)
}
CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
DELAY(1000);
for (i = 0; i < RL_PHY_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);
@ -446,6 +447,7 @@ re_gmii_writereg(device_t dev, int phy, int reg, int data)
CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
(data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
DELAY(1000);
for (i = 0; i < RL_PHY_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);