mirror of
https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
arm64: Fix the TCR_EPD0 definition
Sponsored by: Arm Ltd (cherry picked from commit 8f26d01f53316c055cc1116eb56ff438da50d831)
This commit is contained in:
parent
a9600913b4
commit
bcedcc2aad
1 changed files with 1 additions and 1 deletions
|
|
@ -2167,7 +2167,7 @@
|
|||
#define TCR_IRGN0_SHIFT 8
|
||||
#define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT)
|
||||
#define TCR_EPD0_SHIFT 7
|
||||
#define TCR_EPD0 (1UL << TCR_EPD1_SHIFT)
|
||||
#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT)
|
||||
/* Bit 6 is reserved */
|
||||
#define TCR_T0SZ_SHIFT 0
|
||||
#define TCR_T0SZ_MASK 0x3f
|
||||
|
|
|
|||
Loading…
Reference in a new issue