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Improve DWC OTG USB host side support for isochronous FULL and HIGH

Browse source 
speed data traffic going directly to a USB device or through a
so-called USB transaction translator.

Add checks that we are not overusing the TX FIFO.

MFC after:	2 weeks
This commit is contained in:
Hans Petter Selasky 2014-05-05 11:50:52 +00:00
parent c7c7d7d0f0
commit bc99048296
3 changed files with 771 additions and 264 deletions
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995
sys/dev/usb/controller/dwc_otg.c
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File diff suppressed because it is too large Load diff

30
sys/dev/usb/controller/dwc_otg.h
View file

@ -57,23 +57,24 @@ struct dwc_otg_td {
uint32_t hcsplt; /* HOST CFG */
uint16_t max_packet_size; /* packet_size */
uint16_t npkt;
uint8_t max_packet_count; /* packet_count */
uint8_t errcnt;
uint8_t tmr_res;
uint8_t tmr_val;
uint8_t curr_frame;
uint8_t ep_no;
uint8_t channel;
uint8_t tt_index; /* TT data */
uint8_t tt_start_slot; /* TT data */
uint8_t tt_complete_slot; /* TT data */
uint8_t tt_xactpos; /* TT data */
uint8_t state;
#define DWC_CHAN_ST_START 0
#define DWC_CHAN_ST_WAIT_ANE 1
#define DWC_CHAN_ST_WAIT_S_ANE 2
#define DWC_CHAN_ST_WAIT_C_ANE 3
#define DWC_CHAN_ST_RX_PKT 4
#define DWC_CHAN_ST_RX_SPKT 5
#define DWC_CHAN_ST_RX_SPKT_SYNC 6
#define DWC_CHAN_ST_TX_PKT 4
#define DWC_CHAN_ST_TX_CPKT 5
#define DWC_CHAN_ST_TX_PKT_SYNC 6
#define DWC_CHAN_ST_WAIT_C_PKT 4
#define DWC_CHAN_ST_TX_PKT_ISOC 5
#define DWC_CHAN_ST_TX_WAIT_ISOC 6
uint8_t error:1;
uint8_t error_any:1;
uint8_t error_stall:1;
@ -84,6 +85,7 @@ struct dwc_otg_td {
uint8_t set_toggle:1;
uint8_t got_short:1;
uint8_t did_nak:1;
uint8_t tt_scheduled:1;
};
struct dwc_otg_std_temp {
@ -103,6 +105,7 @@ struct dwc_otg_std_temp {
uint8_t setup_alt_next;
uint8_t did_stall;
uint8_t bulk_or_control;
uint8_t tt_index;
};
struct dwc_otg_config_desc {
@ -143,11 +146,18 @@ struct dwc_otg_profile {
struct dwc_otg_chan_state {
uint32_t hcint;
uint32_t tx_size;
uint8_t wait_sof;
uint8_t allocated;
uint8_t suspended;
};
struct dwc_otg_tt_info {
uint16_t bytes_used;
uint8_t slot_index;
uint8_t dummy;
};
struct dwc_otg_softc {
struct usb_bus sc_bus;
union dwc_otg_hub_temp sc_hub_temp;
@ -163,9 +173,11 @@ struct dwc_otg_softc {
bus_space_handle_t sc_io_hdl;
uint32_t sc_rx_bounce_buffer[1024 / 4];
uint32_t sc_tx_bounce_buffer[(512 * DWC_OTG_MAX_TXP) / 4];
uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4];
uint32_t sc_fifo_size;
uint32_t sc_tx_max_size;
uint32_t sc_tx_cur_size;
uint32_t sc_irq_mask;
uint32_t sc_last_rx_status;
uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS];
@ -174,7 +186,9 @@ struct dwc_otg_softc {
uint32_t sc_tmr_val;
uint32_t sc_hprt_val;
struct dwc_otg_tt_info sc_tt_info[DWC_OTG_MAX_DEVICES];
uint16_t sc_active_rx_ep;
uint16_t sc_last_frame_num;
uint8_t sc_timer_active;
uint8_t sc_dev_ep_max;

10
sys/dev/usb/controller/dwc_otgreg.h
View file

@ -536,6 +536,11 @@
#define HCSPLT_COMPSPLT (1<<16)
#define HCSPLT_XACTPOS_SHIFT 14
#define HCSPLT_XACTPOS_MASK 0x0000c000
#define HCSPLT_XACTPOS_MIDDLE 0
#define HCSPLT_XACTPOS_LAST 1
#define HCSPLT_XACTPOS_BEGIN 2
#define HCSPLT_XACTPOS_ALL 3
#define HCSPLT_XACTLEN_MAX 188 /* bytes */
#define HCSPLT_HUBADDR_SHIFT 7
#define HCSPLT_HUBADDR_MASK 0x00003f80
#define HCSPLT_PRTADDR_SHIFT 0
@ -545,6 +550,11 @@
(HCINT_BBLERR | HCINT_XACTERR)
#define HCINT_RETRY \
(HCINT_DATATGLERR | HCINT_FRMOVRUN | HCINT_NAK)
#define HCINT_DEFAULT_MASK \
(HCINT_STALL | HCINT_BBLERR | \
HCINT_XACTERR | HCINT_NAK | HCINT_ACK | HCINT_NYET | \
HCINT_CHHLTD | HCINT_FRMOVRUN | \
HCINT_DATATGLERR)
#define HCINT_SOFTWARE_ONLY (1<<20) /* BSD only */
#define HCINT_DATATGLERR (1<<10)