From ba079c0d9fbf587fa4da60456e0f7c6c11f013d2 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Thu, 25 Sep 2003 23:36:41 +0000 Subject: [PATCH] aic79xx_pci.c: aic7xxx_pci.c: When performing our register test, be careful to avoid resetting the chip when pausing the controller. The test reads the HCNTRL register and then writes it back with the PAUSE bit explicitly set. If the last write to the controller before our probe is to reset it, the CHIPRST bit will still be set, so we must mask it off before the PAUSE operation. On some chip versions, we cannot access registers for a few 100us after a reset, so this inadvertant reset was causing PCI errors to occur on the read to check for paused status. Submitted by: gibbs --- sys/dev/aic7xxx/aic79xx_pci.c | 6 ++++-- sys/dev/aic7xxx/aic7xxx_pci.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/sys/dev/aic7xxx/aic79xx_pci.c b/sys/dev/aic7xxx/aic79xx_pci.c index 1996cc77e9f..0523ed60f42 100644 --- a/sys/dev/aic7xxx/aic79xx_pci.c +++ b/sys/dev/aic7xxx/aic79xx_pci.c @@ -38,7 +38,7 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGES. * - * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#76 $ + * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ */ #include @@ -453,8 +453,10 @@ ahd_pci_test_register_access(struct ahd_softc *ahd) * or read prefetching could be initiated by the * CPU or host bridge. Our device does not support * either, so look for data corruption and/or flaged - * PCI errors. + * PCI errors. First pause without causing another + * chip reset. */ + hcntrl &= ~CHIPRST; ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); while (ahd_is_paused(ahd) == 0) ; diff --git a/sys/dev/aic7xxx/aic7xxx_pci.c b/sys/dev/aic7xxx/aic7xxx_pci.c index 9e1e81e3dd0..49ba1f2b07a 100644 --- a/sys/dev/aic7xxx/aic7xxx_pci.c +++ b/sys/dev/aic7xxx/aic7xxx_pci.c @@ -39,7 +39,7 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGES. * - * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $ + * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#72 $ */ #include @@ -1285,8 +1285,10 @@ ahc_pci_test_register_access(struct ahc_softc *ahc) * or read prefetching could be initiated by the * CPU or host bridge. Our device does not support * either, so look for data corruption and/or flagged - * PCI errors. + * PCI errors. First pause without causing another + * chip reset. */ + hcntrl &= ~CHIPRST; ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); while (ahc_is_paused(ahc) == 0) ;