mirror of
https://github.com/opnsense/src.git
synced 2026-06-09 08:43:19 -04:00
Map the second CS of the compact flash too. This allow us access to
the alternate status and the control registers. Remove the local version of ata_reset. Add support for the ADI Pronghorn Metro boards. They use CS3 and CS4 instead of Avila's CS1 and CS2. OKed by: sam, cognet
This commit is contained in:
John Hay
parent
626d3f9f41
commit
b4078e515f
1 changed files with 82 additions and 113 deletions
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@ -32,9 +32,12 @@ __FBSDID("$FreeBSD$");
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/*
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* Compact Flash Support for the Avila Gateworks XScale boards.
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* There are 1 or 2 optional CF slots operated in "True IDE" mode.
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* Registers are on the Expansion Bus connected to CS1. Interrupts
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* are tied to GPIO pin 12. No DMA, just PIO.
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* The CF slot is operated in "True IDE" mode. Registers are on
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* the Expansion Bus connected to CS1 and CS2. Interrupts are
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* tied to GPIO pin 12. No DMA, just PIO.
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*
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* The ADI Pronghorn Metro is very similar. It use CS3 and CS4 and
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* GPIO pin 0 for interrupts.
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*
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* See also http://www.intel.com/design/network/applnots/302456.htm.
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*/
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@ -64,17 +67,24 @@ __FBSDID("$FreeBSD$");
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#include <dev/ata/ata-all.h>
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#include <ata_if.h>
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#define AVILA_IDE_GPIN 12 /* GPIO pin # */
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#define AVILA_IDE_IRQ IXP425_INT_GPIO_12
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#define AVILA_IDE_CTRL 0x1e /* control register */
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#define AVILA_IDE_GPIN 12 /* GPIO pin # */
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#define AVILA_IDE_IRQ IXP425_INT_GPIO_12
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#define AVILA_IDE_CTRL 0x06 /* control register */
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#define PRONGHORN_IDE_GPIN 0 /* GPIO pin # */
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#define PRONGHORN_IDE_IRQ IXP425_INT_GPIO_0
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#define PRONGHORN_IDE_CNTRL 0x06 /* control register */
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struct ata_avila_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_exp_ioh; /* Exp Bus config registers */
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bus_space_handle_t sc_ioh; /* CS1 data registers */
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bus_space_handle_t sc_ioh; /* CS1/3 data registers */
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bus_space_handle_t sc_alt_ioh; /* CS2/4 data registers */
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struct bus_space sc_expbus_tag;
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struct resource sc_ata; /* hand-crafted for ATA */
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struct resource sc_alt_ata; /* hand-crafted for ATA */
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u_int32_t sc_16bit_off; /* EXP_TIMING_CSx_OFFSET */
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int sc_rid; /* rid for IRQ */
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struct resource *sc_irq; /* IRQ resource */
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void *sc_ih; /* interrupt handler */
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@ -94,8 +104,14 @@ static void ata_bs_wm_2_s(void *, bus_space_handle_t, bus_size_t,
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static int
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ata_avila_probe(device_t dev)
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{
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struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
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/* XXX any way to check? */
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device_set_desc_copy(dev, "Gateworks Avila IDE/CF Controller");
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if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
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device_set_desc_copy(dev, "Gateworks Avila IDE/CF Controller");
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else
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device_set_desc_copy(dev,
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"ADI Pronghorn Metro IDE/CF Controller");
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return 0;
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}
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@ -104,14 +120,43 @@ ata_avila_attach(device_t dev)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
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u_int32_t alt_t_off, board_type, ide_gpin, ide_irq;
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board_type = 0;
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sc->sc_dev = dev;
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/* NB: borrow from parent */
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sc->sc_iot = sa->sc_iot;
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sc->sc_exp_ioh = sa->sc_exp_ioh;
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if (bus_space_map(sc->sc_iot,
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IXP425_EXP_BUS_CS1_HWBASE, IXP425_EXP_BUS_CS1_SIZE, 0, &sc->sc_ioh))
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panic("%s: unable to map Expansion Bus CS1 window", __func__);
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if (EXP_BUS_READ_4(sc, EXP_TIMING_CS2_OFFSET) != 0)
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board_type = 1; /* Avila board */
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if (board_type == 1) {
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if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS1_HWBASE,
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IXP425_EXP_BUS_CS1_SIZE, 0, &sc->sc_ioh))
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panic("%s: unable to map Expansion Bus CS1 window",
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__func__);
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if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS2_HWBASE,
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IXP425_EXP_BUS_CS2_SIZE, 0, &sc->sc_alt_ioh))
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panic("%s: unable to map Expansion Bus CS2 window",
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__func__);
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ide_gpin = AVILA_IDE_GPIN;
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ide_irq = AVILA_IDE_IRQ;
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sc->sc_16bit_off = EXP_TIMING_CS1_OFFSET;
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alt_t_off = EXP_TIMING_CS2_OFFSET;
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} else {
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if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS3_HWBASE,
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IXP425_EXP_BUS_CS3_SIZE, 0, &sc->sc_ioh))
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panic("%s: unable to map Expansion Bus CS3 window",
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__func__);
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if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS4_HWBASE,
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IXP425_EXP_BUS_CS4_SIZE, 0, &sc->sc_alt_ioh))
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panic("%s: unable to map Expansion Bus CS4 window",
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__func__);
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ide_gpin = PRONGHORN_IDE_GPIN;
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ide_irq = PRONGHORN_IDE_IRQ;
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sc->sc_16bit_off = EXP_TIMING_CS3_OFFSET;
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alt_t_off = EXP_TIMING_CS4_OFFSET;
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}
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/*
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* Craft special resource for ATA bus space ops
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@ -137,27 +182,34 @@ ata_avila_attach(device_t dev)
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rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
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rman_set_bushandle(&sc->sc_ata, sc->sc_ioh);
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rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
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rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
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GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPOER,
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GPIO_CONF_READ_4(sa, IXP425_GPIO_GPOER) | (1<<AVILA_IDE_GPIN));
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/* interrupt is active low */
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GPIO_CONF_WRITE_4(sa, GPIO_TYPE_REG(AVILA_IDE_GPIN),
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GPIO_CONF_READ_4(sa, GPIO_TYPE_REG(AVILA_IDE_GPIN) |
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GPIO_TYPE(AVILA_IDE_GPIN, GPIO_TYPE_ACT_LOW)));
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GPIO_CONF_READ_4(sa, IXP425_GPIO_GPOER) | (1<<ide_gpin));
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/* interrupt is active high */
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GPIO_CONF_WRITE_4(sa, GPIO_TYPE_REG(ide_gpin),
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(GPIO_CONF_READ_4(sa, GPIO_TYPE_REG(ide_gpin)) &
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~GPIO_TYPE(ide_gpin, GPIO_TYPE_MASK)) |
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GPIO_TYPE(ide_gpin, GPIO_TYPE_ACT_HIGH));
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/* clear ISR */
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GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPISR, (1<<AVILA_IDE_GPIN));
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GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPISR, (1<<ide_gpin));
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/* configure CS1 window, leaving timing unchanged */
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EXP_BUS_WRITE_4(sc, EXP_TIMING_CS1_OFFSET,
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EXP_BUS_READ_4(sc, EXP_TIMING_CS1_OFFSET) |
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/* configure CS1/3 window, leaving timing unchanged */
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) |
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EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
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/* configure CS2/4 window, leaving timing unchanged */
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EXP_BUS_WRITE_4(sc, alt_t_off,
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EXP_BUS_READ_4(sc, alt_t_off) |
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EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
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/* setup interrupt */
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sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid,
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AVILA_IDE_IRQ, AVILA_IDE_IRQ, 1, RF_ACTIVE);
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ide_irq, ide_irq, 1, RF_ACTIVE);
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if (!sc->sc_irq)
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panic("Unable to allocate irq %u.\n", AVILA_IDE_IRQ);
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panic("Unable to allocate irq %u.\n", ide_irq);
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bus_setup_intr(dev, sc->sc_irq,
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INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
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NULL, ata_avila_intr, sc, &sc->sc_ih);
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@ -261,8 +313,8 @@ ata_avila_teardown_intr(device_t dev, device_t child, struct resource *irq,
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static void __inline
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enable_16(struct ata_avila_softc *sc)
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{
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EXP_BUS_WRITE_4(sc, EXP_TIMING_CS1_OFFSET,
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EXP_BUS_READ_4(sc, EXP_TIMING_CS1_OFFSET) &~ EXP_BYTE_EN);
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) &~ EXP_BYTE_EN);
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DELAY(100); /* XXX? */
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}
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@ -270,8 +322,8 @@ static void __inline
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disable_16(struct ata_avila_softc *sc)
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{
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DELAY(100); /* XXX? */
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EXP_BUS_WRITE_4(sc, EXP_TIMING_CS1_OFFSET,
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EXP_BUS_READ_4(sc, EXP_TIMING_CS1_OFFSET) | EXP_BYTE_EN);
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN);
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}
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uint8_t
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@ -439,10 +491,11 @@ avila_channel_attach(device_t dev)
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/* NB: should be used only for ATAPI devices */
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ch->r_io[ATA_IREASON].offset = ATA_COUNT;
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ch->r_io[ATA_STATUS].offset = ATA_COMMAND;
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/* alias this; required by ata_generic_status */
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ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_STATUS].offset;
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/* NB: the control register is special */
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/* NB: the control and alt status registers are special */
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ch->r_io[ATA_ALTSTAT].res = &sc->sc_alt_ata;
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ch->r_io[ATA_ALTSTAT].offset = AVILA_IDE_CTRL;
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ch->r_io[ATA_CONTROL].res = &sc->sc_alt_ata;
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ch->r_io[ATA_CONTROL].offset = AVILA_IDE_CTRL;
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/* NB: by convention this points at the base of registers */
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@ -452,88 +505,6 @@ avila_channel_attach(device_t dev)
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return ata_attach(dev);
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}
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/* XXX override ata_generic_reset to handle non-standard status */
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static void
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avila_channel_reset(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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u_int8_t ostat0 = 0, stat0 = 0;
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u_int8_t err = 0, lsb = 0, msb = 0;
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int mask = 0, timeout;
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/* do we have any signs of ATA/ATAPI HW being present ? */
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
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DELAY(10);
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ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
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if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
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stat0 = ATA_S_BUSY;
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mask |= 0x01;
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}
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if (bootverbose)
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device_printf(dev, "%s: reset tp1 mask=%02x ostat0=%02x\n",
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__func__, mask, ostat0);
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/* if nothing showed up there is no need to get any further */
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/* XXX SOS is that too strong?, we just might loose devices here */
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ch->devices = 0;
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if (!mask)
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return;
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/* reset (both) devices on this channel */
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
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DELAY(10);
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ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
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ata_udelay(10000);
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ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
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ata_udelay(100000);
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ATA_IDX_INB(ch, ATA_ERROR);
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/* wait for BUSY to go inactive */
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for (timeout = 0; timeout < 310; timeout++) {
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if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
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DELAY(10);
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err = ATA_IDX_INB(ch, ATA_ERROR);
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lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
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msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
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stat0 = ATA_IDX_INB(ch, ATA_STATUS);
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if (bootverbose)
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device_printf(dev,
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"%s: stat0=0x%02x err=0x%02x lsb=0x%02x "
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"msb=0x%02x\n", __func__,
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stat0, err, lsb, msb);
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if (stat0 == err && lsb == err && msb == err &&
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timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
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mask &= ~0x01;
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if (!(stat0 & ATA_S_BUSY)) {
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if ((err & 0x7f) == ATA_E_ILI || err == 0) {
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if (lsb == ATAPI_MAGIC_LSB &&
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msb == ATAPI_MAGIC_MSB) {
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ch->devices |= ATA_ATAPI_MASTER;
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} else if (stat0 & ATA_S_READY) {
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ch->devices |= ATA_ATA_MASTER;
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}
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} else if ((stat0 & 0x0f) &&
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err == lsb && err == msb) {
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stat0 |= ATA_S_BUSY;
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}
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}
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}
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if (mask == 0x00) /* nothing to wait for */
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break;
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/* wait for master */
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if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
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break;
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ata_udelay(100000);
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}
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if (bootverbose)
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device_printf(dev, "%s: reset tp2 stat0=%02x devices=0x%b\n",
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__func__, stat0, ch->devices,
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"\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
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}
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static device_method_t avila_channel_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, avila_channel_probe),
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@ -543,8 +514,6 @@ static device_method_t avila_channel_methods[] = {
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DEVMETHOD(device_suspend, ata_suspend),
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DEVMETHOD(device_resume, ata_resume),
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DEVMETHOD(ata_reset, avila_channel_reset),
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{ 0, 0 }
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};
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