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pci: Implement pci_bar_enabled() for SR-IOV VFs
In a VF's configuration space, "memory space enable" is hard-wired to 0, so the existing implementation always returns false. We need to read the SR-IOV control register from the PF device to get the value of the MSE bit. Fix pci_bar_enabled() to read this register instead for VFs. I don't see any way to access the PF's config space without a backpointer in the pci device ivars, so I added one. This fixes a regression where bhyve(8) fails to map the MSI-X table after commit7fa2335347("bhyve: Map the MSI-X table unconditionally for passthrough") when a VF is passed through, since with that commit we use PCIOCBARMMAP to map the table and that ioctl always fails for VFs without this change. As a bonus, pciconf(8) now correctly reports the enablement of BARs for VFs. Reported and tested by: Raúl Muñoz <raul.munoz@custos.es> Reviewed by: rstone, jhb Sponsored by: The FreeBSD Foundation (cherry picked from commit1f960e646b)
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3 changed files with 12 additions and 0 deletions
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@ -3150,6 +3150,16 @@ pci_bar_enabled(device_t dev, struct pci_map *pm)
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if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
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!(pm->pm_value & PCIM_BIOS_ENABLE))
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return (0);
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#ifdef PCI_IOV
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if ((dinfo->cfg.flags & PCICFG_VF) != 0) {
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struct pcicfg_iov *iov;
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iov = dinfo->cfg.iov;
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cmd = pci_read_config(iov->iov_pf,
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iov->iov_pos + PCIR_SRIOV_CTL, 2);
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return ((cmd & PCIM_SRIOV_VF_MSE) != 0);
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}
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#endif
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
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return ((cmd & PCIM_CMD_MEMEN) != 0);
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@ -151,6 +151,7 @@ pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
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error = EBUSY;
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goto cleanup;
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}
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iov->iov_pf = dev;
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iov->iov_pos = iov_pos;
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schema = pci_iov_build_schema(&pf_schema, &vf_schema);
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@ -37,6 +37,7 @@ struct pci_iov_bar {
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};
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struct pcicfg_iov {
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device_t iov_pf;
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struct cdev *iov_cdev;
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nvlist_t *iov_schema;
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