diff --git a/sys/dev/sdhci/sdhci_fsl_fdt.c b/sys/dev/sdhci/sdhci_fsl_fdt.c
index 41804f6c1a1..5d4052a12a2 100644
--- a/sys/dev/sdhci/sdhci_fsl_fdt.c
+++ b/sys/dev/sdhci/sdhci_fsl_fdt.c
@@ -885,16 +885,6 @@ sdhci_fsl_fdt_attach(device_t dev)
 	sc->slot.max_clk = sc->maxclk_hz;
 	sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
 
-	/*
-	 * Pulse width detection is not reliable on some boards. Perform
-	 * workaround by clearing register's bit according to errata.
-	 */
-	if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) {
-		val = RD4(sc, SDHCI_FSL_DLLCFG1);
-		val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH;
-		WR4(sc, SDHCI_FSL_DLLCFG1, val);
-	}
-
 	/*
 	 * Set the buffer watermark level to 128 words (512 bytes) for both
 	 * read and write. The hardware has a restriction that when the read or
@@ -1028,6 +1018,16 @@ sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask)
 		WR4(sc, SDHCI_FSL_TBCTL, val);
 	}
 
+	/*
+	 * Pulse width detection is not reliable on some boards. Perform
+	 * workaround by clearing register's bit according to errata.
+	 */
+	if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) {
+		val = RD4(sc, SDHCI_FSL_DLLCFG1);
+		val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH;
+		WR4(sc, SDHCI_FSL_DLLCFG1, val);
+	}
+
 	sc->flags &= ~SDHCI_FSL_HS400_DONE;
 }