From a73d5cc09f9a6366cdbb13b547f29a3eb7c3c7e0 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Fri, 30 Oct 2015 23:07:32 +0000 Subject: [PATCH] arge: do an explicit flush between updating the TX ring and starting transmit. The MIPS busdma sync operations currently are a big no-op on coherent memory. This isn't strictly correct behaviour as we need a SYNC in here to ensure that the writes have finished and are visible in main memory before the MMIO accesses occur. This will have to be addressed in a later commit. But, before that happens, let's at least do a flush here to make things more "correct". This is required for even remotely sensible behaviour on mips74k with write-through memory enabled. --- sys/mips/atheros/if_arge.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/mips/atheros/if_arge.c b/sys/mips/atheros/if_arge.c index 3dffe18169f..00b92418bd3 100644 --- a/sys/mips/atheros/if_arge.c +++ b/sys/mips/atheros/if_arge.c @@ -1550,6 +1550,9 @@ arge_encap(struct arge_softc *sc, struct mbuf **m_head) sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* Flush writes */ + ARGE_BARRIER_WRITE(sc); + /* Start transmitting */ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n", __func__);