From a65bd3c84b2e0182117b8da5624496ec60fea56f Mon Sep 17 00:00:00 2001 From: Michal Meloun Date: Thu, 4 Feb 2016 14:02:42 +0000 Subject: [PATCH] ARM: Set UNAL_ENABLE bit in SCTLR CP15 register. This bit is RAO/SBOP for ARMv7. For ARMv6, it controls ARMv5 compatible alignment support. This bit have no effect until unaligned access is enabled. --- sys/arm/arm/locore-v6.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/arm/arm/locore-v6.S b/sys/arm/arm/locore-v6.S index eda60146dd5..b93af2c4b6b 100644 --- a/sys/arm/arm/locore-v6.S +++ b/sys/arm/arm/locore-v6.S @@ -132,9 +132,9 @@ ASENTRY_NP(_start) bic r7, #CPU_CONTROL_DC_ENABLE bic r7, #CPU_CONTROL_MMU_ENABLE bic r7, #CPU_CONTROL_IC_ENABLE - bic r7, #CPU_CONTROL_UNAL_ENABLE bic r7, #CPU_CONTROL_BPRD_ENABLE bic r7, #CPU_CONTROL_SW_ENABLE + orr r7, #CPU_CONTROL_UNAL_ENABLE orr r7, #CPU_CONTROL_AFLT_ENABLE orr r7, #CPU_CONTROL_VECRELOC mcr CP15_SCTLR(r7) @@ -456,9 +456,9 @@ ASENTRY_NP(mpentry) bic r0, #CPU_CONTROL_MMU_ENABLE bic r0, #CPU_CONTROL_DC_ENABLE bic r0, #CPU_CONTROL_IC_ENABLE - bic r0, #CPU_CONTROL_UNAL_ENABLE bic r0, #CPU_CONTROL_BPRD_ENABLE bic r0, #CPU_CONTROL_SW_ENABLE + orr r0, #CPU_CONTROL_UNAL_ENABLE orr r0, #CPU_CONTROL_AFLT_ENABLE orr r0, #CPU_CONTROL_VECRELOC mcr CP15_SCTLR(r0)