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Add initial clocks support for Rockchip RK3568 SoC.
Partially from: https://reviews.freebsd.org/D36027 This can be eventually improved or simplified or fixed if necessary. Following devices work with proper drivers and with the necessary clocks: Native networking via eqos driver USB3 and USB2 PCIe support is working but a bit picky about what hardware it supports (but so is Linux) SD & (e)MMC With the EDK2 loader video also works Supported hardwares are Quartz64, NanoPI R5S and Firefly Station P2, more to come as DTS files gets done.
This commit is contained in:
Søren Schmidt
Ganbold Tsagaankhuu
parent
0e3c99cbed
commit
a48301a5e0
2 changed files with 1388 additions and 0 deletions
1063
sys/arm64/rockchip/clk/rk3568_cru.c
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1063
sys/arm64/rockchip/clk/rk3568_cru.c
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File diff suppressed because it is too large
Load diff
325
sys/arm64/rockchip/clk/rk3568_pmucru.c
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325
sys/arm64/rockchip/clk/rk3568_pmucru.c
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <arm64/rockchip/clk/rk_cru.h>
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#include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h>
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#define RK3568_PLLSEL_CON(x) ((x) * 0x20)
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#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
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#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
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#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
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#define PNAME(_name) static const char *_name[]
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/* PLL clock */
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#define RK_PLL(_id, _name, _pnames, _off, _shift) \
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{ \
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.type = RK3328_CLK_PLL, \
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.clk.pll = &(struct rk_clk_pll_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pnames, \
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.clkdef.parent_cnt = nitems(_pnames), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.base_offset = RK3568_PLLSEL_CON(_off), \
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.mode_reg = 0x80, \
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.mode_shift = _shift, \
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.rates = rk3568_pll_rates, \
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}, \
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}
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/* Composite */
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#define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw, _f)\
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{ \
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.type = RK_CLK_COMPOSITE, \
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.clk.composite = &(struct rk_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pnames, \
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.clkdef.parent_cnt = nitems(_pnames), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.muxdiv_offset = RK3568_CLKSEL_CON(_o), \
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.mux_shift = _ms, \
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.mux_width = _mw, \
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.div_shift = _ds, \
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.div_width = _dw, \
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.gate_offset = RK3568_CLKGATE_CON(_go), \
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.gate_shift = _gw, \
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | \
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RK_CLK_COMPOSITE_HAVE_GATE | _f, \
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}, \
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}
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/* Composite no mux */
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#define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \
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{ \
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.type = RK_CLK_COMPOSITE, \
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.clk.composite = &(struct rk_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.muxdiv_offset = RK3568_CLKSEL_CON(_o), \
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.div_shift = _ds, \
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.div_width = _dw, \
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.gate_offset = RK3568_CLKGATE_CON(_go), \
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.gate_shift = _gw, \
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.flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \
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}, \
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}
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/* Fixed factor mux/div */
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#define RK_FACTOR(_id, _name, _pname, _mult, _div) \
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{ \
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.type = RK_CLK_FIXED, \
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.clk.fixed = &(struct clk_fixed_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.mult = _mult, \
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.div = _div, \
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}, \
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}
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/* Fractional */
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#define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \
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{ \
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.type = RK_CLK_FRACT, \
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.clk.fract = &(struct rk_clk_fract_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = RK3568_CLKSEL_CON(_o), \
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.gate_offset = RK3568_CLKGATE_CON(_go), \
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.gate_shift = _gw, \
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.flags = RK_CLK_FRACT_HAVE_GATE | _f, \
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}, \
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}
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/* Multiplexer */
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#define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \
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{ \
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.type = RK_CLK_MUX, \
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.clk.mux = &(struct rk_clk_mux_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pnames, \
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.clkdef.parent_cnt = nitems(_pnames), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = RK3568_CLKSEL_CON(_o), \
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.shift = _ms, \
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.width = _mw, \
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.mux_flags = _f, \
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}, \
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}
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#define RK_GATE(_id, _name, _pname, _o, _s) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _pname, \
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.offset = RK3568_CLKGATE_CON(_o), \
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.shift = _s, \
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}
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extern struct rk_clk_pll_rate rk3568_pll_rates[];
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/* Parent clock defines */
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PNAME(mux_pll_p) = { "xin24m" };
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PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
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PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
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PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
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PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
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PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };
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PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };
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PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
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PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
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PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
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PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
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PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
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PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
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PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };
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PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
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PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
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/* CLOCKS */
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static struct rk_clk rk3568_clks[] = {
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/* External clocks */
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LINK("xin24m"),
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LINK("cpll"),
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LINK("gpll"),
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LINK("usb480m"),
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LINK("clk_32k_pvtm"),
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/* SRC_CLK */
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RK_MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, 0, 6, 2, 0),
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RK_MUX(0, "sclk_uart0_mux", sclk_uart0_p, 4, 10, 2, 0),
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/* PLL's */
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RK_PLL(PLL_PPLL, "ppll", mux_pll_p, 0, 0),
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RK_PLL(PLL_HPLL, "hpll", mux_pll_p, 2, 2),
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/* PD_PMU */
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RK_FACTOR(0, "ppll_ph0", "ppll", 1, 2),
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RK_FACTOR(0, "ppll_ph180", "ppll", 1, 2),
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RK_FACTOR(0, "hpll_ph0", "hpll", 1, 2),
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RK_MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 2, 15, 1, 0),
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RK_COMPNOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 2, 0, 5, 0, 2, 0),
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RK_COMPNOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 3, 0, 7, 1, 1, 0),
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RK_FRACTION(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", 1, 0, 1, 0),
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RK_COMPNOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, 0, 5, 0, 0, 0),
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RK_COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div",
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ppll_usb480m_cpll_gpll_p, 4, 8, 2, 0, 7, 1, 3, 0),
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RK_FRACTION(CLK_UART0_FRAC, "sclk_uart0_frac",
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"sclk_uart0_div", 5, 1, 4, 0),
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RK_MUX(DBCLK_GPIO0, "dbclk_gpio0_c", xin24m_32k_p, 6, 15, 1, 0),
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RK_COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 6, 7, 1, 0, 7, 1, 7, 0),
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RK_COMPNOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 7, 0, 6, 2, 0, 0),
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RK_MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref",
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clk_usbphy0_ref_p, 8, 0, 1, 0),
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RK_MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref",
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clk_usbphy1_ref_p, 8, 1, 1, 0),
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RK_MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref",
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clk_mipidsiphy0_ref_p, 8, 2, 1, 0),
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RK_MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref",
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clk_mipidsiphy1_ref_p, 8, 3, 1, 0),
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RK_COMPNOMUX(CLK_WIFI_DIV, "clk_wifi_div",
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"clk_pdpmu", 8, 8, 6, 2, 5, 0),
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RK_MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, 8, 15, 1, 0),
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RK_COMPNOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div",
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"ppll_ph0", 9, 0, 3, 2, 7, 0),
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RK_MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref",
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clk_pciephy0_ref_p, 9, 3, 1, 0),
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RK_COMPNOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div",
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"ppll_ph0", 9, 4, 3, 2, 9, 0),
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RK_MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref",
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clk_pciephy1_ref_p, 9, 7, 1, 0),
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RK_COMPNOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div",
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"ppll_ph0", 9, 8, 3, 2, 11, 0),
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RK_MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref",
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clk_pciephy2_ref_p, 9, 11, 1, 0),
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RK_MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 8, 7, 1, 0),
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};
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/* GATES */
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static struct rk_cru_gate rk3568_gates[] = {
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RK_GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6),
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RK_GATE(DBCLK_GPIO0, "dbclk_gpio0", "dbclk_gpio0_c", 1, 10),
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RK_GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
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RK_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0),
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RK_GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),
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RK_GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 1, 5),
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RK_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 1, 9),
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RK_GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 1, 6),
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RK_GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 1, 8),
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RK_GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 1, 11),
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RK_GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12),
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RK_GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 1, 13),
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RK_GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 2, 1),
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RK_GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 2, 2),
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RK_GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g",
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"xin24m", 2, 3),
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RK_GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g",
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"xin24m", 2, 4),
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RK_GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 2, 6),
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RK_GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 2, 8),
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RK_GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 2, 10),
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RK_GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 2, 12),
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RK_GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 2, 13),
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RK_GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 2,14),
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RK_GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 2, 15),
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};
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static int
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rk3568_pmucru_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "rockchip,rk3568-pmucru")) {
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device_set_desc(dev, "Rockchip RK3568 PMU Clock & Reset Unit");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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rk3568_pmucru_attach(device_t dev)
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{
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struct rk_cru_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->clks = rk3568_clks;
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sc->nclks = nitems(rk3568_clks);
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sc->gates = rk3568_gates;
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sc->ngates = nitems(rk3568_gates);
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sc->reset_offset = 0x200;
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sc->reset_num = 4;
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return (rk_cru_attach(dev));
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}
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static device_method_t methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rk3568_pmucru_probe),
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DEVMETHOD(device_attach, rk3568_pmucru_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(rk3568_pmucru, rk3568_pmucru_driver, methods,
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sizeof(struct rk_cru_softc), rk_cru_driver);
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EARLY_DRIVER_MODULE(rk3568_pmucru, simplebus, rk3568_pmucru_driver,
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0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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||||
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