From a39b3aa463f3474fabb3aedb5aecf943b54b4357 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 4 Mar 2024 21:30:54 +0100 Subject: [PATCH] Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks): MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [PEI] Don't zero out noreg operands A tail call may have $noreg operands. Fixes a crash. Reviewed By: xgupta Differential Revision: https://reviews.llvm.org/D156485 This should fix an assertion failure building qemu, specifically those parts using -fzero-call-used-regs. Reported by: Daniel Berrangé PR: 277474 MFC after: 3 days --- .../llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp index e323aaaeefa..49047719fda 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1285,6 +1285,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; MCRegister Reg = MO.getReg(); + if (!Reg) + continue; // This picks up sibling registers (e.q. %al -> %ah). for (MCRegUnit Unit : TRI.regunits(Reg)) @@ -1308,8 +1310,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { if (!MO.isReg()) continue; - for (const MCPhysReg &Reg : - TRI.sub_and_superregs_inclusive(MO.getReg())) + MCRegister Reg = MO.getReg(); + if (!Reg) + continue; + + for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg)) RegsToZero.reset(Reg); } }