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fu740_pci_dw: Fix PERST delay and keep asserted for rest of reset sequence

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DELAY takes microseconds not milliseconds, so 100 was too low. Moreover,
when enabling hw.pci.clear_pcib, PCI emeration would still stop at one
of the first bridges, but by asserting PERST for the rest of the reset
sequence that appears to be reliably addressed.

Fixes:	896e217a0e ("fu740_pci_dw: Add SiFive FU740 PCIe controller driver")

(cherry picked from commit 28aaa58fa64ecb89d47f0a8396954ad8ca82d8ef)
This commit is contained in:
Jessica Clarke 2024-06-02 21:42:18 +01:00
parent 4acf9ba16d
commit 9ae4c66bff
1 changed files with 6 additions and 6 deletions
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12
sys/riscv/sifive/fu740_pci_dw.c
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@ -216,12 +216,6 @@ fupci_phy_init(struct fupci_softc *sc)
return (error);
}
/* Hold PERST for 100ms as per the PCIe spec */
DELAY(100);
/* Deassert PERST_N */
FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 1);
/* Deassert core power-on reset (active low) */
error = gpio_pin_set_active(sc->porst_pin, true);
if (error != 0) {
@ -281,6 +275,12 @@ fupci_phy_init(struct fupci_softc *sc)
/* Put the controller in Root Complex mode */
FUDW_MGMT_WRITE(sc, FUDW_MGMT_DEVICE_TYPE, FUDW_MGMT_DEVICE_TYPE_RC);
/* Hold PERST for 100ms as per the PCIe spec */
DELAY(100000);
/* Deassert PERST_N */
FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 1);
return (0);
}